u-boot: bump Rockchip to 2025.10-rc4 and update patchset

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>

packages/tools/u-boot/package.mk

@@ -13,8 +13,8 @@ PKG_STAMP="${UBOOT_SYSTEM} ${UBOOT_TARGET}"
 
 case ${PROJECT} in
   Rockchip)
-    PKG_VERSION="2025.10-rc3" # plus Kwiboo changes for RK3576 support
+    PKG_VERSION="2025.10-rc4" # plus Kwiboo changes for RK3576 support
-    PKG_SHA256="1224f85046da9a8687df26b7f87ce74fe3b29d40b0151b06f9add88be5c3dc9d"
+    PKG_SHA256="a30574d74a4a761ed683a2b74d938ddb89e3ffacc3b2a6aabf3f40be91d03ebe"
     PKG_URL="https://ftp.denx.de/pub/u-boot/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
     ;;
   *)

projects/Rockchip/patches/u-boot/rockchip-0001-phy-rockchip-naneng-combphy-Enable-U3-port-for-USB3O.patch

@@ -1,7 +1,7 @@
-From 23b7834fa5265f7b4c14b84c454951783adb2156 Mon Sep 17 00:00:00 2001
+From 853612b964d72d9e9d12b7baeea05970be71120b Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 13:09:38 +0000
-Subject: [PATCH 12/84] phy: rockchip: naneng-combphy: Enable U3 port for
+Subject: [PATCH 01/51] phy: rockchip: naneng-combphy: Enable U3 port for
  USB3OTG on RK3568
 
 The USB OTG U3 port may have been disabled early, add support to the
@@ -13,10 +13,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 8 insertions(+)
 
 diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index 7f107a11606..81195de60bc 100644
+index d602f965d6a..82353ae7678 100644
 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
 +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -301,6 +301,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+@@ -399,6 +399,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
  		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
  		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
  		param_write(priv->phy_grf, &cfg->usb_mode_set, true);

projects/Rockchip/patches/u-boot/rockchip-0001-rockchip-rockchip-inno-usb2-Fix-Synchronous-Abort-on.patch

@@ -1,76 +0,0 @@
-From 84361828ad40949a0ca4f9a39b7248c46bf71b7c Mon Sep 17 00:00:00 2001
-From: Alex Shumsky <alexthreed@gmail.com>
-Date: Thu, 3 Jul 2025 09:04:48 +0300
-Subject: [PATCH 01/84] rockchip: rockchip-inno-usb2: Fix Synchronous Abort on
- usb start
-
-Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
-enabled before device probe. This early clock enable call happen in process
-of parent clock activation added in ac30d90f3367.
-
-Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy").
-Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
-Co-authored-by: Jonas Karlman <jonas@kwiboo.se>
-Signed-off-by: Alex Shumsky <alexthreed@gmail.com>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++++++++++-----
- 1 file changed, 14 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-index 88b33de1b2a..3cc5956aed5 100644
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = {
- 	.of_xlate = rockchip_usb2phy_of_xlate,
- };
- 
--static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
--					const struct usb2phy_reg **clkout_ctl)
-+static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
-+				       const struct usb2phy_reg **clkout_ctl)
- {
- 	struct udevice *parent = dev_get_parent(clk->dev);
- 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
- 	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
- 
--	if (priv->phy_cfg->clkout_ctl_phy.enable) {
-+	// phy_cfg can be NULL if this function called before probe (when parent
-+	// clocks are enabled)
-+	if (!phy_cfg)
-+		return -EINVAL;
-+
-+	if (phy_cfg->clkout_ctl_phy.enable) {
- 		*base = priv->phy_base;
- 		*clkout_ctl = &phy_cfg->clkout_ctl_phy;
- 	} else {
- 		*base = priv->reg_base;
- 		*clkout_ctl = &phy_cfg->clkout_ctl;
- 	}
-+
-+	return 0;
- }
- 
- /**
-@@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
- 	const struct usb2phy_reg *clkout_ctl;
- 	struct regmap *base;
- 
--	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
-+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
-+		return -ENOSYS;
- 
- 	/* turn on 480m clk output if it is off */
- 	if (!property_enabled(base, clkout_ctl)) {
-@@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)
- 	const struct usb2phy_reg *clkout_ctl;
- 	struct regmap *base;
- 
--	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
-+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
-+		return -ENOSYS;
- 
- 	/* turn off 480m clk output */
- 	property_enable(base, clkout_ctl, false);
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0002-phy-rockchip-usbdp-Fix-Generic-PHY-reference-countin.patch

@@ -1,72 +0,0 @@
-From 813fb2de3997d55a44c82769bc26fa6e548ad9d1 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:10 +0000
-Subject: [PATCH 02/84] phy: rockchip: usbdp: Fix Generic PHY reference
- counting
-
-Generic PHY reference counting helps ensure driver ops for init/exit and
-power on/off are called at correct state. For this to work the PHY
-driver must initialize PHY-id to a persistent value in of_xlate ops.
-
-The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
-typically lead to use of unshared reference counting among different
-struct phy instances.
-
-Initialize the PHY-id in of_xlate ops to ensure use of shared reference
-counting among all struct phy instances.
-
-E.g. on a ROCK 5B following could be observed:
-
-  => usb start
-  starting USB...
-  [...]
-  Bus usb@fc400000: 2 USB Device(s) found
-         scanning usb for storage devices... 1 Storage Device(s) found
-
-  => usb reset
-  resetting USB...
-  [...]
-  rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
-  rockchip_udphy phy@fed90000: failed to init usbdp combophy
-  rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
-  Can't init PHY1
-  Bus usb@fc400000: probe failed, error -110
-         scanning usb for storage devices... 0 Storage Device(s) found
-
-With shared reference counting this is fixed:
-
-  => usb reset
-  resetting USB...
-  [...]
-  Bus usb@fc400000: 2 USB Device(s) found
-         scanning usb for storage devices... 1 Storage Device(s) found
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-index 9deec47ae46..56963c87183 100644
---- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
-+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -587,12 +587,16 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
- static int rockchip_u3phy_of_xlate(struct phy *phy,
- 				   struct ofnode_phandle_args *args)
- {
-+	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
-+
- 	if (args->args_count == 0)
- 		return -EINVAL;
- 
- 	if (args->args[0] != PHY_TYPE_USB3)
- 		return -EINVAL;
- 
-+	phy->id = udphy->id;
-+
- 	return 0;
- }
- 
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0002-rockchip-rk3568-Disable-USB3OTG-U3-ports-early.patch

@@ -1,7 +1,7 @@
-From 8d5f4e5a9e5e2281386e4d273e5232a8636bfff8 Mon Sep 17 00:00:00 2001
+From 2890fa911ceadb70514af483acae2a3c8e546ae3 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 13:10:36 +0000
-Subject: [PATCH 13/84] rockchip: rk3568: Disable USB3OTG U3 ports early
+Subject: [PATCH 02/51] rockchip: rk3568: Disable USB3OTG U3 ports early
 
 The RK3568 SoC comes with USB OTG support using a DWC3 controller with
 a USB2 PHY and a USB3 PHY (COMBPHY).

projects/Rockchip/patches/u-boot/rockchip-0003-mmc-rockchip_sdhci-Set-xx_TAP_VALUE-for-RK3528.patch

@@ -1,7 +1,7 @@
-From e3cb5639cb00274c6517f28e47d0849534bab000 Mon Sep 17 00:00:00 2001
+From 5896962c834789527d2a54eb409f8c3a18146d75 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Mon, 14 Jul 2025 20:34:07 +0000
-Subject: [PATCH 14/84] mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
+Subject: [PATCH 03/51] mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
 
 eMMC erase and write support on RK3528 is somewhat unreliable, sometime
 e.g. mmc erase and write commands will fail with an error.
@@ -19,7 +19,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 22 insertions(+), 5 deletions(-)
 
 diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
-index 761e3619329..cca917da68e 100644
+index 5e025d76a82..8116e464278 100644
 --- a/drivers/mmc/rockchip_sdhci.c
 +++ b/drivers/mmc/rockchip_sdhci.c
 @@ -9,6 +9,7 @@

projects/Rockchip/patches/u-boot/rockchip-0003-phy-rockchip-usbdp-Simplify-init-ops.patch

@@ -1,134 +0,0 @@
-From ef03459846d7be6b231c19e07f4613ec1f74b884 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:11 +0000
-Subject: [PATCH 03/84] phy: rockchip: usbdp: Simplify init ops
-
-With working shared reference counting for Generic PHY ops there is no
-need for the Rockchip USBDP PHY driver to keep its own status (reference
-counting) handling.
-
-Simplify the init ops now that shared reference counting is working.
-This also removes the unused mode_change handling as part of the
-simplication.
-
-No runtime change is expected with this simplication.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 71 +++--------------------
- 1 file changed, 8 insertions(+), 63 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-index 56963c87183..6cfbef02b4a 100644
---- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
-+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -96,9 +96,7 @@ struct rockchip_udphy {
- 
- 	/* PHY status management */
- 	bool flip;
--	bool mode_change;
- 	u8 mode;
--	u8 status;
- 
- 	/* utilized for USB */
- 	bool hs; /* flag for high-speed */
-@@ -525,65 +523,6 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
- 	return 0;
- }
- 
--static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
--{
--	int ret;
--
--	if (!(udphy->mode & mode)) {
--		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
--		return 0;
--	}
--
--	if (udphy->status == UDPHY_MODE_NONE) {
--		udphy->mode_change = false;
--		ret = udphy_setup(udphy);
--		if (ret)
--			return ret;
--
--		if (udphy->mode & UDPHY_MODE_USB)
--			udphy_u3_port_disable(udphy, false);
--	} else if (udphy->mode_change) {
--		udphy->mode_change = false;
--		udphy->status = UDPHY_MODE_NONE;
--		if (udphy->mode == UDPHY_MODE_DP)
--			udphy_u3_port_disable(udphy, true);
--
--		ret = udphy_disable(udphy);
--		if (ret)
--			return ret;
--		ret = udphy_setup(udphy);
--		if (ret)
--			return ret;
--	}
--
--	udphy->status |= mode;
--
--	return 0;
--}
--
--static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
--{
--	int ret;
--
--	if (!(udphy->mode & mode)) {
--		dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
--		return 0;
--	}
--
--	if (!udphy->status)
--		return 0;
--
--	udphy->status &= ~mode;
--
--	if (udphy->status == UDPHY_MODE_NONE) {
--		ret = udphy_disable(udphy);
--		if (ret)
--			return ret;
--	}
--
--	return 0;
--}
--
- static int rockchip_u3phy_of_xlate(struct phy *phy,
- 				   struct ofnode_phandle_args *args)
- {
-@@ -603,6 +542,7 @@ static int rockchip_u3phy_of_xlate(struct phy *phy,
- static int rockchip_u3phy_init(struct phy *phy)
- {
- 	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
-+	int ret;
- 
- 	/* DP only or high-speed, disable U3 port */
- 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
-@@ -610,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy)
- 		return 0;
- 	}
- 
--	return udphy_power_on(udphy, UDPHY_MODE_USB);
-+	ret = udphy_setup(udphy);
-+	if (ret)
-+		return ret;
-+
-+	udphy_u3_port_disable(udphy, false);
-+	return 0;
- }
- 
- static int rockchip_u3phy_exit(struct phy *phy)
-@@ -621,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy)
- 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
- 		return 0;
- 
--	return udphy_power_off(udphy, UDPHY_MODE_USB);
-+	return udphy_disable(udphy);
- }
- 
- static const struct phy_ops rockchip_u3phy_ops = {
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0004-HACK-rockchip-dts-upstream-use-v6.17-rockchip-dts64-.patch

@@ -1,7 +1,7 @@
-From 66aaba61526a93e9544e38206a77c8793bc74807 Mon Sep 17 00:00:00 2001
+From 761e2216beda33b15a91a1952add73ccca9a8586 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 10:13:08 +0000
-Subject: [PATCH 23/84] HACK: rockchip: dts/upstream: use
+Subject: [PATCH 04/51] HACK: rockchip: dts/upstream: use
  v6.17-rockchip-dts64-2 RK3528 DTs
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0004-phy-rockchip-naneng-combphy-Fix-Generic-PHY-referenc.patch

@@ -1,37 +0,0 @@
-From 5338a239b47d28a04da856bd9fbc18d4fefa96ba Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:12 +0000
-Subject: [PATCH 04/84] phy: rockchip: naneng-combphy: Fix Generic PHY
- reference counting
-
-Generic PHY reference counting helps ensure driver ops for init/exit and
-power on/off are called at correct state. For this to work the PHY
-driver must initialize PHY-id to a persistent value in of_xlate ops.
-
-The Rockchip COMBPHY driver does not initialize the PHY-id field, this
-typically lead to use of unshared reference counting among different
-struct phy instances.
-
-Initialize the PHY-id in of_xlate ops to ensure use of shared reference
-counting among all struct phy instances.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index 5145b517aa4..a3038d067d3 100644
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -223,6 +223,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a
- 		return -EINVAL;
- 	}
- 
-+	phy->id = priv->id;
- 	priv->mode = args->args[0];
- 
- 	return 0;
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0005-phy-rockchip-naneng-combphy-Simplify-init-ops.patch

@@ -1,159 +0,0 @@
-From 87ec15bbdc953d552dde11a5772b1e3dadc855f4 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:13 +0000
-Subject: [PATCH 05/84] phy: rockchip: naneng-combphy: Simplify init ops
-
-The init ops for Rockchip COMBPHY driver is more complex than it needs
-to be, e.g. declaring multiple init functions that only differ in the
-error message.
-
-Simplify the init ops based on code from the Linux mainline driver.
-
-This change also ensure that errors returned from combphy_cfg() and
-reset_deassert_bulk() is propertly propagated to the caller. No other
-runtime change is expected with this simplication.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- .../rockchip/phy-rockchip-naneng-combphy.c    | 101 ++++--------------
- 1 file changed, 19 insertions(+), 82 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index a3038d067d3..f246c8db2d6 100644
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -98,104 +98,41 @@ static int param_write(struct regmap *base,
- 	return regmap_write(base, reg->offset, val);
- }
- 
--static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
--{
--	int ret = 0;
--
--	if (priv->cfg->combphy_cfg) {
--		ret = priv->cfg->combphy_cfg(priv);
--		if (ret) {
--			dev_err(priv->dev, "failed to init phy for pcie\n");
--			return ret;
--		}
--	}
--
--	return ret;
--}
--
--static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
--{
--	int ret = 0;
--
--	if (priv->cfg->combphy_cfg) {
--		ret = priv->cfg->combphy_cfg(priv);
--		if (ret) {
--			dev_err(priv->dev, "failed to init phy for usb3\n");
--			return ret;
--		}
--	}
--
--	return ret;
--}
--
--static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
--{
--	int ret = 0;
--
--	if (priv->cfg->combphy_cfg) {
--		ret = priv->cfg->combphy_cfg(priv);
--		if (ret) {
--			dev_err(priv->dev, "failed to init phy for sata\n");
--			return ret;
--		}
--	}
--
--	return ret;
--}
--
--static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
-+static int rockchip_combphy_init(struct phy *phy)
- {
--	int ret = 0;
--
--	if (priv->cfg->combphy_cfg) {
--		ret = priv->cfg->combphy_cfg(priv);
--		if (ret) {
--			dev_err(priv->dev, "failed to init phy for sgmii\n");
--			return ret;
--		}
--	}
-+	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
-+	int ret;
- 
--	return ret;
--}
-+	ret = clk_enable(&priv->ref_clk);
-+	if (ret < 0 && ret != -ENOSYS)
-+		return ret;
- 
--static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
--{
- 	switch (priv->mode) {
- 	case PHY_TYPE_PCIE:
--		rockchip_combphy_pcie_init(priv);
--		break;
- 	case PHY_TYPE_USB3:
--		rockchip_combphy_usb3_init(priv);
--		break;
- 	case PHY_TYPE_SATA:
--		rockchip_combphy_sata_init(priv);
--		break;
- 	case PHY_TYPE_SGMII:
- 	case PHY_TYPE_QSGMII:
--		return rockchip_combphy_sgmii_init(priv);
-+		if (priv->cfg->combphy_cfg)
-+			ret = priv->cfg->combphy_cfg(priv);
-+		else
-+			ret = 0;
-+		break;
- 	default:
- 		dev_err(priv->dev, "incompatible PHY type\n");
--		return -EINVAL;
-+		ret = -EINVAL;
-+		break;
- 	}
- 
--	return 0;
--}
--
--static int rockchip_combphy_init(struct phy *phy)
--{
--	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
--	int ret;
--
--	ret = clk_enable(&priv->ref_clk);
--	if (ret < 0 && ret != -ENOSYS)
--		return ret;
-+	if (ret) {
-+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode);
-+		goto err_clk;
-+	}
- 
--	ret = rockchip_combphy_set_mode(priv);
-+	ret = reset_deassert_bulk(&priv->phy_rsts);
- 	if (ret)
- 		goto err_clk;
- 
--	reset_deassert_bulk(&priv->phy_rsts);
--
- 	return 0;
- 
- err_clk:
-@@ -305,7 +242,7 @@ static int rockchip_combphy_probe(struct udevice *udev)
- 	}
- 
- 	priv->dev = udev;
--	priv->mode = PHY_TYPE_SATA;
-+	priv->mode = PHY_NONE;
- 	priv->cfg = phy_cfg;
- 
- 	return rockchip_combphy_parse_dt(udev, priv);
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0005-rockchip-rk3528-radxa-e20c-Drop-eMMC-HS200-prop-from.patch

@@ -1,7 +1,7 @@
-From f46aba244531135b5349418c5a1d386a5af54ee9 Mon Sep 17 00:00:00 2001
+From a75fe1d67e8adf70c6f70c09a0956345069d0531 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 15:23:27 +0000
-Subject: [PATCH 24/84] rockchip: rk3528-radxa-e20c: Drop eMMC HS200 prop from
+Subject: [PATCH 05/51] rockchip: rk3528-radxa-e20c: Drop eMMC HS200 prop from
  board u-boot.dtsi
 
 The commit f8cb3fde935e ("arm: dts: rockchip: Fix eMMC write on RK3528")

projects/Rockchip/patches/u-boot/rockchip-0006-HACK-rockchip-dts-upstream-use-work-in-progress-RK35.patch

@@ -1,7 +1,7 @@
-From ea6c170437917c10bfae93ea2e1b58edc8b6eab8 Mon Sep 17 00:00:00 2001
+From 6baa2c963767dd90a4186483422d7c83902750d1 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 12 Mar 2025 00:32:03 +0000
-Subject: [PATCH 25/84] HACK: rockchip: dts/upstream: use work-in-progress
+Subject: [PATCH 06/51] HACK: rockchip: dts/upstream: use work-in-progress
  RK3528 DTs
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0006-phy-rockchip-naneng-combphy-Use-syscon_regmap_lookup.patch

@@ -1,53 +0,0 @@
-From eec16e822568cf506da371bd8d4ea21c04567dc9 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:14 +0000
-Subject: [PATCH 06/84] phy: rockchip: naneng-combphy: Use
- syscon_regmap_lookup_by_phandle
-
-Change to use syscon_regmap_lookup_by_phandle() helper instead of
-finding the syscon udevice and making a call to syscon_get_regmap().
-
-No runtime change is expected with this simplication.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- .../phy/rockchip/phy-rockchip-naneng-combphy.c  | 17 +++++++----------
- 1 file changed, 7 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index f246c8db2d6..7f107a11606 100644
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -175,22 +175,19 @@ static const struct phy_ops rockchip_combphy_ops = {
- static int rockchip_combphy_parse_dt(struct udevice *dev,
- 				     struct rockchip_combphy_priv *priv)
- {
--	struct udevice *syscon;
- 	int ret;
- 
--	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon);
--	if (ret) {
--		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap");
--		return ret;
-+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
-+	if (IS_ERR(priv->pipe_grf)) {
-+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
-+		return PTR_ERR(priv->pipe_grf);
- 	}
--	priv->pipe_grf = syscon_get_regmap(syscon);
- 
--	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon);
--	if (ret) {
-+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf");
-+	if (IS_ERR(priv->phy_grf)) {
- 		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
--		return ret;
-+		return PTR_ERR(priv->phy_grf);
- 	}
--	priv->phy_grf = syscon_get_regmap(syscon);
- 
- 	ret = clk_get_by_index(dev, 0, &priv->ref_clk);
- 	if (ret) {
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0007-phy-rockchip-inno-usb2-Fix-improper-use-of-UCLASS_PH.patch

@@ -1,35 +0,0 @@
-From 677ca627443e49b96b0b21fe9d33070848b26a7b Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:15 +0000
-Subject: [PATCH 07/84] phy: rockchip: inno-usb2: Fix improper use of
- UCLASS_PHY
-
-The Rockchip USB2PHY glue driver improperly present itself as a
-UCLASS_PHY driver, without ever implementing the required phy_ops.
-
-This is something that in special circumstances can lead to a NULL
-pointer dereference followed by a SError crash.
-
-Change the glue driver to use UCLASS_NOP to fix this.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-index 3cc5956aed5..a3222138b9d 100644
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -547,7 +547,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = {
- 
- U_BOOT_DRIVER(rockchip_usb2phy) = {
- 	.name	= "rockchip_usb2phy",
--	.id	= UCLASS_PHY,
-+	.id	= UCLASS_NOP,
- 	.of_match = rockchip_usb2phy_ids,
- 	.probe = rockchip_usb2phy_probe,
- 	.bind = rockchip_usb2phy_bind,
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0007-rockchip-rk3528-generic-Add-basic-support-for-USB-OT.patch

@@ -1,7 +1,7 @@
-From bc38f857e5ae6e1dd211151c6cbf458d8a878774 Mon Sep 17 00:00:00 2001
+From 3786a7326b5a6a0c1129e09dd6afb1c73b03a5e8 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 10:08:16 +0000
-Subject: [PATCH 26/84] rockchip: rk3528-generic: Add basic support for USB OTG
+Subject: [PATCH 07/51] rockchip: rk3528-generic: Add basic support for USB OTG
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
 ---

projects/Rockchip/patches/u-boot/rockchip-0008-phy-rockchip-typec-Fix-improper-use-of-UCLASS_PHY.patch

@@ -1,34 +0,0 @@
-From b607543bf26e94417f401654f5eed7459f6a7547 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:16 +0000
-Subject: [PATCH 08/84] phy: rockchip: typec: Fix improper use of UCLASS_PHY
-
-The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY
-driver, without ever implementing the required phy_ops.
-
-This is something that in special circumstances can lead to a NULL
-pointer dereference followed by a SError crash.
-
-Change the glue driver to use UCLASS_NOP to fix this.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-typec.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
-index c48a5cd5267..66d1d32d25c 100644
---- a/drivers/phy/rockchip/phy-rockchip-typec.c
-+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
-@@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
- 
- U_BOOT_DRIVER(rockchip_typec_phy) = {
- 	.name	= "rockchip_typec_phy",
--	.id	= UCLASS_PHY,
-+	.id	= UCLASS_NOP,
- 	.of_match = rockchip_typec_phy_ids,
- 	.probe = rockchip_tcphy_probe,
- 	.bind = rockchip_tcphy_bind,
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0008-rockchip-rk3528-Add-support-for-booting-from-SPI-fla.patch

@@ -1,7 +1,7 @@
-From 6f012de41460639e7efd9a6713ee3757b40a0c85 Mon Sep 17 00:00:00 2001
+From 5287ab111719d5be9ca32b2419061095529de70e Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 23 Jul 2025 22:22:36 +0000
-Subject: [PATCH 27/84] rockchip: rk3528: Add support for booting from SPI
+Subject: [PATCH 08/51] rockchip: rk3528: Add support for booting from SPI
  flash
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0009-WIP-net-rockchip-Allow-use-of-rx-tx-delayline-for-rg.patch

@@ -1,7 +1,7 @@
-From 81809fd8f075a3fd12d7388d8222609f17fbc6f5 Mon Sep 17 00:00:00 2001
+From fa397cbb00e6217c591243541dd7bafeec62e001 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 27 Jul 2025 08:45:50 +0000
-Subject: [PATCH 28/84] WIP: net: rockchip: Allow use of rx/tx delayline for
+Subject: [PATCH 09/51] WIP: net: rockchip: Allow use of rx/tx delayline for
  rgmii-id modes
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0009-rockchip-rk3588-Disable-USB3OTG-U3-ports-early.patch

@@ -1,50 +0,0 @@
-From 12d3074fb4c7c8ab80bbc5f5faae505e25609385 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:17 +0000
-Subject: [PATCH 09/84] rockchip: rk3588: Disable USB3OTG U3 ports early
-
-The RK3588 SoC comes with USB OTG support using a DWC3 controller with
-a USB2 PHY and a USB3 PHY (USBDP PHY).
-
-Some board designs may not use the USBDP PHY for USB3 purpose. For these
-board to use USB OTG the input clock source must change to use UTMI clk
-instead of PIPE clk.
-
-Change to always disable the USB3OTG U3 ports early and leave it to the
-USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
-in the board device tree.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
-index e2278ff792b..c01a4002089 100644
---- a/arch/arm/mach-rockchip/rk3588/rk3588.c
-+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
-@@ -15,6 +15,10 @@
- #include <asm/arch-rockchip/hardware.h>
- #include <asm/arch-rockchip/ioc_rk3588.h>
- 
-+#define USB_GRF_BASE			0xfd5ac000
-+#define USB3OTG0_CON1			0x001c
-+#define USB3OTG1_CON1			0x0034
-+
- #define FIREWALL_DDR_BASE		0xfe030000
- #define FW_DDR_MST5_REG			0x54
- #define FW_DDR_MST13_REG		0x74
-@@ -184,6 +188,10 @@ int arch_cpu_init(void)
- 	/* Disable JTAG exposed on SDMMC */
- 	rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
- #endif
-+
-+	/* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
-+	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
-+	writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
- #endif
- 
- 	return 0;
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0010-WIP-net-rockchip-Use-CRU-as-default-TX-clk-source-fo.patch

@@ -1,7 +1,7 @@
-From c95d9d8bb9c312e78c3027fb89139200c5421bfb Mon Sep 17 00:00:00 2001
+From bd1ae5092d835376db267a50f31e9dbb45ccf681 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 27 Jul 2025 08:46:40 +0000
-Subject: [PATCH 29/84] WIP: net: rockchip Use CRU as default TX clk source for
+Subject: [PATCH 10/51] WIP: net: rockchip Use CRU as default TX clk source for
  RGMII modes
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0010-rockchip-rk3576-Disable-USB3OTG0-U3-port-early.patch

@@ -1,47 +0,0 @@
-From bbf94bdbe33c3644ae2172d723d3ae88a3c57a98 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:18 +0000
-Subject: [PATCH 10/84] rockchip: rk3576: Disable USB3OTG0 U3 port early
-
-The RK3576 SoC comes with USB OTG support using a DWC3 controller with
-a USB2 PHY and a USB3 PHY (USBDP PHY).
-
-Some board designs may not use the USBDP PHY for USB3 purpose. For these
-board to use USB OTG the input clock source must change to use UTMI clk
-instead of PIPE clk.
-
-Change to always disable the USB3OTG0 U3 port early and leave it to the
-USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
-in the board device tree.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
-index ba5c94b4b3d..dc53941ab2f 100644
---- a/arch/arm/mach-rockchip/rk3576/rk3576.c
-+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
-@@ -29,6 +29,9 @@
- #define SGRF_DOMAIN_CON4	0x10
- #define SGRF_DOMAIN_CON5	0x14
- 
-+#define USB_GRF_BASE		0x2601E000
-+#define USB3OTG0_CON1		0x0030
-+
- const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- 	[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
- 	[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
-@@ -151,5 +154,8 @@ int arch_cpu_init(void)
- 	 */
- 	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
- 
-+	/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
-+	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
-+
- 	return 0;
- }
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0011-WIP-board-rockchip-Add-Radxa-ROCK-2A-2F.patch

@@ -1,7 +1,7 @@
-From 69af49f3e3f54baf88b09a003f33c9bcc04c2ae2 Mon Sep 17 00:00:00 2001
+From 9a7f27696bf3f19206d8a5cdbf921c62e18720e8 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 12 Mar 2025 00:13:48 +0000
-Subject: [PATCH 30/84] WIP: board: rockchip: Add Radxa ROCK 2A/2F
+Subject: [PATCH 11/51] WIP: board: rockchip: Add Radxa ROCK 2A/2F
 
 Features tested on a ROCK 2A v1.202:
 - SD-card boot
@@ -326,7 +326,7 @@ index 00000000000..b9261de460b
 +CONFIG_USB_FUNCTION_ROCKUSB=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index b88299cbba2..263291884b0 100644
+index de3aa79cb5c..c9cf3e4d2a9 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -102,6 +102,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0011-rockchip-rk3588-generic-Move-usb-nodes-to-board-dts.patch

@@ -1,90 +0,0 @@
-From 3504dae677104a8cf12d625ad628726c5b061c7b Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 21 Jul 2025 22:07:19 +0000
-Subject: [PATCH 11/84] rockchip: rk3588-generic: Move usb nodes to board dts
-
-After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes
-in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
-usb nodes for the Generic RK3588 board in the board u-boot.dtsi.
-
-Move usb related nodes from board u-boot.dtsi to main board device tree.
-
-While at it, also drop use of the usb3-phy as we only want to enable the
-usb2-phy to be compatible with as many boards as possible.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/dts/rk3588-generic-u-boot.dtsi | 18 ------------------
- arch/arm/dts/rk3588-generic.dts         | 16 ++++++++++++++++
- configs/generic-rk3588_defconfig        |  1 -
- 3 files changed, 16 insertions(+), 19 deletions(-)
-
-diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi
-index f67301d87a6..853ed58cfe5 100644
---- a/arch/arm/dts/rk3588-generic-u-boot.dtsi
-+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
-@@ -1,21 +1,3 @@
- // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- 
- #include "rk3588s-u-boot.dtsi"
--
--&u2phy0 {
--	status = "okay";
--};
--
--&u2phy0_otg {
--	status = "okay";
--};
--
--&usbdp_phy0 {
--	status = "okay";
--};
--
--&usb_host0_xhci {
--	dr_mode = "peripheral";
--	maximum-speed = "high-speed";
--	status = "okay";
--};
-diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
-index 95d757676f1..6740f9866f1 100644
---- a/arch/arm/dts/rk3588-generic.dts
-+++ b/arch/arm/dts/rk3588-generic.dts
-@@ -39,7 +39,23 @@
- 	status = "okay";
- };
- 
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
- &uart2 {
- 	pinctrl-0 = <&uart2m0_xfer>;
- 	status = "okay";
- };
-+
-+&usb_host0_xhci {
-+	dr_mode = "peripheral";
-+	maximum-speed = "high-speed";
-+	phys = <&u2phy0_otg>;
-+	phy-names = "usb2-phy";
-+	status = "okay";
-+};
-diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
-index ed2f936b324..dfa8efabe6b 100644
---- a/configs/generic-rk3588_defconfig
-+++ b/configs/generic-rk3588_defconfig
-@@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_ROCKCHIP=y
- CONFIG_PHY_ROCKCHIP_INNO_USB2=y
--CONFIG_PHY_ROCKCHIP_USBDP=y
- CONFIG_SPL_PINCTRL=y
- CONFIG_SPL_RAM=y
- CONFIG_BAUDRATE=1500000
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0012-WIP-board-rockchip-Add-ArmSoM-Sige1.patch

@@ -1,7 +1,7 @@
-From 9911469f091441d62832338bce312b3c2bab1434 Mon Sep 17 00:00:00 2001
+From 32786ea5b3d187a884bcd76f0cc4c97f6fd74434 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 12 Mar 2025 00:30:54 +0000
-Subject: [PATCH 31/84] WIP: board: rockchip: Add ArmSoM Sige1
+Subject: [PATCH 12/51] WIP: board: rockchip: Add ArmSoM Sige1
 
 Features tested on a ArmSoM Sige1 v1.1:
 - SD-card boot
@@ -122,7 +122,7 @@ index 00000000000..6061427ce94
 +CONFIG_USB_FUNCTION_ROCKUSB=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 263291884b0..d2ff8653e2a 100644
+index c9cf3e4d2a9..44e161c45fe 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -100,6 +100,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0013-WIP-board-rockchip-Add-FriendlyElec-NanoPi-Zero2.patch

@@ -1,7 +1,7 @@
-From bdd09deddc01633c4bfc3be932b8b865003211b5 Mon Sep 17 00:00:00 2001
+From e0fe0b326cfd4c78d3a276e599bdea42044a2aed Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Mon, 17 Mar 2025 00:29:24 +0000
-Subject: [PATCH 32/84] WIP: board: rockchip: Add FriendlyElec NanoPi Zero2
+Subject: [PATCH 13/51] WIP: board: rockchip: Add FriendlyElec NanoPi Zero2
 
 Features tested on a FriendlyElec NanoPi Zero2 2407:
 - SD-card boot
@@ -125,7 +125,7 @@ index 00000000000..0913f6cc195
 +CONFIG_USB_FUNCTION_ROCKUSB=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index d2ff8653e2a..1e46f2b5619 100644
+index 44e161c45fe..183ae3f0322 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0014-WIP-board-rockchip-Add-Radxa-E24C.patch

@@ -1,7 +1,7 @@
-From 4a14e69f721fbc3843c2a3e8207576bbb6133816 Mon Sep 17 00:00:00 2001
+From e9c40ab22f55543ddb519992f8ce223512ecf5ea Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 23 Jul 2025 22:25:26 +0000
-Subject: [PATCH 33/84] WIP: board: rockchip: Add Radxa E24C
+Subject: [PATCH 14/51] WIP: board: rockchip: Add Radxa E24C
 
 Features tested on a E24C v1.203 (D4E0S16):
 - SD-card boot
@@ -342,7 +342,7 @@ index b9261de460b..06cc6c3d5e7 100644
  CONFIG_USB_XHCI_HCD=y
  CONFIG_USB_EHCI_HCD=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 1e46f2b5619..4072a7b058b 100644
+index 183ae3f0322..42828cc6618 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -104,6 +104,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0015-HACK-use-usb3-host-mode-on-rock-2a.patch

@@ -1,7 +1,7 @@
-From b820293e44501010c656d7e1941f910dfc5c7c89 Mon Sep 17 00:00:00 2001
+From a4df83dfc47d9a5d7d94ebf5aa42cfb4b81965ad Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 13:11:09 +0000
-Subject: [PATCH 34/84] HACK: use usb3 host mode on rock-2a
+Subject: [PATCH 15/51] HACK: use usb3 host mode on rock-2a
 
 ---
  arch/arm/dts/rk3528-rock-2a-u-boot.dtsi | 4 ++++

projects/Rockchip/patches/u-boot/rockchip-0015-rockchip-rk3528-generic-Fix-boot-after-dts-upstream-.patch

@@ -1,44 +0,0 @@
-From 31932a9b2babf23c3c95b412bdb4af35176e1826 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:42 +0000
-Subject: [PATCH 15/84] rockchip: rk3528-generic: Fix boot after dts/upstream
- v6.16-dts merge
-
-The rk3528-generic target can no longer boot after v6.16-dts was merged
-into dts/upstream, and instead end up in a boot loop:
-
-  No serial driver found
-  resetting ...
-
-After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
-i2c+uart aliases to board files") there is no longer an alias for
-serial0 defined for the U-Boot only rk3528-generic device tree.
-
-Add a board specific aliases node that include the missing serial0 alias
-to resolve the boot issue and ensure that stdout-path = "serial0:..."
-can be resolved by U-Boot.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/dts/rk3528-generic.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
-index 3f6f0bed108..fe9e72c41cd 100644
---- a/arch/arm/dts/rk3528-generic.dts
-+++ b/arch/arm/dts/rk3528-generic.dts
-@@ -10,6 +10,11 @@
- 	model = "Generic RK3528";
- 	compatible = "rockchip,rk3528";
- 
-+	aliases {
-+		mmc0 = &sdhci;
-+		serial0 = &uart0;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial0:1500000n8";
- 	};
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0016-arm-dts-rockchip-Use-sdmmc-node-from-dts-upstream-on.patch

@@ -1,121 +0,0 @@
-From 3e100c18fe037bde5f4c08d9ff06ba68caee85d5 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:43 +0000
-Subject: [PATCH 16/84] arm: dts: rockchip: Use sdmmc node from dts/upstream on
- RK3528
-
-Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node
-from rk3528.dtsi with v6.16-dts now merged to dts/upstream.
-
-This cleanup has no intended functional change.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/dts/rk3528-generic-u-boot.dtsi    |  9 ---------
- arch/arm/dts/rk3528-generic.dts            | 12 +++++++++++-
- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi |  9 ---------
- arch/arm/dts/rk3528-u-boot.dtsi            | 18 ------------------
- 4 files changed, 11 insertions(+), 37 deletions(-)
-
-diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
-index cc830b51456..9e1fb2a7eef 100644
---- a/arch/arm/dts/rk3528-generic-u-boot.dtsi
-+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
-@@ -1,12 +1,3 @@
- // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- 
- #include "rk3528-u-boot.dtsi"
--
--&sdmmc {
--	bus-width = <4>;
--	cap-sd-highspeed;
--	disable-wp;
--	no-mmc;
--	no-sdio;
--	status = "okay";
--};
-diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
-index fe9e72c41cd..637ca03325e 100644
---- a/arch/arm/dts/rk3528-generic.dts
-+++ b/arch/arm/dts/rk3528-generic.dts
-@@ -1,6 +1,6 @@
- // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-- * Minimal generic DT for RK3528 with eMMC enabled
-+ * Minimal generic DT for RK3528 with eMMC and SD-card enabled
-  */
- 
- /dts-v1/;
-@@ -12,6 +12,7 @@
- 
- 	aliases {
- 		mmc0 = &sdhci;
-+		mmc1 = &sdmmc;
- 		serial0 = &uart0;
- 	};
- 
-@@ -30,6 +31,15 @@
- 	status = "okay";
- };
- 
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	no-mmc;
-+	no-sdio;
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0m0_xfer>;
-diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-index 1372d8f1e38..05a58c136bc 100644
---- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-@@ -5,12 +5,3 @@
- &sdhci {
- 	mmc-hs200-1_8v;
- };
--
--&sdmmc {
--	bus-width = <4>;
--	cap-mmc-highspeed;
--	cap-sd-highspeed;
--	disable-wp;
--	vmmc-supply = <&vcc_3v3>;
--	status = "okay";
--};
-diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
-index eb6a55cd5c9..a18d33b3d36 100644
---- a/arch/arm/dts/rk3528-u-boot.dtsi
-+++ b/arch/arm/dts/rk3528-u-boot.dtsi
-@@ -27,24 +27,6 @@
- 			compatible = "rockchip,rk3528-otp";
- 			reg = <0x0 0xffce0000 0x0 0x4000>;
- 		};
--
--		sdmmc: mmc@ffc30000 {
--			compatible = "rockchip,rk3528-dw-mshc",
--				     "rockchip,rk3288-dw-mshc";
--			reg = <0x0 0xffc30000 0x0 0x4000>;
--			clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
--			clock-names = "biu", "ciu";
--			fifo-depth = <0x100>;
--			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
--			max-frequency = <150000000>;
--			pinctrl-names = "default";
--			pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
--				    <&sdmmc_det>;
--			resets = <&cru SRST_H_SDMMC0>;
--			reset-names = "reset";
--			rockchip,default-sample-phase = <90>;
--			status = "disabled";
--		};
- 	};
- };
- 
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0016-rockchip-sdram-Add-rockchip_sdram_type-helper.patch

@@ -1,7 +1,7 @@
-From df76b4ebfb1fa9d600d5e28dba5c4a9a1f3b30fd Mon Sep 17 00:00:00 2001
+From 7a1532221bff00fbc5cde72203fbd2e9bbe623ff Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 20 Jul 2025 13:07:25 +0000
-Subject: [PATCH 35/84] rockchip: sdram: Add rockchip_sdram_type() helper
+Subject: [PATCH 16/51] rockchip: sdram: Add rockchip_sdram_type() helper
 
 Add a helper function based on rockchip_sdram_size() that return what
 DRAM type is used on current running board.

projects/Rockchip/patches/u-boot/rockchip-0017-arm-dts-rockchip-Set-init-microvolt-for-pwm-regulato.patch

@@ -1,35 +0,0 @@
-From 021508b653ce85a4528a63834457d5754724e4a1 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:44 +0000
-Subject: [PATCH 17/84] arm: dts: rockchip: Set init-microvolt for
- pwm-regulators on Radxa E20C
-
-Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic.
-
-Add init-microvolt props to ensure the regulators are initialized at
-the recommended power-on sequence voltage instead of at max voltage.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-index 05a58c136bc..16c47e6b9a9 100644
---- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
-@@ -5,3 +5,11 @@
- &sdhci {
- 	mmc-hs200-1_8v;
- };
-+
-+&vdd_arm {
-+	regulator-init-microvolt = <953000>;
-+};
-+
-+&vdd_logic {
-+	regulator-init-microvolt = <900000>;
-+};
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0017-rockchip-rock5b-rk3588-Add-support-for-ROCK-5B.patch

@@ -1,7 +1,7 @@
-From 0e8492adb9af36ec07969652638295b92e662840 Mon Sep 17 00:00:00 2001
+From 26a50f1661ef1d698ed4806a807130551fcf0a6a Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Mon, 14 Jul 2025 19:08:46 +0000
-Subject: [PATCH 36/84] rockchip: rock5b-rk3588: Add support for ROCK 5B+
+Subject: [PATCH 17/51] rockchip: rock5b-rk3588: Add support for ROCK 5B+
 
 Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
 code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
@@ -172,10 +172,10 @@ index 6349e879145..967cebc2054 100644
  CONFIG_SPL_DM_SEQ_ALIAS=y
  CONFIG_SPL_REGMAP=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 4072a7b058b..347c344a7c5 100644
+index 42828cc6618..dd9563d9124 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
-@@ -156,7 +156,7 @@ List of mainline supported Rockchip boards:
+@@ -159,7 +159,7 @@ List of mainline supported Rockchip boards:
       - Pine64 QuartzPro64 (quartzpro64-rk3588)
       - Radxa ROCK 5 ITX (rock-5-itx-rk3588)
       - Radxa ROCK 5A (rock5a-rk3588s)

projects/Rockchip/patches/u-boot/rockchip-0018-rockchip-rk3528-Disable-USB3OTG-U3-port-early.patch

@@ -1,48 +0,0 @@
-From 95e59308dcc7a38811241ccee900c22d151ff507 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:45 +0000
-Subject: [PATCH 18/84] rockchip: rk3528: Disable USB3OTG U3 port early
-
-The RK3528 SoC comes with USB OTG support using a DWC3 controller with
-a USB2 PHY and a USB3 PHY (COMBPHY).
-
-Some board designs may not use the COMBPHY for USB3 purpose. For these
-board to use USB OTG the input clock source must change to use UTMI clk
-instead of PIPE clk.
-
-Change to always disable the USB3OTG U3 port early and leave it to the
-COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
-the board device tree.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
-index 4892ff6ba9d..f9bfc445b85 100644
---- a/arch/arm/mach-rockchip/rk3528/rk3528.c
-+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
-@@ -9,6 +9,9 @@
- #include <asm/arch-rockchip/bootrom.h>
- #include <asm/arch-rockchip/hardware.h>
- 
-+#define VPU_GRF_BASE			0xff340000
-+#define USB3OTG_CON1			0x44
-+
- #define FIREWALL_DDR_BASE		0xff2e0000
- #define FW_DDR_MST6_REG			0x58
- #define FW_DDR_MST7_REG			0x5c
-@@ -69,6 +72,9 @@ int arch_cpu_init(void)
- 	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
- 	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
- 
-+	/* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
-+	writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
-+
- 	return 0;
- }
- 
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0018-spi-rockchip_sfc-Support-sclk_x2-version.patch

@@ -1,7 +1,7 @@
-From 113b2c01405d21703c15e34b56eb61520f3adccc Mon Sep 17 00:00:00 2001
+From aa575e20b0ac6032b0628553638dd2c4cb54b3c6 Mon Sep 17 00:00:00 2001
 From: Jon Lin <jon.lin@rock-chips.com>
 Date: Fri, 11 Jul 2025 23:06:03 +0000
-Subject: [PATCH 48/84] spi: rockchip_sfc: Support sclk_x2 version
+Subject: [PATCH 18/51] spi: rockchip_sfc: Support sclk_x2 version
 
 SFC after version 8 supports dtr mode, so the IO is the binary output of
 the controller clock.

projects/Rockchip/patches/u-boot/rockchip-0019-rockchip-clk-clk_rk3528-Add-dummy-CLK_REF_PCIE_INNER.patch

@@ -1,29 +0,0 @@
-From 257c7fd65c9e070089127b1ca17a49e5a349c863 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:46 +0000
-Subject: [PATCH 19/84] rockchip: clk: clk_rk3528: Add dummy
- CLK_REF_PCIE_INNER_PHY support
-
-Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
-the phy-rockchip-naneng-combphy driver on RK3528.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/clk/rockchip/clk_rk3528.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
-index 06f20895acc..d58557ff56d 100644
---- a/drivers/clk/rockchip/clk_rk3528.c
-+++ b/drivers/clk/rockchip/clk_rk3528.c
-@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
- 	/* Might occur in cru assigned-clocks, can be ignored here */
- 	case ACLK_BUS_VOPGL_ROOT:
- 	case BCLK_EMMC:
-+	case CLK_REF_PCIE_INNER_PHY:
- 	case XIN_OSC0_DIV:
- 		ret = 0;
- 		break;
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0019-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch

@@ -1,7 +1,7 @@
-From 8c261270d150b57c3094f16cfe8abc48396bcf69 Mon Sep 17 00:00:00 2001
+From 4a98c5fe68ae303bb7d0f21a52432e016da30e2a Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 23:06:04 +0000
-Subject: [PATCH 49/84] rockchip: spl: Add a read_brom_bootsource_id() helper
+Subject: [PATCH 19/51] rockchip: spl: Add a read_brom_bootsource_id() helper
 
 The bootsource ids reported by BootROM of RK3576 for e.g. SPI NOR and
 USB differs slightly compared to prior SoCs:

projects/Rockchip/patches/u-boot/rockchip-0020-rockchip-rk3576-Add-SPI-Flash-boot-support.patch

@@ -1,7 +1,7 @@
-From de7ac8d5909a3153ae9513eaba23266bd4771a3b Mon Sep 17 00:00:00 2001
+From 6d9a84704bb84e86f87efec0f70973b0ee3b4bed Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 23:06:05 +0000
-Subject: [PATCH 50/84] rockchip: rk3576: Add SPI Flash boot support
+Subject: [PATCH 20/51] rockchip: rk3576: Add SPI Flash boot support
 
 The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
 differs slightly compared to prior SoCs:

projects/Rockchip/patches/u-boot/rockchip-0020-usb-dwc3-generic-Use-combined-glue-and-ctrl-node-for.patch

@@ -1,31 +0,0 @@
-From f01c443ad30c51d9ed055aa30e0a5cba864d2610 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:47 +0000
-Subject: [PATCH 20/84] usb: dwc3-generic: Use combined glue and ctrl node for
- RK3528
-
-Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single
-node to represent the glue and ctrl for USB 3.0.
-
-Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/usb/dwc3/dwc3-generic.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
-index 3cda2b74b7e..6b2016c0cd3 100644
---- a/drivers/usb/dwc3/dwc3-generic.c
-+++ b/drivers/usb/dwc3/dwc3-generic.c
-@@ -698,6 +698,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
- 	{ .compatible = "ti,am654-dwc3" },
- 	{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "rockchip,rk3399-dwc3" },
-+	{ .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0021-board-rockchip-Add-Radxa-ROCK-4D.patch

@@ -1,7 +1,7 @@
-From c2f38fb0dd818b73ba80b32304a9cbef9d442308 Mon Sep 17 00:00:00 2001
+From 871d420f2f2a0270207b42e17a7525ca8b7ac12d Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 23:06:06 +0000
-Subject: [PATCH 51/84] board: rockchip: Add Radxa ROCK 4D
+Subject: [PATCH 21/51] board: rockchip: Add Radxa ROCK 4D
 
 The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
 numerous top-tier functions, features, and expansion options.
@@ -141,7 +141,7 @@ index 00000000000..140a3e0ccd8
 +CONFIG_USB_DWC3_GENERIC=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index e50dde2ccb1..97266d370bf 100644
+index dd9563d9124..2b902002f66 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0021-phy-rockchip-naneng-combphy-Add-support-for-RK3528.patch

@@ -1,145 +0,0 @@
-From 243470bb288e50adbe36b0d4d8c512546b4b9aa8 Mon Sep 17 00:00:00 2001
-From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
-Date: Wed, 30 Jul 2025 23:52:48 +0000
-Subject: [PATCH 21/84] phy: rockchip: naneng-combphy: Add support for RK3528
-
-Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.
-
-Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
-
-Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- .../rockchip/phy-rockchip-naneng-combphy.c    | 102 ++++++++++++++++++
- 1 file changed, 102 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index 81195de60bc..432a8f8e03a 100644
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg {
- 	struct combphy_reg pipe_rxterm_set;
- 	struct combphy_reg pipe_txelec_set;
- 	struct combphy_reg pipe_txcomp_set;
-+	struct combphy_reg pipe_clk_24m;
- 	struct combphy_reg pipe_clk_25m;
- 	struct combphy_reg pipe_clk_100m;
- 	struct combphy_reg pipe_phymode_sel;
-@@ -245,6 +246,103 @@ static int rockchip_combphy_probe(struct udevice *udev)
- 	return rockchip_combphy_parse_dt(udev, priv);
- }
- 
-+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
-+{
-+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-+	u32 val;
-+
-+	switch (priv->mode) {
-+	case PHY_TYPE_PCIE:
-+		/* Set SSC downward spread spectrum */
-+		val = readl(priv->mmio + 0x18);
-+		val &= ~GENMASK(5, 4);
-+		val |= 0x01 << 4;
-+		writel(val, priv->mmio + 0x18);
-+
-+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
-+		break;
-+	case PHY_TYPE_USB3:
-+		/* Set SSC downward spread spectrum */
-+		val = readl(priv->mmio + 0x18);
-+		val &= ~GENMASK(5, 4);
-+		val |= 0x01 << 4;
-+		writel(val, priv->mmio + 0x18);
-+
-+		/* Enable adaptive CTLE for USB3.0 Rx */
-+		val = readl(priv->mmio + 0x200);
-+		val &= ~GENMASK(17, 17);
-+		val |= 0x01 << 17;
-+		writel(val, priv->mmio + 0x200);
-+
-+		/* Set Rx squelch input filler bandwidth */
-+		val = readl(priv->mmio + 0x20c);
-+		val &= ~GENMASK(2, 0);
-+		val |= 0x06;
-+		writel(val, priv->mmio + 0x20c);
-+
-+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
-+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
-+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
-+		param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
-+		break;
-+	default:
-+		dev_err(priv->dev, "incompatible PHY type\n");
-+		return -EINVAL;
-+	}
-+
-+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
-+
-+	if (priv->mode == PHY_TYPE_PCIE) {
-+		/* PLL KVCO tuning fine */
-+		val = readl(priv->mmio + 0x18);
-+		val &= ~(0x7 << 10);
-+		val |= 0x2 << 10;
-+		writel(val, priv->mmio + 0x18);
-+
-+		/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
-+		val = readl(priv->mmio + 0x108);
-+		val &= ~(0x7f7);
-+		val |= 0x4f0;
-+		writel(val, priv->mmio + 0x108);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
-+	/* pipe-phy-grf */
-+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
-+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
-+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
-+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
-+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
-+	.pipe_clk_24m		= { 0x0004, 14, 13, 0x00, 0x00 },
-+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
-+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
-+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
-+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
-+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
-+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
-+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x110 },
-+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x00 },
-+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x101 },
-+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
-+	/* pipe-grf */
-+	.u3otg0_port_en		= { 0x0044, 15, 0, 0x0181, 0x1100 },
-+};
-+
-+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
-+	.num_phys = 1,
-+	.phy_ids = {
-+		0xffdc0000,
-+	},
-+	.grfcfg		= &rk3528_combphy_grfcfgs,
-+	.combphy_cfg	= rk3528_combphy_cfg,
-+};
-+
- static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
- {
- 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-@@ -503,6 +601,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
- };
- 
- static const struct udevice_id rockchip_combphy_ids[] = {
-+	{
-+		.compatible = "rockchip,rk3528-naneng-combphy",
-+		.data = (ulong)&rk3528_combphy_cfgs
-+	},
- 	{
- 		.compatible = "rockchip,rk3568-naneng-combphy",
- 		.data = (ulong)&rk3568_combphy_cfgs
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0022-rockchip-rk3528-radxa-e20c-Enable-USB-gadget-Kconfig.patch

@@ -1,61 +0,0 @@
-From 5dff95a52ade3b461fab6608786ac92e8ac5a47f Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 30 Jul 2025 23:52:49 +0000
-Subject: [PATCH 22/84] rockchip: rk3528-radxa-e20c: Enable USB gadget Kconfig
- options
-
-Radxa E20C has a USB OTG Type-C port for Debug and Data.
-
-Add required Kconfig options to use USB gadget features once pending
-USB nodes finally lands in dts/upstream by a future sync.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- configs/radxa-e20c-rk3528_defconfig | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
-index f5e097f3edf..0941d1b9be8 100644
---- a/configs/radxa-e20c-rk3528_defconfig
-+++ b/configs/radxa-e20c-rk3528_defconfig
-@@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y
- CONFIG_CMD_MISC=y
- CONFIG_CMD_MMC=y
- CONFIG_CMD_USB=y
-+CONFIG_CMD_ROCKUSB=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
- # CONFIG_CMD_SETEXPR is not set
- CONFIG_CMD_RNG=y
- CONFIG_CMD_REGULATOR=y
-@@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
- CONFIG_BUTTON=y
- CONFIG_BUTTON_ADC=y
- CONFIG_BUTTON_GPIO=y
-+# CONFIG_USB_FUNCTION_FASTBOOT is not set
- CONFIG_ROCKCHIP_GPIO=y
- CONFIG_LED=y
- CONFIG_LED_GPIO=y
-@@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y
- CONFIG_DWC_ETH_QOS=y
- CONFIG_DWC_ETH_QOS_ROCKCHIP=y
- CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
- CONFIG_REGULATOR_PWM=y
- CONFIG_DM_REGULATOR_GPIO=y
- CONFIG_PWM_ROCKCHIP=y
-@@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000
- CONFIG_DEBUG_UART_SHIFT=2
- CONFIG_SYS_NS16550_MEM32=y
- CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
- CONFIG_USB_EHCI_HCD=y
- CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_USB_FUNCTION_ROCKUSB=y
- CONFIG_ERRNO_STR=y
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0022-rockchip-spl-boot-order-Defer-probe-of-boot-device.patch

@@ -1,7 +1,7 @@
-From f2102f6d2743b6db7a35a0082326bf39b5fd16e5 Mon Sep 17 00:00:00 2001
+From e4c235bb6563aba6cc654e62c46ca980d07e0dc8 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sat, 12 Jul 2025 21:12:29 +0000
-Subject: [PATCH 52/84] rockchip: spl-boot-order: Defer probe of boot device
+Subject: [PATCH 22/51] rockchip: spl-boot-order: Defer probe of boot device
 
 Boot devices are being probed when SPL boot order is determined. This
 may delay boot slightly and can prevent booting from SPI Flash on boards

projects/Rockchip/patches/u-boot/rockchip-0023-rockchip-Ensure-env-in-SPI-Flash-can-work-correctly.patch

@@ -1,7 +1,7 @@
-From eb0eb85a065095685056da32409bbcbbe2fb5dd4 Mon Sep 17 00:00:00 2001
+From 49a0d7e854e126698b1ca9cfae94feaabd94a36d Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sat, 12 Jul 2025 21:27:07 +0000
-Subject: [PATCH 53/84] rockchip: Ensure env in SPI Flash can work correctly
+Subject: [PATCH 23/51] rockchip: Ensure env in SPI Flash can work correctly
 
 Ensure that the spi/sfc node for SPI flash is aviliable during pre-reloc
 phase so that env can successfully be loaded from SPI Flash.

projects/Rockchip/patches/u-boot/rockchip-0024-clk-px30-Allow-use-of-GPU-and-WIFI_PMU-in-assigned-c.patch

@@ -1,7 +1,7 @@
-From 1d9809d479e99125850b2eadbbca633435ea273f Mon Sep 17 00:00:00 2001
+From 9cfd4e04b148bb5ccf62ab0acdaef806cccc166d Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:49 +0000
-Subject: [PATCH 55/84] clk: px30: Allow use of GPU and WIFI_PMU in
+Subject: [PATCH 24/51] clk: px30: Allow use of GPU and WIFI_PMU in
  assigned-clocks
 
 Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to

projects/Rockchip/patches/u-boot/rockchip-0025-rockchip-odroid-go2-Remove-cru-assigned-clocks-overr.patch

@@ -1,7 +1,7 @@
-From aa6ea252bf5c82e4b277c6101569b722c756875f Mon Sep 17 00:00:00 2001
+From c95439a755f9a29692591c0147e0b0091cb7bae8 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:50 +0000
-Subject: [PATCH 56/84] rockchip: odroid-go2: Remove cru assigned-clocks
+Subject: [PATCH 25/51] rockchip: odroid-go2: Remove cru assigned-clocks
  override
 
 Remove the cru assigned-clocks override now that SCLK_GPU is supported

projects/Rockchip/patches/u-boot/rockchip-0026-rockchip-odroid-go2-Remove-u-boot.dtsi-props-already.patch

@@ -1,7 +1,7 @@
-From 82df30c64326c27218bbefc4f4b3ce24e07efc28 Mon Sep 17 00:00:00 2001
+From 0b97cab93001fe399f114a09004ef6f38da22d63 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:51 +0000
-Subject: [PATCH 57/84] rockchip: odroid-go2: Remove u-boot.dtsi props already
+Subject: [PATCH 26/51] rockchip: odroid-go2: Remove u-boot.dtsi props already
  defined
 
 DTs from dts/upstream already contain aliases for i2c, mmc and serial.

projects/Rockchip/patches/u-boot/rockchip-0027-rockchip-odroid-go2-Use-appropriate-bootph-props.patch

@@ -1,7 +1,7 @@
-From 7f9f8ec3bf764a6475b923822b6f7b1951532293 Mon Sep 17 00:00:00 2001
+From ec6d1722325780fb2b7ca6a963288743f20e9a8c Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:52 +0000
-Subject: [PATCH 58/84] rockchip: odroid-go2: Use appropriate bootph props
+Subject: [PATCH 27/51] rockchip: odroid-go2: Use appropriate bootph props
 
 GPIO devices are needed in U-Boot proper phase, sdmmc and sfc devices
 are needed in SPL and pre-reloc phase.

projects/Rockchip/patches/u-boot/rockchip-0028-rockchip-odroid-go2-Move-SoC-common-overrides-into-a.patch

@@ -1,7 +1,7 @@
-From fe2785fc50dd69aefa6efb9acae0b8f51878f43d Mon Sep 17 00:00:00 2001
+From d19a9805b702f7a380292f4341cbae8e9a48c2b7 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:53 +0000
-Subject: [PATCH 59/84] rockchip: odroid-go2: Move SoC common overrides into a
+Subject: [PATCH 28/51] rockchip: odroid-go2: Move SoC common overrides into a
  SoC u-boot.dtsi
 
 Add a new common rk3326-u-boot.dtsi and move the SoC common overrides

projects/Rockchip/patches/u-boot/rockchip-0029-rockchip-odroid-go2-Remove-unsupported-Kconfig-optio.patch

@@ -1,7 +1,7 @@
-From 467deac3ad081c7d8b960c8df04ca4a575073c08 Mon Sep 17 00:00:00 2001
+From d6233cc52c43a601df804cefcefd51daacd22346 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:54 +0000
-Subject: [PATCH 60/84] rockchip: odroid-go2: Remove unsupported Kconfig
+Subject: [PATCH 29/51] rockchip: odroid-go2: Remove unsupported Kconfig
  options
 
 The handheld gaming devices that this defconfig tagets does not contain

projects/Rockchip/patches/u-boot/rockchip-0030-rockchip-odroid-go2-Update-Kconfig-options-for-SPL.patch

@@ -1,7 +1,7 @@
-From e7e406bdfc634127304dbc1f70d051f46e3f683e Mon Sep 17 00:00:00 2001
+From 37b82ba73c9b8f2ae9868a8512dc5370b62d4653 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:55 +0000
-Subject: [PATCH 61/84] rockchip: odroid-go2: Update Kconfig options for SPL
+Subject: [PATCH 30/51] rockchip: odroid-go2: Update Kconfig options for SPL
 
 Drop SPL_DRIVERS_MISC, it is not needed/used on these devices.
 

projects/Rockchip/patches/u-boot/rockchip-0031-rockchip-odroid-go2-Include-pinctrl-for-sdmmc-sfc-an.patch

@@ -1,7 +1,7 @@
-From 28ee80ddeb0611760a2540168d36ff88c8cb62de Mon Sep 17 00:00:00 2001
+From 523a6585956c9971f4b78e28c195fe42381fb9d2 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:56 +0000
-Subject: [PATCH 62/84] rockchip: odroid-go2: Include pinctrl for sdmmc, sfc
+Subject: [PATCH 31/51] rockchip: odroid-go2: Include pinctrl for sdmmc, sfc
  and uart in SPL
 
 Include pinctrl nodes and props for sdmmc, sfc and uart in SPL to ensure

projects/Rockchip/patches/u-boot/rockchip-0032-rockchip-odroid-go2-Use-power-off-at-power-plug-in-e.patch

@@ -1,7 +1,7 @@
-From 1f53e8b192440fc37144acc6469fae4f839ff2f0 Mon Sep 17 00:00:00 2001
+From 21dd4189ca39e4276a69fc2292a9858cee6f51ff Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:57 +0000
-Subject: [PATCH 63/84] rockchip: odroid-go2: Use power off at power plug-in
+Subject: [PATCH 32/51] rockchip: odroid-go2: Use power off at power plug-in
  event
 
 Include the RK817 PMIC in SPL and enable Kconfig options to power off

projects/Rockchip/patches/u-boot/rockchip-0033-rockchip-odroid-go2-Add-support-for-SPI-flash-boot.patch

@@ -1,7 +1,7 @@
-From 6fb5e32dff040ea7ee9991009764007ed760016d Mon Sep 17 00:00:00 2001
+From a2f1cfb18ca139dce0b760581f8769522a53506f Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:58 +0000
-Subject: [PATCH 64/84] rockchip: odroid-go2: Add support for SPI flash boot
+Subject: [PATCH 33/51] rockchip: odroid-go2: Add support for SPI flash boot
 
 The ODROID GO2 devices come with onboard SPI flash, add support for
 using the SPI flash.

projects/Rockchip/patches/u-boot/rockchip-0034-rockchip-odroid-go2-Select-board-FDT-from-FIT-in-SPL.patch

@@ -1,7 +1,7 @@
-From 01c2dbb5ca0d85541a3261c06abb65ef326fed85 Mon Sep 17 00:00:00 2001
+From 91b9e02a41ae9e41fa6d05281cb79af5f58f19be Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:33:59 +0000
-Subject: [PATCH 65/84] rockchip: odroid-go2: Select board FDT from FIT in SPL
+Subject: [PATCH 34/51] rockchip: odroid-go2: Select board FDT from FIT in SPL
 
 Include FDTs for all three board variants in the FIT image and adjust
 the board selection code to use correct FDT in U-Boot proper.

projects/Rockchip/patches/u-boot/rockchip-0035-rockchip-odroid-go2-Use-env-from-same-storage-FIT-wa.patch

@@ -1,7 +1,7 @@
-From d7124db56d3addd0a7ef6aa5741003a24ec55f7a Mon Sep 17 00:00:00 2001
+From 7277465cbe51e0bad8f6301625dbcac817c9e9b4 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:00 +0000
-Subject: [PATCH 66/84] rockchip: odroid-go2: Use env from same storage FIT was
+Subject: [PATCH 35/51] rockchip: odroid-go2: Use env from same storage FIT was
  loaded from
 
 Change to dynamically select what storage media to use for the U-Boot

projects/Rockchip/patches/u-boot/rockchip-0036-rockchip-odroid-go2-Enable-RockUSB-button-LED-and-RN.patch

@@ -1,7 +1,7 @@
-From 399ac4e2e05dbed42d023c38e4227263c3a97cb7 Mon Sep 17 00:00:00 2001
+From 476c60e9347488ef2fc92dab98afd9e10be68fb4 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:01 +0000
-Subject: [PATCH 67/84] rockchip: odroid-go2: Enable RockUSB, button, LED and
+Subject: [PATCH 36/51] rockchip: odroid-go2: Enable RockUSB, button, LED and
  RNG support
 
 Enable Kconfig options to support RockUSB, buttons, LEDs and RNG

projects/Rockchip/patches/u-boot/rockchip-0037-rng-rockchip_rng-Add-compatible-for-RK3576.patch

@@ -1,42 +0,0 @@
-From 90a310f17ea0f5066a957f3f4c94b7566135a1ba Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:21:17 +0000
-Subject: [PATCH 37/84] rng: rockchip_rng: Add compatible for RK3576
-
-The RK3576 SoC contains a RKRNG block that can be used to generate
-random numbers using the rockchip_rng driver.
-
-Add compatible for RK3576 to support random numbers:
-
-  => rng list
-  RNG #0 - rng@2a410000
-
-  => rng
-  00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90  6........6...=..
-  00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a  ...uk'H..b.lP.G.
-  00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a  .M.C..-..'.&.ia*
-  00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5  op..N..zZl|.C.>.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/rng/rockchip_rng.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
-index d854ea90044..8cf750e043c 100644
---- a/drivers/rng/rockchip_rng.c
-+++ b/drivers/rng/rockchip_rng.c
-@@ -393,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = {
- 		.compatible = "rockchip,rk3588-rng",
- 		.data = (ulong)&rk_trngv1_soc_data,
- 	},
-+	{
-+		.compatible = "rockchip,rk3576-rng",
-+		.data = (ulong)&rkrng_soc_data,
-+	},
- 	{
- 		.compatible = "rockchip,rkrng",
- 		.data = (ulong)&rkrng_soc_data,
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0037-rockchip-odroid-go2-Turn-on-the-blue-LED-at-boot.patch

@@ -1,7 +1,7 @@
-From 5153c47f925ee11d1407df82b2787a909a6be8e9 Mon Sep 17 00:00:00 2001
+From 35cab2f4625df7b30b461a0661eb0bb0c7629e7d Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:02 +0000
-Subject: [PATCH 68/84] rockchip: odroid-go2: Turn on the blue LED at boot
+Subject: [PATCH 37/51] rockchip: odroid-go2: Turn on the blue LED at boot
 
 Use default-state prop to ensure that the blue heartbeat LED turns on
 at boot to inticate that U-Boot proper has been reached.

projects/Rockchip/patches/u-boot/rockchip-0038-rockchip-Add-default-USB_GADGET_PRODUCT_NUM-for-RK35.patch

@@ -1,28 +0,0 @@
-From faefa832fa5e175ff2c548469dcc148b12ac9c6a Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:21:18 +0000
-Subject: [PATCH 38/84] rockchip: Add default USB_GADGET_PRODUCT_NUM for RK3576
-
-Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID
-being used by the BootROM when the device is in MASKROM mode.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/usb/gadget/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
-index 46a83141481..bab88567ea6 100644
---- a/drivers/usb/gadget/Kconfig
-+++ b/drivers/usb/gadget/Kconfig
-@@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM
- 	default 0x350a if ROCKCHIP_RK3568
- 	default 0x350b if ROCKCHIP_RK3588
- 	default 0x350c if ROCKCHIP_RK3528
-+	default 0x350e if ROCKCHIP_RK3576
- 	default 0x0
- 	help
- 	  Product ID of the USB device emulated, reported to the host device.
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0038-rockchip-odroid-go2-Enable-more-commands.patch

@@ -1,7 +1,7 @@
-From 48faf6188d73d0f83937c6e36946c2fc6b722958 Mon Sep 17 00:00:00 2001
+From 5aa466b19506ef075494d9392101ffcd8bdb11dc Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:03 +0000
-Subject: [PATCH 69/84] rockchip: odroid-go2: Enable more commands
+Subject: [PATCH 38/51] rockchip: odroid-go2: Enable more commands
 
 Enable the default commands and some more useful commands that can be
 useful to determin the state of the board from U-Boot CLI.

projects/Rockchip/patches/u-boot/rockchip-0039-board-rockchip-Add-minimal-generic-RK3576-board.patch

@@ -1,190 +0,0 @@
-From 2a37796ed7fb46db2f44ce296e9d5c15781161b3 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:21:19 +0000
-Subject: [PATCH 39/84] board: rockchip: Add minimal generic RK3576 board
-
-Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
-OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
-most RK3576 boards that follow reference board design.
-
-eMMC and SD-card boot tested on:
-- ArmSoM CM5
-- ArmSoM Sige5
-- FriendlyElec NanoPi M5
-- Luckfox Omni3576
-- Toybrick TB-RK3576D
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/rk3576-generic-u-boot.dtsi   |  3 ++
- arch/arm/dts/rk3576-generic.dts           | 63 +++++++++++++++++++++++
- arch/arm/mach-rockchip/rk3576/MAINTAINERS |  5 ++
- configs/generic-rk3576_defconfig          | 50 ++++++++++++++++++
- doc/board/rockchip/rockchip.rst           |  1 +
- 5 files changed, 122 insertions(+)
- create mode 100644 arch/arm/dts/rk3576-generic-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3576-generic.dts
- create mode 100644 arch/arm/mach-rockchip/rk3576/MAINTAINERS
- create mode 100644 configs/generic-rk3576_defconfig
-
-diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi
-new file mode 100644
-index 00000000000..632fabb6af5
---- /dev/null
-+++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3576-u-boot.dtsi"
-diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts
-new file mode 100644
-index 00000000000..123be5378d9
---- /dev/null
-+++ b/arch/arm/dts/rk3576-generic.dts
-@@ -0,0 +1,63 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include "rk3576.dtsi"
-+
-+/ {
-+	model = "Generic RK3576";
-+	compatible = "rockchip,rk3576";
-+
-+	aliases {
-+		mmc0 = &sdhci;
-+		mmc1 = &sdmmc;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:1500000n8";
-+	};
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	mmc-hs200-1_8v;
-+	no-sd;
-+	no-sdio;
-+	non-removable;
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	no-mmc;
-+	no-sdio;
-+	status = "okay";
-+};
-+
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0m0_xfer>;
-+	status = "okay";
-+};
-+
-+&usb_drd0_dwc3 {
-+	dr_mode = "peripheral";
-+	maximum-speed = "high-speed";
-+	phys = <&u2phy0_otg>;
-+	phy-names = "usb2-phy";
-+	status = "okay";
-+};
-diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-new file mode 100644
-index 00000000000..b5190c81846
---- /dev/null
-+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-@@ -0,0 +1,5 @@
-+GENERIC-RK3576
-+M:	Jonas Karlman <jonas@kwiboo.se>
-+S:	Maintained
-+F:	arch/arm/dts/rk3576-generic*
-+F:	configs/generic-rk3576_defconfig
-diff --git a/configs/generic-rk3576_defconfig b/configs/generic-rk3576_defconfig
-new file mode 100644
-index 00000000000..5e25653820c
---- /dev/null
-+++ b/configs/generic-rk3576_defconfig
-@@ -0,0 +1,50 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic"
-+CONFIG_ROCKCHIP_RK3576=y
-+CONFIG_SYS_LOAD_ADDR=0x40c00800
-+CONFIG_DEBUG_UART_BASE=0x2AD40000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_BOOTMETH_VBE is not set
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_CMD_MEMINFO=y
-+CONFIG_CMD_MEMINFO_MAP=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MISC=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_ROCKUSB=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_RNG=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+# CONFIG_OF_UPSTREAM is not set
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_NO_NET=y
-+# CONFIG_ADC is not set
-+# CONFIG_USB_FUNCTION_FASTBOOT is not set
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_SDMA=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_SYSRESET_PSCI=y
-+CONFIG_USB=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_USB_FUNCTION_ROCKUSB=y
-+CONFIG_ERRNO_STR=y
-diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 347c344a7c5..54fa941f236 100644
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -139,6 +139,7 @@ List of mainline supported Rockchip boards:
- 
- * rk3576
-      - Firefly ROC-RK3576-PC (roc-pc-rk3576)
-+     - Generic RK3576 (generic-rk3576)
- 
- * rk3588
-      - ArmSoM Sige7 (sige7-rk3588)
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0039-rockchip-odroid-go2-Add-myself-as-a-reviewer.patch

@@ -1,7 +1,7 @@
-From bb596d4d3071aef91c84098b033fe9839e69842b Mon Sep 17 00:00:00 2001
+From cccdc00c7825a3f53224a7c621398987b4a84039 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:04 +0000
-Subject: [PATCH 70/84] rockchip: odroid-go2: Add myself as a reviewer
+Subject: [PATCH 39/51] rockchip: odroid-go2: Add myself as a reviewer
 
 I have the ORDOID-GO Super variant of this board. Add myself as a
 reviewer to help review future patches targeting this device.

projects/Rockchip/patches/u-boot/rockchip-0040-arm-dts-rockchip-Include-OTP-in-U-Boot-pre-reloc-pha.patch

@@ -1,7 +1,7 @@
-From 2408339af2bb95cca72c43a51709e59a9d75cae2 Mon Sep 17 00:00:00 2001
+From 524a10fa7e649adc015768e958a8e1737221fd53 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sun, 13 Jul 2025 23:34:05 +0000
-Subject: [PATCH 71/84] arm: dts: rockchip: Include OTP in U-Boot pre-reloc
+Subject: [PATCH 40/51] arm: dts: rockchip: Include OTP in U-Boot pre-reloc
  phase for RK3326
 
 Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for

projects/Rockchip/patches/u-boot/rockchip-0040-rockchip-rk3576-Implement-checkboard-to-print-SoC-va.patch

@@ -1,88 +0,0 @@
-From 9cebb3ad5497aba16f3b2575cafe17fd9477e8f7 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:21:20 +0000
-Subject: [PATCH 40/84] rockchip: rk3576: Implement checkboard() to print SoC
- variant
-
-Implement checkboard() to print current SoC model used by a board when
-U-Boot proper is running.
-
-  U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
-
-  Model: Generic RK3576
-  SoC:   RK3576
-  DRAM:  8 GiB
-
-Information about the SoC model and variant is read from OTP.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/mach-rockchip/rk3576/rk3576.c | 48 ++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
-diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
-index dc53941ab2f..a6c2fbdc484 100644
---- a/arch/arm/mach-rockchip/rk3576/rk3576.c
-+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
-@@ -3,6 +3,10 @@
-  * Copyright (c) 2024 Rockchip Electronics Co., Ltd
-  */
- 
-+#define LOG_CATEGORY LOGC_ARCH
-+
-+#include <dm.h>
-+#include <misc.h>
- #include <asm/armv8/mmu.h>
- #include <asm/arch-rockchip/bootrom.h>
- #include <asm/arch-rockchip/hardware.h>
-@@ -159,3 +163,47 @@ int arch_cpu_init(void)
- 
- 	return 0;
- }
-+
-+#define RK3576_OTP_CPU_CODE_OFFSET		0x02
-+#define RK3576_OTP_SPECIFICATION_OFFSET		0x08
-+
-+int checkboard(void)
-+{
-+	u8 cpu_code[2], specification;
-+	struct udevice *dev;
-+	char suffix[2];
-+	int ret;
-+
-+	if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
-+		return 0;
-+
-+	ret = uclass_get_device_by_driver(UCLASS_MISC,
-+					  DM_DRIVER_GET(rockchip_otp), &dev);
-+	if (ret) {
-+		log_debug("Could not find otp device, ret=%d\n", ret);
-+		return 0;
-+	}
-+
-+	/* cpu-code: SoC model, e.g. 0x35 0x76 */
-+	ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2);
-+	if (ret < 0) {
-+		log_debug("Could not read cpu-code, ret=%d\n", ret);
-+		return 0;
-+	}
-+
-+	/* specification: SoC variant, e.g. 0xA for RK3576J */
-+	ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1);
-+	if (ret < 0) {
-+		log_debug("Could not read specification, ret=%d\n", ret);
-+		return 0;
-+	}
-+	specification &= 0x1f;
-+
-+	/* for RK3576J i.e. '@' + 0xA = 'J' */
-+	suffix[0] = specification > 1 ? '@' + specification : '\0';
-+	suffix[1] = '\0';
-+
-+	printf("SoC:   RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
-+
-+	return 0;
-+}
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0041-arm-dts-rockchip-Include-OTP-in-U-Boot-pre-reloc-pha.patch

@@ -1,39 +0,0 @@
-From 069af748f2441fac896b353b1d009d57c216a609 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:21:21 +0000
-Subject: [PATCH 41/84] arm: dts: rockchip: Include OTP in U-Boot pre-reloc
- phase for RK3576
-
-Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
-checkboard() to be able to read information about the running SoC model
-and variant from OTP and print it during boot:
-
-  U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
-
-  Model: Generic RK3576
-  SoC:   RK3576
-  DRAM:  8 GiB
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- arch/arm/dts/rk3576-u-boot.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
-index be99a48a630..fb5a107f47d 100644
---- a/arch/arm/dts/rk3576-u-boot.dtsi
-+++ b/arch/arm/dts/rk3576-u-boot.dtsi
-@@ -49,6 +49,10 @@
- 	bootph-all;
- };
- 
-+&otp {
-+	bootph-some-ram;
-+};
-+
- &pcfg_pull_none {
- 	bootph-all;
- };
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0041-rockchip-mkimage-Split-size_and_off-and-size_and_nim.patch

@@ -1,7 +1,7 @@
-From bef74902961b6ecc08b188016d7d60ca68d4efb0 Mon Sep 17 00:00:00 2001
+From 3421116bf43b5e04c2ef6e4fecde88ff886f03dd Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:27 +0000
-Subject: [PATCH 72/84] rockchip: mkimage: Split size_and_off and
+Subject: [PATCH 41/51] rockchip: mkimage: Split size_and_off and
  size_and_nimage
 
 Split 32-bit size_and_off and size_and_nimage fields of the v2 image

projects/Rockchip/patches/u-boot/rockchip-0042-rockchip-mkimage-Print-image-information-for-all-emb.patch

@@ -1,7 +1,7 @@
-From a1a3a2d00251f392274251225e266673dd3fbeca Mon Sep 17 00:00:00 2001
+From efab191eb144a44817258ef06f584241ee583235 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:28 +0000
-Subject: [PATCH 73/84] rockchip: mkimage: Print image information for all
+Subject: [PATCH 42/51] rockchip: mkimage: Print image information for all
  embedded images
 
 The v2 image format can embed up to 4 data files compared to the two

projects/Rockchip/patches/u-boot/rockchip-0042-usb-dwc3-generic-Use-combined-glue-and-ctrl-node-for.patch

@@ -1,31 +0,0 @@
-From efb11d2b75da04c2e5ddc257989881248adb9f65 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 16 Feb 2025 19:17:20 +0000
-Subject: [PATCH 42/84] usb: dwc3-generic: Use combined glue and ctrl node for
- RK3576
-
-Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single
-node to represent the glue and ctrl for USB 3.0.
-
-Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/usb/dwc3/dwc3-generic.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
-index 6b2016c0cd3..c09014aec60 100644
---- a/drivers/usb/dwc3/dwc3-generic.c
-+++ b/drivers/usb/dwc3/dwc3-generic.c
-@@ -700,6 +700,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
- 	{ .compatible = "rockchip,rk3399-dwc3" },
- 	{ .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
-+	{ .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
- 	{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
- 	{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0043-phy-rockchip-inno-usb2-Add-support-for-RK3576.patch

@@ -1,62 +0,0 @@
-From 8f79cc0dc08fe79eec426dbf15d48ff71e848749 Mon Sep 17 00:00:00 2001
-From: Frank Wang <frank.wang@rock-chips.com>
-Date: Wed, 5 Feb 2025 01:00:33 +0000
-Subject: [PATCH 43/84] phy: rockchip-inno-usb2: Add support for RK3576
-
-Add support for the USB2.0 PHYs used in the RK3576 SoC.
-
-Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
-
-Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-index a3222138b9d..4ea6600ce7f 100644
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -465,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
- 	{ /* sentinel */ }
- };
- 
-+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
-+	{
-+		.reg		= 0x0000,
-+		.clkout_ctl	= { 0x0008, 0, 0, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x0000, 1, 0, 2, 1 },
-+			}
-+		},
-+	},
-+	{
-+		.reg		= 0x2000,
-+		.clkout_ctl	= { 0x2008, 0, 0, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x2000, 1, 0, 2, 1 },
-+			}
-+		},
-+	},
-+	{ /* sentinel */ }
-+};
-+
- static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
- 	{
- 		.reg		= 0x0000,
-@@ -526,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
- 		.compatible = "rockchip,rk3568-usb2phy",
- 		.data = (ulong)&rk3568_phy_cfgs,
- 	},
-+	{
-+		.compatible = "rockchip,rk3576-usb2phy",
-+		.data = (ulong)&rk3576_phy_cfgs,
-+	},
- 	{
- 		.compatible = "rockchip,rk3588-usb2phy",
- 		.data = (ulong)&rk3588_phy_cfgs,
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0043-rockchip-mkimage-Print-boot0-and-boot1-parameters.patch

@@ -1,7 +1,7 @@
-From f7f5be20cf184817a7d26801012cc4d439064217 Mon Sep 17 00:00:00 2001
+From 37395f3e04361de2e142d242a4b00dd5cd35d54c Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:29 +0000
-Subject: [PATCH 74/84] rockchip: mkimage: Print boot0 and boot1 parameters
+Subject: [PATCH 43/51] rockchip: mkimage: Print boot0 and boot1 parameters
 
 The v2 image format embeds boot0 and boot1 parameters, the vendor tool
 boot_merger may write these parameters based on the rkboot miniall.ini

projects/Rockchip/patches/u-boot/rockchip-0044-phy-rockchip-usbdp-Add-support-for-RK3576.patch

@@ -1,62 +0,0 @@
-From c239806d4c322c24938880467e30eb1244955a73 Mon Sep 17 00:00:00 2001
-From: Frank Wang <frank.wang@rock-chips.com>
-Date: Thu, 10 Jul 2025 20:33:58 +0000
-Subject: [PATCH 44/84] phy: rockchip: usbdp: Add support for RK3576
-
-Add support for the USB3.0+DP PHY used in the RK3576 SoC.
-
-Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
-
-Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 26 +++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-index 6cfbef02b4a..cca67dd3611 100644
---- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
-+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -762,6 +762,28 @@ static const char * const rk3588_udphy_rst_l[] = {
- 	"init", "cmn", "lane", "pcs_apb", "pma_apb"
- };
- 
-+static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = {
-+	.num_phys = 1,
-+	.phy_ids = {
-+		0x2b010000,
-+	},
-+	.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
-+	.rst_list = rk3588_udphy_rst_l,
-+	.grfcfg	= {
-+		/* u2phy-grf */
-+		.bvalid_phy_con		= { 0x0010, 1, 0, 0x2, 0x3 },
-+		.bvalid_grf_con		= { 0x0000, 15, 14, 0x1, 0x3 },
-+
-+		/* usb-grf */
-+		.usb3otg0_cfg		= { 0x0030, 15, 0, 0x1100, 0x0188 },
-+
-+		/* usbdpphy-grf */
-+		.low_pwrn		= { 0x0004, 13, 13, 0, 1 },
-+		.rx_lfps		= { 0x0004, 14, 14, 0, 1 },
-+	},
-+	.combophy_init = rk3588_udphy_init,
-+};
-+
- static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
- 	.num_phys = 2,
- 	.phy_ids = {
-@@ -787,6 +809,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
- };
- 
- static const struct udevice_id rockchip_udphy_dt_match[] = {
-+	{
-+		.compatible = "rockchip,rk3576-usbdp-phy",
-+		.data = (ulong)&rk3576_udphy_cfgs
-+	},
- 	{
- 		.compatible = "rockchip,rk3588-usbdp-phy",
- 		.data = (ulong)&rk3588_udphy_cfgs
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0044-rockchip-mkimage-Add-option-to-change-image-offset-a.patch

@@ -1,7 +1,7 @@
-From d036163270cb7572898de8872c6074dbb49117d3 Mon Sep 17 00:00:00 2001
+From 45311d3682bf06ca3d05906531c1aa68d2fe0ec7 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:30 +0000
-Subject: [PATCH 75/84] rockchip: mkimage: Add option to change image offset
+Subject: [PATCH 44/51] rockchip: mkimage: Add option to change image offset
  alignment
 
 The vendor boot_merger tool support a ALIGN parameter that is used to

projects/Rockchip/patches/u-boot/rockchip-0045-rockchip-clk-clk_rk3576-Add-dummy-CLK_REF_PCIEx_PHY-.patch

@@ -1,30 +0,0 @@
-From 59e0942f5cb2c61521bf740e6fcd1270072cf65a Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:44:34 +0000
-Subject: [PATCH 45/84] rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY
- support
-
-Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
-phy-rockchip-naneng-combphy driver on RK3576.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/clk/rockchip/clk_rk3576.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
-index e84a0943a94..125b08ee832 100644
---- a/drivers/clk/rockchip/clk_rk3576.c
-+++ b/drivers/clk/rockchip/clk_rk3576.c
-@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
- 	case CLK_CPLL_DIV10:
- 	case FCLK_DDR_CM0_CORE:
- 	case ACLK_PHP_ROOT:
-+	case CLK_REF_PCIE0_PHY:
-+	case CLK_REF_PCIE1_PHY:
- 		ret = 0;
- 		break;
- #ifndef CONFIG_SPL_BUILD
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0045-rockchip-mkimage-Add-support-for-up-to-4-input-files.patch

@@ -1,7 +1,7 @@
-From 2fca780304046185284f223fd41de20a7199004e Mon Sep 17 00:00:00 2001
+From f96bb3b450a8503bce8863dbf25af1b8f5de88da Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:31 +0000
-Subject: [PATCH 76/84] rockchip: mkimage: Add support for up to 4 input files
+Subject: [PATCH 45/51] rockchip: mkimage: Add support for up to 4 input files
 
 The v2 image format can support up to 4 embedded images that can be
 loaded by the BootROM using the back-to-bootrom method.

projects/Rockchip/patches/u-boot/rockchip-0046-phy-rockchip-naneng-combphy-Add-support-for-RK3576.patch

@@ -1,183 +0,0 @@
-From cd325d4d441c7d4ee44b157b45f14f12b2f814df Mon Sep 17 00:00:00 2001
-From: Jon Lin <jon.lin@rock-chips.com>
-Date: Fri, 11 Jul 2025 22:44:35 +0000
-Subject: [PATCH 46/84] phy: rockchip: naneng-combphy: Add support for RK3576
-
-Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC.
-
-Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
-
-Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- .../rockchip/phy-rockchip-naneng-combphy.c    | 147 ++++++++++++++++++
- 1 file changed, 147 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-index 432a8f8e03a..82353ae7678 100644
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -494,6 +494,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
- 	.combphy_cfg	= rk3568_combphy_cfg,
- };
- 
-+static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
-+{
-+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-+	u32 val;
-+
-+	switch (priv->mode) {
-+	case PHY_TYPE_PCIE:
-+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
-+		break;
-+	case PHY_TYPE_USB3:
-+		/* Set SSC downward spread spectrum */
-+		val = readl(priv->mmio + (0x1f << 2));
-+		val &= ~GENMASK(5, 4);
-+		val |= 0x01 << 4;
-+		writel(val, priv->mmio + 0x7c);
-+
-+		/* Enable adaptive CTLE for USB3.0 Rx */
-+		val = readl(priv->mmio + (0x0e << 2));
-+		val &= ~GENMASK(0, 0);
-+		val |= 0x01;
-+		writel(val, priv->mmio + (0x0e << 2));
-+
-+		/* Set PLL KVCO fine tuning signals */
-+		val = readl(priv->mmio + (0x20 << 2));
-+		val &= ~(0x7 << 2);
-+		val |= 0x2 << 2;
-+		writel(val, priv->mmio + (0x20 << 2));
-+
-+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
-+		writel(0x4, priv->mmio + (0xb << 2));
-+
-+		/* Set PLL input clock divider 1/2 */
-+		val = readl(priv->mmio + (0x5 << 2));
-+		val &= ~(0x3 << 6);
-+		val |= 0x1 << 6;
-+		writel(val, priv->mmio + (0x5 << 2));
-+
-+		/* Set PLL loop divider */
-+		writel(0x32, priv->mmio + (0x11 << 2));
-+
-+		/* Set PLL KVCO to min and set PLL charge pump current to max */
-+		writel(0xf0, priv->mmio + (0xa << 2));
-+
-+		/* Set Rx squelch input filler bandwidth */
-+		writel(0x0d, priv->mmio + (0x14 << 2));
-+
-+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
-+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
-+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
-+		param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
-+		break;
-+	case PHY_TYPE_SATA:
-+		/* Enable adaptive CTLE for SATA Rx */
-+		val = readl(priv->mmio + (0x0e << 2));
-+		val &= ~GENMASK(0, 0);
-+		val |= 0x01;
-+		writel(val, priv->mmio + (0x0e << 2));
-+		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
-+		writel(0x8F, priv->mmio + (0x06 << 2));
-+
-+		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
-+		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
-+		param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
-+		break;
-+	case PHY_TYPE_SGMII:
-+	case PHY_TYPE_QSGMII:
-+	default:
-+		dev_err(priv->dev, "incompatible PHY type\n");
-+		return -EINVAL;
-+	}
-+
-+	/* 100MHz refclock signal is good */
-+	clk_set_rate(&priv->ref_clk, 100000000);
-+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
-+	if (priv->mode == PHY_TYPE_PCIE) {
-+		/* gate_tx_pck_sel length select work for L1SS */
-+		writel(0xc0, priv->mmio + 0x74);
-+
-+		/* PLL KVCO tuning fine */
-+		val = readl(priv->mmio + (0x20 << 2));
-+		val &= ~(0x7 << 2);
-+		val |= 0x2 << 2;
-+		writel(val, priv->mmio + (0x20 << 2));
-+
-+		/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
-+		writel(0x4c, priv->mmio + (0x1b << 2));
-+
-+		/* Set up su_trim: T3_P1 650mv */
-+		writel(0x90, priv->mmio + (0xa << 2));
-+		writel(0x43, priv->mmio + (0xb << 2));
-+		writel(0x88, priv->mmio + (0xc << 2));
-+		writel(0x56, priv->mmio + (0xd << 2));
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
-+	/* pipe-phy-grf */
-+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
-+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
-+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
-+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
-+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
-+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
-+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
-+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
-+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
-+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
-+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
-+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
-+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
-+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
-+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
-+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
-+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
-+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
-+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
-+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
-+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
-+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
-+	/* php-grf */
-+	.pipe_con0_for_sata	= { 0x001C, 2, 0, 0x00, 0x2 },
-+	.pipe_con1_for_sata	= { 0x0020, 2, 0, 0x00, 0x2 },
-+	.u3otg1_port_en		= { 0x0038, 15, 0, 0x0181, 0x1100 },
-+};
-+
-+static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
-+	.num_phys = 2,
-+	.phy_ids = {
-+		0x2b050000,
-+		0x2b060000,
-+	},
-+	.grfcfg		= &rk3576_combphy_grfcfgs,
-+	.combphy_cfg	= rk3576_combphy_cfg,
-+};
-+
- static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
- {
- 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-@@ -609,6 +752,10 @@ static const struct udevice_id rockchip_combphy_ids[] = {
- 		.compatible = "rockchip,rk3568-naneng-combphy",
- 		.data = (ulong)&rk3568_combphy_cfgs
- 	},
-+	{
-+		.compatible = "rockchip,rk3576-naneng-combphy",
-+		.data = (ulong)&rk3576_combphy_cfgs
-+	},
- 	{
- 		.compatible = "rockchip,rk3588-naneng-combphy",
- 		.data = (ulong)&rk3588_combphy_cfgs
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0046-rockchip-mkimage-Add-option-for-image-load-address-a.patch

@@ -1,7 +1,7 @@
-From 5dc781bf680c34a57817b8ac1ab247497253c3d7 Mon Sep 17 00:00:00 2001
+From e7044c65dc50e4fd005d7262af4f6c5536cce038 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Wed, 29 Jan 2025 22:36:32 +0000
-Subject: [PATCH 77/84] rockchip: mkimage: Add option for image load address
+Subject: [PATCH 46/51] rockchip: mkimage: Add option for image load address
  and flag
 
 The v2 image format supports defining a load address and flag for each

projects/Rockchip/patches/u-boot/rockchip-0047-WIP-rockchip-mkimage-Add-rk3576-align-and-sd-card-wo.patch

@@ -1,7 +1,7 @@
-From b07ffc8797bbd19fab705b46751957b5d2160d72 Mon Sep 17 00:00:00 2001
+From 1de2afa953309c62ad0bfd5a0efb58bc5c59e763 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Tue, 28 Jan 2025 01:30:12 +0000
-Subject: [PATCH 78/84] WIP: rockchip: mkimage: Add rk3576 align and sd-card
+Subject: [PATCH 47/51] WIP: rockchip: mkimage: Add rk3576 align and sd-card
  workaround
 
 The BootROM on RK3576 has an issue loading boot images from an SD-card.

projects/Rockchip/patches/u-boot/rockchip-0047-board-rockchip-Add-ArmSoM-Sige5.patch

@@ -1,153 +0,0 @@
-From e7ce0ba19940ca5750cf8ab420f93289e1f16417 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Fri, 11 Jul 2025 22:44:36 +0000
-Subject: [PATCH 47/84] board: rockchip: Add ArmSoM Sige5
-
-ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
-platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
-for up to 16GB of large memory. It supports 4K video encoding and
-decoding, offers rich interfaces including dual gigabit Ethernet ports,
-WiFi 6 & BT5, and various video outputs.
-
-Features tested on a ArmSoM Sige5 v1.1:
-- SD-card boot
-- eMMC boot
-- Ethernet
-- PCIe NVMe
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi | 18 ++++++
- arch/arm/mach-rockchip/rk3576/MAINTAINERS    |  6 ++
- configs/sige5-rk3576_defconfig               | 66 ++++++++++++++++++++
- doc/board/rockchip/rockchip.rst              |  1 +
- 4 files changed, 91 insertions(+)
- create mode 100644 arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
- create mode 100644 configs/sige5-rk3576_defconfig
-
-diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
-new file mode 100644
-index 00000000000..7e0530d85d1
---- /dev/null
-+++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
-@@ -0,0 +1,18 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3576-u-boot.dtsi"
-+
-+/ {
-+	aliases {
-+		mmc0 = &sdhci;
-+		mmc1 = &sdmmc;
-+	};
-+};
-+
-+&red_led {
-+	default-state = "on";
-+};
-+
-+&sdhci {
-+	cap-mmc-highspeed;
-+};
-diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-index b5190c81846..94ef74d429f 100644
---- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-@@ -3,3 +3,9 @@ M:	Jonas Karlman <jonas@kwiboo.se>
- S:	Maintained
- F:	arch/arm/dts/rk3576-generic*
- F:	configs/generic-rk3576_defconfig
-+
-+SIGE5-RK3576
-+M:	Jonas Karlman <jonas@kwiboo.se>
-+S:	Maintained
-+F:	arch/arm/dts/rk3576-armsom-sige5*
-+F:	configs/sige5-rk3576_defconfig
-diff --git a/configs/sige5-rk3576_defconfig b/configs/sige5-rk3576_defconfig
-new file mode 100644
-index 00000000000..c515e145595
---- /dev/null
-+++ b/configs/sige5-rk3576_defconfig
-@@ -0,0 +1,66 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5"
-+CONFIG_ROCKCHIP_RK3576=y
-+CONFIG_SYS_LOAD_ADDR=0x40c00800
-+CONFIG_DEBUG_UART_BASE=0x2AD40000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_CMD_MEMINFO=y
-+CONFIG_CMD_MEMINFO_MAP=y
-+CONFIG_CMD_ADC=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MISC=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_ROCKUSB=y
-+CONFIG_CMD_USB_MASS_STORAGE=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_RNG=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+# CONFIG_USB_FUNCTION_FASTBOOT is not set
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_SDMA=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_PHY_REALTEK=y
-+CONFIG_DWC_ETH_QOS=y
-+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
-+CONFIG_NVME_PCI=y
-+CONFIG_PCIE_DW_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_PHY_ROCKCHIP_USBDP=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_SYSRESET_PSCI=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_USB_FUNCTION_ROCKUSB=y
-+CONFIG_ERRNO_STR=y
-diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 54fa941f236..e50dde2ccb1 100644
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -138,6 +138,7 @@ List of mainline supported Rockchip boards:
-      - Radxa ROCK 3B (rock-3b-rk3568)
- 
- * rk3576
-+     - ArmSoM Sige5 (sige5-rk3576)
-      - Firefly ROC-RK3576-PC (roc-pc-rk3576)
-      - Generic RK3576 (generic-rk3576)
- 
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0048-HACK-rockchip-dts-upstream-use-v6.17-rockchip-dts64-.patch

@@ -1,7 +1,7 @@
-From e87a7def725875f5f036d13f5704c688fcc918ce Mon Sep 17 00:00:00 2001
+From 52da058f1cd55cc14709cadc6ac3cb1a40dc8fb4 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 10:16:13 +0000
-Subject: [PATCH 79/84] HACK: rockchip: dts/upstream: use
+Subject: [PATCH 48/51] HACK: rockchip: dts/upstream: use
  v6.17-rockchip-dts64-2 RK3576 DTs
 
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

projects/Rockchip/patches/u-boot/rockchip-0049-WIP-board-rockchip-Add-Luckfox-Omni3576.patch

@@ -1,7 +1,7 @@
-From 3523f73954d4d6194739d1cd8b0e2e9c35889741 Mon Sep 17 00:00:00 2001
+From 0bb6c3cbe39776ef5327e375a7f2b6f89593aeb0 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 11:05:55 +0000
-Subject: [PATCH 80/84] WIP: board: rockchip: Add Luckfox Omni3576
+Subject: [PATCH 49/51] WIP: board: rockchip: Add Luckfox Omni3576
 
 Features tested with a Core3576 Rev1.1 on a Omni3576 carrier board:
 - SD-card boot
@@ -124,7 +124,7 @@ index 00000000000..13ef3112f1b
 +CONFIG_USB_FUNCTION_ROCKUSB=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index 97266d370bf..e751bac9ca7 100644
+index 2b902002f66..5dff856f6f5 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0050-WIP-board-rockchip-Add-FriendlyElec-NanoPi-M5.patch

@@ -1,7 +1,7 @@
-From d337711a255fd3c6953f2a86ac242fabc5d419c2 Mon Sep 17 00:00:00 2001
+From 46589839cfb3f9be217dabf242dd2a121ff37856 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Fri, 11 Jul 2025 11:05:19 +0000
-Subject: [PATCH 81/84] WIP: board: rockchip: Add FriendlyElec NanoPi M5
+Subject: [PATCH 50/51] WIP: board: rockchip: Add FriendlyElec NanoPi M5
 
 Features tested on a NanoPi M5 2411:
 - SD-card boot
@@ -162,7 +162,7 @@ index 00000000000..28427390a62
 +CONFIG_USB_FUNCTION_ROCKUSB=y
 +CONFIG_ERRNO_STR=y
 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
-index e751bac9ca7..ffd8671bbc8 100644
+index 5dff856f6f5..03d3284c650 100644
 --- a/doc/board/rockchip/rockchip.rst
 +++ b/doc/board/rockchip/rockchip.rst
 @@ -140,6 +140,7 @@ List of mainline supported Rockchip boards:

projects/Rockchip/patches/u-boot/rockchip-0051-KNAERZCHE-rockchip-rk3288-Pick-SD-card-as-first-boot.patch

@@ -1,7 +1,7 @@
-From 8220d7fe1068fbcca2d587e1315503a70c498961 Mon Sep 17 00:00:00 2001
+From b442081dea79bfe373ea14a50ca13a8c86c67a0e Mon Sep 17 00:00:00 2001
 From: Alex Bee <knaerzche@gmail.com>
 Date: Mon, 31 Oct 2022 17:13:47 +0100
-Subject: [PATCH 84/84] KNAERZCHE: rockchip: rk3288: Pick SD card as first boot
+Subject: [PATCH 51/51] KNAERZCHE: rockchip: rk3288: Pick SD card as first boot
  device
 
 In order to be able to boot from SD card at SPL level, always check

projects/Rockchip/patches/u-boot/rockchip-0054-rockchip-px30-rk3326-Implement-checkboard-to-print-S.patch

@@ -1,167 +0,0 @@
-From 24fc7c42d539648a107ab7096d45cfdab0647707 Mon Sep 17 00:00:00 2001
-From: Quentin Schulz <quentin.schulz@cherry.de>
-Date: Tue, 10 Jun 2025 11:42:50 +0200
-Subject: [PATCH 54/84] rockchip: px30/rk3326: Implement checkboard() to print
- SoC variant
-
-This implements checkboard() to print the current SoC model used by a
-board, e.g. one of:
-
-SoC:   PX30
-SoC:   PX30S
-SoC:   PX30K
-SoC:   RK3326
-SoC:   RK3326S
-
-when U-Boot proper is running.
-
-The information is read from the OTP and also the DDR_GRF. There's no
-public information as far as I know about the layout and stored
-information on OTP but this was provided by Rockchip themselves through
-their support channel.
-
-The OTP stores the information of whether the SoC is PX30K or something
-else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
-to read some undocumented bitfield in a DDR_GRF register as done in
-vendor kernel,
-c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
-
-I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
-properly.
-
-Also add the OTP node to the pre-relocation phase of U-Boot proper so
-that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
-This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
-happens after relocation. If both are enabled, then the SoC variant will
-be printed twice in the boot log, e.g.:
-
-U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200)
-
-Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
-SoC:   PX30  <---- due to DISPLAY_BOARDINFO
-DRAM:  2 GiB
-PMIC:  RK809 (on=0x40, off=0x00)
-Core:  293 devices, 27 uclasses, devicetree: separate
-MMC:   mmc@ff370000: 1, mmc@ff390000: 0
-Loading Environment from MMC... Reading from MMC(1)... OK
-
-In:    serial@ff030000
-Out:   serial@ff030000
-Err:   serial@ff030000
-Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
-SoC:   PX30  <----- due to DISPLAY_BOARDINFO_LATE
-Net:   eth0: ethernet@ff360000
-
-Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
-Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/px30-u-boot.dtsi      |  4 ++
- arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++
- 2 files changed, 65 insertions(+)
-
-diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
-index 157d0ea6930..2f726b0aaba 100644
---- a/arch/arm/dts/px30-u-boot.dtsi
-+++ b/arch/arm/dts/px30-u-boot.dtsi
-@@ -27,6 +27,10 @@
- 	};
- };
- 
-+&otp {
-+	bootph-some-ram;
-+};
-+
- &uart2 {
- 	clock-frequency = <24000000>;
- 	bootph-all;
-diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
-index 8ce9ac561f0..5a5c119328f 100644
---- a/arch/arm/mach-rockchip/px30/px30.c
-+++ b/arch/arm/mach-rockchip/px30/px30.c
-@@ -2,10 +2,14 @@
- /*
-  * Copyright (c) 2017 Rockchip Electronics Co., Ltd
-  */
-+
-+#define LOG_CATEGORY LOGC_ARCH
-+
- #include <clk.h>
- #include <dm.h>
- #include <fdt_support.h>
- #include <init.h>
-+#include <misc.h>
- #include <spl.h>
- #include <asm/armv8/mmu.h>
- #include <asm/arch-rockchip/bootrom.h>
-@@ -15,6 +19,7 @@
- #include <asm/arch-rockchip/clock.h>
- #include <asm/arch-rockchip/cru_px30.h>
- #include <dt-bindings/clock/px30-cru.h>
-+#include <linux/bitfield.h>
- 
- const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- 	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
-@@ -442,3 +447,59 @@ void board_debug_uart_init(void)
- #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
- }
- #endif /* CONFIG_DEBUG_UART_BOARD_INIT */
-+
-+#define PX30_OTP_SPECIFICATION_OFFSET		0x06
-+
-+#define DDR_GRF_BASE_ADDR               0xff630000
-+#define DDR_GRF_CON(n)                  (0 + (n) * 4)
-+
-+int checkboard(void)
-+{
-+	struct udevice *dev;
-+	u8 specification;
-+	u32 base_soc;
-+	int ret;
-+
-+	if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
-+		return 0;
-+
-+	ret = uclass_get_device_by_driver(UCLASS_MISC,
-+					  DM_DRIVER_GET(rockchip_otp), &dev);
-+	if (ret) {
-+		log_debug("Could not find otp device, ret=%d\n", ret);
-+		return 0;
-+	}
-+
-+	/* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
-+	ret = misc_read(dev, 0, &base_soc, 4);
-+	if (ret < 0) {
-+		log_debug("Could not read specification, ret=%d\n", ret);
-+		return 0;
-+	}
-+
-+	if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
-+		log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
-+		return 0;
-+	}
-+
-+	/* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
-+	ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
-+	if (ret < 0) {
-+		log_debug("Could not read specification, ret=%d\n", ret);
-+		return 0;
-+	}
-+
-+	if (specification == 0x2b) {
-+		printf("SoC:   PX30K\n");
-+		return 0;
-+	}
-+
-+	/* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
-+	specification = FIELD_GET(GENMASK(15, 14),
-+				  readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
-+	log_debug("DDR specification is %d\n", specification);
-+	printf("SoC:   %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
-+	       specification == 0x3 ? "S" : "");
-+
-+	return 0;
-+}
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0082-FROMLIST-v1-ram-rk3328-add-ddr4-1600-sdram-timing.patch

@@ -1,250 +0,0 @@
-From 04e581a594e65a6e401bdfc7458bb8b2de3ab6f0 Mon Sep 17 00:00:00 2001
-From: Da Xue <da@libre.computer>
-Date: Tue, 10 Jun 2025 19:08:19 +0000
-Subject: [PATCH 82/84] FROMLIST(v1): ram: rk3328: add ddr4-1600 sdram timing
-
-Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
-for the ROC-3328-CC board.
-
-Signed-off-by: Da Xue <da@libre.computer>
-Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
----
- arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++
- 1 file changed, 226 insertions(+)
- create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-
-diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-new file mode 100644
-index 00000000000..9594bb42839
---- /dev/null
-+++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-@@ -0,0 +1,226 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
-+
-+&dmc {
-+	rockchip,sdram-params = <
-+		0x1
-+		0xA
-+		0x2
-+		0x1
-+		0x0
-+		0x0
-+		0x11
-+		0x0
-+		0x11
-+		0x0
-+		0
-+
-+		0x94496354
-+		0x00000000
-+		0x0000002a
-+		0x000004e2
-+		0x00000015
-+		0x0000034a
-+		0x000000ff
-+
-+		800
-+		0
-+		1
-+		0
-+		0
-+
-+		0x00000000
-+		0x43041010
-+		0x00000064
-+		0x0061008c
-+		0x000000d0
-+		0x000200c5
-+		0x000000d4
-+		0x00500000
-+		0x000000d8
-+		0x00000100
-+		0x000000dc
-+		0x03140401
-+		0x000000e0
-+		0x00000000
-+		0x000000e4
-+		0x00110000
-+		0x000000e8
-+		0x00000420
-+		0x000000ec
-+		0x00000400
-+		0x000000f4
-+		0x000f011f
-+		0x00000100
-+		0x0c0e1b0e
-+		0x00000104
-+		0x00030314
-+		0x00000108
-+		0x0506050b
-+		0x0000010c
-+		0x0040400c
-+		0x00000110
-+		0x06030307
-+		0x00000114
-+		0x04040302
-+		0x00000120
-+		0x06060b06
-+		0x00000124
-+		0x00020308
-+		0x00000180
-+		0x01000040
-+		0x00000184
-+		0x00000000
-+		0x00000190
-+		0x07040003
-+		0x00000198
-+		0x05001100
-+		0x000001a0
-+		0xc0400003
-+		0x00000240
-+		0x0600060c
-+		0x00000244
-+		0x00000201
-+		0x00000250
-+		0x00000f00
-+		0x00000490
-+		0x00000001
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+
-+		0x00000004
-+		0x0000000c
-+		0x00000028
-+		0x0000000c
-+		0x0000002c
-+		0x00000000
-+		0x00000030
-+		0x00000009
-+		0xffffffff
-+		0xffffffff
-+
-+		0x77
-+		0x88
-+		0x79
-+		0x79
-+		0x87
-+		0x97
-+		0x87
-+		0x78
-+		0x77
-+		0x78
-+		0x87
-+		0x88
-+		0x87
-+		0x87
-+		0x77
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x79
-+		0x9
-+	>;
-+};
--- 
-2.34.1
-

projects/Rockchip/patches/u-boot/rockchip-0083-FROMLIST-v1-arm64-dts-rockchip-roc-3328-cc-use-1600-.patch

@@ -1,30 +0,0 @@
-From 13151018751bf8ded0ed0148526106853a1a60ba Mon Sep 17 00:00:00 2001
-From: Da Xue <da@libre.computer>
-Date: Tue, 10 Jun 2025 19:08:20 +0000
-Subject: [PATCH 83/84] FROMLIST(v1): arm64: dts: rockchip: roc-3328-cc: use
- 1600 ddr4 timing
-
-Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
-
-Signed-off-by: Da Xue <da@libre.computer>
-Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
----
- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-index 582d6ba49b4..c47d29c59de 100644
---- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-@@ -4,7 +4,7 @@
-  */
- 
- #include "rk3328-u-boot.dtsi"
--#include "rk3328-sdram-ddr4-666.dtsi"
-+#include "rk3328-sdram-ddr4-1600.dtsi"
- 
- / {
- 	smbios {
--- 
-2.34.1
-