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49 lines
1.6 KiB
Diff
49 lines
1.6 KiB
Diff
From 95e59308dcc7a38811241ccee900c22d151ff507 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 30 Jul 2025 23:52:45 +0000
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Subject: [PATCH 18/84] rockchip: rk3528: Disable USB3OTG U3 port early
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The RK3528 SoC comes with USB OTG support using a DWC3 controller with
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a USB2 PHY and a USB3 PHY (COMBPHY).
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Some board designs may not use the COMBPHY for USB3 purpose. For these
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board to use USB OTG the input clock source must change to use UTMI clk
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instead of PIPE clk.
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Change to always disable the USB3OTG U3 port early and leave it to the
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COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
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the board device tree.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
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index 4892ff6ba9d..f9bfc445b85 100644
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--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
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+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
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@@ -9,6 +9,9 @@
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/hardware.h>
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+#define VPU_GRF_BASE 0xff340000
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+#define USB3OTG_CON1 0x44
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+
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#define FIREWALL_DDR_BASE 0xff2e0000
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#define FW_DDR_MST6_REG 0x58
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#define FW_DDR_MST7_REG 0x5c
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@@ -69,6 +72,9 @@ int arch_cpu_init(void)
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
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writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
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+ /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
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+ writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
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+
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return 0;
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}
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--
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2.34.1
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