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https://github.com/LibreELEC/LibreELEC.tv
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30 lines
970 B
Diff
30 lines
970 B
Diff
From 257c7fd65c9e070089127b1ca17a49e5a349c863 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 30 Jul 2025 23:52:46 +0000
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Subject: [PATCH 19/84] rockchip: clk: clk_rk3528: Add dummy
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CLK_REF_PCIE_INNER_PHY support
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Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
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the phy-rockchip-naneng-combphy driver on RK3528.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/clk/rockchip/clk_rk3528.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
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index 06f20895acc..d58557ff56d 100644
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--- a/drivers/clk/rockchip/clk_rk3528.c
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+++ b/drivers/clk/rockchip/clk_rk3528.c
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@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
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/* Might occur in cru assigned-clocks, can be ignored here */
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case ACLK_BUS_VOPGL_ROOT:
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case BCLK_EMMC:
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+ case CLK_REF_PCIE_INNER_PHY:
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case XIN_OSC0_DIV:
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ret = 0;
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break;
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--
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2.34.1
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