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https://github.com/LibreELEC/LibreELEC.tv
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146 lines
4.7 KiB
Diff
146 lines
4.7 KiB
Diff
From 243470bb288e50adbe36b0d4d8c512546b4b9aa8 Mon Sep 17 00:00:00 2001
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From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
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Date: Wed, 30 Jul 2025 23:52:48 +0000
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Subject: [PATCH 21/84] phy: rockchip: naneng-combphy: Add support for RK3528
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Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.
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Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
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Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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.../rockchip/phy-rockchip-naneng-combphy.c | 102 ++++++++++++++++++
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1 file changed, 102 insertions(+)
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diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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index 81195de60bc..432a8f8e03a 100644
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--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg {
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struct combphy_reg pipe_rxterm_set;
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struct combphy_reg pipe_txelec_set;
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struct combphy_reg pipe_txcomp_set;
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+ struct combphy_reg pipe_clk_24m;
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struct combphy_reg pipe_clk_25m;
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struct combphy_reg pipe_clk_100m;
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struct combphy_reg pipe_phymode_sel;
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@@ -245,6 +246,103 @@ static int rockchip_combphy_probe(struct udevice *udev)
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return rockchip_combphy_parse_dt(udev, priv);
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}
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+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
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+{
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+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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+ u32 val;
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+
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+ switch (priv->mode) {
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+ case PHY_TYPE_PCIE:
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+ /* Set SSC downward spread spectrum */
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+ val = readl(priv->mmio + 0x18);
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+ val &= ~GENMASK(5, 4);
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+ val |= 0x01 << 4;
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+ writel(val, priv->mmio + 0x18);
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+
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+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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+ break;
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+ case PHY_TYPE_USB3:
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+ /* Set SSC downward spread spectrum */
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+ val = readl(priv->mmio + 0x18);
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+ val &= ~GENMASK(5, 4);
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+ val |= 0x01 << 4;
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+ writel(val, priv->mmio + 0x18);
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+
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+ /* Enable adaptive CTLE for USB3.0 Rx */
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+ val = readl(priv->mmio + 0x200);
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+ val &= ~GENMASK(17, 17);
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+ val |= 0x01 << 17;
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+ writel(val, priv->mmio + 0x200);
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+
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+ /* Set Rx squelch input filler bandwidth */
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+ val = readl(priv->mmio + 0x20c);
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+ val &= ~GENMASK(2, 0);
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+ val |= 0x06;
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+ writel(val, priv->mmio + 0x20c);
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+
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+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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+ param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
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+ break;
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+ default:
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+ dev_err(priv->dev, "incompatible PHY type\n");
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+ return -EINVAL;
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+ }
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+
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+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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+
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+ if (priv->mode == PHY_TYPE_PCIE) {
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+ /* PLL KVCO tuning fine */
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+ val = readl(priv->mmio + 0x18);
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+ val &= ~(0x7 << 10);
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+ val |= 0x2 << 10;
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+ writel(val, priv->mmio + 0x18);
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+
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+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
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+ val = readl(priv->mmio + 0x108);
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+ val &= ~(0x7f7);
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+ val |= 0x4f0;
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+ writel(val, priv->mmio + 0x108);
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
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+ /* pipe-phy-grf */
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+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
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+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
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+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
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+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
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+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
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+ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
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+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
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+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
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+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
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+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
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+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
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+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
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+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
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+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
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+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
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+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
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+ /* pipe-grf */
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+ .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
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+};
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+
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+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
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+ .num_phys = 1,
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+ .phy_ids = {
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+ 0xffdc0000,
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+ },
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+ .grfcfg = &rk3528_combphy_grfcfgs,
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+ .combphy_cfg = rk3528_combphy_cfg,
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+};
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+
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static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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@@ -503,6 +601,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
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};
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static const struct udevice_id rockchip_combphy_ids[] = {
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+ {
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+ .compatible = "rockchip,rk3528-naneng-combphy",
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+ .data = (ulong)&rk3528_combphy_cfgs
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+ },
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{
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.compatible = "rockchip,rk3568-naneng-combphy",
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.data = (ulong)&rk3568_combphy_cfgs
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--
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2.34.1
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