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Migrate Radxa Cubie A5E to mainline 6.16 (#8447)

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* migrate u-boot and kernel to mainline

* Add patches for 6.17

* fix compile for patches addes

* Orderer patches, switch kernel config to sunxi64, recreate some patches for fix build

* Update linux-sunxi64-edge.config after pm-domain & sun55i-gmac200 activate

* enable wifi and bluetooth

* revert linux-sunxi64-edge.config

- Revert linux-sunxi64-edge.config
- Add modules: CONFIG_IOMMUFD, CONFIG_SUN50I_IOMMU, CONFIG_SUN55I_PCK600.

* drop sunxi-dev-6.14 and cleanup involved patches

* Update radxa-cubie-a5e.csc

make change proposed by igorpecovnik
This commit is contained in:
juanesf
2025-08-07 16:17:15 -04:00
committed by GitHub
parent 750d4eda7d
commit 83f33fa122
38 changed files with 2455 additions and 93902 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
config/boards/radxa-cubie-a5e.csc
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@@ -2,10 +2,10 @@
BOARD_NAME="radxa cubie a5e"
BOARDFAMILY="sun55iw3"
BOARD_MAINTAINER=""
BOOTCONFIG="radxa-a5e_defconfig"
BOOTCONFIG="radxa-cubie-a5e_defconfig"
OVERLAY_PREFIX="sun55i-a527"
#BOOT_LOGO="desktop"
KERNEL_TARGET="dev"
KERNEL_TARGET="edge"
BOOT_FDT_FILE="dtb/allwinner/sun55i-a527-radxa-a5e.dtb"
IMAGE_PARTITION_TABLE="gpt"
#IMAGE_PARTITION_TABLE="msdos"
@@ -14,9 +14,42 @@ BOOTSTART="1"
BOOTSIZE="512"
ROOTSTART="513"
function post_family_tweaks__radxa_cubie-a5e() {
display_alert "Applying wifi firmware"
pushd "$SDCARD/lib/firmware"
ln -s "aic8800/SDIO/aic8800D80" "aic8800_sdio" # use armbian-firmware
popd
PACKAGE_LIST_BOARD="rfkill bluetooth bluez bluez-tools"
# AIC8800
AIC8800_TYPE="sdio"
enable_extension "radxa-aic8800"
# AIC8800 Wireless
function post_family_tweaks_bsp__aic8800_wireless() {
display_alert "$BOARD" "Installing AIC8800 Tweaks" "info"
mkdir -p "${destination}"/etc/modprobe.d
mkdir -p "${destination}"/etc/modules-load.d
# Add wireless conf
cat > "${destination}"/etc/modprobe.d/aic8800-wireless.conf <<- EOT
options aic8800_fdrv_sdio aicwf_dbg_level=0 custregd=0 ps_on=0
#options aic8800_bsp_sdio aic_fw_path=/lib/firmware/aic8800_fw/SDIO/aic8800
EOT
# Add needed bluetooth modules
cat > "${destination}"/etc/modules-load.d/aic8800-btlpm.conf <<- EOT
hidp
rfcomm
bnep
aic8800_btlpm_sdio
EOT
# Add AIC8800 Bluetooth Service and Script
if [[ -d "$SRC/packages/bsp/aic8800" ]]; then
mkdir -p "${destination}"/etc/systemd/system
mkdir -p "${destination}"/usr/bin
cp -f "$SRC/packages/bsp/aic8800/aic-bluetooth" "${destination}"/usr/bin
chmod +x "${destination}"/usr/bin/aic-bluetooth
cp -f "$SRC/packages/bsp/aic8800/aic-bluetooth.service" "${destination}"/etc/systemd/system
fi
}
# Enable AIC8800 Bluetooth Service
function post_family_tweaks__enable_aic8800_bluetooth_service() {
display_alert "$BOARD" "Enabling AIC8800 Bluetooth Service" "info"
chroot_sdcard systemctl --no-reload enable aic-bluetooth.service
}

3
config/kernel/linux-sunxi64-edge.config
View File

@@ -2234,10 +2234,13 @@ CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=m
CONFIG_ARM_SMMU_V3=m
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_IOMMUFD=m
CONFIG_SUN50I_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
CONFIG_SUN20I_PPU=y
CONFIG_SUN50I_H6_PRCM_PPU=m
CONFIG_SUN55I_PCK600=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y

16
config/sources/families/sun55iw3.conf
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@@ -13,23 +13,21 @@ declare -g ATF_TARGET_MAP="PLAT=sun55i_a523 DEBUG=1 bl31;;build/sun55i_a523/debu
declare -g ATFBRANCH="branch:a523"
declare -g BOOTSCRIPT='boot-sun50i-next.cmd:boot.cmd'
declare -g BOOTDELAY=1
declare -g BOOTSOURCE='https://github.com/jernejsk/u-boot/'
declare -g BOOTSOURCE='https://github.com/u-boot/u-boot.git'
declare -g BOOTPATCHDIR="sunxi-dev-${BOOTPATCHDIR:-"u-boot-a523"}"
declare -g BOOTBRANCH="${BOOTBRANCH:-"branch:a523"}"
declare -g BOOTBRANCH="${BOOTBRANCH:-"branch:master"}"
declare -g BOOTENV_FILE='sunxi.txt'
declare -g UBOOT_TARGET_MAP="${UBOOT_TARGET_MAP:-BINMAN_ALLOW_MISSING=1;;u-boot-sunxi-with-spl.bin}"
declare -g OVERLAY_DIR="/boot/dtb/allwinner/overlay"
declare -g LINUXFAMILY="sun55iw3"
declare -g LINUXFAMILY="sunxi64"
case "${BRANCH}" in
dev)
declare -g KERNELSOURCE='https://github.com/apritzel/linux'
declare -g KERNELBRANCH='branch:a523-v3'
declare -g KERNEL_MAJOR_MINOR="6.14" # Major and minor versions of this kernel.
KERNELPATCHDIR="archive/sunxi-dev-${KERNEL_MAJOR_MINOR}"
edge)
declare -g KERNEL_MAJOR_MINOR="6.16" # Major and minor versions of this kernel.
declare -g KERNELBRANCH="tag:v6.16"
KERNELPATCHDIR="archive/sunxi-${KERNEL_MAJOR_MINOR}"
;;
esac
family_tweaks() {

44
patch/kernel/archive/sunxi-6.16/00-Add-leds-Radxa-Cubie-A5E.patch Normal file
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@@ -0,0 +1,44 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sat, 14 Jun 2025 19:07:52 -0400
Subject: Add leds to Radxa Cubie A5E
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 16 ++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 0f58d92a6adc..1c56306dffa1 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -18,10 +18,26 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "radxa:green:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "radxa:blue:user";
+ gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ linux,default-trigger = "default-on";
+ };
+ };
+
ext_osc32k: ext-osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "ext_osc32k";
--
Created with Armbian build tools https://github.com/armbian/build

78
patch/kernel/archive/sunxi-6.16/01-Add-wifi-to-Radxa-Cubie-A5E.patch Normal file
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@@ -0,0 +1,78 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Fri, 4 Jul 2025 15:17:54 -0400
Subject: Add wifi (mmc1) to Radxa Cubie A5E
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 ++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 1c56306dffa1..d9bbfb916090 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -11,10 +11,11 @@ / {
model = "Radxa Cubie A5E";
compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";
aliases {
ethernet0 = &gmac0;
+ ethernet2 = &sdio_wifi;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
@@ -41,10 +42,20 @@ ext_osc32k: ext-osc32k-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "ext_osc32k";
};
+ reg_3v3_wifi: 3v3-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc5v>;
+ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ enable-active-high;
+ };
+
reg_vcc5v: vcc5v {
/* board wide 5V supply from the USB-C connector */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
@@ -94,10 +105,27 @@ &mmc0 {
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
bus-width = <4>;
status = "okay";
};
+&mmc1_pins {
+ drive-strength = <40>;
+};
+
+&mmc1 {
+ bus-width = <4>;
+ vmmc-supply = <&reg_3v3_wifi>;
+ non-removable;
+ // todo: investigate why clock above 40MHz makes data errors
+ max-frequency = <35000000>;
+ status = "okay";
+
+ sdio_wifi: wifi@1 {
+ reg = <1>;
+ };
+};
+
&ohci0 {
status = "okay";
};
&ohci1 {
--
Created with Armbian build tools https://github.com/armbian/build

42
patch/kernel/archive/sunxi-6.16/02-arm64-dts-allwinner-a523-add-Mali-GPU-node.patch Normal file
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@@ -0,0 +1,42 @@
From: Mikhail Kalashnikov <iuncuim@gmail.com>
The Allwinner A523 SoC features the Mali-G57 MC1 GPU, which belongs
to the Mali Valhall (v9) family. There is a power domain specifically
for this GPU that needs to be enabled to utilize it.
To enable in a specific device, we need to enable the gpu node and specify
the “mali-supply” regulator additionally in the device tree.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index dd6fa22f9..d3528d498 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -108,6 +108,21 @@ soc {
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ gpu: gpu@1800000 {
+ compatible = "allwinner,sun55i-a523-mali",
+ "arm,mali-valhall-jm";
+ reg = <0x1800000 0x10000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ power-domains = <&pck600 PD_GPU>;
+ resets = <&ccu RST_BUS_GPU>;
+ status = "disabled";
+ };
+
pio: pinctrl@2000000 {
compatible = "allwinner,sun55i-a523-pinctrl";
reg = <0x2000000 0x800>;
--
2.50.0

57
patch/kernel/archive/sunxi-6.16/03-arm64-dts-allwinner-a523-Add-power-controller-device-nodes.patch Normal file
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@@ -0,0 +1,57 @@
From: Chen-Yu Tsai <wens@csie.org>
The A523 SoC family has two power controllers, one based on the existing
PPU, and one newer one based on ARM's PCK-600.
Add device nodes for both of them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 6f62201fd739..255e0ef98219 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -7,6 +7,8 @@
#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
#include <dt-bindings/reset/sun55i-a523-ccu.h>
#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
+#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h>
+#include <dt-bindings/power/allwinner,sun55i-a523-pck600.h>
/ {
interrupt-parent = <&gic>;
@@ -576,6 +578,14 @@ mdio0: mdio {
};
};
+ ppu: power-controller@7001400 {
+ compatible = "allwinner,sun55i-a523-ppu";
+ reg = <0x07001400 0x400>;
+ clocks = <&r_ccu CLK_BUS_R_PPU1>;
+ resets = <&r_ccu RST_BUS_R_PPU1>;
+ #power-domain-cells = <1>;
+ };
+
r_ccu: clock-controller@7010000 {
compatible = "allwinner,sun55i-a523-r-ccu";
reg = <0x7010000 0x250>;
@@ -622,6 +632,14 @@ r_i2c_pins: r-i2c-pins {
};
};
+ pck600: power-controller@7060000 {
+ compatible = "allwinner,sun55i-a523-pck-600";
+ reg = <0x07060000 0x8000>;
+ clocks = <&r_ccu CLK_BUS_R_PPU0>;
+ resets = <&r_ccu RST_BUS_R_PPU0>;
+ #power-domain-cells = <1>;
+ };
+
r_i2c0: i2c@7081400 {
compatible = "allwinner,sun55i-a523-i2c",
"allwinner,sun8i-v536-i2c",
--
2.39.5

41
patch/kernel/archive/sunxi-6.16/04-arm64-dts-allwinner-a523-Add-UART1-pins.patch Normal file
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@@ -0,0 +1,41 @@
From: Chen-Yu Tsai <wens@csie.org>
UART1 is normally used to connect to the Bluetooth side of a Broadcom
WiFi+BT combo chip. The connection uses 4 pins.
Add pinmux nodes for UART1, one for the RX/TX pins, and one for the
RTS/CTS pins.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 4839411e51cf..cf0bc39aab04 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -168,6 +168,20 @@ uart0_pb_pins: uart0-pb-pins {
allwinner,pinmux = <2>;
function = "uart0";
};
+
+ /omit-if-no-ref/
+ uart1_pins: uart1-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ allwinner,pinmux = <2>;
+ };
+
+ /omit-if-no-ref/
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ allwinner,pinmux = <2>;
+ };
};
ccu: clock-controller@2001000 {
--
2.39.5

164
patch/kernel/archive/sunxi-6.16/05-arm64-dts-allwinner-a523-Move-mmc-nodes-to-correct-position.patch Normal file
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@@ -0,0 +1,164 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sat, 5 Jul 2025 22:27:55 -0400
Subject: From: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 124 +++++-----
1 file changed, 63 insertions(+), 61 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 720580f9764c..979edfc79816 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -193,72 +193,11 @@ ccu: clock-controller@2001000 {
"iosc", "losc-fanout";
#clock-cells = <1>;
#reset-cells = <1>;
};
- mmc0: mmc@4020000 {
- compatible = "allwinner,sun55i-a523-mmc",
- "allwinner,sun20i-d1-mmc";
- reg = <0x04020000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC0>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- status = "disabled";
-
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc@4021000 {
- compatible = "allwinner,sun55i-a523-mmc",
- "allwinner,sun20i-d1-mmc";
- reg = <0x04021000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC1>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- status = "disabled";
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc@4022000 {
- compatible = "allwinner,sun55i-a523-mmc",
- "allwinner,sun20i-d1-mmc";
- reg = <0x04022000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
- clock-names = "ahb", "mmc";
- resets = <&ccu RST_BUS_MMC2>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
- status = "disabled";
-
- max-frequency = <150000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- cap-sdio-irq;
- #address-cells = <1>;
- #size-cells = <0>;
- };
wdt: watchdog@2050000 {
compatible = "allwinner,sun55i-a523-wdt";
reg = <0x2050000 0x20>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -461,10 +400,73 @@ its: msi-controller@3440000 {
#msi-cells = <1>;
dma-noncoherent;
};
};
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun55i-a523-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun55i-a523-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "disabled";
+
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun55i-a523-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04022000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ status = "disabled";
+
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
usb_otg: usb@4100000 {
compatible = "allwinner,sun55i-a523-musb",
"allwinner,sun8i-a33-musb";
reg = <0x4100000 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
--
Created with Armbian build tools https://github.com/armbian/build

59
patch/kernel/archive/sunxi-6.16/06-arm64-dts-allwinner-a523-Move-rgmii0-pins-to-correct-location.patch Normal file
View File

@@ -0,0 +1,59 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sat, 2 Aug 2025 00:22:05 -0400
Subject: Subject: From: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 20 +++++-----
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 0136ac625605..7fbba60ec76e 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -141,20 +141,10 @@ pio: pinctrl@2000000 {
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
- rgmii0_pins: rgmii0-pins {
- pins = "PH0", "PH1", "PH2", "PH3", "PH4",
- "PH5", "PH6", "PH7", "PH9", "PH10",
- "PH14", "PH15", "PH16", "PH17", "PH18";
- allwinner,pinmux = <5>;
- function = "gmac0";
- drive-strength = <40>;
- bias-disable;
- };
-
mmc0_pins: mmc0-pins {
pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5";
allwinner,pinmux = <2>;
function = "mmc0";
drive-strength = <30>;
@@ -178,10 +168,20 @@ mmc2_pins: mmc2-pins {
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
+ rgmii0_pins: rgmii0-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH9", "PH10",
+ "PH14", "PH15", "PH16", "PH17", "PH18";
+ allwinner,pinmux = <5>;
+ function = "gmac0";
+ drive-strength = <40>;
+ bias-disable;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
allwinner,pinmux = <2>;
function = "uart0";
};
--
Created with Armbian build tools https://github.com/armbian/build

29
patch/kernel/archive/sunxi-6.16/07-arm64-dts-allwinner-a527-cubie-a5e-Add-ethernet-PHY-reset-setting.patch Normal file
View File

@@ -0,0 +1,29 @@
From: Chen-Yu Tsai <wens@csie.org>
The external Ethernet PHY has a reset pin that is connected to the SoC.
It is missing from the original submission.
Add it to complete the description.
Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 8bc0f2c72a24..c57ecc420aed 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -70,6 +70,9 @@ &mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
};
};
--
2.39.5

82
patch/kernel/archive/sunxi-6.16/08-arm64-dts-allwinner-a527-cubie-a5e-Enable-second-Ethernet-port.patch Normal file
View File

@@ -0,0 +1,82 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sat, 5 Jul 2025 22:59:14 -0400
Subject: From: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 26 +++++++++-
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 76e41202ecc8..592a50436454 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -11,10 +11,11 @@ / {
model = "Radxa Cubie A5E";
compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";
aliases {
ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
ethernet2 = &sdio_wifi;
serial0 = &uart0;
};
chosen {
@@ -82,29 +83,50 @@ &ehci1 {
status = "okay";
};
&gmac0 {
phy-mode = "rgmii-id";
- phy-handle = <&ext_rgmii_phy>;
+ phy-handle = <&ext_rgmii0_phy>;
phy-supply = <&reg_cldo3>;
allwinner,tx-delay-ps = <300>;
allwinner,rx-delay-ps = <400>;
status = "okay";
};
+&gmac1 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii1_phy>;
+ phy-supply = <&reg_cldo4>;
+
+ allwinner,tx-delay-ps = <300>;
+ allwinner,rx-delay-ps = <400>;
+
+ status = "okay";
+};
+
&mdio0 {
- ext_rgmii_phy: ethernet-phy@1 {
+ ext_rgmii0_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
reset-assert-us = <10000>;
reset-deassert-us = <150000>;
};
};
+&mdio1 {
+ ext_rgmii1_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo3>;
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
bus-width = <4>;
status = "okay";
--
Created with Armbian build tools https://github.com/armbian/build

441
patch/kernel/archive/sunxi-6.16/09-arm64-dts-allwinner-t527-Add-OrangePi-4A-board.patch Normal file
View File

@@ -0,0 +1,441 @@
From: Chen-Yu Tsai <wens@csie.org>
The OrangePi 4A is a typical Raspberry Pi model B sized development
board from Xunlong designed around an Allwinner T527 SoC.
The board has the following features:
- Allwinner T527 SoC
- AXP717B + AXP323 PMICs
- Up to 4GB LPDDR4 DRAM
- micro SD slot
- optional eMMC module
- M.2 slot for PCIe 2.0 x1
- 16 MB SPI-NOR flash
- 4x USB 2.0 type-A ports (one can be used in gadget mode)
- 1x Gigabit ethernet w/ Motorcomm PHY (through yet to be supported GMAC200)
- 3.5mm audio jack via internal audio codec
- HDMI 2.0 output
- eDP, MIPI CSI (2-lane and 4-lane) and MIPI DSI (4-lane) connectors
- USB type-C port purely for power
- AP6256 (Broadcom BCM4345) WiFi 5.0 + BT 5.0
- unsoldered headers for ADC and an additional USB 2.0 host port
- 40-pin GPIO header
Add a device tree for it, enabling all peripherals currently supported.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
Changes since v1:
- Fixed regulator names for bldo3 and bldo4
- Dropped labels for aldo1, bldo3, and bldo4, which are not really used
- Added voltage constraints to aldo2, based on specifications from
schematic
- Appended "-usb-0v9" to cpusldo's regulator name
- Added comments to explain how axp323 aldo1 and dldo1 are tied together
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun55i-t527-orangepi-4a.dts | 383 ++++++++++++++++++
2 files changed, 384 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 773cc02a13d0..780aeba0f3a4 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-orangepi-4a.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
new file mode 100644
index 000000000000..ff2fd8e71e03
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
+ */
+
+/dts-v1/;
+
+#include "sun55i-a523.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "OrangePi 4A";
+ compatible = "xunlong,orangepi-4a", "allwinner,sun55i-t527";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ext_osc32k: ext-osc32k-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* PWM capable pin, but PWM isn't supported yet. */
+ led {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
+ clock-names = "ext_clock";
+ };
+
+ reg_otg_vbus: regulator-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "otg-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ gpio = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ enable-active-high;
+ };
+
+ reg_pcie_vcc3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-pcie-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc5v>;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-active-high;
+ };
+
+ reg_usb_vbus: regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ gpio = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */
+ enable-active-high;
+ };
+
+ reg_vcc5v: regulator-vcc5v {
+ /* board wide 5V supply from USB type-C port */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_cldo3>;
+ cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_dldo1_323>;
+ vqmmc-supply = <&reg_bldo1>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&reg_cldo3>;
+ vqmmc-supply = <&reg_cldo1>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <&reg_cldo3>; /* via VCC-IO */
+ vcc-pc-supply = <&reg_cldo1>;
+ vcc-pd-supply = <&reg_cldo3>;
+ vcc-pe-supply = <&reg_aldo2>;
+ vcc-pf-supply = <&reg_cldo3>; /* VCC-IO for 3.3v; VCC-MCSI for 1.8v */
+ vcc-pg-supply = <&reg_bldo1>;
+ vcc-ph-supply = <&reg_cldo3>; /* via VCC-IO */
+ vcc-pi-supply = <&reg_cldo3>;
+ vcc-pj-supply = <&reg_cldo1>;
+ vcc-pk-supply = <&reg_cldo1>;
+};
+
+&r_i2c0 {
+ status = "okay";
+
+ axp717: pmic@35 {
+ compatible = "x-powers,axp717";
+ reg = <0x35>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts-extended = <&nmi_intc 0 IRQ_TYPE_LEVEL_LOW>;
+
+ vin1-supply = <&reg_vcc5v>;
+ vin2-supply = <&reg_vcc5v>;
+ vin3-supply = <&reg_vcc5v>;
+ vin4-supply = <&reg_vcc5v>;
+ aldoin-supply = <&reg_vcc5v>;
+ bldoin-supply = <&reg_vcc5v>;
+ cldoin-supply = <&reg_vcc5v>;
+
+ regulators {
+ /* Supplies the "little" cluster (1.4 GHz cores) */
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-cpul";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <920000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1160000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vcc-dram";
+ };
+
+ reg_dcdc4: dcdc4 {
+ /* feeds 3.3V pin on GPIO header */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd-io";
+ };
+
+ aldo1 {
+ /* not actually connected */
+ regulator-name = "avdd-csi";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pe";
+ };
+
+ reg_aldo3: aldo3 {
+ /* supplies the I2C pins for this PMIC */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl-usb";
+ };
+
+ reg_aldo4: aldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pll-dxco-avcc";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg-wifi";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pm-lpddr";
+ };
+
+ bldo3 {
+ /* not actually connected */
+ regulator-name = "afvcc-csi";
+ };
+
+ bldo4 {
+ /* not actually connected */
+ regulator-name = "dvdd-csi";
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-cvp-pc-lvds-mcsi-pk-efuse-pcie-edp-1v8";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-csi";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-io-mmc-nand-pd-pi-usb";
+ };
+
+ reg_cldo4: cldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-phy1-lcd";
+ };
+
+ reg_cpusldo: cpusldo {
+ /* supplies the management core */
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd-cpus";
+ };
+ };
+ };
+
+ axp323: pmic@36 {
+ compatible = "x-powers,axp323";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ status = "okay";
+
+ vin1-supply = <&reg_vcc5v>;
+ vin2-supply = <&reg_vcc5v>;
+ vin3-supply = <&reg_vcc5v>;
+
+ regulators {
+ reg_aldo1_323: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ };
+
+ reg_dldo1_323: dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi2";
+ };
+
+ /* Supplies the "big" cluster (1.8 GHz cores) */
+ reg_dcdc1_323: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-name = "vdd-cpub";
+ };
+
+ /* DCDC2 is polyphased with DCDC1 */
+
+ /* Some RISC-V management core related voltage */
+ reg_dcdc3_323: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd-dnr";
+ };
+ };
+ };
+};
+
+&r_pio {
+/*
+ * Specifying the supply would create a circular dependency.
+ *
+ * vcc-pl-supply = <&reg_aldo3>;
+ */
+ vcc-pm-supply = <&reg_bldo2>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_aldo1_323>;
+ vddio-supply = <&reg_bldo1>;
+ device-wakeup-gpios = <&r_pio 1 3 GPIO_ACTIVE_HIGH>; /* PM3 */
+ host-wakeup-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
+ shutdown-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
+ };
+};
+
+&usb_otg {
+ /*
+ * The OTG controller is connected to one of the type-A ports.
+ * There is a regulator, controlled by a GPIO, to provide VBUS power
+ * to the port, and a VBUSDET GPIO, to detect externally provided
+ * power. But without ID or CC pins there is no real way to do a
+ * runtime role detection.
+ */
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <&reg_otg_vbus>;
+ usb0_vbus_det-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ usb1_vbus-supply = <&reg_usb_vbus>;
+ status = "okay";
+};
--
2.39.5

30
patch/kernel/archive/sunxi-6.16/10-clk-sunxi-ng-sun55i-a523-r-ccu-Add-missing-PPU0-reset.patch Normal file
View File

@@ -0,0 +1,30 @@
From: Chen-Yu Tsai <wens@csie.org>
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
index b5464d8083c8..70ce0ca0cb7d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
@@ -204,6 +204,7 @@ static struct ccu_reset_map sun55i_a523_r_ccu_resets[] = {
[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
+ [RST_BUS_R_PPU0] = { 0x1ac, BIT(16) },
};
static const struct sunxi_ccu_desc sun55i_a523_r_ccu_desc = {
--
2.39.5

134
patch/kernel/archive/sunxi-6.16/11-dt-bindings-net-sun8i-emac-Add-A523-GMAC200-compatible.patch Normal file
View File

@@ -0,0 +1,134 @@
From: Chen-Yu Tsai <wens@csie.org>
The Allwinner A523 SoC family has a second Ethernet controller, called
the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
numbering. This controller, according to BSP sources, is fully
compatible with a slightly newer version of the Synopsys DWMAC core.
The glue layer around the controller is the same as found around older
DWMAC cores on Allwinner SoCs. The only slight difference is that since
this is the second controller on the SoC, the register for the clock
delay controls is at a different offset. Last, the integration includes
a dedicated clock gate for the memory bus and the whole thing is put in
a separately controllable power domain.
Add a compatible string entry for it, and work in the requirements for
a second clock and a power domain.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
.../net/allwinner,sun8i-a83t-emac.yaml | 68 ++++++++++++++++++-
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 2ac709a4c472..1058e5af92ba 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -26,6 +26,9 @@ properties:
- allwinner,sun50i-h616-emac0
- allwinner,sun55i-a523-gmac0
- const: allwinner,sun50i-a64-emac
+ - items:
+ - const: allwinner,sun55i-a523-gmac200
+ - const: snps,dwmac-4.20a
reg:
maxItems: 1
@@ -37,14 +40,19 @@ properties:
const: macirq
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clock-names:
- const: stmmaceth
+ minItems: 1
+ maxItems: 2
phy-supply:
description: PHY regulator
+ power-domains:
+ maxItems: 1
+
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -75,6 +83,7 @@ allOf:
- allwinner,sun8i-h3-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun55i-a523-gmac200
then:
properties:
@@ -191,6 +200,31 @@ allOf:
- mdio-parent-bus
- mdio@1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun55i-a523-gmac200
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ items:
+ - const: stmmaceth
+ - const: mbus
+ required:
+ - power-domains
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: stmmaceth
+ power-domains: false
+
+
unevaluatedProperties: false
examples:
@@ -323,4 +357,34 @@ examples:
};
};
+ - |
+ ethernet@4510000 {
+ compatible = "allwinner,sun55i-a523-gmac200",
+ "snps,dwmac-4.20a";
+ reg = <0x04510000 0x10000>;
+ clocks = <&ccu 117>, <&ccu 79>;
+ clock-names = "stmmaceth", "mbus";
+ resets = <&ccu 43>;
+ reset-names = "stmmaceth";
+ interrupts = <0 47 4>;
+ interrupt-names = "macirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins>;
+ power-domains = <&pck600 4>;
+ syscon = <&syscon>;
+ phy-handle = <&ext_rgmii_phy_1>;
+ phy-mode = "rgmii-id";
+ snps,fixed-burst;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ext_rgmii_phy_1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+ };
...
--
2.39.5

76
patch/kernel/archive/sunxi-6.16/12-dt-bindings-power-Add-A523-PPU-and-PCK600-power-controllers.patch Normal file
View File

@@ -0,0 +1,76 @@
From: Chen-Yu Tsai <wens@csie.org>
The A523 PPU is likely the same kind of hardware seen on previous SoCs.
The A523 PCK600, as the name suggests, is likely a customized version
of ARM's PCK-600 power controller. Comparing the BSP driver against
ARM's PPU datasheet shows that the basic registers line up, but
Allwinner's hardware has some additional delay controls in the reserved
register range. As such it is likely not fully compatible with the
standard ARM version.
Document A523 PPU and PCK600 compatibles.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
.../bindings/power/allwinner,sun20i-d1-ppu.yaml | 2 ++
.../power/allwinner,sun55i-a523-pck600.h | 15 +++++++++++++++
.../dt-bindings/power/allwinner,sun55i-a523-ppu.h | 12 ++++++++++++
3 files changed, 29 insertions(+)
create mode 100644 include/dt-bindings/power/allwinner,sun55i-a523-pck600.h
create mode 100644 include/dt-bindings/power/allwinner,sun55i-a523-ppu.h
diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
index f578be6a3bc8..b9f550994512 100644
--- a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
+++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
@@ -18,6 +18,8 @@ properties:
enum:
- allwinner,sun20i-d1-ppu
- allwinner,sun8i-v853-ppu
+ - allwinner,sun55i-a523-ppu
+ - allwinner,sun55i-a523-pck-600
reg:
maxItems: 1
diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-pck600.h b/include/dt-bindings/power/allwinner,sun55i-a523-pck600.h
new file mode 100644
index 000000000000..6b3d8ea7bb69
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun55i-a523-pck600.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_
+#define _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_
+
+#define PD_VE 0
+#define PD_GPU 1
+#define PD_VI 2
+#define PD_VO0 3
+#define PD_VO1 4
+#define PD_DE 5
+#define PD_NAND 6
+#define PD_PCIE 7
+
+#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ */
diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h
new file mode 100644
index 000000000000..bc9aba73c19a
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_
+#define _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_
+
+#define PD_DSP 0
+#define PD_NPU 1
+#define PD_AUDIO 2
+#define PD_SRAM 3
+#define PD_RISCV 4
+
+#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ */
--
2.39.5

29
patch/kernel/archive/sunxi-6.16/13-dt-bindings-reset-sun55i-a523-r-ccu-Add-missing-PPU0-reset.patch Normal file
View File

@@ -0,0 +1,29 @@
From: Chen-Yu Tsai <wens@csie.org>
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857f0 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
include/dt-bindings/reset/sun55i-a523-r-ccu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
index dd6fbb372e19..eb31ae9958d6 100644
--- a/include/dt-bindings/reset/sun55i-a523-r-ccu.h
+++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
@@ -21,5 +21,6 @@
#define RST_BUS_R_IR_RX 12
#define RST_BUS_R_RTC 13
#define RST_BUS_R_CPUCFG 14
+#define RST_BUS_R_PPU0 15
#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */
--
2.39.5

38
patch/kernel/archive/sunxi-6.16/14-mfd-axp20x-Set-explicit-ID-for-AXP313-regulator.patch Normal file
View File

@@ -0,0 +1,38 @@
From: Chen-Yu Tsai <wens@csie.org>
On newer boards featuring the A523 SoC, the AXP323 (related to the
AXP313) is paired with the AXP717 and serves as a secondary PMIC
providing additional regulator outputs. However the mfd cells are all
registered with PLATFORM_DEVID_NONE, which causes the regulator cells
to conflict with each other.
Commit e37ec3218870 ("mfd: axp20x: Allow multiple regulators") attempted
to fix this by switching to PLATFORM_DEVID_AUTO so that the device names
would all be different, however that broke IIO channel mapping, which is
also tied to the device names. As a result the change was later reverted.
Instead, here we attempt to make sure the AXP313/AXP323 regulator cell
does not conflict by explicitly giving it an ID number. This was
previously done for the AXP809+AXP806 pair used with the A80 SoC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/mfd/axp20x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index e9914e8a29a3..25c639b348cd 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1053,7 +1053,8 @@ static const struct mfd_cell axp152_cells[] = {
};
static struct mfd_cell axp313a_cells[] = {
- MFD_CELL_NAME("axp20x-regulator"),
+ /* AXP323 is sometimes paired with AXP717 as sub-PMIC */
+ MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
};
--
2.39.5

49
patch/kernel/archive/sunxi-6.16/15-mfd-axp20x-set-explicit-ID-for-regulator-cell-if-no-IRQ-line-is-present.patch Normal file
View File

@@ -0,0 +1,49 @@
From: Chen-Yu Tsai <wens@csie.org>
Originally an explicit ID for the AXP313/AXP323 regulator was set to
avoid a conflict with the primary AXP717 PMIC on Allwinner A523 family
boards.
This didn't entirely work since on some or all of these boards, the
interrupt line on this secondary PMIC was left unconnected, and thus
the driver would fall back to the generic "no interrupt; only regulators"
case, which didn't have the explicit ID set, thus undoing the intended
fix.
Also set an explicit ID for the regulator cell in the no IRQ generic
fall back case. This fixes the conflict for the AXP717 + AXP313/AXP323
case. For the actual single PMIC with no IRQ connected case, the ID does
not affect functionality, only the device naming of the regulator cell,
and by extension the name and path under sysfs.
Fixes: 249abf9b1e25 ("mfd: axp20x: Set explicit ID for AXP313 regulator")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
This is an alternative to
mfd: axp20x: Skip PEK on AXP313A/AXP323 if no interrupt line is available
which was deemed too fragile.
---
drivers/mfd/axp20x.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 25c639b348cd..c5f0ebae327f 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1231,9 +1231,8 @@ static const struct mfd_cell axp15060_cells[] = {
/* For boards that don't have IRQ line connected to SOC. */
static const struct mfd_cell axp_regulator_only_cells[] = {
- {
- .name = "axp20x-regulator",
- },
+ /* PMIC without IRQ line may be secondary PMIC */
+ MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
};
static int axp20x_power_off(struct sys_off_data *data)
--
2.39.5

227
patch/kernel/archive/sunxi-6.16/16-net-stmmac-Add-support-for-Allwinner-A523-GMAC200.patch Normal file
View File

@@ -0,0 +1,227 @@
From: Chen-Yu Tsai <wens@csie.org>
The Allwinner A523 SoC family has a second Ethernet controller, called
the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
numbering. This controller, according to BSP sources, is fully
compatible with a slightly newer version of the Synopsys DWMAC core.
The glue layer around the controller is the same as found around older
DWMAC cores on Allwinner SoCs. The only slight difference is that since
this is the second controller on the SoC, the register for the clock
delay controls is at a different offset. Last, the integration includes
a dedicated clock gate for the memory bus and the whole thing is put in
a separately controllable power domain.
Add a new driver for this hardware supporting the integration layer.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-sun55i.c | 161 ++++++++++++++++++
3 files changed, 174 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 67fa879b1e52..38ce9a0cfb5b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -263,6 +263,18 @@ config DWMAC_SUN8I
stmmac device driver. This driver is used for H3/A83T/A64
EMAC ethernet controller.
+config DWMAC_SUN55I
+ tristate "Allwinner sun55i GMAC200 support"
+ default ARCH_SUNXI
+ depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+ select MDIO_BUS_MUX
+ help
+ Support for Allwinner A523/T527 GMAC200 ethernet controllers.
+
+ This selects Allwinner SoC glue layer support for the
+ stmmac device driver. This driver is used for A523/T527
+ GMAC200 ethernet controller.
+
config DWMAC_THEAD
tristate "T-HEAD dwmac support"
depends on OF && (ARCH_THEAD || COMPILE_TEST)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index b591d93f8503..51e068e26ce4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o
+obj-$(CONFIG_DWMAC_SUN55I) += dwmac-sun55i.o
obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o
obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c
new file mode 100644
index 000000000000..7fadb90e3098
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer
+ *
+ * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
+ *
+ * syscon parts taken from dwmac-sun8i.c, which is
+ *
+ * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/stmmac.h>
+
+#include "stmmac.h"
+#include "stmmac_platform.h"
+
+#define SYSCON_REG 0x34
+
+/* RMII specific bits */
+#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
+/* Generic system control EMAC_CLK bits */
+#define SYSCON_ETXDC_MASK GENMASK(12, 10)
+#define SYSCON_ERXDC_MASK GENMASK(9, 5)
+/* EMAC PHY Interface Type */
+#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
+#define SYSCON_ETCS_MASK GENMASK(1, 0)
+#define SYSCON_ETCS_MII 0x0
+#define SYSCON_ETCS_EXT_GMII 0x1
+#define SYSCON_ETCS_INT_GMII 0x2
+
+#define MASK_TO_VAL(mask) ((mask) >> (__builtin_ffsll(mask) - 1))
+
+static int sun55i_gmac200_set_syscon(struct device *dev,
+ struct plat_stmmacenet_data *plat)
+{
+ struct device_node *node = dev->of_node;
+ struct regmap *regmap;
+ u32 val, reg = 0;
+
+ regmap = syscon_regmap_lookup_by_phandle(node, "syscon");
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n");
+
+ if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
+ if (val % 100) {
+ dev_err(dev, "tx-delay must be a multiple of 100\n");
+ return -EINVAL;
+ }
+ val /= 100;
+ dev_dbg(dev, "set tx-delay to %x\n", val);
+ if (val > MASK_TO_VAL(SYSCON_ETXDC_MASK))
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid TX clock delay: %d\n",
+ val);
+
+ reg |= FIELD_PREP(SYSCON_ETXDC_MASK, val);
+ }
+
+ if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
+ if (val % 100) {
+ dev_err(dev, "rx-delay must be a multiple of 100\n");
+ return -EINVAL;
+ }
+ val /= 100;
+ dev_dbg(dev, "set rx-delay to %x\n", val);
+ if (val > MASK_TO_VAL(SYSCON_ERXDC_MASK))
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid RX clock delay: %d\n",
+ val);
+
+ reg |= FIELD_PREP(SYSCON_ERXDC_MASK, val);
+ }
+
+ switch (plat->mac_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ /* default */
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ reg |= SYSCON_RMII_EN;
+ break;
+ default:
+ dev_err(dev, "Unsupported interface mode: %s",
+ phy_modes(plat->mac_interface));
+ return -EINVAL;
+ }
+
+ regmap_write(regmap, SYSCON_REG, reg);
+
+ return 0;
+}
+
+static int sun55i_gmac200_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct device *dev = &pdev->dev;
+ struct clk *clk;
+ int ret;
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return ret;
+
+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ /* BSP disables it */
+ plat_dat->flags |= STMMAC_FLAG_SPH_DISABLE;
+ plat_dat->host_dma_width = 32;
+
+ ret = sun55i_gmac200_set_syscon(dev, plat_dat);
+ if (ret)
+ return ret;
+
+ clk = devm_clk_get_enabled(dev, "mbus");
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk),
+ "Failed to get or enable MBUS clock\n");
+
+ ret = devm_regulator_get_enable_optional(dev, "phy");
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n");
+
+ return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id sun55i_gmac200_match[] = {
+ { .compatible = "allwinner,sun55i-a523-gmac200" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sun55i_gmac200_match);
+
+static struct platform_driver sun55i_gmac200_driver = {
+ .probe = sun55i_gmac200_probe,
+ .driver = {
+ .name = "sun55i-gmac200",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = sun55i_gmac200_match,
+ },
+};
+module_platform_driver(sun55i_gmac200_driver);
+
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer");
+MODULE_LICENSE("GPL");
--
2.39.5

278
patch/kernel/archive/sunxi-6.16/17-pmdomain-sunxi-add-driver-for-Allwinner-A523's PCK-600-power-controller.patch Normal file
View File

@@ -0,0 +1,278 @@
From: Chen-Yu Tsai <wens@csie.org>
Allwinner A523 family has a second power controller, named PCK-600 in
the datasheets and BSP. It is likely based on ARM's PCK-600 hardware
block, with some additional delay controls. The only documentation for
this hardware is the BSP driver. The standard registers defined in ARM's
Power Policy Unit Architecture Specification line up. Some extra delay
controls are found in the reserved range of registers.
Add a driver for this power controller. Delay control register values
and power domain names are from the BSP driver.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/pmdomain/sunxi/Kconfig | 8 +
drivers/pmdomain/sunxi/Makefile | 1 +
drivers/pmdomain/sunxi/sun55i-pck600.c | 225 +++++++++++++++++++++++++
3 files changed, 234 insertions(+)
create mode 100644 drivers/pmdomain/sunxi/sun55i-pck600.c
diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kconfig
index 43eecb3ea981..3e2b77cd9a2b 100644
--- a/drivers/pmdomain/sunxi/Kconfig
+++ b/drivers/pmdomain/sunxi/Kconfig
@@ -18,3 +18,11 @@ config SUN50I_H6_PRCM_PPU
Say y to enable the Allwinner H6/H616 PRCM power domain driver.
This is required to enable the Mali GPU in the H616 SoC, it is
optional for the H6.
+
+config SUN55I_PCK600
+ bool "Allwinner A523 PCK-600 power domain driver"
+ depends on PM
+ select PM_GENERIC_DOMAINS
+ help
+ Say y to enable the PCK-600 power domain driver. This saves power
+ when certain peripherals, such as the video engine, are idle.
diff --git a/drivers/pmdomain/sunxi/Makefile b/drivers/pmdomain/sunxi/Makefile
index c1343e123759..e344b232fc9f 100644
--- a/drivers/pmdomain/sunxi/Makefile
+++ b/drivers/pmdomain/sunxi/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SUN20I_PPU) += sun20i-ppu.o
obj-$(CONFIG_SUN50I_H6_PRCM_PPU) += sun50i-h6-prcm-ppu.o
+obj-$(CONFIG_SUN55I_PCK600) += sun55i-pck600.o
diff --git a/drivers/pmdomain/sunxi/sun55i-pck600.c b/drivers/pmdomain/sunxi/sun55i-pck600.c
new file mode 100644
index 000000000000..7248f6113665
--- /dev/null
+++ b/drivers/pmdomain/sunxi/sun55i-pck600.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Allwinner PCK-600 power domain support
+ *
+ * Copyright (c) 2025 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/dev_printk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/string_choices.h>
+
+#define PPU_PWPR 0x0
+#define PPU_PWSR 0x8
+#define PPU_DCDR0 0x170
+#define PPU_DCDR1 0x174
+
+#define PPU_PWSR_PWR_STATUS GENMASK(3, 0)
+#define PPU_POWER_MODE_ON 0x8
+#define PPU_POWER_MODE_OFF 0x0
+
+#define PPU_REG_SIZE 0x1000
+
+struct sunxi_pck600_desc {
+ const char * const *pd_names;
+ unsigned int num_domains;
+ u32 logic_power_switch0_delay_offset;
+ u32 logic_power_switch1_delay_offset;
+ u32 off2on_delay_offset;
+ u32 device_ctrl0_delay;
+ u32 device_ctrl1_delay;
+ u32 logic_power_switch0_delay;
+ u32 logic_power_switch1_delay;
+ u32 off2on_delay;
+};
+
+struct sunxi_pck600_pd {
+ struct generic_pm_domain genpd;
+ struct sunxi_pck600 *pck;
+ void __iomem *base;
+};
+
+struct sunxi_pck600 {
+ struct device *dev;
+ struct genpd_onecell_data genpd_data;
+ struct sunxi_pck600_pd pds[];
+};
+
+#define to_sunxi_pd(gpd) container_of(gpd, struct sunxi_pck600_pd, genpd)
+
+static int sunxi_pck600_pd_set_power(struct sunxi_pck600_pd *pd, bool on)
+{
+ struct sunxi_pck600 *pck = pd->pck;
+ struct generic_pm_domain *genpd = &pd->genpd;
+ int ret;
+ u32 val, reg;
+
+ val = on ? PPU_POWER_MODE_ON : PPU_POWER_MODE_OFF;
+
+ reg = readl(pd->base + PPU_PWPR);
+ FIELD_MODIFY(PPU_PWSR_PWR_STATUS, &reg, val);
+ writel(reg, pd->base + PPU_PWPR);
+
+ /* push write out to hardware */
+ reg = readl(pd->base + PPU_PWPR);
+
+ ret = readl_poll_timeout_atomic(pd->base + PPU_PWSR, reg,
+ FIELD_GET(PPU_PWSR_PWR_STATUS, reg) == val,
+ 0, 10000);
+ if (ret)
+ dev_err(pck->dev, "failed to turn domain \"%s\" %s: %d\n",
+ genpd->name, str_on_off(on), ret);
+
+ return ret;
+}
+
+static int sunxi_pck600_power_on(struct generic_pm_domain *domain)
+{
+ struct sunxi_pck600_pd *pd = to_sunxi_pd(domain);
+
+ return sunxi_pck600_pd_set_power(pd, true);
+}
+
+static int sunxi_pck600_power_off(struct generic_pm_domain *domain)
+{
+ struct sunxi_pck600_pd *pd = to_sunxi_pd(domain);
+
+ return sunxi_pck600_pd_set_power(pd, false);
+}
+
+static void sunxi_pck600_pd_setup(struct sunxi_pck600_pd *pd,
+ const struct sunxi_pck600_desc *desc)
+{
+ writel(desc->device_ctrl0_delay, pd->base + PPU_DCDR0);
+ writel(desc->device_ctrl1_delay, pd->base + PPU_DCDR1);
+ writel(desc->logic_power_switch0_delay,
+ pd->base + desc->logic_power_switch0_delay_offset);
+ writel(desc->logic_power_switch1_delay,
+ pd->base + desc->logic_power_switch1_delay_offset);
+ writel(desc->off2on_delay, pd->base + desc->off2on_delay_offset);
+}
+
+static int sunxi_pck600_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct sunxi_pck600_desc *desc;
+ struct genpd_onecell_data *genpds;
+ struct sunxi_pck600 *pck;
+ struct reset_control *rst;
+ struct clk *clk;
+ void __iomem *base;
+ int i, ret;
+
+ desc = of_device_get_match_data(dev);
+
+ pck = devm_kzalloc(dev, struct_size(pck, pds, desc->num_domains), GFP_KERNEL);
+ if (!pck)
+ return -ENOMEM;
+
+ pck->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pck);
+
+ genpds = &pck->genpd_data;
+ genpds->num_domains = desc->num_domains;
+ genpds->domains = devm_kcalloc(dev, desc->num_domains,
+ sizeof(*genpds->domains), GFP_KERNEL);
+ if (!genpds->domains)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ rst = devm_reset_control_get_exclusive_released(dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
+
+ for (i = 0; i < desc->num_domains; i++) {
+ struct sunxi_pck600_pd *pd = &pck->pds[i];
+
+ pd->genpd.name = desc->pd_names[i];
+ pd->genpd.power_off = sunxi_pck600_power_off;
+ pd->genpd.power_on = sunxi_pck600_power_on;
+ pd->base = base + PPU_REG_SIZE * i;
+
+ sunxi_pck600_pd_setup(pd, desc);
+ ret = pm_genpd_init(&pd->genpd, NULL, false);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to initialize power domain\n");
+ goto err_remove_pds;
+ }
+
+ genpds->domains[i] = &pd->genpd;
+ }
+
+ ret = of_genpd_add_provider_onecell(dev_of_node(dev), genpds);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to add PD provider\n");
+ goto err_remove_pds;
+ }
+
+ return 0;
+
+err_remove_pds:
+ for (i--; i >= 0; i--)
+ pm_genpd_remove(genpds->domains[i]);
+
+ return ret;
+}
+
+static const char * const sun55i_a523_pck600_pd_names[] = {
+ "VE", "GPU", "VI", "VO0", "VO1", "DE", "NAND", "PCIE"
+};
+
+static const struct sunxi_pck600_desc sun55i_a523_pck600_desc = {
+ .pd_names = sun55i_a523_pck600_pd_names,
+ .num_domains = ARRAY_SIZE(sun55i_a523_pck600_pd_names),
+ .logic_power_switch0_delay_offset = 0xc00,
+ .logic_power_switch1_delay_offset = 0xc04,
+ .off2on_delay_offset = 0xc10,
+ .device_ctrl0_delay = 0xffffff,
+ .device_ctrl1_delay = 0xffff,
+ .logic_power_switch0_delay = 0x8080808,
+ .logic_power_switch1_delay = 0x808,
+ .off2on_delay = 0x8
+};
+
+static const struct of_device_id sunxi_pck600_of_match[] = {
+ {
+ .compatible = "allwinner,sun55i-a523-pck-600",
+ .data = &sun55i_a523_pck600_desc,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sunxi_pck600_of_match);
+
+static struct platform_driver sunxi_pck600_driver = {
+ .probe = sunxi_pck600_probe,
+ .driver = {
+ .name = "sunxi-pck-600",
+ .of_match_table = sunxi_pck600_of_match,
+ /* Power domains cannot be removed if in use. */
+ .suppress_bind_attrs = true,
+ },
+};
+module_platform_driver(sunxi_pck600_driver);
+
+MODULE_DESCRIPTION("Allwinner PCK-600 power domain driver");
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_LICENSE("GPL");
--
2.39.5

48
patch/kernel/archive/sunxi-6.16/18-pmdomain-sunxi-sun20i-ppu-add-A523-support.patch Normal file
View File

@@ -0,0 +1,48 @@
From: Chen-Yu Tsai <wens@csie.org>
A523 has a PPU like the one in the Allwinner D1 SoC.
Add a compatible entry and a list of power domain names for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/pmdomain/sunxi/sun20i-ppu.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pmdomain/sunxi/sun20i-ppu.c b/drivers/pmdomain/sunxi/sun20i-ppu.c
index 9f002748d224..b65876a68cc1 100644
--- a/drivers/pmdomain/sunxi/sun20i-ppu.c
+++ b/drivers/pmdomain/sunxi/sun20i-ppu.c
@@ -193,6 +193,19 @@ static const struct sun20i_ppu_desc sun8i_v853_ppu_desc = {
.num_domains = ARRAY_SIZE(sun8i_v853_ppu_pd_names),
};
+static const char *const sun55i_a523_ppu_pd_names[] = {
+ "DSP",
+ "NPU",
+ "AUDIO",
+ "SRAM",
+ "RISCV",
+};
+
+static const struct sun20i_ppu_desc sun55i_a523_ppu_desc = {
+ .names = sun55i_a523_ppu_pd_names,
+ .num_domains = ARRAY_SIZE(sun55i_a523_ppu_pd_names),
+};
+
static const struct of_device_id sun20i_ppu_of_match[] = {
{
.compatible = "allwinner,sun20i-d1-ppu",
@@ -202,6 +215,10 @@ static const struct of_device_id sun20i_ppu_of_match[] = {
.compatible = "allwinner,sun8i-v853-ppu",
.data = &sun8i_v853_ppu_desc,
},
+ {
+ .compatible = "allwinner,sun55i-a523-ppu",
+ .data = &sun55i_a523_ppu_desc,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match);
--
2.39.5

135
patch/kernel/archive/sunxi-6.16/19-regulator-axp20x-force-polyphase-setup-for-axp323.patch Normal file
View File

@@ -0,0 +1,135 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sun, 6 Jul 2025 00:31:46 -0400
Subject: From: iuncuim <iuncuim@gmail.com> Date: Mon, 7 Apr 2025 03:28:37
+0300 Subject: [PATCH] regulator: axp20x: force polyphase setup for axp323
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 ++
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 3 ++
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 ++
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 3 ++
drivers/regulator/axp20x-regulator.c | 19 ++++++++++
5 files changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index f7a6221d02c2..369bde1556ff 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -330,10 +330,13 @@ reg_dcdc1_323: dcdc1 {
regulator-max-microvolt = <1160000>;
regulator-name = "vdd-cpub";
};
/* DCDC2 is polyphased with DCDC1 */
+ reg_dcdc2_323: dcdc2 {
+ x-powers,polyphased;
+ };
/* RISC-V management core supply */
reg_dcdc3_323: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <900000>;
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
index 0d7fb419c9b4..5732088add32 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
@@ -253,10 +253,13 @@ reg_dcdc1_323: dcdc1 {
regulator-max-microvolt = <1160000>;
regulator-name = "vdd-cpub";
};
/* DCDC2 is polyphased with DCDC1 */
+ reg_dcdc2_323: dcdc2 {
+ x-powers,polyphased;
+ };
reg_dcdc3_323: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
index 4f2366b3624a..bd1ebb15bb3e 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
@@ -283,10 +283,13 @@ reg_dcdc1_323: dcdc1 {
regulator-max-microvolt = <1160000>;
regulator-name = "vdd-cpub";
};
/* DCDC2 is polyphased with DCDC1 */
+ reg_dcdc2_323: dcdc2 {
+ x-powers,polyphased;
+ };
/* Some RISC-V management core related voltage */
reg_dcdc3_323: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <900000>;
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
index d1ffc9faec80..fb7933091edf 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
@@ -321,10 +321,13 @@ reg_dcdc1_323: dcdc1 {
regulator-max-microvolt = <1150000>;
regulator-name = "vdd-cpub";
};
/* DCDC2 is polyphased with DCDC1 */
+ reg_dcdc2_323: dcdc2 {
+ x-powers,polyphased;
+ };
/* Some RISC-V management core related voltage */
reg_dcdc3_323: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <900000>;
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index da891415efc0..2e2d35d31ce6 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -1479,10 +1479,23 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 work
}
return regmap_update_bits(rdev->regmap, reg, mask, workmode);
}
+static void axp20x_set_polyphased(struct axp20x_dev *axp20x, int id)
+{
+ switch (axp20x->variant) {
+ case AXP323_ID:
+ switch (id) {
+ case AXP313A_DCDC2:
+ regmap_write(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, BIT(1));
+ }
+ break;
+
+ default:
+ }
+}
/*
* This function checks whether a regulator is part of a poly-phase
* output setup based on the registers settings. Returns true if it is.
*/
static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
@@ -1702,10 +1715,16 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
if (axp20x_set_dcdc_workmode(rdev, i, workmode))
dev_err(&pdev->dev, "Failed to set workmode on %s\n",
rdev->desc->name);
}
+ /*
+ * Currently only the AXP323 needs to force dual phase setup.
+ */
+ if (of_property_read_bool(rdev->dev.of_node,"x-powers,polyphased"))
+ axp20x_set_polyphased(axp20x, i);
+
/*
* Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later.
*/
if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
(regulators == axp809_regulators && i == AXP809_DCDC1) ||
--
Created with Armbian build tools https://github.com/armbian/build

42
patch/kernel/archive/sunxi-6.16/20-soc-sunxi-sram-add-entry-for-a523.patch Normal file
View File

@@ -0,0 +1,42 @@
From: Chen-Yu Tsai <wens@csie.org>
The A523 has two Ethernet controllers. So in the system controller
address space, there are two registers for Ethernet clock delays,
one for each controller.
Add a new entry for the A523 system controller that allows access to
the second register.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 08e264ea0697..4f8d510b7e1e 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -320,6 +320,10 @@ static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
.has_ths_offset = true,
};
+static const struct sunxi_sramc_variant sun55i_a523_sramc_variant = {
+ .num_emac_clocks = 2,
+};
+
#define SUNXI_SRAM_THS_OFFSET_REG 0x0
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
#define SUNXI_SYS_LDO_CTRL_REG 0x150
@@ -440,6 +444,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
.compatible = "allwinner,sun50i-h616-system-control",
.data = &sun50i_h616_sramc_variant,
},
+ {
+ .compatible = "allwinner,sun55i-a523-system-control",
+ .data = &sun55i_a523_sramc_variant,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
--
2.39.5

44
patch/kernel/archive/sunxi-6.16/21-soc-sunxi-sram-register-regmap-as-syscon.patch Normal file
View File

@@ -0,0 +1,44 @@
From: Chen-Yu Tsai <wens@csie.org>
Until now, if the system controller had a ethernet controller glue layer
control register, a limited access regmap would be registered and tied
to the system controller struct device for the ethernet driver to use.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/soc/sunxi/sunxi_sram.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 4f8d510b7e1e..63c23bdffa78 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -12,6 +12,7 @@
#include <linux/debugfs.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -377,6 +378,7 @@ static int __init sunxi_sram_probe(struct platform_device *pdev)
const struct sunxi_sramc_variant *variant;
struct device *dev = &pdev->dev;
struct regmap *regmap;
+ int ret;
sram_dev = &pdev->dev;
@@ -394,6 +396,10 @@ static int __init sunxi_sram_probe(struct platform_device *pdev)
regmap = devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+
+ ret = of_syscon_register_regmap(dev->of_node, regmap);
+ if (IS_ERR(ret))
+ return ret;
}
of_platform_populate(dev->of_node, NULL, NULL, dev);
--
2.39.5

96
patch/kernel/archive/sunxi-6.16/22-arm64-dts-allwinner-a523-enable-Mali-GPU-for-all-boards.patch Normal file
View File

@@ -0,0 +1,96 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sun, 6 Jul 2025 00:12:02 -0400
Subject: From: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 5 +++++
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 5 +++++
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 5 +++++
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 5 +++++
4 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 592a50436454..f7a6221d02c2 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -103,10 +103,15 @@ &gmac1 {
allwinner,rx-delay-ps = <400>;
status = "okay";
};
+&gpu {
+ mali-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
&mdio0 {
ext_rgmii0_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
index 59db103546f6..0d7fb419c9b4 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
@@ -52,10 +52,15 @@ &ehci0 {
&ehci1 {
status = "okay";
};
+&gpu {
+ mali-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
bus-width = <4>;
disable-wp;
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
index 142177c1f737..4f2366b3624a 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
@@ -74,10 +74,15 @@ &gmac0 {
allwinner,rx-delay-ps = <300>;
status = "okay";
};
+&gpu {
+ mali-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
&mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
index ff2fd8e71e03..d1ffc9faec80 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
@@ -93,10 +93,15 @@ &ehci0 {
&ehci1 {
status = "okay";
};
+&gpu {
+ mali-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo3>;
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
bus-width = <4>;
status = "okay";
--
Created with Armbian build tools https://github.com/armbian/build

94
patch/kernel/archive/sunxi-6.16/23-arm64-dts-allwinner-a523-Add-GMAC200-ethernet-controller.patch Normal file
View File

@@ -0,0 +1,94 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Sat, 2 Aug 2025 00:36:05 -0400
Subject: Subject: From: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 ++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 7fbba60ec76e..50bebaa67d32 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -178,10 +178,20 @@ rgmii0_pins: rgmii0-pins {
function = "gmac0";
drive-strength = <40>;
bias-disable;
};
+ rgmii1_pins: rgmii1-pins {
+ pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4",
+ "PJ5", "PJ6", "PJ7", "PJ8", "PJ9",
+ "PJ11", "PJ12", "PJ13", "PJ14", "PJ15";
+ allwinner,pinmux = <5>;
+ function = "gmac1";
+ drive-strength = <40>;
+ bias-disable;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
allwinner,pinmux = <2>;
function = "uart0";
};
@@ -593,10 +603,55 @@ mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
+ gmac1: ethernet@4510000 {
+ compatible = "allwinner,sun55i-a523-gmac200",
+ "snps,dwmac-4.20a";
+ reg = <0x04510000 0x10000>;
+ clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
+ clock-names = "stmmaceth", "mbus";
+ resets = <&ccu RST_BUS_EMAC1>;
+ reset-names = "stmmaceth";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins>;
+ power-domains = <&pck600 PD_VO1>;
+ syscon = <&syscon>;
+ snps,fixed-burst;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+
+ queue0 {};
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <256 128 64 32 16 8 4>;
+ };
+
+ gmac1_mtl_tx_setup: tx_queues-config {
+ snps,tx-queues-to-use = <1>;
+
+ queue0 {};
+ };
+ };
+
ppu: power-controller@7001400 {
compatible = "allwinner,sun55i-a523-ppu";
reg = <0x07001400 0x400>;
clocks = <&r_ccu CLK_BUS_R_PPU1>;
resets = <&r_ccu RST_BUS_R_PPU1>;
--
Created with Armbian build tools https://github.com/armbian/build

48
patch/kernel/archive/sunxi-6.16/24-Enable-uart1-on-Radxa-Cubie-A5E.patch Normal file
View File

@@ -0,0 +1,48 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Juan Sanchez <juanesf91@gmail.com>
Date: Tue, 5 Aug 2025 14:55:52 -0400
Subject: Enable uart1 (bluetooth) on Radxa Cubie A5E
Signed-off-by: Juan Sanchez <juanesf91@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 369bde1556ff..37585cac6648 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -14,10 +14,11 @@ / {
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &sdio_wifi;
serial0 = &uart0;
+ serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
@@ -360,10 +361,18 @@ &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+/* Bluetooth */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
&usb_otg {
/*
* The USB-C port is the primary power supply, so in this configuration
* relies on the other end of the USB cable to supply the VBUS power.
* So use this port in peripheral mode.
--
Created with Armbian build tools https://github.com/armbian/build

84726
patch/kernel/archive/sunxi-dev-6.14/0801-net-wireless-backport-aic8800-sdio-v2024_0327_3561b08f.patch
View File

File diff suppressed because it is too large Load Diff

388
patch/kernel/archive/sunxi-dev-6.14/0802-net-wireless-mm2-fixes-aic8800-sdio-v2024_0327_3561b08f.patch
View File

@@ -1,388 +0,0 @@
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_driver.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_driver.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_driver.c 2024-11-03 17:06:15.410016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_driver.c 2024-11-03 17:04:11.540015950 +0100
@@ -472,7 +472,7 @@
#endif
#define MD5(x) x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7],x[8],x[9],x[10],x[11],x[12],x[13],x[14],x[15]
-#define MD5PINRT "file md5:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\r\n"
+#define MD5PINRT "file md5:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
int rwnx_load_firmware(u32 **fw_buf, const char *name, struct device *device)
{
@@ -1489,15 +1489,15 @@
*(data + 15) = aicbt_info[sdiodev->chipid].lpm_enable;
*(data + 17) = aicbt_info[sdiodev->chipid].txpwr_lvl;
- printk("%s bt btmode[%d]:%d \r\n", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].btmode);
- printk("%s bt uart_baud[%d]:%d \r\n", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].uart_baud);
- printk("%s bt uart_flowctrl[%d]:%d \r\n", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].uart_flowctrl);
- printk("%s bt lpm_enable[%d]:%d \r\n", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].lpm_enable);
- printk("%s bt tx_pwr[%d]:%d \r\n", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].txpwr_lvl);
+ printk("%s bt btmode[%d]:%d", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].btmode);
+ printk("%s bt uart_baud[%d]:%d", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].uart_baud);
+ printk("%s bt uart_flowctrl[%d]:%d", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].uart_flowctrl);
+ printk("%s bt lpm_enable[%d]:%d", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].lpm_enable);
+ printk("%s bt tx_pwr[%d]:%d", __func__, sdiodev->chipid, aicbt_info[sdiodev->chipid].txpwr_lvl);
}
if (AICBT_PT_VER == p->type) {
- printk("aicbsp: bt patch version: %s\n", (char *)p->data);
+ printk("aicbsp: bt patch version: %s", (char *)p->data);
continue;
}
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_main.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_main.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_main.c 2024-11-03 17:06:15.410016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_bsp/aic_bsp_main.c 2024-11-03 17:04:11.540015950 +0100
@@ -15,7 +15,8 @@
#define DRV_AUTHOR "AICSemi"
#define DRV_VERS_MOD "1.0"
-int aicwf_dbg_level_bsp = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
+//int aicwf_dbg_level_bsp = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
+int aicwf_dbg_level_bsp = LOGERROR;
static struct platform_device *aicbsp_pdev;
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_btlpm/lpm.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_btlpm/lpm.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_btlpm/lpm.c 2024-11-03 17:06:15.420016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_btlpm/lpm.c 2024-11-03 17:04:11.540015950 +0100
@@ -769,6 +769,16 @@
}
#endif
+enum of_gpio_flags {
+ OF_GPIO_ACTIVE_LOW = 0x1,
+ OF_GPIO_SINGLE_ENDED = 0x2,
+ OF_GPIO_OPEN_DRAIN = 0x4,
+ OF_GPIO_TRANSITORY = 0x8,
+ OF_GPIO_PULL_UP = 0x10,
+ OF_GPIO_PULL_DOWN = 0x20,
+ OF_GPIO_PULL_DISABLE = 0x40,
+};
+
static int bluesleep_probe(struct platform_device *pdev)
{
#if 1
@@ -783,7 +793,7 @@
if (!bsi)
return -ENOMEM;
- bsi->host_wake = of_get_named_gpio_flags(np, "bt_hostwake", 0, &config);
+ bsi->host_wake = of_get_named_gpio(np, "bt_hostwake", 0);
if (!gpio_is_valid(bsi->host_wake)) {
BT_ERR("get gpio bt_hostwake failed\n");
ret = -EINVAL;
@@ -791,7 +801,7 @@
}
/* set host_wake_assert */
- bsi->host_wake_assert = (config == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
+ bsi->host_wake_assert = (config == GPIOF_ACTIVE_LOW) ? 0 : 1;
BT_DBG("bt_hostwake gpio=%d assert=%d\n", bsi->host_wake, bsi->host_wake_assert);
if (assert_level != -1) {
@@ -838,7 +848,7 @@
#endif
}
- bsi->ext_wake = of_get_named_gpio_flags(np, "bt_wake", 0, &config);
+ bsi->ext_wake = of_get_named_gpio(np, "bt_wake", 0);
if (!gpio_is_valid(bsi->ext_wake)) {
BT_ERR("get gpio bt_wake failed\n");
ret = -EINVAL;
@@ -911,11 +921,11 @@
return 0;
err3:
- devm_gpio_free(dev, bsi->ext_wake);
+ //todo devm_gpio_free(dev, bsi->ext_wake);
err2:
device_init_wakeup(dev, false);
err1:
- devm_gpio_free(dev, bsi->host_wake);
+ //todo devm_gpio_free(dev, bsi->host_wake);
err0:
devm_kfree(dev, bsi);
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/aicwf_sdio.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/aicwf_sdio.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/aicwf_sdio.c 2024-11-03 17:06:15.423349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/aicwf_sdio.c 2024-11-03 17:04:11.540015950 +0100
@@ -529,15 +529,15 @@
if(vid == SDIO_VENDOR_ID_AIC8801 && did == SDIO_DEVICE_ID_AIC8801){
sdio_dev->chipid = PRODUCT_ID_AIC8801;
- AICWFDBG(LOGINFO, "%s USE AIC8801\r\n", __func__);
+ AICWFDBG(LOGINFO, "%s USE AIC8801\r", __func__);
return 0;
}else if(vid == SDIO_VENDOR_ID_AIC8800DC && did == SDIO_DEVICE_ID_AIC8800DC){
sdio_dev->chipid = PRODUCT_ID_AIC8800DC;
- AICWFDBG(LOGINFO, "%s USE AIC8800DC\r\n", __func__);
+ AICWFDBG(LOGINFO, "%s USE AIC8800DC\r", __func__);
return 0;
}else if(vid == SDIO_VENDOR_ID_AIC8800D80 && did == SDIO_DEVICE_ID_AIC8800D80){
sdio_dev->chipid = PRODUCT_ID_AIC8800D80;
- AICWFDBG(LOGINFO, "%s USE AIC8800D80\r\n", __func__);
+ AICWFDBG(LOGINFO, "%s USE AIC8800D80\r", __func__);
return 0;
}else{
return -1;
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/Makefile linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/Makefile
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/Makefile 2024-11-03 17:06:15.423349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/Makefile 2024-11-03 17:04:11.540015950 +0100
@@ -132,7 +132,7 @@
# extra DEBUG config
CONFIG_RWNX_SW_PROFILING ?= n
-CONFIG_RWNX_DBG ?= y
+CONFIG_RWNX_DBG ?= n
CONFIG_DEBUG_FS ?= n
obj-$(CONFIG_AIC8800_WLAN_SUPPORT) := $(MODULE_NAME).o
@@ -203,6 +203,8 @@
ccflags-y += -DNX_TX_MAX_RATES=4
ccflags-y += -DNX_CHAN_CTXT_CNT=3
+ccflags-y += -Wno-incompatible-pointer-types
+
# FW ARCH:
ccflags-$(CONFIG_RWNX_SDM) += -DCONFIG_RWNX_SDM
ccflags-$(CONFIG_RWNX_TL4) += -DCONFIG_RWNX_TL4
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_main.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_main.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_main.c 2024-11-03 17:06:15.426683053 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_main.c 2024-11-03 17:04:11.540015950 +0100
@@ -510,7 +510,8 @@
extern uint8_t scanning;
-int aicwf_dbg_level = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
+//int aicwf_dbg_level = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
+int aicwf_dbg_level = LOGERROR;
module_param(aicwf_dbg_level, int, 0660);
int testmode = 0;
char aic_fw_path[200];
@@ -770,7 +771,11 @@
cfg80211_disconnected(vif->ndev, 0, NULL, 0, 0, GFP_KERNEL);
#endif
} else {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0))
+ wiphy_lock(vif->wdev.wiphy);
+#else
mutex_lock(&vif->wdev.mtx);
+#endif
__acquire(&vif->wdev.mtx);
spin_lock_bh(&rwnx_hw->cb_lock);
rwnx_chanctx_unlink(vif);
@@ -782,13 +787,17 @@
rwnx_txq_vif_stop(vif, RWNX_TXQ_STOP_CHAN, rwnx_hw);
spin_unlock_bh(&rwnx_hw->cb_lock);
#if (LINUX_VERSION_CODE >= HIGH_KERNEL_VERSION3)
- cfg80211_ch_switch_notify(vif->ndev, &csa->chandef, 0, 0);
+ cfg80211_ch_switch_notify(vif->ndev, &csa->chandef, 0);
#elif (LINUX_VERSION_CODE >= HIGH_KERNEL_VERSION)
cfg80211_ch_switch_notify(vif->ndev, &csa->chandef, 0);
#else
cfg80211_ch_switch_notify(vif->ndev, &csa->chandef);
#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0))
+ wiphy_lock(vif->wdev.wiphy);
+#else
mutex_unlock(&vif->wdev.mtx);
+#endif
__release(&vif->wdev.mtx);
}
rwnx_del_csa(vif);
@@ -3013,10 +3022,11 @@
bool found = false;
list_for_each_entry(master_vif, &rwnx_hw->vifs, list) {
if ((RWNX_VIF_TYPE(master_vif) == NL80211_IFTYPE_AP) &&
- !(!memcmp(master_vif->ndev->dev_addr, params->macaddr,
- ETH_ALEN))) {
- found = true;
- break;
+ !(!memcmp(master_vif->ndev->dev_addr, params->macaddr, ETH_ALEN)))
+ {
+ memcmp(master_vif->ndev->dev_addr_shadow, params->macaddr, ETH_ALEN);
+ found = true;
+ break;
}
}
@@ -5561,7 +5571,7 @@
} else {
INIT_WORK(&csa->work, rwnx_csa_finish);
#if LINUX_VERSION_CODE >= HIGH_KERNEL_VERSION4
- cfg80211_ch_switch_started_notify(dev, &csa->chandef, 0, params->count, false, 0);
+ cfg80211_ch_switch_started_notify(dev, &csa->chandef, 0, params->count, false);
#elif LINUX_VERSION_CODE >= HIGH_KERNEL_VERSION2
cfg80211_ch_switch_started_notify(dev, &csa->chandef, 0, params->count, false);
#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
@@ -6565,8 +6575,8 @@
.tdls_channel_switch = rwnx_cfg80211_tdls_channel_switch,
.tdls_cancel_channel_switch = rwnx_cfg80211_tdls_cancel_channel_switch,
#endif
- .tdls_mgmt = rwnx_cfg80211_tdls_mgmt,
- .tdls_oper = rwnx_cfg80211_tdls_oper,
+ //todo .tdls_mgmt = rwnx_cfg80211_tdls_mgmt,
+ //todo .tdls_oper = rwnx_cfg80211_tdls_oper,
.change_bss = rwnx_cfg80211_change_bss,
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0) || defined(CONFIG_WPA3_FOR_OLD_KERNEL)
.external_auth = rwnx_cfg80211_external_auth,
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_mod_params.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_mod_params.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_mod_params.c 2024-11-03 17:06:15.430016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_mod_params.c 2024-11-03 17:04:11.540015950 +0100
@@ -1546,9 +1546,6 @@
// function, that needs to be called after wiphy registration
memcpy(country_code, default_ccode, sizeof(default_ccode));
regdomain = getRegdomainFromRwnxDB(wiphy, default_ccode);
- printk(KERN_CRIT
- "\n\n%s: CAUTION: USING PERMISSIVE CUSTOM REGULATORY RULES\n\n",
- __func__);
wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF;
wiphy_apply_custom_regulatory(wiphy, regdomain);
@@ -1580,9 +1577,6 @@
// Apply custom regulatory. Note that for recent kernel versions we use instead the
// REGULATORY_WIPHY_SELF_MANAGED flag, along with the regulatory_set_wiphy_regd()
// function, that needs to be called after wiphy registration
- printk(KERN_CRIT
- "\n\n%s: CAUTION: USING PERMISSIVE CUSTOM REGULATORY RULES\n\n",
- __func__);
wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF;
wiphy_apply_custom_regulatory(wiphy, &rwnx_regdom);
@@ -1725,11 +1719,15 @@
// For older kernel version, the custom regulatory is applied before the wiphy
// registration (in rwnx_set_wiphy_params()), so nothing has to be done here
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)
- if (!rwnx_hw->mod_params->custregd)
- return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
+ // nop
+#else
+ wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF;
+#endif
+ wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED;
- wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF;
- wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED;
+ if (!rwnx_hw->mod_params->custregd)
+ return;
rtnl_lock();
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)
@@ -1743,10 +1741,7 @@
#endif
else{
- wiphy_err(wiphy,"\n"
- "*******************************************************\n"
- "** CAUTION: USING PERMISSIVE CUSTOM REGULATORY RULES **\n"
- "*******************************************************\n");
+ //
}
rtnl_unlock();
#endif
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_platform.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_platform.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_platform.c 2024-11-03 17:06:15.430016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_platform.c 2024-11-03 17:04:11.540015950 +0100
@@ -271,7 +271,7 @@
#endif
#define MD5(x) x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7],x[8],x[9],x[10],x[11],x[12],x[13],x[14],x[15]
-#define MD5PINRT "file md5:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\r\n"
+#define MD5PINRT "file md5:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
static int rwnx_load_firmware(u32 **fw_buf, const char *name, struct device *device)
{
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_radar.c linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_radar.c
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_radar.c 2024-11-03 17:06:15.430016386 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_radar.c 2024-11-03 16:42:50.616678220 +0100
@@ -1399,7 +1399,7 @@
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
&ctxt->chan_def,
#endif
- NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
+ NL80211_RADAR_CAC_FINISHED, GFP_KERNEL, 0);
rwnx_send_apm_stop_cac_req(rwnx_hw, radar->cac_vif);
rwnx_chanctx_unlink(radar->cac_vif);
@@ -1499,7 +1499,7 @@
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
&ctxt->chan_def,
#endif
- NL80211_RADAR_CAC_ABORTED, GFP_KERNEL);
+ NL80211_RADAR_CAC_ABORTED, GFP_KERNEL, 0);
rwnx_chanctx_unlink(radar->cac_vif);
}
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_version.h linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_version.h
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_version.h 2024-11-03 17:06:15.433349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/aic8800_fdrv/rwnx_version.h 2024-11-03 17:04:11.540015950 +0100
@@ -6,7 +6,7 @@
static inline void rwnx_print_version(void)
{
AICWFDBG(LOGINFO, RWNX_VERS_BANNER"\n");
- AICWFDBG(LOGINFO, "RELEASE_DATE:%s \r\n", RELEASE_DATE);
+ AICWFDBG(LOGINFO, "RELEASE_DATE:%s \r", RELEASE_DATE);
}
#endif /* _RWNX_VERSION_H_ */
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/.gitignore linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/.gitignore
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/.gitignore 2024-11-03 17:06:15.433349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/.gitignore 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-*.symvers
-*.order
-*.symvers.cmd
-*.order.cmd
-.tmp_versions/
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Kconfig linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Kconfig
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Kconfig 2024-11-03 17:06:15.433349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Kconfig 2024-11-03 17:04:11.540015950 +0100
@@ -1,18 +1,17 @@
-config AIC_WLAN_SUPPORT
- bool "AIC wireless Support"
+config AIC_SDIO_WLAN_SUPPORT
+ bool "AIC 8800 SDIO wireless Support"
default n
help
- This is support for aic wireless chip.
+ This is support for aic 8800 wireless chip with SDIO interface.
config AIC_FW_PATH
- depends on AIC_WLAN_SUPPORT
+ depends on AIC_SDIO_WLAN_SUPPORT
string "Firmware & config file path"
- default "/vendor/etc/firmware"
- #default "/lib/firmware/aic8800_sdio"
+ default "/lib/firmware/aic8800_sdio"
help
Path to the firmware & config file.
-if AIC_WLAN_SUPPORT
-source "drivers/net/wireless/aic8800/aic8800_fdrv/Kconfig"
-source "drivers/net/wireless/aic8800/aic8800_btlpm/Kconfig"
+if AIC_SDIO_WLAN_SUPPORT
+source "drivers/net/wireless/aic8800_sdio/aic8800_fdrv/Kconfig"
+source "drivers/net/wireless/aic8800_sdio/aic8800_btlpm/Kconfig"
endif
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Makefile linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Makefile
--- linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Makefile 2024-11-03 17:06:15.433349720 +0100
+++ linux-6.12-rc5/drivers/net/wireless/aic8800_sdio/Makefile 2024-11-03 17:04:11.543349283 +0100
@@ -1,12 +1,10 @@
CONFIG_AIC8800_BTLPM_SUPPORT := m
CONFIG_AIC8800_WLAN_SUPPORT := m
-CONFIG_AIC_WLAN_SUPPORT := m
+CONFIG_AIC_SDIO_WLAN_SUPPORT := m
obj-$(CONFIG_AIC8800_BTLPM_SUPPORT) += aic8800_btlpm/
obj-$(CONFIG_AIC8800_WLAN_SUPPORT) += aic8800_fdrv/
-obj-$(CONFIG_AIC_WLAN_SUPPORT) += aic8800_bsp/
-
-MAKEFLAGS +=-j$(shell nproc)
+obj-$(CONFIG_AIC_SDIO_WLAN_SUPPORT) += aic8800_bsp/
########## config option ##########
export CONFIG_USE_FW_REQUEST = n

60
patch/kernel/archive/sunxi-dev-6.14/1103-mfd-axp20x-Allow-multiple-regulators.patch
View File

@@ -1,60 +0,0 @@
From 12045a9ab272974528afea72781f5308c662a1d0 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Tue, 1 Oct 2024 22:28:41 +0100
Subject: [PATCH 03/37] mfd: axp20x: Allow multiple regulators
At the moment trying to register a second AXP chip makes the probe fail,
as some sysfs registration fails due to a duplicate name:
...
[ 3.688215] axp20x-i2c 0-0035: AXP20X driver loaded
[ 3.695610] axp20x-i2c 0-0036: AXP20x variant AXP323 found
[ 3.706151] sysfs: cannot create duplicate filename '/bus/platform/devices/axp20x-regulator'
[ 3.714718] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.12.0-rc1-00026-g50bf2e2c079d-dirty #192
[ 3.724020] Hardware name: Avaota A1 (DT)
[ 3.728029] Call trace:
[ 3.730477] dump_backtrace+0x94/0xec
[ 3.734146] show_stack+0x18/0x24
[ 3.737462] dump_stack_lvl+0x80/0xf4
[ 3.741128] dump_stack+0x18/0x24
[ 3.744444] sysfs_warn_dup+0x64/0x80
[ 3.748109] sysfs_do_create_link_sd+0xf0/0xf8
[ 3.752553] sysfs_create_link+0x20/0x40
[ 3.756476] bus_add_device+0x64/0x104
[ 3.760229] device_add+0x310/0x760
[ 3.763717] platform_device_add+0x10c/0x238
[ 3.767990] mfd_add_device+0x4ec/0x5c8
[ 3.771829] mfd_add_devices+0x88/0x11c
[ 3.775666] axp20x_device_probe+0x70/0x184
[ 3.779851] axp20x_i2c_probe+0x9c/0xd8
...
This is because we use PLATFORM_DEVID_NONE for the mfd_add_devices()
call, which would number the child devices in the same 0-based way, even
for the second (or any other) instance.
Use PLATFORM_DEVID_AUTO instead, which automatically assigns
non-conflicting device numbers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/mfd/axp20x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 5ceea359289..bc08ae43326 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1419,7 +1419,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
}
- ret = mfd_add_devices(axp20x->dev, PLATFORM_DEVID_NONE, axp20x->cells,
+ ret = mfd_add_devices(axp20x->dev, PLATFORM_DEVID_AUTO, axp20x->cells,
axp20x->nr_cells, NULL, 0, NULL);
if (ret) {
--
2.46.0

368
patch/kernel/archive/sunxi-dev-6.14/1137-net-phy-add-Maxio-MAE0621A-phy-driver.patch
View File

@@ -1,368 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: John Doe <john.doe@somewhere.on.planet>
Date: Sat, 15 Mar 2025 00:57:55 -0300
Subject: [PATCH] Add Maxio MAE0621A PHY driver
Signed-off-by: John Doe <john.doe@somewhere.on.planet>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/maxio.c | 254 ++++++++++
drivers/net/phy/phy_device.c | 9 +
5 files changed, 274 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index d04543e5697b..c8cf84fa4091 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7826,10 +7826,11 @@ int stmmac_suspend(struct device *dev)
priv->speed = SPEED_UNKNOWN;
return 0;
}
EXPORT_SYMBOL_GPL(stmmac_suspend);
+#define MAXIO_PHY_MAE0621A_ID 0x7b744411
static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
@@ -7922,10 +7923,14 @@ int stmmac_resume(struct device *dev)
stmmac_reset_queues_param(priv);
stmmac_free_tx_skbufs(priv);
stmmac_clear_descriptors(priv, &priv->dma_conf);
+ if (ndev->phydev->drv->config_init) {
+ if (ndev->phydev->phy_id == MAXIO_PHY_MAE0621A_ID)
+ ndev->phydev->drv->config_init(ndev->phydev);
+ }
stmmac_hw_setup(ndev, false);
stmmac_init_coalesce(priv);
stmmac_set_rx_mode(ndev);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 41c15a2c2037..6a5de0ce5723 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -360,10 +360,15 @@ config RENESAS_PHY
config ROCKCHIP_PHY
tristate "Rockchip Ethernet PHYs"
help
Currently supports the integrated Ethernet PHY.
+config MAXIO_PHY
+ tristate "Maxio PHYs"
+ help
+ Supports the Maxio MAExxxx PHY.
+
config SMSC_PHY
tristate "SMSC PHYs"
select CRC16
help
Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index c8dac6e92278..2bdde53a3885 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -94,10 +94,11 @@ obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja.o
obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-y += qcom/
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek/
+obj-$(CONFIG_MAXIO_PHY) += maxio.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
obj-$(CONFIG_SMSC_PHY) += smsc.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
new file mode 100644
index 000000000000..fd227e86794f
--- /dev/null
+++ b/drivers/net/phy/maxio.c
@@ -0,0 +1,254 @@
+/*
+ * drivers/net/phy/maxio.c
+ *
+ * Driver for maxio PHYs
+ *
+ * Author: zhao yang <yang_zhao@maxio-tech.com>
+ *
+ * Copyright (c) 2004 maxio technology, Inc.
+ */
+#include <linux/bitops.h>
+#include <linux/phy.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/timer.h>
+#include <linux/netdevice.h>
+
+#define MAXIO_PAGE_SELECT 0x1f
+#define MAXIO_MAE0621A_INER 0x12
+#define MAXIO_MAE0621A_INER_LINK_STATUS BIT(4)
+#define MAXIO_MAE0621A_INSR 0x1d
+#define MAXIO_MAE0621A_TX_DELAY (BIT(6)|BIT(7))
+#define MAXIO_MAE0621A_RX_DELAY (BIT(4)|BIT(5))
+#define MAXIO_MAE0621A_CLK_MODE_REG 0x02
+#define MAXIO_MAE0621A_WORK_STATUS_REG 0x1d
+
+
+static int maxio_read_paged(struct phy_device *phydev, int page, u32 regnum)
+{
+ int ret = 0, oldpage;
+
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+ if (oldpage >= 0) {
+ phy_write(phydev, MAXIO_PAGE_SELECT, page);
+ ret = phy_read(phydev, regnum);
+ }
+ phy_write(phydev, MAXIO_PAGE_SELECT, oldpage);
+
+ return ret;
+}
+
+static int maxio_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
+{
+ int ret = 0, oldpage;
+
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+ if (oldpage >= 0) {
+ phy_write(phydev, MAXIO_PAGE_SELECT, page);
+ ret = phy_write(phydev, regnum, val);
+ }
+ phy_write(phydev, MAXIO_PAGE_SELECT, oldpage);
+
+ return ret;
+}
+
+static int maxio_mae0621a_clk_init(struct phy_device *phydev)
+{
+ u32 workmode,clkmode,oldpage;
+
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+ if (oldpage == 0xFFFF) {
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+ }
+
+ //soft reset
+ phy_write(phydev, MAXIO_PAGE_SELECT, 0x0);
+ phy_write(phydev, MII_BMCR, BMCR_RESET | phy_read(phydev, MII_BMCR));
+
+ //get workmode
+ phy_write(phydev, MAXIO_PAGE_SELECT, 0xa43);
+ workmode = phy_read(phydev, MAXIO_MAE0621A_WORK_STATUS_REG);
+
+ //get clkmode
+ phy_write( phydev, MAXIO_PAGE_SELECT, 0xd92 );
+ clkmode = phy_read( phydev, MAXIO_MAE0621A_CLK_MODE_REG );
+
+ //abnormal
+ if (0 == (workmode&BIT(5))) {
+ if (0 == (clkmode&BIT(8))) {
+ //oscillator
+ phy_write(phydev, 0x02, clkmode | BIT(8));
+ printk("****maxio_mae0621a_clk_init**clkmode**0x210a: 0x%x\n", phydev->phy_id);
+ } else {
+ //crystal
+ printk("****maxio_mae0621a_clk_init**clkmode**0x200a: 0x%x\n", phydev->phy_id);
+ phy_write(phydev, 0x02, clkmode &(~ BIT(8)));
+ }
+ }
+ phy_write(phydev, MAXIO_PAGE_SELECT, 0x0);
+
+ phy_write(phydev, MAXIO_PAGE_SELECT, oldpage);
+
+ return 0;
+}
+
+static int maxio_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
+{
+ int ret = 0, oldpage;
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+
+ if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {// eee info
+ phy_write(phydev, MAXIO_PAGE_SELECT ,0);
+ phy_write(phydev, 0xd, MDIO_MMD_AN);
+ phy_write(phydev, 0xe, MDIO_AN_EEE_ADV);
+ phy_write(phydev, 0xd, 0x4000 | MDIO_MMD_AN);
+ ret = phy_read(phydev, 0x0e);
+ } else {
+ ret = -EOPNOTSUPP;
+ }
+ phy_write(phydev, MAXIO_PAGE_SELECT, oldpage);
+
+ return ret;
+}
+
+static int maxio_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val)
+{
+ int ret = 0, oldpage;
+ oldpage = phy_read(phydev, MAXIO_PAGE_SELECT);
+
+ if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { // eee info
+ phy_write(phydev, MAXIO_PAGE_SELECT ,0);
+ ret |= phy_write(phydev, 0xd, MDIO_MMD_AN);
+ ret |= phy_write(phydev, 0xe, MDIO_AN_EEE_ADV);
+ ret |= phy_write(phydev, 0xd, 0x4000 | MDIO_MMD_AN);
+ ret |= phy_write(phydev, 0xe, val);
+ msleep(100);
+ ret |= genphy_restart_aneg(phydev);
+ } else {
+ ret = -EOPNOTSUPP;
+ }
+ phy_write(phydev, MAXIO_PAGE_SELECT, oldpage);
+
+ return ret;
+}
+
+static int maxio_mae0621a_config_aneg(struct phy_device *phydev)
+{
+ return genphy_config_aneg(phydev);
+}
+
+
+static int maxio_mae0621a_config_init(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ u16 val;
+ int ret;
+ u32 broken = 0;
+
+ maxio_mae0621a_clk_init(phydev);
+
+ //disable eee
+ printk("eee value: 0x%x \n",maxio_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV));
+ maxio_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
+ printk("eee value: 0x%x \n",maxio_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV));
+ broken |= MDIO_EEE_100TX;
+ broken |= MDIO_EEE_1000T;
+ memcpy(phydev->eee_broken_modes, broken, sizeof(phydev->eee_broken_modes));
+
+ //enable auto_speed_down
+ ret = maxio_write_paged(phydev, 0xd8f, 0x0, 0x300 );
+
+ //adjust TX/RX delay
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ val = 0x0;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ val = MAXIO_MAE0621A_TX_DELAY | MAXIO_MAE0621A_RX_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ val = MAXIO_MAE0621A_RX_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val = MAXIO_MAE0621A_TX_DELAY;
+ break;
+ default: /* the rest of the modes imply leaving delays as is. */
+ goto delay_skip;
+ }
+
+ ret = maxio_read_paged(phydev, 0xd96, 0x0);
+ if (ret < 0) {
+ dev_err(dev, "Failed to update the TX delay register\n");
+ return ret;
+ }
+
+ ret =maxio_write_paged(phydev, 0xd96, 0x0, val|ret );
+ if (ret < 0) {
+ dev_err(dev, "Failed to update the TX delay register\n");
+ return ret;
+ } else if (ret == 0) {
+ dev_dbg(dev,
+ "2ns delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
+ val ? "enabled" : "disabled");
+ }
+delay_skip:
+
+ phy_write(phydev, MII_BMCR, BMCR_RESET | phy_read(phydev, MII_BMCR));
+ msleep(1);
+ phy_write(phydev, MAXIO_PAGE_SELECT, 0x0);
+
+ return 0;
+}
+
+
+static int maxio_mae0621a_resume(struct phy_device *phydev)
+{
+ int ret = genphy_resume(phydev);
+
+ ret |= phy_write(phydev, MII_BMCR, BMCR_RESET | phy_read(phydev, MII_BMCR));
+
+ msleep(20);
+
+ return ret;
+}
+
+int maxio_mae0621a_suspend(struct phy_device *phydev)
+{
+ genphy_suspend(phydev);
+ phy_write(phydev, MAXIO_PAGE_SELECT ,0);
+
+ return 0;
+}
+
+static int maxio_mae0621a_status(struct phy_device *phydev)
+{
+ return genphy_read_status(phydev);
+}
+
+static int maxio_mae0621a_probe(struct phy_device *phydev)
+{
+ int ret = maxio_mae0621a_clk_init(phydev);
+ mdelay(100);
+ return ret;
+}
+
+static struct phy_driver maxio_nc_drvs[] = {
+ {
+ .phy_id = 0x7b744411,
+ .phy_id_mask = 0x7fffffff,
+ .name = "MAE0621A Gigabit Ethernet",
+ .features = PHY_GBIT_FEATURES,
+ .probe = maxio_mae0621a_probe,
+ .config_init = maxio_mae0621a_config_init,
+ .config_aneg = maxio_mae0621a_config_aneg,
+ .read_status = maxio_mae0621a_status,
+ .suspend = maxio_mae0621a_suspend,
+ .resume = maxio_mae0621a_resume,
+ },
+};
+module_phy_driver(maxio_nc_drvs);
+
+MODULE_DESCRIPTION("Maxio PHY driver");
+MODULE_AUTHOR("Zhao Yang");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 46713d27412b..1a9514360673 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -858,10 +858,19 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr,
*/
static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
{
int phy_reg;
+#ifdef CONFIG_MAXIO_PHY
+ /*
+ *An MDIO connects to multiple PHYs requiring write before read.
+ *This operation does not affect one MDIO connected to a single PHY
+ *MII_PHYSID2 is a read-only register and writine to it has no effect
+ */
+ mdiobus_write(bus,addr,MII_PHYSID2,0);
+#endif
+
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
if (phy_reg < 0) {
/* returning -ENODEV doesn't stop bus scanning */
return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
--
Created with Armbian build tools https://github.com/armbian/build

3238
patch/kernel/archive/sunxi-dev-6.14/1139-net-ethernet-allwinner-add-gmac200-support.patch
View File

File diff suppressed because it is too large Load Diff

4470
patch/kernel/archive/sunxi-dev-6.14/1140-net-ethernet-allwinner-add-gmac-support.patch
View File

File diff suppressed because it is too large Load Diff

99
patch/kernel/archive/sunxi-dev-6.14/1151-arm64-dtsi-allwinner-add-gmac1-in-A523-dtsi.patch
View File

@@ -1,99 +0,0 @@
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12.4/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi linux-6.12.4/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
--- linux-6.12.4/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi 2024-12-17 16:00:39.127051177 +0100
+++ linux-6.12.4/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi 2024-12-18 12:33:17.756857967 +0100
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
#include <dt-bindings/reset/sun55i-a523-ccu.h>
#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
interrupt-parent = <&gic>;
@@ -110,6 +112,28 @@
allwinner,pinmux = <2>;
function = "uart0";
};
+
+ /omit-if-no-ref/
+ gmac1_pins_default: gmac1@0 {
+ pins = "PJ0", "PJ1", "PJ2", "PJ3",
+ "PJ4", "PJ5", "PJ6", "PJ7",
+ "PJ8", "PJ9", "PJ10", "PJ11",
+ "PJ12","PJ13", "PJ14", "PJ15";
+ allwinner,pinmux = <5>;
+ function = "gmac1";
+ drive-strength = <40>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ gmac1_pins_sleep: gmac1@1 {
+ pins = "PJ0", "PJ1", "PJ2", "PJ3",
+ "PJ4", "PJ5", "PJ6", "PJ7",
+ "PJ8", "PJ9", "PJ10", "PJ11",
+ "PJ12","PJ13", "PJ14", "PJ15";
+ allwinner,pinmux = <0>;
+ function = "gpio_in";
+ };
};
ccu: clock@2001000 {
@@ -380,5 +404,58 @@
clock-names = "bus", "hosc", "ahb";
#clock-cells = <1>;
};
+
+ gmac1: ethernet@4510000 {
+ compatible = "allwinner,sunxi-gmac-200", "snps,dwmac-4.20a";
+ reg = <0x04510000 0x10000>,
+ <0x03000034 0x4>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>, <&ccu CLK_EMAC1_25M>;
+ clock-names = "stmmaceth", "pclk", "phy25m";
+ resets = <&ccu RST_BUS_EMAC1>;
+ reset-names = "stmmaceth";
+ phy-handle = <&gmac1_phy0>;
+ //todo power-domains = <&pd1 A523_PCK_VO1>;
+ status = "disabled";
+
+ snps,fixed-burst;
+
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <256 128 64 32 16 8 4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx_queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ mdio1: mdio1@1 {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gmac1_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ max-speed = <1000>; /* Max speed capability */
+ reset-gpios = <&pio 9 27 GPIO_ACTIVE_LOW>; /* PJ27; 9 is PJ */
+ /* PHY datasheet rst time */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+ };
+ };
};
};

69
patch/kernel/archive/sunxi-dev-6.14/1152-arm64-dtsi-allwinner-add-gmac0-in-A523-dtsi.patch
View File

@@ -1,69 +0,0 @@
diff --speed-large-files --no-dereference --minimal -Naur linux-6.12.10/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi linux-6.12.10/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
--- linux-6.12.10/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi 2025-01-22 15:45:11.961240491 +0100
+++ linux-6.12.10/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi 2025-01-22 13:16:06.127667018 +0100
@@ -159,6 +159,28 @@
allwinner,pinmux = <2>;
function = "uart0";
};
+
+ /omit-if-no-ref/
+ gmac0_pins_default: gmac0@0 {
+ pins = "PH0", "PH1", "PH2", "PH3",
+ "PH4", "PH5", "PH6", "PH7",
+ "PH9", "PH10","PH13","PH14",
+ "PH15","PH16","PH17","PH18";
+ allwinner,pinmux = <5>;
+ function = "gmac0";
+ drive-strength = <40>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ gmac0_pins_sleep: gmac0@1 {
+ pins = "PH0", "PH1", "PH2", "PH3",
+ "PH4", "PH5", "PH6", "PH7",
+ "PH9", "PH10","PH13","PH14",
+ "PH15","PH16","PH17","PH18";
+ allwinner,pinmux = <0>;
+ function = "gpio_in";
+ };
/omit-if-no-ref/
gmac1_pins_default: gmac1@0 {
@@ -610,6 +632,36 @@
#clock-cells = <1>;
};
+ mdio0: mdio0@4500048 {
+ compatible = "allwinner,sunxi-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x04500048 0x8>;
+ status = "disabled";
+
+ gmac0_phy0: ethernet-phy@1 {
+ reg = <1>;
+ max-speed = <1000>; /* Max speed capability */
+ reset-gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; /* PH19 */
+ /* PHY datasheet rst time */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+ };
+
+ gmac0: gmac0@4500000 {
+ compatible = "allwinner,sunxi-gmac";
+ reg = <0x04500000 0x10000>,
+ <0x03000030 0x4>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gmacirq";
+ clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC0_25M>;
+ clock-names = "gmac", "phy25m";
+ resets = <&ccu RST_BUS_EMAC0>;
+ phy-handle = <&gmac0_phy0>;
+ status = "disabled";
+ };
+
gmac1: ethernet@4510000 {
compatible = "allwinner,sunxi-gmac-200", "snps,dwmac-4.20a";
reg = <0x04510000 0x10000>,

307
patch/kernel/archive/sunxi-dev-6.14/1208-thermal-drivers-sun8i-Add-initial-support-for-A523-T.patch
View File

@@ -1,307 +0,0 @@
From a5476261558ca640f5c414d66f4f7f619796d7b3 Mon Sep 17 00:00:00 2001
From: iuncuim <iuncuim@gmail.com>
Date: Sat, 22 Mar 2025 05:11:02 +0300
Subject: [PATCH] thermal/drivers/sun8i: Add initial support for A523 THS0/THS1
controller
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
.../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 123 ++++++++++++++++++
drivers/thermal/sun8i_thermal.c | 51 +++++++-
2 files changed, 171 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index ee485899b..ad3722b5c 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -22,6 +22,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0x000>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -29,6 +30,7 @@ cpu1: cpu@100 {
device_type = "cpu";
reg = <0x100>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -36,6 +38,7 @@ cpu2: cpu@200 {
device_type = "cpu";
reg = <0x200>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -43,6 +46,7 @@ cpu3: cpu@300 {
device_type = "cpu";
reg = <0x300>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -50,6 +54,7 @@ cpu4: cpu@400 {
device_type = "cpu";
reg = <0x400>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -57,6 +62,7 @@ cpu5: cpu@500 {
device_type = "cpu";
reg = <0x500>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu6: cpu@600 {
@@ -64,6 +70,7 @@ cpu6: cpu@600 {
device_type = "cpu";
reg = <0x600>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
cpu7: cpu@700 {
@@ -71,6 +78,7 @@ cpu7: cpu@700 {
device_type = "cpu";
reg = <0x700>;
enable-method = "psci";
+ #cooling-cells = <2>;
};
};
@@ -171,6 +179,40 @@ ccu: clock-controller@2001000 {
#reset-cells = <1>;
};
+ ths1: thermal-sensor@2009400 {
+ compatible = "allwinner,sun55i-a523-ths1";
+ reg = <0x02009400 0x400>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>;
+ clock-names = "bus", "gpadc";
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+
+ ths0: thermal-sensor@200a000 {
+ compatible = "allwinner,sun55i-a523-ths0";
+ reg = <0x0200a000 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>;
+ clock-names = "bus", "gpadc";
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+
+ sid: efuse@3006000 {
+ compatible = "allwinner,sun50i-a523-sid", "allwinner,sun50i-a64-sid";
+ reg = <0x03006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* TODO: we need set proper calibration values */
+ ths_calibration: thermal-sensor-calibration@38 {
+ reg = <0x38 0x10>;
+ };
+ };
+
mmc0: mmc@4020000 {
compatible = "allwinner,sun55i-a523-mmc",
"allwinner,sun20i-d1-mmc";
@@ -595,4 +637,85 @@ rtc: rtc@7090000 {
#clock-cells = <1>;
};
};
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths1 1>;
+ sustainable-power = <1200>;
+
+ trips {
+ cpu0_threshold: cpu-trip-0 {
+ temperature = <70000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu0_target: cpu-trip-1 {
+ temperature = <90000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu0_critical: cpu-trip-2 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ cpu4_thermal: cpu4-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths1 0>;
+ sustainable-power = <1600>;
+
+ trips {
+ cpu4_threshold: cpu-trip-0 {
+ temperature = <70000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu4_target: cpu-trip-1 {
+ temperature = <90000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu4_critical: cpu-trip-2 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths1 2>;
+ sustainable-power = <2400>;
+
+ trips {
+ gpu_temp_critical: gpu-trip-0 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths0 0>;
+
+ trips {
+ ddr_temp_critical: ddr-trip-0 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+ };
};
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 226747906..bd4f7d781 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -66,8 +66,9 @@ struct tsensor {
};
struct ths_thermal_chip {
- bool has_mod_clk;
- bool has_bus_clk_reset;
+ bool has_gpadc_clk;
+ bool has_mod_clk;
+ bool has_bus_clk_reset;
bool needs_sram;
int sensor_num;
int offset;
@@ -89,7 +90,8 @@ struct ths_device {
struct regmap_field *sram_regmap_field;
struct reset_control *reset;
struct clk *bus_clk;
- struct clk *mod_clk;
+ struct clk *mod_clk;
+ struct clk *gpadc_clk;
struct tsensor sensor[MAX_SENSOR_NUM];
};
@@ -114,6 +116,15 @@ static int sun50i_h5_calc_temp(struct ths_device *tmdev,
return -1590 * reg / 10 + 276000;
}
+static int sun55i_a523_calc_temp(struct ths_device *tmdev,
+ int id, int reg)
+{
+ if (reg >= 0x7c8)
+ return 74 * (2736 - reg);
+ else
+ return 65 * (2825 - reg);
+}
+
static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp)
{
struct tsensor *s = thermal_zone_device_priv(tz);
@@ -417,6 +428,16 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
if (ret)
return ret;
+ if (tmdev->chip->has_gpadc_clk) {
+ tmdev->gpadc_clk = devm_clk_get_enabled(&pdev->dev, "gpadc");
+ if (IS_ERR(tmdev->gpadc_clk))
+ return PTR_ERR(tmdev->gpadc_clk);
+ }
+
+ ret = clk_prepare_enable(tmdev->gpadc_clk);
+ if (ret)
+ return ret;
+
if (tmdev->chip->needs_sram) {
struct regmap *regmap;
@@ -709,6 +730,28 @@ static const struct ths_thermal_chip sun50i_h616_ths = {
.calc_temp = sun8i_ths_calc_temp,
};
+static const struct ths_thermal_chip sun55i_a523_ths0 = {
+ .sensor_num = 1,
+ .has_bus_clk_reset = false, /* TODO: same reset with sun55i_a523_ths1, gives an error */
+ .has_gpadc_clk = true,
+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .calibrate = sun50i_h6_ths_calibrate, /* TODO: calibration function has not yet been added */
+ .init = sun50i_h6_thermal_init,
+ .irq_ack = sun50i_h6_irq_ack,
+ .calc_temp = sun55i_a523_calc_temp,
+};
+
+static const struct ths_thermal_chip sun55i_a523_ths1 = {
+ .sensor_num = 3,
+ .has_bus_clk_reset = true,
+ .has_gpadc_clk = true,
+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .calibrate = sun50i_h6_ths_calibrate, /* TODO: calibration function has not yet been added */
+ .init = sun50i_h6_thermal_init,
+ .irq_ack = sun50i_h6_irq_ack,
+ .calc_temp = sun55i_a523_calc_temp,
+};
+
static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
@@ -719,6 +762,8 @@ static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
+ { .compatible = "allwinner,sun55i-a523-ths0", .data = &sun55i_a523_ths0 },
+ { .compatible = "allwinner,sun55i-a523-ths1", .data = &sun55i_a523_ths1 },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, of_ths_match);
--
2.49.0

161
patch/kernel/archive/sunxi-dev-6.14/update-cubie-a5e-dts.patch
View File

@@ -1,161 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: John Doe <john.doe@somewhere.on.planet>
Date: Sat, 15 Mar 2025 17:18:05 -0300
Subject: Patch sun55i-a527-radxa-a5e.dts Add gmac0/1 wifi
Signed-off-by: John Doe <john.doe@somewhere.on.planet>
---
arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts | 99 ++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts
index 912e1bda974c..8cf16035796e 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts
@@ -11,16 +11,38 @@ / {
model = "Radxa A5E";
compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527";
aliases {
serial0 = &uart0;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &mmc2;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &wlan;
};
chosen {
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "radxa:green:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "radxa:blue:user";
+ gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ linux,default-trigger = "default-on";
+ };
+ };
+
ext_osc32k: ext-osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "ext_osc32k";
@@ -42,10 +64,20 @@ reg_usb_vbus: vbus {
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_vcc5v>;
gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
enable-active-high;
};
+
+ reg_3v3_wifi: 3v3-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc5v>;
+ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ enable-active-high;
+ };
};
&ehci0 {
status = "okay";
};
@@ -59,10 +91,27 @@ &mmc0 {
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; /* PF6 */
bus-width = <4>;
status = "okay";
};
+&mmc1_pins {
+ drive-strength = <40>;
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_3v3_wifi>;
+ bus-width = <4>;
+ non-removable;
+ // todo: investigate why clock above 40MHz makes data errors
+ max-frequency = <35000000>;
+ status = "okay";
+
+ wlan: wifi@1 {
+ reg = <1>;
+ };
+};
+
&ohci0 {
status = "okay";
};
&ohci1 {
@@ -295,5 +344,55 @@ &usb_otg {
&usbphy {
usb0_vbus-supply = <&reg_vcc5v>;
usb1_vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&gmac0_pins_default>;
+ pinctrl-1 = <&gmac0_pins_sleep>;
+ sunxi,phy-clk-type = <0>;
+ tx-delay = <2>;
+ rx-delay = <4>;
+ gmac3v3-supply = <&reg_cldo3>;
+ status = "okay";
+};
+
+&mdio0 {
+ compatible = "allwinner,sunxi-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x04500048 0x8>;
+ status = "okay";
+
+ gmac0_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&gmac1_pins_default>;
+ pinctrl-1 = <&gmac1_pins_sleep>;
+ aw,soc-phy25m;
+ tx-delay = <3>;
+ rx-delay = <4>;
+ dwmac3v3-supply = <&reg_cldo3>;
+ status = "okay";
+
+ mdio1: mdio1@1 {
+ gmac1_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+ };
+};
--
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