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u-boot: use 2025.10 plus Kwiboo patches for Rockchip

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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
This commit is contained in:
Christian Hewitt
2025-07-19 08:08:56 +00:00
parent f2b8c14756
commit f0acbd3fce
86 changed files with 12550 additions and 56 deletions
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16
packages/tools/u-boot/package.mk
View File

@@ -3,17 +3,27 @@
# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
PKG_NAME="u-boot"
PKG_VERSION="2025.07"
PKG_SHA256="0f933f6c5a426895bf306e93e6ac53c60870e4b54cda56d95211bec99e63bec7"
PKG_ARCH="arm aarch64"
PKG_LICENSE="GPL"
PKG_SITE="https://www.denx.de/wiki/U-Boot"
PKG_URL="https://ftp.denx.de/pub/u-boot/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
PKG_DEPENDS_TARGET="toolchain openssl:host pkg-config:host Python3:host swig:host pyelftools:host"
PKG_LONGDESC="Das U-Boot is a cross-platform bootloader for embedded systems."
PKG_STAMP="${UBOOT_SYSTEM} ${UBOOT_TARGET}"
case ${PROJECT} in
Rockchip)
PKG_VERSION="2025.10-rc3" # plus Kwiboo changes for RK3576 support
PKG_SHA256="1224f85046da9a8687df26b7f87ce74fe3b29d40b0151b06f9add88be5c3dc9d"
PKG_URL="https://ftp.denx.de/pub/u-boot/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
;;
*)
PKG_VERSION="2025.07"
PKG_SHA256="0f933f6c5a426895bf306e93e6ac53c60870e4b54cda56d95211bec99e63bec7"
PKG_URL="https://ftp.denx.de/pub/u-boot/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
;;
esac
[ -n "${KERNEL_TOOLCHAIN}" ] && PKG_DEPENDS_TARGET+=" gcc-${KERNEL_TOOLCHAIN}:host"
if [ -n "${UBOOT_FIRMWARE}" ]; then

39
projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch
View File

@@ -1,39 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Date: Sat, 23 Jul 2022 13:23:19 +0200
Subject: [PATCH 4/6] rockchip: rk3328: Set VOP QoS to high priority
The default priority for the quality of service for the video
output results in unsightly glitches on the output whenever there
is memory pressure on the system, which happens a lot.
This sets the VOP QoS to high priority, which fixes this issue.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
arch/arm/mach-rockchip/rk3328/rk3328.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index de17b88682..58300bdf3f 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -16,6 +16,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xFF100000
#define UART2_BASE 0xFF130000
#define FW_DDR_CON_REG 0xFF7C0040
+#define QOS_VOP_OFFSET 0xFF760080
+#define QOS_VOP_PRIORITY 0x8
#define EFUSE_NS_BASE 0xFF260000
#define EFUSE_MOD 0x0000
@@ -54,6 +56,9 @@ int arch_cpu_init(void)
writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
+#else
+ printf("Setting VOP QoS\n");
+ rk_setreg(QOS_VOP_OFFSET + QOS_VOP_PRIORITY, 0xF);
#endif
return 0;
}

76
projects/Rockchip/patches/u-boot/rockchip-0001-rockchip-rockchip-inno-usb2-Fix-Synchronous-Abort-on.patch Normal file
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@@ -0,0 +1,76 @@
From 84361828ad40949a0ca4f9a39b7248c46bf71b7c Mon Sep 17 00:00:00 2001
From: Alex Shumsky <alexthreed@gmail.com>
Date: Thu, 3 Jul 2025 09:04:48 +0300
Subject: [PATCH 01/84] rockchip: rockchip-inno-usb2: Fix Synchronous Abort on
usb start
Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
enabled before device probe. This early clock enable call happen in process
of parent clock activation added in ac30d90f3367.
Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy").
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Co-authored-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Shumsky <alexthreed@gmail.com>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 88b33de1b2a..3cc5956aed5 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = {
.of_xlate = rockchip_usb2phy_of_xlate,
};
-static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
- const struct usb2phy_reg **clkout_ctl)
+static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+ const struct usb2phy_reg **clkout_ctl)
{
struct udevice *parent = dev_get_parent(clk->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
- if (priv->phy_cfg->clkout_ctl_phy.enable) {
+ // phy_cfg can be NULL if this function called before probe (when parent
+ // clocks are enabled)
+ if (!phy_cfg)
+ return -EINVAL;
+
+ if (phy_cfg->clkout_ctl_phy.enable) {
*base = priv->phy_base;
*clkout_ctl = &phy_cfg->clkout_ctl_phy;
} else {
*base = priv->reg_base;
*clkout_ctl = &phy_cfg->clkout_ctl;
}
+
+ return 0;
}
/**
@@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
const struct usb2phy_reg *clkout_ctl;
struct regmap *base;
- rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+ if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+ return -ENOSYS;
/* turn on 480m clk output if it is off */
if (!property_enabled(base, clkout_ctl)) {
@@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)
const struct usb2phy_reg *clkout_ctl;
struct regmap *base;
- rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+ if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+ return -ENOSYS;
/* turn off 480m clk output */
property_enable(base, clkout_ctl, false);
--
2.34.1

72
projects/Rockchip/patches/u-boot/rockchip-0002-phy-rockchip-usbdp-Fix-Generic-PHY-reference-countin.patch Normal file
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@@ -0,0 +1,72 @@
From 813fb2de3997d55a44c82769bc26fa6e548ad9d1 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:10 +0000
Subject: [PATCH 02/84] phy: rockchip: usbdp: Fix Generic PHY reference
counting
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 9deec47ae46..56963c87183 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -587,12 +587,16 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
static int rockchip_u3phy_of_xlate(struct phy *phy,
struct ofnode_phandle_args *args)
{
+ struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
+
if (args->args_count == 0)
return -EINVAL;
if (args->args[0] != PHY_TYPE_USB3)
return -EINVAL;
+ phy->id = udphy->id;
+
return 0;
}
--
2.34.1

134
projects/Rockchip/patches/u-boot/rockchip-0003-phy-rockchip-usbdp-Simplify-init-ops.patch Normal file
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@@ -0,0 +1,134 @@
From ef03459846d7be6b231c19e07f4613ec1f74b884 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:11 +0000
Subject: [PATCH 03/84] phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 71 +++--------------------
1 file changed, 8 insertions(+), 63 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 56963c87183..6cfbef02b4a 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -96,9 +96,7 @@ struct rockchip_udphy {
/* PHY status management */
bool flip;
- bool mode_change;
u8 mode;
- u8 status;
/* utilized for USB */
bool hs; /* flag for high-speed */
@@ -525,65 +523,6 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
return 0;
}
-static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
-{
- int ret;
-
- if (!(udphy->mode & mode)) {
- dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
- return 0;
- }
-
- if (udphy->status == UDPHY_MODE_NONE) {
- udphy->mode_change = false;
- ret = udphy_setup(udphy);
- if (ret)
- return ret;
-
- if (udphy->mode & UDPHY_MODE_USB)
- udphy_u3_port_disable(udphy, false);
- } else if (udphy->mode_change) {
- udphy->mode_change = false;
- udphy->status = UDPHY_MODE_NONE;
- if (udphy->mode == UDPHY_MODE_DP)
- udphy_u3_port_disable(udphy, true);
-
- ret = udphy_disable(udphy);
- if (ret)
- return ret;
- ret = udphy_setup(udphy);
- if (ret)
- return ret;
- }
-
- udphy->status |= mode;
-
- return 0;
-}
-
-static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
-{
- int ret;
-
- if (!(udphy->mode & mode)) {
- dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
- return 0;
- }
-
- if (!udphy->status)
- return 0;
-
- udphy->status &= ~mode;
-
- if (udphy->status == UDPHY_MODE_NONE) {
- ret = udphy_disable(udphy);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static int rockchip_u3phy_of_xlate(struct phy *phy,
struct ofnode_phandle_args *args)
{
@@ -603,6 +542,7 @@ static int rockchip_u3phy_of_xlate(struct phy *phy,
static int rockchip_u3phy_init(struct phy *phy)
{
struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
+ int ret;
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
@@ -610,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy)
return 0;
}
- return udphy_power_on(udphy, UDPHY_MODE_USB);
+ ret = udphy_setup(udphy);
+ if (ret)
+ return ret;
+
+ udphy_u3_port_disable(udphy, false);
+ return 0;
}
static int rockchip_u3phy_exit(struct phy *phy)
@@ -621,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy)
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
return 0;
- return udphy_power_off(udphy, UDPHY_MODE_USB);
+ return udphy_disable(udphy);
}
static const struct phy_ops rockchip_u3phy_ops = {
--
2.34.1

37
projects/Rockchip/patches/u-boot/rockchip-0004-phy-rockchip-naneng-combphy-Fix-Generic-PHY-referenc.patch Normal file
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@@ -0,0 +1,37 @@
From 5338a239b47d28a04da856bd9fbc18d4fefa96ba Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:12 +0000
Subject: [PATCH 04/84] phy: rockchip: naneng-combphy: Fix Generic PHY
reference counting
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 5145b517aa4..a3038d067d3 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -223,6 +223,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a
return -EINVAL;
}
+ phy->id = priv->id;
priv->mode = args->args[0];
return 0;
--
2.34.1

159
projects/Rockchip/patches/u-boot/rockchip-0005-phy-rockchip-naneng-combphy-Simplify-init-ops.patch Normal file
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@@ -0,0 +1,159 @@
From 87ec15bbdc953d552dde11a5772b1e3dadc855f4 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:13 +0000
Subject: [PATCH 05/84] phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 101 ++++--------------
1 file changed, 19 insertions(+), 82 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index a3038d067d3..f246c8db2d6 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -98,104 +98,41 @@ static int param_write(struct regmap *base,
return regmap_write(base, reg->offset, val);
}
-static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
-{
- int ret = 0;
-
- if (priv->cfg->combphy_cfg) {
- ret = priv->cfg->combphy_cfg(priv);
- if (ret) {
- dev_err(priv->dev, "failed to init phy for pcie\n");
- return ret;
- }
- }
-
- return ret;
-}
-
-static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
-{
- int ret = 0;
-
- if (priv->cfg->combphy_cfg) {
- ret = priv->cfg->combphy_cfg(priv);
- if (ret) {
- dev_err(priv->dev, "failed to init phy for usb3\n");
- return ret;
- }
- }
-
- return ret;
-}
-
-static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
-{
- int ret = 0;
-
- if (priv->cfg->combphy_cfg) {
- ret = priv->cfg->combphy_cfg(priv);
- if (ret) {
- dev_err(priv->dev, "failed to init phy for sata\n");
- return ret;
- }
- }
-
- return ret;
-}
-
-static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
+static int rockchip_combphy_init(struct phy *phy)
{
- int ret = 0;
-
- if (priv->cfg->combphy_cfg) {
- ret = priv->cfg->combphy_cfg(priv);
- if (ret) {
- dev_err(priv->dev, "failed to init phy for sgmii\n");
- return ret;
- }
- }
+ struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
+ int ret;
- return ret;
-}
+ ret = clk_enable(&priv->ref_clk);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
-static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
-{
switch (priv->mode) {
case PHY_TYPE_PCIE:
- rockchip_combphy_pcie_init(priv);
- break;
case PHY_TYPE_USB3:
- rockchip_combphy_usb3_init(priv);
- break;
case PHY_TYPE_SATA:
- rockchip_combphy_sata_init(priv);
- break;
case PHY_TYPE_SGMII:
case PHY_TYPE_QSGMII:
- return rockchip_combphy_sgmii_init(priv);
+ if (priv->cfg->combphy_cfg)
+ ret = priv->cfg->combphy_cfg(priv);
+ else
+ ret = 0;
+ break;
default:
dev_err(priv->dev, "incompatible PHY type\n");
- return -EINVAL;
+ ret = -EINVAL;
+ break;
}
- return 0;
-}
-
-static int rockchip_combphy_init(struct phy *phy)
-{
- struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
- int ret;
-
- ret = clk_enable(&priv->ref_clk);
- if (ret < 0 && ret != -ENOSYS)
- return ret;
+ if (ret) {
+ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode);
+ goto err_clk;
+ }
- ret = rockchip_combphy_set_mode(priv);
+ ret = reset_deassert_bulk(&priv->phy_rsts);
if (ret)
goto err_clk;
- reset_deassert_bulk(&priv->phy_rsts);
-
return 0;
err_clk:
@@ -305,7 +242,7 @@ static int rockchip_combphy_probe(struct udevice *udev)
}
priv->dev = udev;
- priv->mode = PHY_TYPE_SATA;
+ priv->mode = PHY_NONE;
priv->cfg = phy_cfg;
return rockchip_combphy_parse_dt(udev, priv);
--
2.34.1

53
projects/Rockchip/patches/u-boot/rockchip-0006-phy-rockchip-naneng-combphy-Use-syscon_regmap_lookup.patch Normal file
View File

@@ -0,0 +1,53 @@
From eec16e822568cf506da371bd8d4ea21c04567dc9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:14 +0000
Subject: [PATCH 06/84] phy: rockchip: naneng-combphy: Use
syscon_regmap_lookup_by_phandle
Change to use syscon_regmap_lookup_by_phandle() helper instead of
finding the syscon udevice and making a call to syscon_get_regmap().
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../phy/rockchip/phy-rockchip-naneng-combphy.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index f246c8db2d6..7f107a11606 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -175,22 +175,19 @@ static const struct phy_ops rockchip_combphy_ops = {
static int rockchip_combphy_parse_dt(struct udevice *dev,
struct rockchip_combphy_priv *priv)
{
- struct udevice *syscon;
int ret;
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon);
- if (ret) {
- dev_err(dev, "failed to find peri_ctrl pipe-grf regmap");
- return ret;
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
+ if (IS_ERR(priv->pipe_grf)) {
+ dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+ return PTR_ERR(priv->pipe_grf);
}
- priv->pipe_grf = syscon_get_regmap(syscon);
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon);
- if (ret) {
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf");
+ if (IS_ERR(priv->phy_grf)) {
dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
- return ret;
+ return PTR_ERR(priv->phy_grf);
}
- priv->phy_grf = syscon_get_regmap(syscon);
ret = clk_get_by_index(dev, 0, &priv->ref_clk);
if (ret) {
--
2.34.1

35
projects/Rockchip/patches/u-boot/rockchip-0007-phy-rockchip-inno-usb2-Fix-improper-use-of-UCLASS_PH.patch Normal file
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@@ -0,0 +1,35 @@
From 677ca627443e49b96b0b21fe9d33070848b26a7b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:15 +0000
Subject: [PATCH 07/84] phy: rockchip: inno-usb2: Fix improper use of
UCLASS_PHY
The Rockchip USB2PHY glue driver improperly present itself as a
UCLASS_PHY driver, without ever implementing the required phy_ops.
This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.
Change the glue driver to use UCLASS_NOP to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 3cc5956aed5..a3222138b9d 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -547,7 +547,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = {
U_BOOT_DRIVER(rockchip_usb2phy) = {
.name = "rockchip_usb2phy",
- .id = UCLASS_PHY,
+ .id = UCLASS_NOP,
.of_match = rockchip_usb2phy_ids,
.probe = rockchip_usb2phy_probe,
.bind = rockchip_usb2phy_bind,
--
2.34.1

34
projects/Rockchip/patches/u-boot/rockchip-0008-phy-rockchip-typec-Fix-improper-use-of-UCLASS_PHY.patch Normal file
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@@ -0,0 +1,34 @@
From b607543bf26e94417f401654f5eed7459f6a7547 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:16 +0000
Subject: [PATCH 08/84] phy: rockchip: typec: Fix improper use of UCLASS_PHY
The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY
driver, without ever implementing the required phy_ops.
This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.
Change the glue driver to use UCLASS_NOP to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-typec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index c48a5cd5267..66d1d32d25c 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
U_BOOT_DRIVER(rockchip_typec_phy) = {
.name = "rockchip_typec_phy",
- .id = UCLASS_PHY,
+ .id = UCLASS_NOP,
.of_match = rockchip_typec_phy_ids,
.probe = rockchip_tcphy_probe,
.bind = rockchip_tcphy_bind,
--
2.34.1

50
projects/Rockchip/patches/u-boot/rockchip-0009-rockchip-rk3588-Disable-USB3OTG-U3-ports-early.patch Normal file
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@@ -0,0 +1,50 @@
From 12d3074fb4c7c8ab80bbc5f5faae505e25609385 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:17 +0000
Subject: [PATCH 09/84] rockchip: rk3588: Disable USB3OTG U3 ports early
The RK3588 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 ports early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index e2278ff792b..c01a4002089 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -15,6 +15,10 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
+#define USB_GRF_BASE 0xfd5ac000
+#define USB3OTG0_CON1 0x001c
+#define USB3OTG1_CON1 0x0034
+
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
@@ -184,6 +188,10 @@ int arch_cpu_init(void)
/* Disable JTAG exposed on SDMMC */
rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
+
+ /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
#endif
return 0;
--
2.34.1

47
projects/Rockchip/patches/u-boot/rockchip-0010-rockchip-rk3576-Disable-USB3OTG0-U3-port-early.patch Normal file
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@@ -0,0 +1,47 @@
From bbf94bdbe33c3644ae2172d723d3ae88a3c57a98 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:18 +0000
Subject: [PATCH 10/84] rockchip: rk3576: Disable USB3OTG0 U3 port early
The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
index ba5c94b4b3d..dc53941ab2f 100644
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -29,6 +29,9 @@
#define SGRF_DOMAIN_CON4 0x10
#define SGRF_DOMAIN_CON5 0x14
+#define USB_GRF_BASE 0x2601E000
+#define USB3OTG0_CON1 0x0030
+
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
@@ -151,5 +154,8 @@ int arch_cpu_init(void)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
+ /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+
return 0;
}
--
2.34.1

90
projects/Rockchip/patches/u-boot/rockchip-0011-rockchip-rk3588-generic-Move-usb-nodes-to-board-dts.patch Normal file
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@@ -0,0 +1,90 @@
From 3504dae677104a8cf12d625ad628726c5b061c7b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 21 Jul 2025 22:07:19 +0000
Subject: [PATCH 11/84] rockchip: rk3588-generic: Move usb nodes to board dts
After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes
in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
usb nodes for the Generic RK3588 board in the board u-boot.dtsi.
Move usb related nodes from board u-boot.dtsi to main board device tree.
While at it, also drop use of the usb3-phy as we only want to enable the
usb2-phy to be compatible with as many boards as possible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3588-generic-u-boot.dtsi | 18 ------------------
arch/arm/dts/rk3588-generic.dts | 16 ++++++++++++++++
configs/generic-rk3588_defconfig | 1 -
3 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi
index f67301d87a6..853ed58cfe5 100644
--- a/arch/arm/dts/rk3588-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -1,21 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588s-u-boot.dtsi"
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&usbdp_phy0 {
- status = "okay";
-};
-
-&usb_host0_xhci {
- dr_mode = "peripheral";
- maximum-speed = "high-speed";
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
index 95d757676f1..6740f9866f1 100644
--- a/arch/arm/dts/rk3588-generic.dts
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -39,7 +39,23 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index ed2f936b324..dfa8efabe6b 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
--
2.34.1

36
projects/Rockchip/patches/u-boot/rockchip-0012-phy-rockchip-naneng-combphy-Enable-U3-port-for-USB3O.patch Normal file
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@@ -0,0 +1,36 @@
From 23b7834fa5265f7b4c14b84c454951783adb2156 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 13:09:38 +0000
Subject: [PATCH 12/84] phy: rockchip: naneng-combphy: Enable U3 port for
USB3OTG on RK3568
The USB OTG U3 port may have been disabled early, add support to the
COMBPHY driver to re-enable the U3 port.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 7f107a11606..81195de60bc 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -301,6 +301,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ switch (priv->id) {
+ case 0:
+ param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
+ break;
+ case 1:
+ param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
+ break;
+ }
break;
case PHY_TYPE_SATA:
writel(0x41, priv->mmio + 0x38);
--
2.34.1

49
projects/Rockchip/patches/u-boot/rockchip-0013-rockchip-rk3568-Disable-USB3OTG-U3-ports-early.patch Normal file
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@@ -0,0 +1,49 @@
From 8d5f4e5a9e5e2281386e4d273e5232a8636bfff8 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 13:10:36 +0000
Subject: [PATCH 13/84] rockchip: rk3568: Disable USB3OTG U3 ports early
The RK3568 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 ports early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index c2b96902d2d..560af336be4 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -14,6 +14,9 @@
#include <dt-bindings/clock/rk3568-cru.h>
#define PMUGRF_BASE 0xfdc20000
+#define PIPE_GRF_BASE 0xfdc50000
+#define USB3OTG0_CON1 0x104
+#define USB3OTG1_CON1 0x144
#define GRF_BASE 0xfdc60000
#define GRF_GPIO1B_DS_2 0x218
#define GRF_GPIO1B_DS_3 0x21c
@@ -139,6 +142,10 @@ int arch_cpu_init(void)
/* Enable VO power domain for display */
writel((PMU_PD_VO_DWN_ENA << 16),
PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
+
+ /* Disable USB3OTG U3 ports, later enabled in COMBPHY driver */
+ writel(0xffff0181, PIPE_GRF_BASE + USB3OTG0_CON1);
+ writel(0xffff0181, PIPE_GRF_BASE + USB3OTG1_CON1);
#endif
return 0;
}
--
2.34.1

113
projects/Rockchip/patches/u-boot/rockchip-0014-mmc-rockchip_sdhci-Set-xx_TAP_VALUE-for-RK3528.patch Normal file
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@@ -0,0 +1,113 @@
From e3cb5639cb00274c6517f28e47d0849534bab000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 14 Jul 2025 20:34:07 +0000
Subject: [PATCH 14/84] mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
eMMC erase and write support on RK3528 is somewhat unreliable, sometime
e.g. mmc erase and write commands will fail with an error.
Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
This is only enabled for RK3528, remaining SoCs still use the automatic
tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
for RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/rockchip_sdhci.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 761e3619329..cca917da68e 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <dm/ofnode.h>
#include <dt-structs.h>
+#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/libfdt.h>
@@ -86,6 +87,9 @@
#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
+#define DLL_TAPVALUE_FROM_SW BIT(25)
+#define DLL_TAP_VALUE_PREP(x) FIELD_PREP(GENMASK(15, 8), (x))
+#define DLL_LOCK_VALUE_GET(x) FIELD_GET(GENMASK(7, 0), (x))
#define DLL_LOCK_WO_TMOUT(x) \
((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
@@ -93,6 +97,7 @@
#define ROCKCHIP_MAX_CLKS 3
#define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0)
+#define FLAG_TAPVALUE_FROM_SW BIT(1)
struct rockchip_sdhc_plat {
struct mmc_config cfg;
@@ -317,7 +322,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
struct mmc *mmc = host->mmc;
int val, ret;
- u32 extra, txclk_tapnum;
+ u32 extra, txclk_tapnum, dll_tap_value;
if (!enable) {
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
@@ -347,7 +352,15 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
if (ret)
return ret;
- extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
+ if (data->flags & FLAG_TAPVALUE_FROM_SW)
+ dll_tap_value = DLL_TAPVALUE_FROM_SW |
+ DLL_TAP_VALUE_PREP(DLL_LOCK_VALUE_GET(val) * 2);
+ else
+ dll_tap_value = 0;
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_RXCLK_ORI_GATE |
+ dll_tap_value;
if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
extra |= DLL_RXCLK_NO_INVERTER;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
@@ -361,19 +374,22 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
data->hs400_cmdout_tapnum |
- DLL_CMDOUT_TAPNUM_FROM_SW;
+ DLL_CMDOUT_TAPNUM_FROM_SW |
+ dll_tap_value;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
}
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_TXCLK_TAPNUM_FROM_SW |
DLL_TXCLK_NO_INVERTER |
- txclk_tapnum;
+ txclk_tapnum |
+ dll_tap_value;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
data->hs400_strbin_tapnum |
- DLL_STRBIN_TAPNUM_FROM_SW;
+ DLL_STRBIN_TAPNUM_FROM_SW |
+ dll_tap_value;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
/*
@@ -663,6 +679,7 @@ static const struct sdhci_data rk3528_data = {
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
.config_dll = rk3568_sdhci_config_dll,
+ .flags = FLAG_TAPVALUE_FROM_SW,
.hs200_txclk_tapnum = 0xc,
.hs400_txclk_tapnum = 0x6,
.hs400_cmdout_tapnum = 0x6,
--
2.34.1

44
projects/Rockchip/patches/u-boot/rockchip-0015-rockchip-rk3528-generic-Fix-boot-after-dts-upstream-.patch Normal file
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@@ -0,0 +1,44 @@
From 31932a9b2babf23c3c95b412bdb4af35176e1826 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:42 +0000
Subject: [PATCH 15/84] rockchip: rk3528-generic: Fix boot after dts/upstream
v6.16-dts merge
The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:
No serial driver found
resetting ...
After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.
Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-generic.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
index 3f6f0bed108..fe9e72c41cd 100644
--- a/arch/arm/dts/rk3528-generic.dts
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -10,6 +10,11 @@
model = "Generic RK3528";
compatible = "rockchip,rk3528";
+ aliases {
+ mmc0 = &sdhci;
+ serial0 = &uart0;
+ };
+
chosen {
stdout-path = "serial0:1500000n8";
};
--
2.34.1

121
projects/Rockchip/patches/u-boot/rockchip-0016-arm-dts-rockchip-Use-sdmmc-node-from-dts-upstream-on.patch Normal file
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@@ -0,0 +1,121 @@
From 3e100c18fe037bde5f4c08d9ff06ba68caee85d5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:43 +0000
Subject: [PATCH 16/84] arm: dts: rockchip: Use sdmmc node from dts/upstream on
RK3528
Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node
from rk3528.dtsi with v6.16-dts now merged to dts/upstream.
This cleanup has no intended functional change.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-generic-u-boot.dtsi | 9 ---------
arch/arm/dts/rk3528-generic.dts | 12 +++++++++++-
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 9 ---------
arch/arm/dts/rk3528-u-boot.dtsi | 18 ------------------
4 files changed, 11 insertions(+), 37 deletions(-)
diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
index cc830b51456..9e1fb2a7eef 100644
--- a/arch/arm/dts/rk3528-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -1,12 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3528-u-boot.dtsi"
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- no-mmc;
- no-sdio;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
index fe9e72c41cd..637ca03325e 100644
--- a/arch/arm/dts/rk3528-generic.dts
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3528 with eMMC enabled
+ * Minimal generic DT for RK3528 with eMMC and SD-card enabled
*/
/dts-v1/;
@@ -12,6 +12,7 @@
aliases {
mmc0 = &sdhci;
+ mmc1 = &sdmmc;
serial0 = &uart0;
};
@@ -30,6 +31,15 @@
status = "okay";
};
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
index 1372d8f1e38..05a58c136bc 100644
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -5,12 +5,3 @@
&sdhci {
mmc-hs200-1_8v;
};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vmmc-supply = <&vcc_3v3>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
index eb6a55cd5c9..a18d33b3d36 100644
--- a/arch/arm/dts/rk3528-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -27,24 +27,6 @@
compatible = "rockchip,rk3528-otp";
reg = <0x0 0xffce0000 0x0 0x4000>;
};
-
- sdmmc: mmc@ffc30000 {
- compatible = "rockchip,rk3528-dw-mshc",
- "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xffc30000 0x0 0x4000>;
- clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
- <&sdmmc_det>;
- resets = <&cru SRST_H_SDMMC0>;
- reset-names = "reset";
- rockchip,default-sample-phase = <90>;
- status = "disabled";
- };
};
};
--
2.34.1

35
projects/Rockchip/patches/u-boot/rockchip-0017-arm-dts-rockchip-Set-init-microvolt-for-pwm-regulato.patch Normal file
View File

@@ -0,0 +1,35 @@
From 021508b653ce85a4528a63834457d5754724e4a1 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:44 +0000
Subject: [PATCH 17/84] arm: dts: rockchip: Set init-microvolt for
pwm-regulators on Radxa E20C
Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic.
Add init-microvolt props to ensure the regulators are initialized at
the recommended power-on sequence voltage instead of at max voltage.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
index 05a58c136bc..16c47e6b9a9 100644
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -5,3 +5,11 @@
&sdhci {
mmc-hs200-1_8v;
};
+
+&vdd_arm {
+ regulator-init-microvolt = <953000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
+};
--
2.34.1

48
projects/Rockchip/patches/u-boot/rockchip-0018-rockchip-rk3528-Disable-USB3OTG-U3-port-early.patch Normal file
View File

@@ -0,0 +1,48 @@
From 95e59308dcc7a38811241ccee900c22d151ff507 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:45 +0000
Subject: [PATCH 18/84] rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
index 4892ff6ba9d..f9bfc445b85 100644
--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -9,6 +9,9 @@
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
+#define VPU_GRF_BASE 0xff340000
+#define USB3OTG_CON1 0x44
+
#define FIREWALL_DDR_BASE 0xff2e0000
#define FW_DDR_MST6_REG 0x58
#define FW_DDR_MST7_REG 0x5c
@@ -69,6 +72,9 @@ int arch_cpu_init(void)
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
+ writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
+
return 0;
}
--
2.34.1

29
projects/Rockchip/patches/u-boot/rockchip-0019-rockchip-clk-clk_rk3528-Add-dummy-CLK_REF_PCIE_INNER.patch Normal file
View File

@@ -0,0 +1,29 @@
From 257c7fd65c9e070089127b1ca17a49e5a349c863 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:46 +0000
Subject: [PATCH 19/84] rockchip: clk: clk_rk3528: Add dummy
CLK_REF_PCIE_INNER_PHY support
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/clk/rockchip/clk_rk3528.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index 06f20895acc..d58557ff56d 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
/* Might occur in cru assigned-clocks, can be ignored here */
case ACLK_BUS_VOPGL_ROOT:
case BCLK_EMMC:
+ case CLK_REF_PCIE_INNER_PHY:
case XIN_OSC0_DIV:
ret = 0;
break;
--
2.34.1

31
projects/Rockchip/patches/u-boot/rockchip-0020-usb-dwc3-generic-Use-combined-glue-and-ctrl-node-for.patch Normal file
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@@ -0,0 +1,31 @@
From f01c443ad30c51d9ed055aa30e0a5cba864d2610 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:47 +0000
Subject: [PATCH 20/84] usb: dwc3-generic: Use combined glue and ctrl node for
RK3528
Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single
node to represent the glue and ctrl for USB 3.0.
Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/usb/dwc3/dwc3-generic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3cda2b74b7e..6b2016c0cd3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -698,6 +698,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "ti,am654-dwc3" },
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
+ { .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
--
2.34.1

145
projects/Rockchip/patches/u-boot/rockchip-0021-phy-rockchip-naneng-combphy-Add-support-for-RK3528.patch Normal file
View File

@@ -0,0 +1,145 @@
From 243470bb288e50adbe36b0d4d8c512546b4b9aa8 Mon Sep 17 00:00:00 2001
From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Date: Wed, 30 Jul 2025 23:52:48 +0000
Subject: [PATCH 21/84] phy: rockchip: naneng-combphy: Add support for RK3528
Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 81195de60bc..432a8f8e03a 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_rxterm_set;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_txcomp_set;
+ struct combphy_reg pipe_clk_24m;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
@@ -245,6 +246,103 @@ static int rockchip_combphy_probe(struct udevice *udev)
return rockchip_combphy_parse_dt(udev, priv);
}
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ u32 val;
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + 0x200);
+ val &= ~GENMASK(17, 17);
+ val |= 0x01 << 17;
+ writel(val, priv->mmio + 0x200);
+
+ /* Set Rx squelch input filler bandwidth */
+ val = readl(priv->mmio + 0x20c);
+ val &= ~GENMASK(2, 0);
+ val |= 0x06;
+ writel(val, priv->mmio + 0x20c);
+
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
+ break;
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + 0x18);
+ val &= ~(0x7 << 10);
+ val |= 0x2 << 10;
+ writel(val, priv->mmio + 0x18);
+
+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+ val = readl(priv->mmio + 0x108);
+ val &= ~(0x7f7);
+ val |= 0x4f0;
+ writel(val, priv->mmio + 0x108);
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ /* pipe-grf */
+ .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+ .num_phys = 1,
+ .phy_ids = {
+ 0xffdc0000,
+ },
+ .grfcfg = &rk3528_combphy_grfcfgs,
+ .combphy_cfg = rk3528_combphy_cfg,
+};
+
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -503,6 +601,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
};
static const struct udevice_id rockchip_combphy_ids[] = {
+ {
+ .compatible = "rockchip,rk3528-naneng-combphy",
+ .data = (ulong)&rk3528_combphy_cfgs
+ },
{
.compatible = "rockchip,rk3568-naneng-combphy",
.data = (ulong)&rk3568_combphy_cfgs
--
2.34.1

61
projects/Rockchip/patches/u-boot/rockchip-0022-rockchip-rk3528-radxa-e20c-Enable-USB-gadget-Kconfig.patch Normal file
View File

@@ -0,0 +1,61 @@
From 5dff95a52ade3b461fab6608786ac92e8ac5a47f Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 30 Jul 2025 23:52:49 +0000
Subject: [PATCH 22/84] rockchip: rk3528-radxa-e20c: Enable USB gadget Kconfig
options
Radxa E20C has a USB OTG Type-C port for Debug and Data.
Add required Kconfig options to use USB gadget features once pending
USB nodes finally lands in dts/upstream by a future sync.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/radxa-e20c-rk3528_defconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
index f5e097f3edf..0941d1b9be8 100644
--- a/configs/radxa-e20c-rk3528_defconfig
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
@@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
@@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_PWM_ROCKCHIP=y
@@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
--
2.34.1

368
projects/Rockchip/patches/u-boot/rockchip-0023-HACK-rockchip-dts-upstream-use-v6.17-rockchip-dts64-.patch Normal file
View File

@@ -0,0 +1,368 @@
From 66aaba61526a93e9544e38206a77c8793bc74807 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 10:13:08 +0000
Subject: [PATCH 23/84] HACK: rockchip: dts/upstream: use
v6.17-rockchip-dts64-2 RK3528 DTs
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-pinctrl.dtsi | 20 +--
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 6 +
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 166 +++++++++++++++++-
3 files changed, 174 insertions(+), 18 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
index ea051362fb2..59b75c91bbb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
@@ -98,42 +98,42 @@
fephy {
/omit-if-no-ref/
- fephym0_led_dpx: fephym0-led_dpx {
+ fephym0_led_dpx: fephym0-led-dpx {
rockchip,pins =
/* fephy_led_dpx_m0 */
<4 RK_PB5 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym0_led_link: fephym0-led_link {
+ fephym0_led_link: fephym0-led-link {
rockchip,pins =
/* fephy_led_link_m0 */
<4 RK_PC0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym0_led_spd: fephym0-led_spd {
+ fephym0_led_spd: fephym0-led-spd {
rockchip,pins =
/* fephy_led_spd_m0 */
<4 RK_PB7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_dpx: fephym1-led_dpx {
+ fephym1_led_dpx: fephym1-led-dpx {
rockchip,pins =
/* fephy_led_dpx_m1 */
<2 RK_PA4 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_link: fephym1-led_link {
+ fephym1_led_link: fephym1-led-link {
rockchip,pins =
/* fephy_led_link_m1 */
<2 RK_PA6 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_spd: fephym1-led_spd {
+ fephym1_led_spd: fephym1-led-spd {
rockchip,pins =
/* fephy_led_spd_m1 */
<2 RK_PA5 5 &pcfg_pull_none>;
@@ -779,7 +779,7 @@
};
/omit-if-no-ref/
- rgmii_rx_bus2: rgmii-rx_bus2 {
+ rgmii_rx_bus2: rgmii-rx-bus2 {
rockchip,pins =
/* rgmii_rxd0 */
<3 RK_PA3 2 &pcfg_pull_none>,
@@ -790,7 +790,7 @@
};
/omit-if-no-ref/
- rgmii_tx_bus2: rgmii-tx_bus2 {
+ rgmii_tx_bus2: rgmii-tx-bus2 {
rockchip,pins =
/* rgmii_txd0 */
<3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
@@ -801,7 +801,7 @@
};
/omit-if-no-ref/
- rgmii_rgmii_clk: rgmii-rgmii_clk {
+ rgmii_rgmii_clk: rgmii-rgmii-clk {
rockchip,pins =
/* rgmii_rxclk */
<3 RK_PA5 2 &pcfg_pull_none>,
@@ -810,7 +810,7 @@
};
/omit-if-no-ref/
- rgmii_rgmii_bus: rgmii-rgmii_bus {
+ rgmii_rgmii_bus: rgmii-rgmii-bus {
rockchip,pins =
/* rgmii_rxd2 */
<3 RK_PA7 2 &pcfg_pull_none>,
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index 9f6ccd9dd1f..12eec2c1db2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -198,6 +198,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m0_xfer>;
@@ -278,6 +283,7 @@
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index d1c72b52aa4..001a555c83b 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -95,6 +95,36 @@
};
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ opp-suspend;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <950000 950000 1000000>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
@@ -439,13 +469,133 @@
reg = <0x0 0xff540000 0x0 0x40000>;
};
+ pmu: power-management@ff600000 {
+ compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff600000 0x0 0x2000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3528-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+ power-domain@4 {
+ reg = <4>;
+ clocks = <&cru ACLK_GPU_MALI>,
+ <&cru PCLK_GPU_ROOT>;
+ pm_qos = <&qos_gpu_m0>,
+ <&qos_gpu_m1>;
+ #power-domain-cells = <0>;
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@5 {
+ reg = <5>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@6 {
+ reg = <6>;
+ pm_qos = <&qos_rkvenc>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@7 {
+ reg = <7>;
+ pm_qos = <&qos_gmac0>,
+ <&qos_hdcp>,
+ <&qos_jpegdec>,
+ <&qos_rga2_m0ro>,
+ <&qos_rga2_m0wo>,
+ <&qos_sdmmc0>,
+ <&qos_usb2host>,
+ <&qos_vdpp>,
+ <&qos_vop>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@8 {
+ reg = <8>;
+ pm_qos = <&qos_emmc>,
+ <&qos_fspi>,
+ <&qos_gmac1>,
+ <&qos_pcie>,
+ <&qos_sdio0>,
+ <&qos_sdio1>,
+ <&qos_tsp>,
+ <&qos_usb3otg>,
+ <&qos_vpu>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gpu: gpu@ff700000 {
+ compatible = "rockchip,rk3528-mali", "arm,mali-450";
+ reg = <0x0 0xff700000 0x0 0x40000>;
+ assigned-clocks = <&cru ACLK_GPU_MALI>,
+ <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <297000000>, <300000000>;
+ clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
+ clock-names = "bus", "core";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power 4>;
+ resets = <&cru SRST_A_GPU>;
+ status = "disabled";
+ };
+
+ spi0: spi@ff9c0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
+ reg = <0x0 0xff9c0000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 25>, <&dmac 24>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@ff9d0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
+ reg = <0x0 0xff9d0000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 31>, <&dmac 30>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 8>, <&dmac 9>;
+ dmas = <&dmac 9>, <&dmac 8>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -457,7 +607,7 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 10>, <&dmac 11>;
+ dmas = <&dmac 11>, <&dmac 10>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -469,7 +619,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 12>, <&dmac 13>;
+ dmas = <&dmac 13>, <&dmac 12>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -481,7 +631,7 @@
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 14>, <&dmac 15>;
+ dmas = <&dmac 15>, <&dmac 14>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -493,7 +643,7 @@
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 16>, <&dmac 17>;
+ dmas = <&dmac 17>, <&dmac 16>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -505,7 +655,7 @@
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 18>, <&dmac 19>;
+ dmas = <&dmac 19>, <&dmac 18>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -517,7 +667,7 @@
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 20>, <&dmac 21>;
+ dmas = <&dmac 21>, <&dmac 20>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -529,7 +679,7 @@
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 22>, <&dmac 23>;
+ dmas = <&dmac 23>, <&dmac 22>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
--
2.34.1

35
projects/Rockchip/patches/u-boot/rockchip-0024-rockchip-rk3528-radxa-e20c-Drop-eMMC-HS200-prop-from.patch Normal file
View File

@@ -0,0 +1,35 @@
From f46aba244531135b5349418c5a1d386a5af54ee9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 15:23:27 +0000
Subject: [PATCH 24/84] rockchip: rk3528-radxa-e20c: Drop eMMC HS200 prop from
board u-boot.dtsi
The commit f8cb3fde935e ("arm: dts: rockchip: Fix eMMC write on RK3528")
added a missing mmc-hs200-1_8v prop to boart u-boot.dtsi.
Remove the mmc-hs200-1_8v proper now that the board dt from dts/upstream
have been fixed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
index 16c47e6b9a9..3e2fbd81da1 100644
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -2,10 +2,6 @@
#include "rk3528-u-boot.dtsi"
-&sdhci {
- mmc-hs200-1_8v;
-};
-
&vdd_arm {
regulator-init-microvolt = <953000>;
};
--
2.34.1

2246
projects/Rockchip/patches/u-boot/rockchip-0025-HACK-rockchip-dts-upstream-use-work-in-progress-RK35.patch Normal file
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File diff suppressed because it is too large Load Diff

87
projects/Rockchip/patches/u-boot/rockchip-0026-rockchip-rk3528-generic-Add-basic-support-for-USB-OT.patch Normal file
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@@ -0,0 +1,87 @@
From bc38f857e5ae6e1dd211151c6cbf458d8a878774 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 10:08:16 +0000
Subject: [PATCH 26/84] rockchip: rk3528-generic: Add basic support for USB OTG
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-generic.dts | 18 +++++++++++++++++-
configs/generic-rk3528_defconfig | 10 ++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
index 637ca03325e..e0bebf13286 100644
--- a/arch/arm/dts/rk3528-generic.dts
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3528 with eMMC and SD-card enabled
+ * Minimal generic DT for RK3528 with eMMC, SD-card and USB OTG enabled
*/
/dts-v1/;
@@ -40,8 +40,24 @@
status = "okay";
};
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/configs/generic-rk3528_defconfig b/configs/generic-rk3528_defconfig
index c989263e014..130aa124298 100644
--- a/configs/generic-rk3528_defconfig
+++ b/configs/generic-rk3528_defconfig
@@ -19,6 +19,8 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_RNG=y
# CONFIG_SPL_DOS_PARTITION is not set
@@ -26,6 +28,7 @@ CONFIG_CMD_RNG=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_NO_NET=y
# CONFIG_ADC is not set
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
@@ -33,7 +36,14 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
--
2.34.1

86
projects/Rockchip/patches/u-boot/rockchip-0027-rockchip-rk3528-Add-support-for-booting-from-SPI-fla.patch Normal file
View File

@@ -0,0 +1,86 @@
From 6f012de41460639e7efd9a6713ee3757b40a0c85 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 23 Jul 2025 22:22:36 +0000
Subject: [PATCH 27/84] rockchip: rk3528: Add support for booting from SPI
flash
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-u-boot.dtsi | 27 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3528/rk3528.c | 1 +
2 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
index a18d33b3d36..17a2d0ec3ff 100644
--- a/arch/arm/dts/rk3528-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -6,6 +6,7 @@
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
+ spi2 = &sfc;
};
chosen {
@@ -30,6 +31,17 @@
};
};
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
+};
+#endif
+
&cru {
bootph-all;
};
@@ -54,6 +66,16 @@
bootph-some-ram;
};
+&fspi_csn0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&fspi_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&gmac0_clk {
bootph-all;
};
@@ -115,6 +137,11 @@
bootph-some-ram;
};
+&sfc {
+ bootph-some-ram;
+ u-boot,spl-sfc-no-dma;
+};
+
&uart0 {
bootph-all;
clock-frequency = <24000000>;
diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
index f9bfc445b85..7ae8680fb04 100644
--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -20,6 +20,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
+ [BROM_BOOTSOURCE_SPINOR] = "/soc/spi@ffc00000/flash@0",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
};
--
2.34.1

171
projects/Rockchip/patches/u-boot/rockchip-0028-WIP-net-rockchip-Allow-use-of-rx-tx-delayline-for-rg.patch Normal file
View File

@@ -0,0 +1,171 @@
From 81809fd8f075a3fd12d7388d8222609f17fbc6f5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 27 Jul 2025 08:45:50 +0000
Subject: [PATCH 28/84] WIP: net: rockchip: Allow use of rx/tx delayline for
rgmii-id modes
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/net/dwc_eth_qos_rockchip.c | 24 +++++++---
drivers/net/gmac_rockchip.c | 74 +++++++++---------------------
2 files changed, 39 insertions(+), 59 deletions(-)
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index d646d3ebac8..3780d0f79a6 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -764,18 +764,30 @@ static int eqos_start_clks_rk(struct udevice *dev)
if (data->ops->set_clock_selection)
data->ops->set_clock_selection(dev, true);
- tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
- rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
+ tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
+ if (tx_delay == -ENOENT) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ tx_delay = 0;
+ else
+ tx_delay = 0x30;
+ }
+
+ rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
+ if (rx_delay == -ENOENT) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ rx_delay = 0;
+ else
+ rx_delay = 0x10;
+ }
switch (pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
- return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
case PHY_INTERFACE_MODE_RGMII_ID:
- return data->ops->set_to_rgmii(dev, 0, 0);
case PHY_INTERFACE_MODE_RGMII_RXID:
- return data->ops->set_to_rgmii(dev, tx_delay, 0);
case PHY_INTERFACE_MODE_RGMII_TXID:
- return data->ops->set_to_rgmii(dev, 0, rx_delay);
+ return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
case PHY_INTERFACE_MODE_RMII:
return data->ops->set_to_rmii(dev);
}
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c8cfe7448d4..fa246ec374b 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -54,6 +54,7 @@ struct rk_gmac_ops {
static int gmac_rockchip_of_to_plat(struct udevice *dev)
{
struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
+ struct eth_pdata *eth_pdata = &pdata->dw_eth_pdata.eth_pdata;
const char *string;
string = dev_read_string(dev, "clock_in_out");
@@ -62,15 +63,25 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
else
pdata->clock_input = false;
- /* Check the new naming-style first... */
+ eth_pdata->phy_interface = dev_read_phy_mode(dev);
+
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
- pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
+ if (pdata->tx_delay == -ENOENT) {
+ if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ pdata->tx_delay = 0;
+ else
+ pdata->tx_delay = 0x30;
+ }
- /* ... and fall back to the old naming style or default, if necessary */
- if (pdata->tx_delay == -ENOENT)
- pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
- if (pdata->rx_delay == -ENOENT)
- pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
+ pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
+ if (pdata->rx_delay == -ENOENT) {
+ if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ pdata->rx_delay = 0;
+ else
+ pdata->rx_delay = 0x10;
+ }
return designware_eth_of_to_plat(dev);
}
@@ -608,6 +619,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
switch (eth_pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set to RGMII mode */
if (ops->set_to_rgmii)
ops->set_to_rgmii(pdata);
@@ -628,22 +642,6 @@ static int gmac_rockchip_probe(struct udevice *dev)
}
break;
- case PHY_INTERFACE_MODE_RGMII_ID:
- /* Set to RGMII mode */
- if (ops->set_to_rgmii) {
- pdata->tx_delay = 0;
- pdata->rx_delay = 0;
- ops->set_to_rgmii(pdata);
- } else
- return -EPERM;
-
- if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 125000000);
- if (rate != 125000000)
- return -EINVAL;
- }
- break;
-
case PHY_INTERFACE_MODE_RMII:
/* Set to RMII mode */
if (ops->set_to_rmii)
@@ -658,36 +656,6 @@ static int gmac_rockchip_probe(struct udevice *dev)
}
break;
- case PHY_INTERFACE_MODE_RGMII_RXID:
- /* Set to RGMII_RXID mode */
- if (ops->set_to_rgmii) {
- pdata->tx_delay = 0;
- ops->set_to_rgmii(pdata);
- } else
- return -EPERM;
-
- if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 125000000);
- if (rate != 125000000)
- return -EINVAL;
- }
- break;
-
- case PHY_INTERFACE_MODE_RGMII_TXID:
- /* Set to RGMII_TXID mode */
- if (ops->set_to_rgmii) {
- pdata->rx_delay = 0;
- ops->set_to_rgmii(pdata);
- } else
- return -EPERM;
-
- if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 125000000);
- if (rate != 125000000)
- return -EINVAL;
- }
- break;
-
default:
debug("NO interface defined!\n");
return -ENXIO;
--
2.34.1

49
projects/Rockchip/patches/u-boot/rockchip-0029-WIP-net-rockchip-Use-CRU-as-default-TX-clk-source-fo.patch Normal file
View File

@@ -0,0 +1,49 @@
From c95d9d8bb9c312e78c3027fb89139200c5421bfb Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 27 Jul 2025 08:46:40 +0000
Subject: [PATCH 29/84] WIP: net: rockchip Use CRU as default TX clk source for
RGMII modes
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/net/dwc_eth_qos_rockchip.c | 6 +++++-
drivers/net/gmac_rockchip.c | 2 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index 3780d0f79a6..d510db99e1e 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -678,11 +678,15 @@ static int eqos_probe_resources_rk(struct udevice *dev)
}
clock_in_out = dev_read_string(dev, "clock_in_out");
- if (clock_in_out && !strcmp(clock_in_out, "input"))
+ if (!clock_in_out || !strcmp(clock_in_out, "input"))
data->clock_input = true;
else
data->clock_input = false;
+ if (pdata->phy_interface >= PHY_INTERFACE_MODE_RGMII &&
+ pdata->phy_interface <= PHY_INTERFACE_MODE_RGMII_TXID)
+ data->clock_input = false;
+
/* snps,reset props are deprecated, do bare minimum to support them */
if (dev_read_bool(dev, "snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index fa246ec374b..0d92b4ad631 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -58,7 +58,7 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
const char *string;
string = dev_read_string(dev, "clock_in_out");
- if (!strcmp(string, "input"))
+ if (!string || !strcmp(string, "input"))
pdata->clock_input = true;
else
pdata->clock_input = false;
--
2.34.1

342
projects/Rockchip/patches/u-boot/rockchip-0030-WIP-board-rockchip-Add-Radxa-ROCK-2A-2F.patch Normal file
View File

@@ -0,0 +1,342 @@
From 69af49f3e3f54baf88b09a003f33c9bcc04c2ae2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 12 Mar 2025 00:13:48 +0000
Subject: [PATCH 30/84] WIP: board: rockchip: Add Radxa ROCK 2A/2F
Features tested on a ROCK 2A v1.202:
- SD-card boot
- Ethernet
- USB host
Features tested on a ROCK 2F v1.016:
- SD-card boot
- eMMC boot
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 5 ++
arch/arm/dts/rk3528-rock-2-u-boot.dtsi | 16 +++++
arch/arm/dts/rk3528-rock-2a-u-boot.dtsi | 3 +
arch/arm/dts/rk3528-rock-2f-u-boot.dtsi | 3 +
arch/arm/mach-rockchip/rk3528/Kconfig | 7 +++
board/radxa/rock-2-rk3528/Kconfig | 14 +++++
board/radxa/rock-2-rk3528/MAINTAINERS | 6 ++
board/radxa/rock-2-rk3528/Makefile | 3 +
board/radxa/rock-2-rk3528/rock-2-rk3528.c | 60 +++++++++++++++++++
configs/radxa-e20c-rk3528_defconfig | 3 +
configs/rock-2-rk3528_defconfig | 68 ++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
12 files changed, 189 insertions(+)
create mode 100644 arch/arm/dts/rk3528-rock-2-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-rock-2f-u-boot.dtsi
create mode 100644 board/radxa/rock-2-rk3528/Kconfig
create mode 100644 board/radxa/rock-2-rk3528/MAINTAINERS
create mode 100644 board/radxa/rock-2-rk3528/Makefile
create mode 100644 board/radxa/rock-2-rk3528/rock-2-rk3528.c
create mode 100644 configs/rock-2-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
index 3e2fbd81da1..e8c8dc2f032 100644
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -2,6 +2,11 @@
#include "rk3528-u-boot.dtsi"
+&saradc {
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
+};
+
&vdd_arm {
regulator-init-microvolt = <953000>;
};
diff --git a/arch/arm/dts/rk3528-rock-2-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi
new file mode 100644
index 00000000000..e8c8dc2f032
--- /dev/null
+++ b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&saradc {
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
+};
+
+&vdd_arm {
+ regulator-init-microvolt = <953000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
+};
diff --git a/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
new file mode 100644
index 00000000000..bd35ef88298
--- /dev/null
+++ b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-rock-2-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi
new file mode 100644
index 00000000000..bd35ef88298
--- /dev/null
+++ b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-rock-2-u-boot.dtsi"
diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig
index 993b2dd274e..480ac2942ff 100644
--- a/arch/arm/mach-rockchip/rk3528/Kconfig
+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -1,5 +1,10 @@
if ROCKCHIP_RK3528
+config TARGET_RADXA_ROCK_2_RK3528
+ bool "Radxa ROCK 2A/2F"
+ help
+ Radxa ROCK 2A/2F single board computers with a RK3528A SoC.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff370200
@@ -9,6 +14,8 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "rk3528"
+source "board/radxa/rock-2-rk3528/Kconfig"
+
config SYS_CONFIG_NAME
default "rk3528_common"
diff --git a/board/radxa/rock-2-rk3528/Kconfig b/board/radxa/rock-2-rk3528/Kconfig
new file mode 100644
index 00000000000..5f1ad10c0ed
--- /dev/null
+++ b/board/radxa/rock-2-rk3528/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_RADXA_ROCK_2_RK3528
+
+config SYS_BOARD
+ default "rock-2-rk3528"
+
+config SYS_VENDOR
+ default "radxa"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ADC
+ select SPL_ADC
+
+endif
diff --git a/board/radxa/rock-2-rk3528/MAINTAINERS b/board/radxa/rock-2-rk3528/MAINTAINERS
new file mode 100644
index 00000000000..841bd28450f
--- /dev/null
+++ b/board/radxa/rock-2-rk3528/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA-ROCK-2-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/radxa/rock-2-rk3528
+F: configs/rock-2-rk3528_defconfig
+F: arch/arm/dts/rk3528-rock-2*
diff --git a/board/radxa/rock-2-rk3528/Makefile b/board/radxa/rock-2-rk3528/Makefile
new file mode 100644
index 00000000000..b3e0ad0b540
--- /dev/null
+++ b/board/radxa/rock-2-rk3528/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += rock-2-rk3528.o
diff --git a/board/radxa/rock-2-rk3528/rock-2-rk3528.c b/board/radxa/rock-2-rk3528/rock-2-rk3528.c
new file mode 100644
index 00000000000..2d265b67f0d
--- /dev/null
+++ b/board/radxa/rock-2-rk3528/rock-2-rk3528.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <adc.h>
+#include <env.h>
+
+#define HW_ID_CHANNEL 2
+
+struct board_model {
+ unsigned int low;
+ unsigned int high;
+ const char *fdtfile;
+};
+
+static const struct board_model board_models[] = {
+ { 63, 278, "rockchip/rk3528-rock-2a.dtb" },
+ { 291, 392, "rockchip/rk3528-radxa-e20c.dtb" },
+ { 519, 733, "rockchip/rk3528-rock-2f.dtb" },
+};
+
+static const struct board_model *get_board_model(void)
+{
+ unsigned int val;
+ int i, ret;
+
+ ret = adc_channel_single_shot("adc@ffae0000", HW_ID_CHANNEL, &val);
+ if (ret)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(board_models); i++) {
+ unsigned int min = board_models[i].low;
+ unsigned int max = board_models[i].high;
+
+ if (min <= val && val <= max)
+ return &board_models[i];
+ }
+
+ return NULL;
+}
+
+int rk_board_late_init(void)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model)
+ env_set("fdtfile", model->fdtfile);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model && !strcmp(name, model->fdtfile))
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
index 0941d1b9be8..fa20424ee7b 100644
--- a/configs/radxa-e20c-rk3528_defconfig
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -4,12 +4,14 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
CONFIG_ROCKCHIP_RK3528=y
+CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART_BASE=0xFF9F0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_MEMINFO=y
@@ -26,6 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_LIST="rockchip/rk3528-radxa-e20c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
diff --git a/configs/rock-2-rk3528_defconfig b/configs/rock-2-rk3528_defconfig
new file mode 100644
index 00000000000..b9261de460b
--- /dev/null
+++ b/configs/rock-2-rk3528_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-rock-2a"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-rock-2a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_LIST="rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f rockchip/rk3528-radxa-e20c"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index b88299cbba2..263291884b0 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -102,6 +102,7 @@ List of mainline supported Rockchip boards:
* rk3528
- Generic RK3528 (generic-rk3528)
- Radxa E20C (radxa-e20c-rk3528)
+ - Radxa ROCK 2A/2F (rock-2-rk3528)
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
--
2.34.1

138
projects/Rockchip/patches/u-boot/rockchip-0031-WIP-board-rockchip-Add-ArmSoM-Sige1.patch Normal file
View File

@@ -0,0 +1,138 @@
From 9911469f091441d62832338bce312b3c2bab1434 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 12 Mar 2025 00:30:54 +0000
Subject: [PATCH 31/84] WIP: board: rockchip: Add ArmSoM Sige1
Features tested on a ArmSoM Sige1 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi | 11 ++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 ++
configs/sige1-rk3528_defconfig | 65 ++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 83 insertions(+)
create mode 100644 arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi
create mode 100644 configs/sige1-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi
new file mode 100644
index 00000000000..3e2fbd81da1
--- /dev/null
+++ b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&vdd_arm {
+ regulator-init-microvolt = <953000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
+};
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
index f343f71cf7f..ee840396e8b 100644
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -9,3 +9,9 @@ M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3528-radxa-e20c*
F: configs/radxa-e20c-rk3528_defconfig
+
+SIGE1-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-armsom-sige1*
+F: configs/sige1-rk3528_defconfig
diff --git a/configs/sige1-rk3528_defconfig b/configs/sige1-rk3528_defconfig
new file mode 100644
index 00000000000..6061427ce94
--- /dev/null
+++ b/configs/sige1-rk3528_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-armsom-sige1"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-armsom-sige1.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 263291884b0..d2ff8653e2a 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -100,6 +100,7 @@ List of mainline supported Rockchip boards:
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
* rk3528
+ - ArmSoM Sige1 (sige1-rk3528)
- Generic RK3528 (generic-rk3528)
- Radxa E20C (radxa-e20c-rk3528)
- Radxa ROCK 2A/2F (rock-2-rk3528)
--
2.34.1

141
projects/Rockchip/patches/u-boot/rockchip-0032-WIP-board-rockchip-Add-FriendlyElec-NanoPi-Zero2.patch Normal file
View File

@@ -0,0 +1,141 @@
From bdd09deddc01633c4bfc3be932b8b865003211b5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 17 Mar 2025 00:29:24 +0000
Subject: [PATCH 32/84] WIP: board: rockchip: Add FriendlyElec NanoPi Zero2
Features tested on a FriendlyElec NanoPi Zero2 2407:
- SD-card boot
- eMMC boot
- Ethernet
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi | 11 ++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 ++
configs/nanopi-zero2-rk3528_defconfig | 65 ++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 83 insertions(+)
create mode 100644 arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi
create mode 100644 configs/nanopi-zero2-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi
new file mode 100644
index 00000000000..3e2fbd81da1
--- /dev/null
+++ b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&vdd_arm {
+ regulator-init-microvolt = <953000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
+};
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
index ee840396e8b..111fe0270df 100644
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -4,6 +4,12 @@ S: Maintained
F: arch/arm/dts/rk3528-generic*
F: configs/generic-rk3528_defconfig
+NANOPI-ZERO2-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-nanopi-zero2*
+F: configs/nanopi-zero2-rk3528_defconfig
+
RADXA-E20C
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/configs/nanopi-zero2-rk3528_defconfig b/configs/nanopi-zero2-rk3528_defconfig
new file mode 100644
index 00000000000..0913f6cc195
--- /dev/null
+++ b/configs/nanopi-zero2-rk3528_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-nanopi-zero2"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-nanopi-zero2.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index d2ff8653e2a..1e46f2b5619 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -101,6 +101,7 @@ List of mainline supported Rockchip boards:
* rk3528
- ArmSoM Sige1 (sige1-rk3528)
+ - FriendlyElec NanoPi Zero2 (nanopi-zero2-rk3528)
- Generic RK3528 (generic-rk3528)
- Radxa E20C (radxa-e20c-rk3528)
- Radxa ROCK 2A/2F (rock-2-rk3528)
--
2.34.1

358
projects/Rockchip/patches/u-boot/rockchip-0033-WIP-board-rockchip-Add-Radxa-E24C.patch Normal file
View File

@@ -0,0 +1,358 @@
From 4a14e69f721fbc3843c2a3e8207576bbb6133816 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 23 Jul 2025 22:25:26 +0000
Subject: [PATCH 33/84] WIP: board: rockchip: Add Radxa E24C
Features tested on a E24C v1.203 (D4E0S16):
- SD-card boot
- SPI flash boot
- LEDs and buttons
- PCIe/NVMe
- USB host
- USB gadget
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3528-radxa-e24c-u-boot.dtsi | 23 ++++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 ++
board/radxa/rock-2-rk3528/rock-2-rk3528.c | 1 +
configs/radxa-e20c-rk3528_defconfig | 20 ++++-
configs/radxa-e24c-rk3528_defconfig | 87 ++++++++++++++++++++++
configs/rock-2-rk3528_defconfig | 20 ++++-
doc/board/rockchip/rockchip.rst | 1 +
7 files changed, 156 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/rk3528-radxa-e24c-u-boot.dtsi
create mode 100644 configs/radxa-e24c-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-radxa-e24c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e24c-u-boot.dtsi
new file mode 100644
index 00000000000..d3eb0e109fe
--- /dev/null
+++ b/arch/arm/dts/rk3528-radxa-e24c-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&saradc {
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
+};
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+
+&vdd_arm {
+ regulator-init-microvolt = <950000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
+};
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
index 111fe0270df..627d81ac106 100644
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -16,6 +16,12 @@ S: Maintained
F: arch/arm/dts/rk3528-radxa-e20c*
F: configs/radxa-e20c-rk3528_defconfig
+RADXA-E24C
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-radxa-e24c*
+F: configs/radxa-e24c-rk3528_defconfig
+
SIGE1-RK3528
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/board/radxa/rock-2-rk3528/rock-2-rk3528.c b/board/radxa/rock-2-rk3528/rock-2-rk3528.c
index 2d265b67f0d..7c0148965e0 100644
--- a/board/radxa/rock-2-rk3528/rock-2-rk3528.c
+++ b/board/radxa/rock-2-rk3528/rock-2-rk3528.c
@@ -17,6 +17,7 @@ static const struct board_model board_models[] = {
{ 63, 278, "rockchip/rk3528-rock-2a.dtb" },
{ 291, 392, "rockchip/rk3528-radxa-e20c.dtb" },
{ 519, 733, "rockchip/rk3528-rock-2f.dtb" },
+ { 745, 846, "rockchip/rk3528-radxa-e24c.dtb" },
};
static const struct board_model *get_board_model(void)
diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
index fa20424ee7b..93b4ca91302 100644
--- a/configs/radxa-e20c-rk3528_defconfig
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -2,18 +2,26 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
CONFIG_ROCKCHIP_RK3528=y
CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_DEBUG_UART_BASE=0xFF9F0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_ADC=y
@@ -21,6 +29,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -28,13 +37,14 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_OF_LIST="rockchip/rk3528-radxa-e20c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f"
+CONFIG_OF_LIST="rockchip/rk3528-radxa-e20c rockchip/rk3528-radxa-e24c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
@@ -43,19 +53,27 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/radxa-e24c-rk3528_defconfig b/configs/radxa-e24c-rk3528_defconfig
new file mode 100644
index 00000000000..32e68ecfc08
--- /dev/null
+++ b/configs/radxa-e24c-rk3528_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e24c"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e24c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_LIST="rockchip/rk3528-radxa-e24c rockchip/rk3528-radxa-e20c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock-2-rk3528_defconfig b/configs/rock-2-rk3528_defconfig
index b9261de460b..06cc6c3d5e7 100644
--- a/configs/rock-2-rk3528_defconfig
+++ b/configs/rock-2-rk3528_defconfig
@@ -2,18 +2,26 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-rock-2a"
CONFIG_ROCKCHIP_RK3528=y
CONFIG_TARGET_RADXA_ROCK_2_RK3528=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_DEBUG_UART_BASE=0xFF9F0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-rock-2a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_ADC=y
@@ -21,6 +29,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -28,13 +37,14 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_OF_LIST="rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f rockchip/rk3528-radxa-e20c"
+CONFIG_OF_LIST="rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f rockchip/rk3528-radxa-e20c rockchip/rk3528-radxa-e24c"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
@@ -43,19 +53,27 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 1e46f2b5619..4072a7b058b 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -104,6 +104,7 @@ List of mainline supported Rockchip boards:
- FriendlyElec NanoPi Zero2 (nanopi-zero2-rk3528)
- Generic RK3528 (generic-rk3528)
- Radxa E20C (radxa-e20c-rk3528)
+ - Radxa E24C (radxa-e24c-rk3528)
- Radxa ROCK 2A/2F (rock-2-rk3528)
* rk3566
--
2.34.1

24
projects/Rockchip/patches/u-boot/rockchip-0034-HACK-use-usb3-host-mode-on-rock-2a.patch Normal file
View File

@@ -0,0 +1,24 @@
From b820293e44501010c656d7e1941f910dfc5c7c89 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 13:11:09 +0000
Subject: [PATCH 34/84] HACK: use usb3 host mode on rock-2a
---
arch/arm/dts/rk3528-rock-2a-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
index bd35ef88298..7208dfcfda8 100644
--- a/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi
@@ -1,3 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3528-rock-2-u-boot.dtsi"
+
+&usb_host0_xhci {
+ dr_mode = "host";
+};
--
2.34.1

57
projects/Rockchip/patches/u-boot/rockchip-0035-rockchip-sdram-Add-rockchip_sdram_type-helper.patch Normal file
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@@ -0,0 +1,57 @@
From df76b4ebfb1fa9d600d5e28dba5c4a9a1f3b30fd Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 20 Jul 2025 13:07:25 +0000
Subject: [PATCH 35/84] rockchip: sdram: Add rockchip_sdram_type() helper
Add a helper function based on rockchip_sdram_size() that return what
DRAM type is used on current running board.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/include/asm/arch-rockchip/sdram.h | 3 +++
arch/arm/mach-rockchip/sdram.c | 15 +++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index 4fb45ac5c76..476fc1c4ee3 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -87,6 +87,9 @@ enum {
#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
#define SYS_REG_CS1_COL_MASK 3
+/* Get sdram type decode from reg */
+u8 rockchip_sdram_type(phys_addr_t reg);
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 3bc482331c7..d560f90e873 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -345,6 +345,21 @@ int dram_init_banksize(void)
return 0;
}
+u8 rockchip_sdram_type(phys_addr_t reg)
+{
+ u32 dram_type, version;
+ u32 sys_reg2 = readl(reg);
+ u32 sys_reg3 = readl(reg + 4);
+
+ dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
+ version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
+ if (version >= 3)
+ dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
+ SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
+
+ return dram_type;
+}
+
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
--
2.34.1

189
projects/Rockchip/patches/u-boot/rockchip-0036-rockchip-rock5b-rk3588-Add-support-for-ROCK-5B.patch Normal file
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@@ -0,0 +1,189 @@
From 0e8492adb9af36ec07969652638295b92e662840 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 14 Jul 2025 19:08:46 +0000
Subject: [PATCH 36/84] rockchip: rock5b-rk3588: Add support for ROCK 5B+
Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
value is close to 4095.
U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000)
Model: Radxa ROCK 5B+
SoC: RK3588
DRAM: 8 GiB
Features tested on a ROCK 5B+ v1.2:
- SD-card boot
- eMMC boot
- SPI flash boot
- PCIe/NVMe
- Ethernet
- USB/TCPM
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi | 3 +
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 5 ++
board/radxa/rock5b-rk3588/Kconfig | 5 ++
board/radxa/rock5b-rk3588/MAINTAINERS | 3 +-
board/radxa/rock5b-rk3588/rock5b-rk3588.c | 63 ++++++++++++++++++++
configs/rock5b-rk3588_defconfig | 1 +
doc/board/rockchip/rockchip.rst | 2 +-
7 files changed, 79 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
new file mode 100644
index 00000000000..c07696c8391
--- /dev/null
+++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-rock-5b-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index d51fbf51cb8..e07b549c767 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -46,6 +46,11 @@
};
};
+&saradc {
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
+};
+
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
index 41dfe2402b1..98d63011783 100644
--- a/board/radxa/rock5b-rk3588/Kconfig
+++ b/board/radxa/rock5b-rk3588/Kconfig
@@ -9,4 +9,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock5b-rk3588"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ADC
+ select SPL_ADC
+
endif
diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
index 4460c9971a9..c8a43769105 100644
--- a/board/radxa/rock5b-rk3588/MAINTAINERS
+++ b/board/radxa/rock5b-rk3588/MAINTAINERS
@@ -5,5 +5,4 @@ S: Maintained
F: board/radxa/rock5b-rk3588
F: include/configs/rock5b-rk3588.h
F: configs/rock5b-rk3588_defconfig
-F: arch/arm/dts/rk3588-rock-5b.dts
-F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+F: arch/arm/dts/rk3588-rock-5b*
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
index fc2f69db224..6bf4497ce3a 100644
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
@@ -3,8 +3,71 @@
* Copyright (c) 2023-2024 Collabora Ltd.
*/
+#include <adc.h>
+#include <env.h>
#include <fdtdec.h>
#include <fdt_support.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <linux/errno.h>
+
+#define PMU1GRF_BASE 0xfd58a000
+#define OS_REG2_REG 0x208
+
+#define HW_ID_CHANNEL 5
+
+struct board_model {
+ unsigned int dram;
+ unsigned int low;
+ unsigned int high;
+ const char *fdtfile;
+};
+
+static const struct board_model board_models[] = {
+ { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
+};
+
+static const struct board_model *get_board_model(void)
+{
+ unsigned int val, dram_type;
+ int i, ret;
+
+ dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
+
+ ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
+ if (ret)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(board_models); i++) {
+ unsigned int dram = board_models[i].dram;
+ unsigned int min = board_models[i].low;
+ unsigned int max = board_models[i].high;
+
+ if (dram == dram_type && min <= val && val <= max)
+ return &board_models[i];
+ }
+
+ return NULL;
+}
+
+int rk_board_late_init(void)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model)
+ env_set("fdtfile", model->fdtfile);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model && !strcmp(name, model->fdtfile))
+ return 0;
+
+ return -EINVAL;
+}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 6349e879145..967cebc2054 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 4072a7b058b..347c344a7c5 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -156,7 +156,7 @@ List of mainline supported Rockchip boards:
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- - Radxa ROCK 5B (rock5b-rk3588)
+ - Radxa ROCK 5B/5B+ (rock5b-rk3588)
- Radxa ROCK 5C (rock-5c-rk3588s)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
--
2.34.1

42
projects/Rockchip/patches/u-boot/rockchip-0037-rng-rockchip_rng-Add-compatible-for-RK3576.patch Normal file
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@@ -0,0 +1,42 @@
From 90a310f17ea0f5066a957f3f4c94b7566135a1ba Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:21:17 +0000
Subject: [PATCH 37/84] rng: rockchip_rng: Add compatible for RK3576
The RK3576 SoC contains a RKRNG block that can be used to generate
random numbers using the rockchip_rng driver.
Add compatible for RK3576 to support random numbers:
=> rng list
RNG #0 - rng@2a410000
=> rng
00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90 6........6...=..
00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a ...uk'H..b.lP.G.
00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a .M.C..-..'.&.ia*
00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5 op..N..zZl|.C.>.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/rng/rockchip_rng.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index d854ea90044..8cf750e043c 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -393,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = {
.compatible = "rockchip,rk3588-rng",
.data = (ulong)&rk_trngv1_soc_data,
},
+ {
+ .compatible = "rockchip,rk3576-rng",
+ .data = (ulong)&rkrng_soc_data,
+ },
{
.compatible = "rockchip,rkrng",
.data = (ulong)&rkrng_soc_data,
--
2.34.1

28
projects/Rockchip/patches/u-boot/rockchip-0038-rockchip-Add-default-USB_GADGET_PRODUCT_NUM-for-RK35.patch Normal file
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@@ -0,0 +1,28 @@
From faefa832fa5e175ff2c548469dcc148b12ac9c6a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:21:18 +0000
Subject: [PATCH 38/84] rockchip: Add default USB_GADGET_PRODUCT_NUM for RK3576
Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID
being used by the BootROM when the device is in MASKROM mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/usb/gadget/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 46a83141481..bab88567ea6 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM
default 0x350a if ROCKCHIP_RK3568
default 0x350b if ROCKCHIP_RK3588
default 0x350c if ROCKCHIP_RK3528
+ default 0x350e if ROCKCHIP_RK3576
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
--
2.34.1

190
projects/Rockchip/patches/u-boot/rockchip-0039-board-rockchip-Add-minimal-generic-RK3576-board.patch Normal file
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@@ -0,0 +1,190 @@
From 2a37796ed7fb46db2f44ce296e9d5c15781161b3 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:21:19 +0000
Subject: [PATCH 39/84] board: rockchip: Add minimal generic RK3576 board
Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
most RK3576 boards that follow reference board design.
eMMC and SD-card boot tested on:
- ArmSoM CM5
- ArmSoM Sige5
- FriendlyElec NanoPi M5
- Luckfox Omni3576
- Toybrick TB-RK3576D
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3576-generic-u-boot.dtsi | 3 ++
arch/arm/dts/rk3576-generic.dts | 63 +++++++++++++++++++++++
arch/arm/mach-rockchip/rk3576/MAINTAINERS | 5 ++
configs/generic-rk3576_defconfig | 50 ++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
5 files changed, 122 insertions(+)
create mode 100644 arch/arm/dts/rk3576-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3576-generic.dts
create mode 100644 arch/arm/mach-rockchip/rk3576/MAINTAINERS
create mode 100644 configs/generic-rk3576_defconfig
diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi
new file mode 100644
index 00000000000..632fabb6af5
--- /dev/null
+++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts
new file mode 100644
index 00000000000..123be5378d9
--- /dev/null
+++ b/arch/arm/dts/rk3576-generic.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3576.dtsi"
+
+/ {
+ model = "Generic RK3576";
+ compatible = "rockchip,rk3576";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+&usb_drd0_dwc3 {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
new file mode 100644
index 00000000000..b5190c81846
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -0,0 +1,5 @@
+GENERIC-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-generic*
+F: configs/generic-rk3576_defconfig
diff --git a/configs/generic-rk3576_defconfig b/configs/generic-rk3576_defconfig
new file mode 100644
index 00000000000..5e25653820c
--- /dev/null
+++ b/configs/generic-rk3576_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 347c344a7c5..54fa941f236 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -139,6 +139,7 @@ List of mainline supported Rockchip boards:
* rk3576
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
+ - Generic RK3576 (generic-rk3576)
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
--
2.34.1

88
projects/Rockchip/patches/u-boot/rockchip-0040-rockchip-rk3576-Implement-checkboard-to-print-SoC-va.patch Normal file
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@@ -0,0 +1,88 @@
From 9cebb3ad5497aba16f3b2575cafe17fd9477e8f7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:21:20 +0000
Subject: [PATCH 40/84] rockchip: rk3576: Implement checkboard() to print SoC
variant
Implement checkboard() to print current SoC model used by a board when
U-Boot proper is running.
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Information about the SoC model and variant is read from OTP.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/rk3576/rk3576.c | 48 ++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
index dc53941ab2f..a6c2fbdc484 100644
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -3,6 +3,10 @@
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
@@ -159,3 +163,47 @@ int arch_cpu_init(void)
return 0;
}
+
+#define RK3576_OTP_CPU_CODE_OFFSET 0x02
+#define RK3576_OTP_SPECIFICATION_OFFSET 0x08
+
+int checkboard(void)
+{
+ u8 cpu_code[2], specification;
+ struct udevice *dev;
+ char suffix[2];
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x76 */
+ ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* specification: SoC variant, e.g. 0xA for RK3576J */
+ ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+ specification &= 0x1f;
+
+ /* for RK3576J i.e. '@' + 0xA = 'J' */
+ suffix[0] = specification > 1 ? '@' + specification : '\0';
+ suffix[1] = '\0';
+
+ printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
+ return 0;
+}
--
2.34.1

39
projects/Rockchip/patches/u-boot/rockchip-0041-arm-dts-rockchip-Include-OTP-in-U-Boot-pre-reloc-pha.patch Normal file
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@@ -0,0 +1,39 @@
From 069af748f2441fac896b353b1d009d57c216a609 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:21:21 +0000
Subject: [PATCH 41/84] arm: dts: rockchip: Include OTP in U-Boot pre-reloc
phase for RK3576
Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3576-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
index be99a48a630..fb5a107f47d 100644
--- a/arch/arm/dts/rk3576-u-boot.dtsi
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -49,6 +49,10 @@
bootph-all;
};
+&otp {
+ bootph-some-ram;
+};
+
&pcfg_pull_none {
bootph-all;
};
--
2.34.1

31
projects/Rockchip/patches/u-boot/rockchip-0042-usb-dwc3-generic-Use-combined-glue-and-ctrl-node-for.patch Normal file
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@@ -0,0 +1,31 @@
From efb11d2b75da04c2e5ddc257989881248adb9f65 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 16 Feb 2025 19:17:20 +0000
Subject: [PATCH 42/84] usb: dwc3-generic: Use combined glue and ctrl node for
RK3576
Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single
node to represent the glue and ctrl for USB 3.0.
Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/usb/dwc3/dwc3-generic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 6b2016c0cd3..c09014aec60 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -700,6 +700,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
+ { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
--
2.34.1

62
projects/Rockchip/patches/u-boot/rockchip-0043-phy-rockchip-inno-usb2-Add-support-for-RK3576.patch Normal file
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@@ -0,0 +1,62 @@
From 8f79cc0dc08fe79eec426dbf15d48ff71e848749 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Wed, 5 Feb 2025 01:00:33 +0000
Subject: [PATCH 43/84] phy: rockchip-inno-usb2: Add support for RK3576
Add support for the USB2.0 PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index a3222138b9d..4ea6600ce7f 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -465,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
+ {
+ .reg = 0x0000,
+ .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0000, 1, 0, 2, 1 },
+ }
+ },
+ },
+ {
+ .reg = 0x2000,
+ .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x2000, 1, 0, 2, 1 },
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
{
.reg = 0x0000,
@@ -526,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
.compatible = "rockchip,rk3568-usb2phy",
.data = (ulong)&rk3568_phy_cfgs,
},
+ {
+ .compatible = "rockchip,rk3576-usb2phy",
+ .data = (ulong)&rk3576_phy_cfgs,
+ },
{
.compatible = "rockchip,rk3588-usb2phy",
.data = (ulong)&rk3588_phy_cfgs,
--
2.34.1

62
projects/Rockchip/patches/u-boot/rockchip-0044-phy-rockchip-usbdp-Add-support-for-RK3576.patch Normal file
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@@ -0,0 +1,62 @@
From c239806d4c322c24938880467e30eb1244955a73 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Thu, 10 Jul 2025 20:33:58 +0000
Subject: [PATCH 44/84] phy: rockchip: usbdp: Add support for RK3576
Add support for the USB3.0+DP PHY used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 6cfbef02b4a..cca67dd3611 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -762,6 +762,28 @@ static const char * const rk3588_udphy_rst_l[] = {
"init", "cmn", "lane", "pcs_apb", "pma_apb"
};
+static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = {
+ .num_phys = 1,
+ .phy_ids = {
+ 0x2b010000,
+ },
+ .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
+ .rst_list = rk3588_udphy_rst_l,
+ .grfcfg = {
+ /* u2phy-grf */
+ .bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 },
+ .bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 },
+
+ /* usb-grf */
+ .usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 },
+
+ /* usbdpphy-grf */
+ .low_pwrn = { 0x0004, 13, 13, 0, 1 },
+ .rx_lfps = { 0x0004, 14, 14, 0, 1 },
+ },
+ .combophy_init = rk3588_udphy_init,
+};
+
static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
.num_phys = 2,
.phy_ids = {
@@ -787,6 +809,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
};
static const struct udevice_id rockchip_udphy_dt_match[] = {
+ {
+ .compatible = "rockchip,rk3576-usbdp-phy",
+ .data = (ulong)&rk3576_udphy_cfgs
+ },
{
.compatible = "rockchip,rk3588-usbdp-phy",
.data = (ulong)&rk3588_udphy_cfgs
--
2.34.1

30
projects/Rockchip/patches/u-boot/rockchip-0045-rockchip-clk-clk_rk3576-Add-dummy-CLK_REF_PCIEx_PHY-.patch Normal file
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@@ -0,0 +1,30 @@
From 59e0942f5cb2c61521bf740e6fcd1270072cf65a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:44:34 +0000
Subject: [PATCH 45/84] rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY
support
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/clk/rockchip/clk_rk3576.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index e84a0943a94..125b08ee832 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
case CLK_CPLL_DIV10:
case FCLK_DDR_CM0_CORE:
case ACLK_PHP_ROOT:
+ case CLK_REF_PCIE0_PHY:
+ case CLK_REF_PCIE1_PHY:
ret = 0;
break;
#ifndef CONFIG_SPL_BUILD
--
2.34.1

183
projects/Rockchip/patches/u-boot/rockchip-0046-phy-rockchip-naneng-combphy-Add-support-for-RK3576.patch Normal file
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@@ -0,0 +1,183 @@
From cd325d4d441c7d4ee44b157b45f14f12b2f814df Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 11 Jul 2025 22:44:35 +0000
Subject: [PATCH 46/84] phy: rockchip: naneng-combphy: Add support for RK3576
Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 147 ++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 432a8f8e03a..82353ae7678 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -494,6 +494,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
.combphy_cfg = rk3568_combphy_cfg,
};
+static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ u32 val;
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ /* Set PLL KVCO fine tuning signals */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ /* Set PLL input clock divider 1/2 */
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ /* Set PLL loop divider */
+ writel(0x32, priv->mmio + (0x11 << 2));
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ /* Set Rx squelch input filler bandwidth */
+ writel(0x0d, priv->mmio + (0x14 << 2));
+
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
+ break;
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
+ writel(0x8F, priv->mmio + (0x06 << 2));
+
+ param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+ param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+ param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
+ break;
+ case PHY_TYPE_SGMII:
+ case PHY_TYPE_QSGMII:
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ /* 100MHz refclock signal is good */
+ clk_set_rate(&priv->ref_clk, 100000000);
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* gate_tx_pck_sel length select work for L1SS */
+ writel(0xc0, priv->mmio + 0x74);
+
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+ writel(0x4c, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T3_P1 650mv */
+ writel(0x90, priv->mmio + (0xa << 2));
+ writel(0x43, priv->mmio + (0xb << 2));
+ writel(0x88, priv->mmio + (0xc << 2));
+ writel(0x56, priv->mmio + (0xd << 2));
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
+ /* php-grf */
+ .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
+ .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
+ .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
+ .num_phys = 2,
+ .phy_ids = {
+ 0x2b050000,
+ 0x2b060000,
+ },
+ .grfcfg = &rk3576_combphy_grfcfgs,
+ .combphy_cfg = rk3576_combphy_cfg,
+};
+
static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -609,6 +752,10 @@ static const struct udevice_id rockchip_combphy_ids[] = {
.compatible = "rockchip,rk3568-naneng-combphy",
.data = (ulong)&rk3568_combphy_cfgs
},
+ {
+ .compatible = "rockchip,rk3576-naneng-combphy",
+ .data = (ulong)&rk3576_combphy_cfgs
+ },
{
.compatible = "rockchip,rk3588-naneng-combphy",
.data = (ulong)&rk3588_combphy_cfgs
--
2.34.1

153
projects/Rockchip/patches/u-boot/rockchip-0047-board-rockchip-Add-ArmSoM-Sige5.patch Normal file
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@@ -0,0 +1,153 @@
From e7ce0ba19940ca5750cf8ab420f93289e1f16417 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 22:44:36 +0000
Subject: [PATCH 47/84] board: rockchip: Add ArmSoM Sige5
ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.
Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi | 18 ++++++
arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
configs/sige5-rk3576_defconfig | 66 ++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 91 insertions(+)
create mode 100644 arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
create mode 100644 configs/sige5-rk3576_defconfig
diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
new file mode 100644
index 00000000000..7e0530d85d1
--- /dev/null
+++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+};
+
+&red_led {
+ default-state = "on";
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+};
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
index b5190c81846..94ef74d429f 100644
--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -3,3 +3,9 @@ M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3576-generic*
F: configs/generic-rk3576_defconfig
+
+SIGE5-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-armsom-sige5*
+F: configs/sige5-rk3576_defconfig
diff --git a/configs/sige5-rk3576_defconfig b/configs/sige5-rk3576_defconfig
new file mode 100644
index 00000000000..c515e145595
--- /dev/null
+++ b/configs/sige5-rk3576_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 54fa941f236..e50dde2ccb1 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -138,6 +138,7 @@ List of mainline supported Rockchip boards:
- Radxa ROCK 3B (rock-3b-rk3568)
* rk3576
+ - ArmSoM Sige5 (sige5-rk3576)
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
- Generic RK3576 (generic-rk3576)
--
2.34.1

55
projects/Rockchip/patches/u-boot/rockchip-0048-spi-rockchip_sfc-Support-sclk_x2-version.patch Normal file
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@@ -0,0 +1,55 @@
From 113b2c01405d21703c15e34b56eb61520f3adccc Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 11 Jul 2025 23:06:03 +0000
Subject: [PATCH 48/84] spi: rockchip_sfc: Support sclk_x2 version
SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 73738ab26d3..60e74117057 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -108,6 +108,7 @@
#define SFC_VER_3 0x3
#define SFC_VER_4 0x4
#define SFC_VER_5 0x5
+#define SFC_VER_8 0x8
/* Delay line controller resiter */
#define SFC_DLL_CTRL0 0x3C
@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op
return 0;
}
+#if CONFIG_IS_ENABLED(CLK)
+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
+{
+ if (sfc->version >= SFC_VER_8)
+ return clk_set_rate(&sfc->clk, speed * 2);
+ else
+ return clk_set_rate(&sfc->clk, speed);
+}
+#endif
+
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
struct rockchip_sfc *sfc = dev_get_plat(bus);
@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
return 0;
#if CONFIG_IS_ENABLED(CLK)
- int ret = clk_set_rate(&sfc->clk, speed);
+ int ret = rockchip_sfc_clk_set_rate(sfc, speed);
if (ret < 0) {
dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
--
2.34.1

62
projects/Rockchip/patches/u-boot/rockchip-0049-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch Normal file
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@@ -0,0 +1,62 @@
From 8c261270d150b57c3094f16cfe8abc48396bcf69 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 23:06:04 +0000
Subject: [PATCH 49/84] rockchip: spl: Add a read_brom_bootsource_id() helper
The bootsource ids reported by BootROM of RK3576 for e.g. SPI NOR and
USB differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81.
Add a helper function to read the bootsource id. This helper function
will be used to translate the new values to the common BROM_BOOTSOURCE
enum values on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
arch/arm/mach-rockchip/spl.c | 7 ++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index e736772fda7..b15938c021d 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -64,4 +64,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
*/
#define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10)
+u32 read_brom_bootsource_id(void);
+
#endif
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index f4d29bbdd17..1ce3a3b0554 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
};
+__weak u32 read_brom_bootsource_id(void)
+{
+ return readl(BROM_BOOTSOURCE_ID_ADDR);
+}
+
const char *board_spl_was_booted_from(void)
{
static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN;
@@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(void)
if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN)
bootdevice_brom_id = brom_bootsource_id_cache;
else
- bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+ bootdevice_brom_id = read_brom_bootsource_id();
if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
bootdevice_ofpath = boot_devices[bootdevice_brom_id];
--
2.34.1

137
projects/Rockchip/patches/u-boot/rockchip-0050-rockchip-rk3576-Add-SPI-Flash-boot-support.patch Normal file
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@@ -0,0 +1,137 @@
From de7ac8d5909a3153ae9513eaba23266bd4771a3b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 23:06:05 +0000
Subject: [PATCH 50/84] rockchip: rk3576: Add SPI Flash boot support
The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81.
Add a RK3576 specific read_brom_bootsource_id() function to help decode
the new bootsource id values and the required boot_devices mapping of
sfc0 and sfc1 to help support booting from SPI flash on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3576-u-boot.dtsi | 36 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3576/rk3576.c | 23 ++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
index fb5a107f47d..c7ed09e03ee 100644
--- a/arch/arm/dts/rk3576-u-boot.dtsi
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -6,6 +6,11 @@
#include "rockchip-u-boot.dtsi"
/ {
+ aliases {
+ spi5 = &sfc0;
+ spi6 = &sfc1;
+ };
+
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
@@ -16,6 +21,17 @@
};
};
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
+};
+#endif
+
&cru {
bootph-all;
};
@@ -45,6 +61,16 @@
bootph-some-ram;
};
+&fspi0_csn0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&fspi0_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&ioc_grf {
bootph-all;
};
@@ -116,6 +142,16 @@
bootph-some-ram;
};
+&sfc0 {
+ bootph-some-ram;
+ u-boot,spl-sfc-no-dma;
+};
+
+&sfc1 {
+ bootph-some-ram;
+ u-boot,spl-sfc-no-dma;
+};
+
&sys_grf {
bootph-all;
};
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
index a6c2fbdc484..3d5bdeeeb84 100644
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -36,8 +36,17 @@
#define USB_GRF_BASE 0x2601E000
#define USB3OTG0_CON1 0x0030
+enum {
+ BROM_BOOTSOURCE_FSPI0 = 3,
+ BROM_BOOTSOURCE_FSPI1_M0 = 4,
+ BROM_BOOTSOURCE_FSPI1_M1 = 6,
+};
+
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
+ [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
+ [BROM_BOOTSOURCE_FSPI1_M0] = "/soc/spi@2a300000/flash@0",
+ [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
};
@@ -85,6 +94,20 @@ void board_debug_uart_init(void)
{
}
+u32 read_brom_bootsource_id(void)
+{
+ u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+
+ if (bootsource_id == 0x23)
+ return BROM_BOOTSOURCE_FSPI1_M1;
+ else if (bootsource_id == 0x81)
+ return BROM_BOOTSOURCE_USB;
+ else if (bootsource_id > BROM_LAST_BOOTSOURCE)
+ log_debug("Unknown bootsource %x\n", bootsource_id);
+
+ return bootsource_id;
+}
+
#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
#define HP_CTRL_REG 0x04
#define TIMER_EN BIT(0)
--
2.34.1

157
projects/Rockchip/patches/u-boot/rockchip-0051-board-rockchip-Add-Radxa-ROCK-4D.patch Normal file
View File

@@ -0,0 +1,157 @@
From c2f38fb0dd818b73ba80b32304a9cbef9d442308 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 23:06:06 +0000
Subject: [PATCH 51/84] board: rockchip: Add Radxa ROCK 4D
The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
numerous top-tier functions, features, and expansion options.
Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
Features tested on a Radxa ROCK 4D v1.112:
- SPI Flash boot
- Ethernet
ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
or directly from USB when the MASKROM button is pressed, booting
directly from SD-card is not possible on these boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3576-rock-4d-u-boot.dtsi | 15 +++++
arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
configs/rock-4d-rk3576_defconfig | 68 +++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 90 insertions(+)
create mode 100644 arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
create mode 100644 configs/rock-4d-rk3576_defconfig
diff --git a/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
new file mode 100644
index 00000000000..5056a1cecb8
--- /dev/null
+++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+&rgmii_phy0 {
+ /delete-property/ reset-gpio;
+ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+};
+
+&sfc0 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
index 94ef74d429f..54c75f451f0 100644
--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -4,6 +4,12 @@ S: Maintained
F: arch/arm/dts/rk3576-generic*
F: configs/generic-rk3576_defconfig
+ROCK-4D-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-rock-4d*
+F: configs/rock-4d-rk3576_defconfig
+
SIGE5-RK3576
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/configs/rock-4d-rk3576_defconfig b/configs/rock-4d-rk3576_defconfig
new file mode 100644
index 00000000000..140a3e0ccd8
--- /dev/null
+++ b/configs/rock-4d-rk3576_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index e50dde2ccb1..97266d370bf 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:
- ArmSoM Sige5 (sige5-rk3576)
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
- Generic RK3576 (generic-rk3576)
+ - Radxa ROCK 4D (rock-4d-rk3576)
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
--
2.34.1

44
projects/Rockchip/patches/u-boot/rockchip-0052-rockchip-spl-boot-order-Defer-probe-of-boot-device.patch Normal file
View File

@@ -0,0 +1,44 @@
From f2102f6d2743b6db7a35a0082326bf39b5fd16e5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 12 Jul 2025 21:12:29 +0000
Subject: [PATCH 52/84] rockchip: spl-boot-order: Defer probe of boot device
Boot devices are being probed when SPL boot order is determined. This
may delay boot slightly and can prevent booting from SPI Flash on boards
that use same pins for SPI Flash and eMMC due to pinctrl being applied
prior to booting.
Instead defer probe of the boot device until SPL try to load image from
the boot device by using uclass_find_device_by_of_offset() instead of
the get variant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/mach-rockchip/spl-boot-order.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 3dce9b30898..6b1b84dc86d 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -40,7 +40,7 @@ static int spl_node_to_boot_device(int node)
* aware of the block-device layer. Until then (and to avoid unneeded
* delays in getting this feature out), it lives at the board-level.
*/
- if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
+ if (!uclass_find_device_by_of_offset(UCLASS_MMC, node, &parent)) {
struct udevice *dev;
struct blk_desc *desc = NULL;
@@ -72,7 +72,7 @@ static int spl_node_to_boot_device(int node)
* extended with awareness of the BLK layer (and matching OF_CONTROL)
* soon.
*/
- if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+ if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
return BOOT_DEVICE_SPI;
return -1;
--
2.34.1

60
projects/Rockchip/patches/u-boot/rockchip-0053-rockchip-Ensure-env-in-SPI-Flash-can-work-correctly.patch Normal file
View File

@@ -0,0 +1,60 @@
From eb0eb85a065095685056da32409bbcbbe2fb5dd4 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 12 Jul 2025 21:27:07 +0000
Subject: [PATCH 53/84] rockchip: Ensure env in SPI Flash can work correctly
Ensure that the spi/sfc node for SPI flash is aviliable during pre-reloc
phase so that env can successfully be loaded from SPI Flash.
No boards with these SoCs seem to be affected as there is no default use
of ENV_IS_IN_SPI_FLASH=y.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3328-u-boot.dtsi | 4 ++++
arch/arm/dts/rk356x-u-boot.dtsi | 1 +
arch/arm/dts/rk3588s-u-boot.dtsi | 1 +
3 files changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index b0e50a973a8..8ffc9ed3d57 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -132,6 +132,10 @@
bootph-pre-ram;
};
+&spi0 {
+ bootph-some-ram;
+};
+
&uart2 {
bootph-all;
clock-frequency = <24000000>;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 87186973953..738b9673d35 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -157,6 +157,7 @@
};
&sfc {
+ bootph-some-ram;
u-boot,spl-sfc-no-dma;
};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 5eeb138f351..71fd352f640 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -140,6 +140,7 @@
};
&sfc {
+ bootph-some-ram;
u-boot,spl-sfc-no-dma;
};
--
2.34.1

167
projects/Rockchip/patches/u-boot/rockchip-0054-rockchip-px30-rk3326-Implement-checkboard-to-print-S.patch Normal file
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@@ -0,0 +1,167 @@
From 24fc7c42d539648a107ab7096d45cfdab0647707 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@cherry.de>
Date: Tue, 10 Jun 2025 11:42:50 +0200
Subject: [PATCH 54/84] rockchip: px30/rk3326: Implement checkboard() to print
SoC variant
This implements checkboard() to print the current SoC model used by a
board, e.g. one of:
SoC: PX30
SoC: PX30S
SoC: PX30K
SoC: RK3326
SoC: RK3326S
when U-Boot proper is running.
The information is read from the OTP and also the DDR_GRF. There's no
public information as far as I know about the layout and stored
information on OTP but this was provided by Rockchip themselves through
their support channel.
The OTP stores the information of whether the SoC is PX30K or something
else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
to read some undocumented bitfield in a DDR_GRF register as done in
vendor kernel,
c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
properly.
Also add the OTP node to the pre-relocation phase of U-Boot proper so
that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
happens after relocation. If both are enabled, then the SoC variant will
be printed twice in the boot log, e.g.:
U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200)
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <---- due to DISPLAY_BOARDINFO
DRAM: 2 GiB
PMIC: RK809 (on=0x40, off=0x00)
Core: 293 devices, 27 uclasses, devicetree: separate
MMC: mmc@ff370000: 1, mmc@ff390000: 0
Loading Environment from MMC... Reading from MMC(1)... OK
In: serial@ff030000
Out: serial@ff030000
Err: serial@ff030000
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE
Net: eth0: ethernet@ff360000
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/px30-u-boot.dtsi | 4 ++
arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 157d0ea6930..2f726b0aaba 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -27,6 +27,10 @@
};
};
+&otp {
+ bootph-some-ram;
+};
+
&uart2 {
clock-frequency = <24000000>;
bootph-all;
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 8ce9ac561f0..5a5c119328f 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -2,10 +2,14 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
+
+#define LOG_CATEGORY LOGC_ARCH
+
#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <init.h>
+#include <misc.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
@@ -15,6 +19,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <dt-bindings/clock/px30-cru.h>
+#include <linux/bitfield.h>
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
@@ -442,3 +447,59 @@ void board_debug_uart_init(void)
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
}
#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
+
+#define PX30_OTP_SPECIFICATION_OFFSET 0x06
+
+#define DDR_GRF_BASE_ADDR 0xff630000
+#define DDR_GRF_CON(n) (0 + (n) * 4)
+
+int checkboard(void)
+{
+ struct udevice *dev;
+ u8 specification;
+ u32 base_soc;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
+ ret = misc_read(dev, 0, &base_soc, 4);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+
+ if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
+ log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
+ return 0;
+ }
+
+ /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
+ ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+
+ if (specification == 0x2b) {
+ printf("SoC: PX30K\n");
+ return 0;
+ }
+
+ /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
+ specification = FIELD_GET(GENMASK(15, 14),
+ readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
+ log_debug("DDR specification is %d\n", specification);
+ printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
+ specification == 0x3 ? "S" : "");
+
+ return 0;
+}
--
2.34.1

41
projects/Rockchip/patches/u-boot/rockchip-0055-clk-px30-Allow-use-of-GPU-and-WIFI_PMU-in-assigned-c.patch Normal file
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@@ -0,0 +1,41 @@
From 1d9809d479e99125850b2eadbbca633435ea273f Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:49 +0000
Subject: [PATCH 55/84] clk: px30: Allow use of GPU and WIFI_PMU in
assigned-clocks
Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/clk/rockchip/clk_px30.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index ad7e1c0f246..b5054e84c32 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1360,6 +1360,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_GMAC_RMII:
ret = px30_mac_set_speed_clk(priv, rate);
break;
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ case SCLK_GPU:
+ break;
#endif
default:
return -ENOENT;
@@ -1726,6 +1729,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)
case SCLK_UART0_PMU:
ret = px30_pmu_uart0_set_clk(priv, rate);
break;
+ /* Might occur in pmucru assigned-clocks, can be ignored here */
+ case SCLK_WIFI_PMU:
+ break;
default:
return -ENOENT;
}
--
2.34.1

40
projects/Rockchip/patches/u-boot/rockchip-0056-rockchip-odroid-go2-Remove-cru-assigned-clocks-overr.patch Normal file
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@@ -0,0 +1,40 @@
From aa6ea252bf5c82e4b277c6101569b722c756875f Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:50 +0000
Subject: [PATCH 56/84] rockchip: odroid-go2: Remove cru assigned-clocks
override
Remove the cru assigned-clocks override now that SCLK_GPU is supported
by the clock driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index a0ab8b69f2e..f37daa893c7 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -32,18 +32,8 @@
};
};
-/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
bootph-all;
- assigned-clocks = <&cru PLL_NPLL>,
- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
- <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
-
- assigned-clock-rates = <1188000000>,
- <200000000>, <200000000>,
- <150000000>, <150000000>,
- <100000000>, <17000000>;
};
&gpio0 {
--
2.34.1

55
projects/Rockchip/patches/u-boot/rockchip-0057-rockchip-odroid-go2-Remove-u-boot.dtsi-props-already.patch Normal file
View File

@@ -0,0 +1,55 @@
From 82df30c64326c27218bbefc4f4b3ce24e07efc28 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:51 +0000
Subject: [PATCH 57/84] rockchip: odroid-go2: Remove u-boot.dtsi props already
defined
DTs from dts/upstream already contain aliases for i2c, mmc and serial.
Remove the aliases and status=okay that are already defined in upstream
board or SoC DT.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index f37daa893c7..df21747fad7 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -10,15 +10,6 @@
u-boot,spl-boot-order = &sdmmc;
};
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- mmc0 = &sdmmc;
- serial1 = &uart1;
- serial2 = &uart2;
- spi0 = &sfc;
- };
-
dmc {
bootph-all;
compatible = "rockchip,px30-dmc", "syscon";
@@ -28,7 +19,6 @@
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
- status = "okay";
};
};
@@ -85,7 +75,6 @@
&saradc {
bootph-all;
- status = "okay";
};
&sdmmc {
--
2.34.1

81
projects/Rockchip/patches/u-boot/rockchip-0058-rockchip-odroid-go2-Use-appropriate-bootph-props.patch Normal file
View File

@@ -0,0 +1,81 @@
From 7f9f8ec3bf764a6475b923822b6f7b1951532293 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:52 +0000
Subject: [PATCH 58/84] rockchip: odroid-go2: Use appropriate bootph props
GPIO devices are needed in U-Boot proper phase, sdmmc and sfc devices
are needed in SPL and pre-reloc phase.
Update bootph- props to match what boot phase devices are needed at.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index df21747fad7..a27994e450c 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -27,22 +27,18 @@
};
&gpio0 {
- bootph-all;
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
- bootph-all;
gpio-ranges = <&pinctrl 0 32 32>;
};
&gpio2 {
- bootph-all;
gpio-ranges = <&pinctrl 0 64 32>;
};
&gpio3 {
- bootph-all;
gpio-ranges = <&pinctrl 0 96 32>;
};
@@ -78,28 +74,30 @@
};
&sdmmc {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&sfc {
- bootph-all;
+ bootph-some-ram;
};
&{/spi@ff3a0000/flash@0} {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&uart1 {
- clock-frequency = <24000000>;
bootph-all;
+ clock-frequency = <24000000>;
};
&uart2 {
- clock-frequency = <24000000>;
bootph-all;
+ clock-frequency = <24000000>;
};
&xin24m {
--
2.34.1

204
projects/Rockchip/patches/u-boot/rockchip-0059-rockchip-odroid-go2-Move-SoC-common-overrides-into-a.patch Normal file
View File

@@ -0,0 +1,204 @@
From fe2785fc50dd69aefa6efb9acae0b8f51878f43d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:53 +0000
Subject: [PATCH 59/84] rockchip: odroid-go2: Move SoC common overrides into a
SoC u-boot.dtsi
Add a new common rk3326-u-boot.dtsi and move the SoC common overrides
into it.
This should not contain any changes other than a possible reorder of
nodes and props.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 78 ++--------------------
arch/arm/dts/rk3326-u-boot.dtsi | 76 +++++++++++++++++++++
2 files changed, 81 insertions(+), 73 deletions(-)
create mode 100644 arch/arm/dts/rk3326-u-boot.dtsi
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index a27994e450c..06e2c190b1f 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -3,56 +3,7 @@
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
-#include "rockchip-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = &sdmmc;
- };
-
- dmc {
- bootph-all;
- compatible = "rockchip,px30-dmc", "syscon";
- reg = <0x0 0xff2a0000 0x0 0x1000>;
- };
-
- rng: rng@ff0b0000 {
- compatible = "rockchip,cryptov2-rng";
- reg = <0x0 0xff0b0000 0x0 0x4000>;
- };
-};
-
-&cru {
- bootph-all;
-};
-
-&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
-};
-
-&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
-};
-
-&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
-};
-
-&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
-};
-
-&grf {
- bootph-all;
-};
-
-&pmucru {
- bootph-all;
-};
-
-&pmugrf {
- bootph-all;
-};
+#include "rk3326-u-boot.dtsi"
&rk817 {
regulators {
@@ -73,33 +24,14 @@
bootph-all;
};
-&sdmmc {
- bootph-pre-ram;
- bootph-some-ram;
-
- /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
- u-boot,spl-fifo-mode;
-};
-
&sfc {
- bootph-some-ram;
-};
-
-&{/spi@ff3a0000/flash@0} {
- bootph-pre-ram;
- bootph-some-ram;
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
&uart1 {
bootph-all;
clock-frequency = <24000000>;
};
-
-&uart2 {
- bootph-all;
- clock-frequency = <24000000>;
-};
-
-&xin24m {
- bootph-all;
-};
diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi
new file mode 100644
index 00000000000..2894133cfe6
--- /dev/null
+++ b/arch/arm/dts/rk3326-u-boot.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc;
+ };
+
+ dmc {
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ bootph-all;
+ };
+
+ rng: rng@ff0b0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff0b0000 0x0 0x4000>;
+ };
+};
+
+&cru {
+ bootph-all;
+};
+
+&gpio0 {
+ gpio-ranges = <&pinctrl 0 0 32>;
+};
+
+&gpio1 {
+ gpio-ranges = <&pinctrl 0 32 32>;
+};
+
+&gpio2 {
+ gpio-ranges = <&pinctrl 0 64 32>;
+};
+
+&gpio3 {
+ gpio-ranges = <&pinctrl 0 96 32>;
+};
+
+&grf {
+ bootph-all;
+};
+
+&pmucru {
+ bootph-all;
+};
+
+&pmugrf {
+ bootph-all;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&sfc {
+ bootph-some-ram;
+};
+
+&uart2 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&xin24m {
+ bootph-all;
+};
--
2.34.1

66
projects/Rockchip/patches/u-boot/rockchip-0060-rockchip-odroid-go2-Remove-unsupported-Kconfig-optio.patch Normal file
View File

@@ -0,0 +1,66 @@
From 467deac3ad081c7d8b960c8df04ca4a575073c08 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:54 +0000
Subject: [PATCH 60/84] rockchip: odroid-go2: Remove unsupported Kconfig
options
The handheld gaming devices that this defconfig tagets does not contain
an Ethernet port, remove Ethernet related Kconfig options.
They also do not contain any pwm-regulator in their DTs, remove the
PWM regulator related Kconfig option.
Display/video is not supported in U-Boot, remove all display/video
related Kconfig options.
There is no real functional change expected with these options removed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/odroid-go2_defconfig | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 698aad59dec..d6a63bd3a4c 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -21,9 +21,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
-# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
@@ -69,15 +67,11 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
@@ -96,10 +90,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_VIDEO=y
-CONFIG_DISPLAY=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
-CONFIG_OPTEE_LIB=y
--
2.34.1

68
projects/Rockchip/patches/u-boot/rockchip-0061-rockchip-odroid-go2-Update-Kconfig-options-for-SPL.patch Normal file
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@@ -0,0 +1,68 @@
From e7e406bdfc634127304dbc1f70d051f46e3f683e Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:55 +0000
Subject: [PATCH 61/84] rockchip: odroid-go2: Update Kconfig options for SPL
Drop SPL_DRIVERS_MISC, it is not needed/used on these devices.
Enable SPL_FIT_SIGNATURE to ensure the integrity of the FIT images
that are loaded into memory.
Change SPL_MAX_SIZE to 256 KiB, similar to other SoCs where TF-A is
loaded at 0x40000 offset from start of DRAM.
Enable SPL_DM_SEQ_ALIAS to ensure device aliases are applied in SPL.
Drop use of SPL_TINY_MEMSET, there is plenty room for the normal memset.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/odroid-go2_defconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index d6a63bd3a4c..6bc0d12440c 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -10,7 +10,6 @@ CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -19,12 +18,13 @@ CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
@@ -53,6 +53,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -90,7 +91,6 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
--
2.34.1

135
projects/Rockchip/patches/u-boot/rockchip-0062-rockchip-odroid-go2-Include-pinctrl-for-sdmmc-sfc-an.patch Normal file
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@@ -0,0 +1,135 @@
From 28ee80ddeb0611760a2540168d36ff88c8cb62de Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:56 +0000
Subject: [PATCH 62/84] rockchip: odroid-go2: Include pinctrl for sdmmc, sfc
and uart in SPL
Include pinctrl nodes and props for sdmmc, sfc and uart in SPL to ensure
pins are configured according to the device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++
arch/arm/dts/rk3326-u-boot.dtsi | 58 ++++++++++++++++++++++
configs/odroid-go2_defconfig | 2 +-
3 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 06e2c190b1f..6f40654d5e8 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -35,3 +35,13 @@
bootph-all;
clock-frequency = <24000000>;
};
+
+&uart1_cts {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
+&uart1_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi
index 2894133cfe6..196604a9987 100644
--- a/arch/arm/dts/rk3326-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-u-boot.dtsi
@@ -46,6 +46,24 @@
bootph-all;
};
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_none_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&pmucru {
bootph-all;
};
@@ -62,15 +80,55 @@
u-boot,spl-fifo-mode;
};
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&sfc {
bootph-some-ram;
};
+&sfc_bus2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sfc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sfc_cs0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&uart2 {
bootph-all;
clock-frequency = <24000000>;
};
+&uart2m1_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
&xin24m {
bootph-all;
};
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 6bc0d12440c..b0947fe2c8b 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
--
2.34.1

83
projects/Rockchip/patches/u-boot/rockchip-0063-rockchip-odroid-go2-Use-power-off-at-power-plug-in-e.patch Normal file
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@@ -0,0 +1,83 @@
From 1f53e8b192440fc37144acc6469fae4f839ff2f0 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:57 +0000
Subject: [PATCH 63/84] rockchip: odroid-go2: Use power off at power plug-in
event
Include the RK817 PMIC in SPL and enable Kconfig options to power off
the handheld gaming device when it was powered on due to a power cable
plug-in event:
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
Power Off due to plug-in event
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 ++++++++++++++++++
configs/odroid-go2_defconfig | 3 +++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 6f40654d5e8..6c6efa964d8 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -5,8 +5,26 @@
#include "rk3326-u-boot.dtsi"
+&i2c0_xfer {
+ bootph-pre-ram;
+};
+
+&i2s1_2ch_mclk {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_none_smt {
+ bootph-pre-ram;
+};
+
+&pmic_int {
+ bootph-pre-ram;
+};
+
&rk817 {
regulators {
+ bootph-pre-ram;
+
vcc_cam: LDO_REG9 {
regulator-name = "vcc_cam";
regulator-min-microvolt = <3000000>;
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index b0947fe2c8b..a6d02baa520 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x4000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -42,6 +43,7 @@ CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
@@ -73,6 +75,7 @@ CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
--
2.34.1

118
projects/Rockchip/patches/u-boot/rockchip-0064-rockchip-odroid-go2-Add-support-for-SPI-flash-boot.patch Normal file
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@@ -0,0 +1,118 @@
From 6fb5e32dff040ea7ee9991009764007ed760016d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:58 +0000
Subject: [PATCH 64/84] rockchip: odroid-go2: Add support for SPI flash boot
The ODROID GO2 devices come with onboard SPI flash, add support for
using the SPI flash.
The BootROM seem to expect the IDBlock at 64 KiB offset compared to the
typical 32 KiB offset from start of SPI flash used by other SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-u-boot.dtsi | 18 +++++++++++++++++-
configs/odroid-go2_defconfig | 11 +++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi
index 196604a9987..be1dd4f91c1 100644
--- a/arch/arm/dts/rk3326-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-u-boot.dtsi
@@ -6,8 +6,12 @@
#include "rockchip-u-boot.dtsi"
/ {
+ aliases {
+ spi2 = &sfc;
+ };
+
chosen {
- u-boot,spl-boot-order = &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc;
};
dmc {
@@ -22,6 +26,17 @@
};
};
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x10000>;
+ };
+ };
+};
+#endif
+
&cru {
bootph-all;
};
@@ -102,6 +117,7 @@
&sfc {
bootph-some-ram;
+ u-boot,spl-sfc-no-dma;
};
&sfc_bus2 {
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index a6d02baa520..09ba6b7fcfa 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -3,17 +3,23 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=108000000
+CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
@@ -30,6 +36,8 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_TPL_BANNER_PRINT is not set
@@ -70,6 +78,8 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XTX=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -87,6 +97,7 @@ CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SOUND=y
+CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
--
2.34.1

199
projects/Rockchip/patches/u-boot/rockchip-0065-rockchip-odroid-go2-Select-board-FDT-from-FIT-in-SPL.patch Normal file
View File

@@ -0,0 +1,199 @@
From 01c2dbb5ca0d85541a3261c06abb65ef326fed85 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:33:59 +0000
Subject: [PATCH 65/84] rockchip: odroid-go2: Select board FDT from FIT in SPL
Include FDTs for all three board variants in the FIT image and adjust
the board selection code to use correct FDT in U-Boot proper.
E.g. use the odroid-go3 DT for a ODROID-GO Super device:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
DRAM: 1 GiB (total 1022 MiB)
PMIC: RK817 (on=0x80, off=0x08)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 3 +-
.../arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi | 3 ++
arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi | 3 ++
board/hardkernel/odroid_go2/Kconfig | 6 +++
board/hardkernel/odroid_go2/go2.c | 54 +++++++++++++------
configs/odroid-go2_defconfig | 2 +
6 files changed, 55 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 6c6efa964d8..393710246e1 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -39,7 +39,8 @@
};
&saradc {
- bootph-all;
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
};
&sfc {
diff --git a/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi
new file mode 100644
index 00000000000..89b2d9573ad
--- /dev/null
+++ b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3326-odroid-go2-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi
new file mode 100644
index 00000000000..89b2d9573ad
--- /dev/null
+++ b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3326-odroid-go2-u-boot.dtsi"
diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig
index 82988dffb3c..dd6e366282e 100644
--- a/board/hardkernel/odroid_go2/Kconfig
+++ b/board/hardkernel/odroid_go2/Kconfig
@@ -9,4 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "odroid_go2"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ADC
+ select BOARD_TYPES
+ select SPL_ADC
+
endif
diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c
index a0338ead3b5..9d9f3cee36a 100644
--- a/board/hardkernel/odroid_go2/go2.c
+++ b/board/hardkernel/odroid_go2/go2.c
@@ -10,6 +10,8 @@
#include <env.h>
#include <stdlib.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define DTB_DIR "rockchip/"
struct oga_model {
@@ -20,7 +22,7 @@ struct oga_model {
};
enum oga_device_id {
- OGA,
+ OGA = 1,
OGA_V11,
OGS,
};
@@ -50,15 +52,10 @@ static const struct oga_model oga_model_details[] = {
},
};
-/* Detect which Odroid Go Advance device we are using so as to load the
- * correct devicetree for Linux. Set an environment variable once
- * found. The detection depends on the value of ADC channel 0.
- */
-int oga_detect_device(void)
+static int oga_read_board_id(void)
{
u32 adc_info;
- int ret, i;
- int board_id = -ENXIO;
+ int i, ret;
ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info);
if (ret) {
@@ -72,22 +69,32 @@ int oga_detect_device(void)
* accounted for this with a 5% tolerance, so assume a +- value
* of 50 should be enough.
*/
- for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) {
+ for (i = 1; i < ARRAY_SIZE(oga_model_details); i++) {
u32 adc_min = oga_model_details[i].adc_value - 50;
u32 adc_max = oga_model_details[i].adc_value + 50;
- if (adc_min < adc_info && adc_max > adc_info) {
- board_id = i;
- break;
- }
+ if (adc_min < adc_info && adc_max > adc_info)
+ return i;
}
+ return -ENODEV;
+}
+
+/* Detect which Odroid Go Advance device we are using so as to load the
+ * correct devicetree for Linux. Set an environment variable once
+ * found. The detection depends on the value of ADC channel 0.
+ */
+static int oga_detect_device(void)
+{
+ int board_id;
+
+ board_id = oga_read_board_id();
if (board_id < 0)
return board_id;
+ gd->board_type = board_id;
env_set("board", oga_model_details[board_id].board);
- env_set("board_name",
- oga_model_details[board_id].board_name);
+ env_set("board_name", oga_model_details[board_id].board_name);
env_set("fdtfile", oga_model_details[board_id].fdtfile);
return 0;
@@ -105,3 +112,20 @@ int rk_board_late_init(void)
return 0;
}
+
+int board_fit_config_name_match(const char *name)
+{
+ int board_id;
+
+ if (!gd->board_type) {
+ board_id = oga_read_board_id();
+ if (board_id < 0)
+ return board_id;
+ gd->board_type = board_id;
+ }
+
+ if (!strcmp(name, oga_model_details[gd->board_type].fdtfile))
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 09ba6b7fcfa..05d9f9c09de 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -8,6 +8,7 @@ CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
@@ -61,6 +62,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rockchip/rk3326-odroid-go2 rockchip/rk3326-odroid-go2-v11 rockchip/rk3326-odroid-go3"
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
--
2.34.1

107
projects/Rockchip/patches/u-boot/rockchip-0066-rockchip-odroid-go2-Use-env-from-same-storage-FIT-wa.patch Normal file
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@@ -0,0 +1,107 @@
From d7124db56d3addd0a7ef6aa5741003a24ec55f7a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:00 +0000
Subject: [PATCH 66/84] rockchip: odroid-go2: Use env from same storage FIT was
loaded from
Change to dynamically select what storage media to use for the U-Boot
environment depending on from what storage media the FIT images was
loaded from, fall back to use env from nowhere.
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from MMC1
...
Loading Environment from MMC... Reading from MMC(0)...
or
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from SPI
...
Loading Environment from SPIFlash...
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
board/hardkernel/odroid_go2/Kconfig | 1 +
board/hardkernel/odroid_go2/go2.c | 34 +++++++++++++++++++++++++++++
configs/odroid-go2_defconfig | 2 ++
3 files changed, 37 insertions(+)
diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig
index dd6e366282e..6487335972b 100644
--- a/board/hardkernel/odroid_go2/Kconfig
+++ b/board/hardkernel/odroid_go2/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ADC
select BOARD_TYPES
+ select ENV_IS_NOWHERE
select SPL_ADC
endif
diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c
index 9d9f3cee36a..ae32ea87af8 100644
--- a/board/hardkernel/odroid_go2/go2.c
+++ b/board/hardkernel/odroid_go2/go2.c
@@ -7,7 +7,9 @@
#include <adc.h>
#include <asm/io.h>
#include <dm.h>
+#include <dm/uclass-internal.h>
#include <env.h>
+#include <env_internal.h>
#include <stdlib.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -129,3 +131,35 @@ int board_fit_config_name_match(const char *name)
return -EINVAL;
}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const char *boot_device;
+ struct udevice *dev;
+ ofnode node;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device");
+ if (!boot_device) {
+ debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__);
+ return ENVL_NOWHERE;
+ }
+
+ debug("%s: booted from %s\n", __func__, boot_device);
+
+ node = ofnode_path(boot_device);
+ if (!ofnode_valid(node))
+ return ENVL_NOWHERE;
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) &&
+ !uclass_find_device_by_ofnode(UCLASS_SPI_FLASH, node, &dev))
+ return ENVL_SPI_FLASH;
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) &&
+ !uclass_find_device_by_ofnode(UCLASS_MMC, node, &dev))
+ return ENVL_MMC;
+
+ return ENVL_NOWHERE;
+}
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 05d9f9c09de..185d0f1d7c5 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -65,6 +65,8 @@ CONFIG_OF_LIVE=y
CONFIG_OF_LIST="rockchip/rk3326-odroid-go2 rockchip/rk3326-odroid-go2-v11 rockchip/rk3326-odroid-go3"
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
--
2.34.1

64
projects/Rockchip/patches/u-boot/rockchip-0067-rockchip-odroid-go2-Enable-RockUSB-button-LED-and-RN.patch Normal file
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@@ -0,0 +1,64 @@
From 399ac4e2e05dbed42d023c38e4227263c3a97cb7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:01 +0000
Subject: [PATCH 67/84] rockchip: odroid-go2: Enable RockUSB, button, LED and
RNG support
Enable Kconfig options to support RockUSB, buttons, LEDs and RNG
featured on the board or SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/odroid-go2_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 185d0f1d7c5..70d74c65a2f 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -54,6 +54,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SLEEP is not set
@@ -72,12 +73,17 @@ CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_PWM=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
@@ -97,6 +103,8 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -109,6 +117,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
--
2.34.1

32
projects/Rockchip/patches/u-boot/rockchip-0068-rockchip-odroid-go2-Turn-on-the-blue-LED-at-boot.patch Normal file
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@@ -0,0 +1,32 @@
From 5153c47f925ee11d1407df82b2787a909a6be8e9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:02 +0000
Subject: [PATCH 68/84] rockchip: odroid-go2: Turn on the blue LED at boot
Use default-state prop to ensure that the blue heartbeat LED turns on
at boot to inticate that U-Boot proper has been reached.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 393710246e1..170e0f7d847 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -5,6 +5,11 @@
#include "rk3326-u-boot.dtsi"
+&blue_led {
+ default-state = "on";
+ u-boot,default-brightness = <127>;
+};
+
&i2c0_xfer {
bootph-pre-ram;
};
--
2.34.1

52
projects/Rockchip/patches/u-boot/rockchip-0069-rockchip-odroid-go2-Enable-more-commands.patch Normal file
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@@ -0,0 +1,52 @@
From 48faf6188d73d0f83937c6e36946c2fc6b722958 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:03 +0000
Subject: [PATCH 69/84] rockchip: odroid-go2: Enable more commands
Enable the default commands and some more useful commands that can be
useful to determin the state of the board from U-Boot CLI.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
configs/odroid-go2_defconfig | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 70d74c65a2f..512ffefc70f 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -42,22 +42,21 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_TPL_BANNER_PRINT is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
--
2.34.1

29
projects/Rockchip/patches/u-boot/rockchip-0070-rockchip-odroid-go2-Add-myself-as-a-reviewer.patch Normal file
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@@ -0,0 +1,29 @@
From bb596d4d3071aef91c84098b033fe9839e69842b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:04 +0000
Subject: [PATCH 70/84] rockchip: odroid-go2: Add myself as a reviewer
I have the ORDOID-GO Super variant of this board. Add myself as a
reviewer to help review future patches targeting this device.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
board/hardkernel/odroid_go2/MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS
index 9e83bc9452c..ee06c2fa651 100644
--- a/board/hardkernel/odroid_go2/MAINTAINERS
+++ b/board/hardkernel/odroid_go2/MAINTAINERS
@@ -1,6 +1,8 @@
GO2
M: Heiko Stuebner <heiko.stuebner@cherry.de>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/hardkernel/odroid_go2/
F: include/configs/odroid_go2.h
+F: arch/arm/dts/rk3326-odroid-go*
F: configs/odroid-go2_defconfig
--
2.34.1

39
projects/Rockchip/patches/u-boot/rockchip-0071-arm-dts-rockchip-Include-OTP-in-U-Boot-pre-reloc-pha.patch Normal file
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@@ -0,0 +1,39 @@
From 2408339af2bb95cca72c43a51709e59a9d75cae2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 13 Jul 2025 23:34:05 +0000
Subject: [PATCH 71/84] arm: dts: rockchip: Include OTP in U-Boot pre-reloc
phase for RK3326
Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
SoC: RK3326
DRAM: 1 GiB (total 1022 MiB)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3326-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi
index be1dd4f91c1..6503a9382b9 100644
--- a/arch/arm/dts/rk3326-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-u-boot.dtsi
@@ -61,6 +61,10 @@
bootph-all;
};
+&otp {
+ bootph-some-ram;
+};
+
&pcfg_pull_none {
bootph-all;
};
--
2.34.1

127
projects/Rockchip/patches/u-boot/rockchip-0072-rockchip-mkimage-Split-size_and_off-and-size_and_nim.patch Normal file
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@@ -0,0 +1,127 @@
From bef74902961b6ecc08b188016d7d60ca68d4efb0 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:27 +0000
Subject: [PATCH 72/84] rockchip: mkimage: Split size_and_off and
size_and_nimage
Split 32-bit size_and_off and size_and_nimage fields of the v2 image
format header into their own 16-bit size, offset and num_images fields.
Set num_images based on number of images passed by the datafile
parameter and size based on the offset to the hash field to fix using a
single init data file and no boot data file for the v2 image format.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 44 ++++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index a0caa029cc0..e77f3979d12 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -34,15 +34,16 @@ enum hash_type {
/**
* struct image_entry
*
- * @size_and_off: [31:16]image size;[15:0]image offset
- * @address: default as 0xFFFFFFFF
+ * @offset: image offset (unit as 512 byte blocks)
+ * @size: image size (unit as 512 byte blocks)
+ * @address: load address (default as 0xFFFFFFFF)
* @flag: no use
* @counter: no use
* @hash: hash of image
- *
*/
struct image_entry {
- uint32_t size_and_off;
+ uint16_t offset;
+ uint16_t size;
uint32_t address;
uint32_t flag;
uint32_t counter;
@@ -56,16 +57,17 @@ struct image_entry {
* This is stored at SD card block 64 (where each block is 512 bytes)
*
* @magic: Magic (must be RK_MAGIC_V2)
- * @size_and_nimage: [31:16]number of images;[15:0]
- * offset to hash field of header(unit as 4Byte)
- * @boot_flag: [3:0]hash type(0:none,1:sha256,2:sha512)
- * @signature: hash or signature for header info
- *
+ * @size: offset to hash field of header (unit as 4 bytes)
+ * @num_images: number of images
+ * @boot_flag: [3:0] hash type (0:none, 1:sha256, 2:sha512)
+ * @images: images
+ * @hash: hash or signature for header info
*/
struct header0_info_v2 {
uint32_t magic;
uint8_t reserved[4];
- uint32_t size_and_nimage;
+ uint16_t size;
+ uint16_t num_images;
uint32_t boot_flag;
uint8_t reserved1[104];
struct image_entry images[4];
@@ -334,17 +336,18 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
printf("Image Type: Rockchip %s boot image\n",
rkcommon_get_spl_hdr(params));
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
- hdr->magic = cpu_to_le32(RK_MAGIC_V2);
- hdr->size_and_nimage = cpu_to_le32((2 << 16) + 384);
+ hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
sector_offset = 4;
image_size_array[0] = spl_params.init_size;
image_size_array[1] = spl_params.boot_size;
for (i = 0; i < 2; i++) {
+ if (!image_size_array[i])
+ break;
image_sector_count = image_size_array[i] / RK_BLK_SIZE;
- hdr->images[i].size_and_off = cpu_to_le32((image_sector_count
- << 16) + sector_offset);
+ hdr->images[i].offset = cpu_to_le16(sector_offset);
+ hdr->images[i].size = cpu_to_le16(image_sector_count);
hdr->images[i].address = 0xFFFFFFFF;
hdr->images[i].counter = cpu_to_le32(i + 1);
image_ptr = buf + sector_offset * RK_BLK_SIZE;
@@ -353,6 +356,8 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
sector_offset = sector_offset + image_sector_count;
}
+ hdr->num_images = cpu_to_le16(i);
+ hdr->size = cpu_to_le16(offsetof(typeof(*hdr), hash) / sizeof(uint32_t));
do_sha256_hash(buf, (void *)hdr->hash - buf, hdr->hash);
}
@@ -499,10 +504,8 @@ void rkcommon_print_header(const void *buf, struct image_tool_params *params)
return;
}
- init_size = header0_v2.images[0].size_and_off >> 16;
- init_size = init_size * RK_BLK_SIZE;
- boot_size = header0_v2.images[1].size_and_off >> 16;
- boot_size = boot_size * RK_BLK_SIZE;
+ init_size = le16_to_cpu(header0_v2.images[0].size) * RK_BLK_SIZE;
+ boot_size = le16_to_cpu(header0_v2.images[1].size) * RK_BLK_SIZE;
} else {
ret = rkcommon_parse_header(buf, &header0, &spl_info);
@@ -516,8 +519,9 @@ void rkcommon_print_header(const void *buf, struct image_tool_params *params)
}
image_type = ret;
- init_size = header0.init_size * RK_BLK_SIZE;
- boot_size = header0.init_boot_size * RK_BLK_SIZE - init_size;
+ init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE;
+ boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE -
+ init_size;
printf("Image Type: Rockchip %s (%s) boot image\n",
spl_info->spl_hdr,
--
2.34.1

113
projects/Rockchip/patches/u-boot/rockchip-0073-rockchip-mkimage-Print-image-information-for-all-emb.patch Normal file
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@@ -0,0 +1,113 @@
From a1a3a2d00251f392274251225e266673dd3fbeca Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:28 +0000
Subject: [PATCH 73/84] rockchip: mkimage: Print image information for all
embedded images
The v2 image format can embed up to 4 data files compared to the two
init and boot data files using the older image format.
Add support for displaying more of the image header information that
exists in the v2 image format, e.g. image load address and flag.
Example for v2 image format:
> tools/mkimage -l rk3576_idblock_v1.09.107.img
Rockchip Boot Image (v2)
Image 1: 4096 @ 0x1000
- Load address: 0x3ffc0000
Image 2: 77824 @ 0x2000
- Load address: 0x3ff81000
Image 3: 262144 @ 0x15000
Example for older image format:
> tools/mkimage -l u-boot-rockchip.bin
Rockchip RK32 (SD/MMC) Boot Image
Init Data: 20480 @ 0x800
Boot Data: 112640 @ 0x5800
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 41 +++++++++++++++++++++++++++++++----------
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index e77f3979d12..b2820062d04 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -333,8 +333,6 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
uint8_t *image_ptr = NULL;
int i;
- printf("Image Type: Rockchip %s boot image\n",
- rkcommon_get_spl_hdr(params));
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
@@ -488,6 +486,29 @@ int rkcommon_verify_header(unsigned char *buf, int size,
return -ENOENT;
}
+static void rkcommon_print_header_v2(const struct header0_info_v2 *hdr)
+{
+ uint32_t val;
+ int i;
+
+ printf("Rockchip Boot Image (v2)\n");
+
+ for (i = 0; i < le16_to_cpu(hdr->num_images); i++) {
+ printf("Image %u: %u @ 0x%x\n",
+ le32_to_cpu(hdr->images[i].counter),
+ le16_to_cpu(hdr->images[i].size) * RK_BLK_SIZE,
+ le16_to_cpu(hdr->images[i].offset) * RK_BLK_SIZE);
+
+ val = le32_to_cpu(hdr->images[i].address);
+ if (val != 0xFFFFFFFF)
+ printf("- Load address: 0x%x\n", val);
+
+ val = le32_to_cpu(hdr->images[i].flag);
+ if (val)
+ printf("- Flag: 0x%x\n", val);
+ }
+}
+
void rkcommon_print_header(const void *buf, struct image_tool_params *params)
{
struct header0_info header0;
@@ -504,8 +525,7 @@ void rkcommon_print_header(const void *buf, struct image_tool_params *params)
return;
}
- init_size = le16_to_cpu(header0_v2.images[0].size) * RK_BLK_SIZE;
- boot_size = le16_to_cpu(header0_v2.images[1].size) * RK_BLK_SIZE;
+ rkcommon_print_header_v2(&header0_v2);
} else {
ret = rkcommon_parse_header(buf, &header0, &spl_info);
@@ -523,15 +543,16 @@ void rkcommon_print_header(const void *buf, struct image_tool_params *params)
boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE -
init_size;
- printf("Image Type: Rockchip %s (%s) boot image\n",
- spl_info->spl_hdr,
+ printf("Rockchip %s (%s) Boot Image\n", spl_info->spl_hdr,
(image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
- }
- printf("Init Data Size: %d bytes\n", init_size);
+ printf("Init Data: %d @ 0x%x\n", init_size,
+ le16_to_cpu(header0.init_offset) * RK_BLK_SIZE);
- if (boot_size != RK_MAX_BOOT_SIZE)
- printf("Boot Data Size: %d bytes\n", boot_size);
+ if (boot_size != RK_MAX_BOOT_SIZE)
+ printf("Boot Data: %d @ 0x%x\n", boot_size, init_size +
+ le16_to_cpu(header0.init_offset) * RK_BLK_SIZE);
+ }
}
void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size)
--
2.34.1

75
projects/Rockchip/patches/u-boot/rockchip-0074-rockchip-mkimage-Print-boot0-and-boot1-parameters.patch Normal file
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@@ -0,0 +1,75 @@
From f7f5be20cf184817a7d26801012cc4d439064217 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:29 +0000
Subject: [PATCH 74/84] rockchip: mkimage: Print boot0 and boot1 parameters
The v2 image format embeds boot0 and boot1 parameters, the vendor tool
boot_merger may write these parameters based on the rkboot miniall.ini
files.
E.g. a RK3576 boot image may contain a boot1 parameter that signals
BootROM or vendor blobs to use 1 GHz instead of the regular 24 MHz rate
for the high precision timer.
Add support for printing boot0 and boot1 parameters, e.g.:
> tools/mkimage -l rk3576_idblock_v1.09.107.img
Rockchip Boot Image (v2)
Boot1 2: 0x100
Image 1: 4096 @ 0x1000
- Load address: 0x3ffc0000
Image 2: 77824 @ 0x2000
- Load address: 0x3ff81000
Image 3: 262144 @ 0x15000
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index b2820062d04..ff00e57a5f5 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -62,6 +62,8 @@ struct image_entry {
* @boot_flag: [3:0] hash type (0:none, 1:sha256, 2:sha512)
* @images: images
* @hash: hash or signature for header info
+ *
+ * Other fields are not used by U-Boot
*/
struct header0_info_v2 {
uint32_t magic;
@@ -69,7 +71,9 @@ struct header0_info_v2 {
uint16_t size;
uint16_t num_images;
uint32_t boot_flag;
- uint8_t reserved1[104];
+ uint8_t reserved1[32];
+ uint32_t boot0_param[10];
+ uint32_t boot1_param[8];
struct image_entry images[4];
uint8_t reserved2[1064];
uint8_t hash[512];
@@ -493,6 +497,18 @@ static void rkcommon_print_header_v2(const struct header0_info_v2 *hdr)
printf("Rockchip Boot Image (v2)\n");
+ for (i = 0; i < ARRAY_SIZE(hdr->boot0_param); i++) {
+ val = le32_to_cpu(hdr->boot0_param[i]);
+ if (val)
+ printf("Boot0 %d: 0x%x\n", i, val);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(hdr->boot1_param); i++) {
+ val = le32_to_cpu(hdr->boot1_param[i]);
+ if (val)
+ printf("Boot1 %d: 0x%x\n", i, val);
+ }
+
for (i = 0; i < le16_to_cpu(hdr->num_images); i++) {
printf("Image %u: %u @ 0x%x\n",
le32_to_cpu(hdr->images[i].counter),
--
2.34.1

215
projects/Rockchip/patches/u-boot/rockchip-0075-rockchip-mkimage-Add-option-to-change-image-offset-a.patch Normal file
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@@ -0,0 +1,215 @@
From d036163270cb7572898de8872c6074dbb49117d3 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:30 +0000
Subject: [PATCH 75/84] rockchip: mkimage: Add option to change image offset
alignment
The vendor boot_merger tool support a ALIGN parameter that is used to
define offset alignment of the embedded images.
Vendor use this for RK3576 to change offset alignment from the common
2 KiB to 4 KiB, presumably it may have something to do with UFS.
Testing with eMMC has shown that using a 512-byte alignment also work.
Add support for overriding offset alignment in case this is needed for
e.g. RK3576 in the future.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 75 +++++++++++++++++++++++++++++++-----------------
tools/rkcommon.h | 2 --
2 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index ff00e57a5f5..0a32cc7ae49 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -124,6 +124,7 @@ struct spl_info {
const uint32_t spl_size;
const bool spl_rc4;
const uint32_t header_ver;
+ const uint32_t align;
};
static struct spl_info spl_infos[] = {
@@ -183,14 +184,19 @@ static struct spl_info *rkcommon_get_spl_info(char *imagename)
return NULL;
}
-static int rkcommon_get_aligned_size(struct image_tool_params *params,
- const char *fname)
+static bool rkcommon_is_header_v2(struct image_tool_params *params)
{
- int size;
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
- size = imagetool_get_filesize(params, fname);
- if (size < 0)
- return -1;
+ return (info->header_ver == RK_HEADER_V2);
+}
+
+static int rkcommon_get_aligned_size(struct image_tool_params *params, int size)
+{
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
+
+ if (info->align)
+ return ROUND(size, info->align * RK_BLK_SIZE);
/*
* Pad to a 2KB alignment, as required for init/boot size by the ROM
@@ -199,6 +205,27 @@ static int rkcommon_get_aligned_size(struct image_tool_params *params,
return ROUND(size, RK_SIZE_ALIGN);
}
+static int rkcommon_get_header_size(struct image_tool_params *params)
+{
+ int header_size = rkcommon_is_header_v2(params) ?
+ sizeof(struct header0_info_v2) :
+ sizeof(struct header0_info);
+
+ return rkcommon_get_aligned_size(params, header_size);
+}
+
+static int rkcommon_get_aligned_filesize(struct image_tool_params *params,
+ const char *fname)
+{
+ int size;
+
+ size = imagetool_get_filesize(params, fname);
+ if (size < 0)
+ return -1;
+
+ return rkcommon_get_aligned_size(params, size);
+}
+
int rkcommon_check_params(struct image_tool_params *params)
{
int i, size;
@@ -221,14 +248,14 @@ int rkcommon_check_params(struct image_tool_params *params)
spl_params.boot_file += 1;
}
- size = rkcommon_get_aligned_size(params, spl_params.init_file);
+ size = rkcommon_get_aligned_filesize(params, spl_params.init_file);
if (size < 0)
return EXIT_FAILURE;
spl_params.init_size = size;
/* Boot file is optional, and only for back-to-bootrom functionality. */
if (spl_params.boot_file) {
- size = rkcommon_get_aligned_size(params, spl_params.boot_file);
+ size = rkcommon_get_aligned_filesize(params, spl_params.boot_file);
if (size < 0)
return EXIT_FAILURE;
spl_params.boot_size = size;
@@ -285,13 +312,6 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params)
return info->spl_rc4;
}
-bool rkcommon_is_header_v2(struct image_tool_params *params)
-{
- struct spl_info *info = rkcommon_get_spl_info(params->imagename);
-
- return (info->header_ver == RK_HEADER_V2);
-}
-
static void do_sha256_hash(uint8_t *buf, uint32_t size, uint8_t *out)
{
sha256_context ctx;
@@ -304,12 +324,13 @@ static void do_sha256_hash(uint8_t *buf, uint32_t size, uint8_t *out)
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
{
struct header0_info *hdr = buf;
- uint32_t init_boot_size;
+ uint32_t init_boot_size, init_offset;
- memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
+ init_offset = rkcommon_get_header_size(params) / RK_BLK_SIZE;
+ memset(buf, '\0', init_offset * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC);
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
- hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET);
+ hdr->init_offset = cpu_to_le16(init_offset);
hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
/*
@@ -337,10 +358,10 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
uint8_t *image_ptr = NULL;
int i;
- memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
+ sector_offset = rkcommon_get_header_size(params) / RK_BLK_SIZE;
+ memset(buf, '\0', sector_offset * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
- sector_offset = 4;
image_size_array[0] = spl_params.init_size;
image_size_array[1] = spl_params.boot_size;
@@ -366,11 +387,12 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
- struct header1_info *hdr = buf + RK_SPL_HDR_START;
-
if (rkcommon_is_header_v2(params)) {
rkcommon_set_header0_v2(buf, params);
} else {
+ int header_size = rkcommon_get_header_size(params);
+ struct header1_info *hdr = buf + header_size;
+
rkcommon_set_header0(buf, params);
/* Set up the SPL name (i.e. copy spl_hdr over) */
@@ -378,12 +400,12 @@ void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
+ rkcommon_rc4_encode_spl(buf, header_size,
spl_params.init_size);
if (spl_params.boot_file) {
if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START,
+ rkcommon_rc4_encode_spl(buf + header_size,
spl_params.init_size,
spl_params.boot_size);
}
@@ -608,7 +630,7 @@ int rkcommon_vrec_header(struct image_tool_params *params,
* 4 bytes of these images can safely be overwritten using the
* boot magic.
*/
- tparams->header_size = RK_SPL_HDR_START;
+ tparams->header_size = rkcommon_get_header_size(params);
/* Allocate, clear and install the header */
tparams->hdr = malloc(tparams->header_size);
@@ -626,7 +648,8 @@ int rkcommon_vrec_header(struct image_tool_params *params,
params->orig_file_size = tparams->header_size +
spl_params.init_size + spl_params.boot_size;
- params->file_size = ROUND(params->orig_file_size, RK_SIZE_ALIGN);
+ params->file_size = rkcommon_get_aligned_size(params,
+ params->orig_file_size);
/* Ignoring pad len, since we are using our own copy_image() */
return 0;
diff --git a/tools/rkcommon.h b/tools/rkcommon.h
index 5d2770a80f1..c887a659a95 100644
--- a/tools/rkcommon.h
+++ b/tools/rkcommon.h
@@ -10,9 +10,7 @@
enum {
RK_BLK_SIZE = 512,
RK_SIZE_ALIGN = 2048,
- RK_INIT_OFFSET = 4,
RK_MAX_BOOT_SIZE = 512 << 10,
- RK_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
RK_SPL_HDR_SIZE = 4,
};
--
2.34.1

207
projects/Rockchip/patches/u-boot/rockchip-0076-rockchip-mkimage-Add-support-for-up-to-4-input-files.patch Normal file
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@@ -0,0 +1,207 @@
From 2fca780304046185284f223fd41de20a7199004e Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:31 +0000
Subject: [PATCH 76/84] rockchip: mkimage: Add support for up to 4 input files
The v2 image format can support up to 4 embedded images that can be
loaded by the BootROM using the back-to-bootrom method.
Currently two input files can be passed in using the datafile parameter,
separated by a colon (":").
Extend the datafile parameter parsing to support up to 4 input files
separated by a colon (":") for use with the v2 image format.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 93 +++++++++++++++++++++++-------------------------
1 file changed, 44 insertions(+), 49 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0a32cc7ae49..8f0616375c1 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -150,17 +150,15 @@ static struct spl_info spl_infos[] = {
/**
* struct spl_params - spl params parsed in check_params()
*
- * @init_file: Init data file path
- * @init_size: Aligned size of init data in bytes
- * @boot_file: Boot data file path
- * @boot_size: Aligned size of boot data in bytes
+ * @file: image file path
+ * @size: aligned size of image in bytes
*/
struct spl_params {
- char *init_file;
- uint32_t init_size;
- char *boot_file;
- uint32_t boot_size;
+ struct {
+ char *file;
+ uint32_t size;
+ } images[4];
};
static struct spl_params spl_params = { 0 };
@@ -240,31 +238,32 @@ int rkcommon_check_params(struct image_tool_params *params)
if (!rkcommon_get_spl_info(params->imagename))
goto err_spl_info;
- spl_params.init_file = params->datafile;
+ spl_params.images[0].file = params->datafile;
+ for (i = 1; i < ARRAY_SIZE(spl_params.images); i++) {
+ spl_params.images[i].file =
+ strchr(spl_params.images[i - 1].file, ':');
+ if (!spl_params.images[i].file)
+ break;
- spl_params.boot_file = strchr(spl_params.init_file, ':');
- if (spl_params.boot_file) {
- *spl_params.boot_file = '\0';
- spl_params.boot_file += 1;
+ *spl_params.images[i].file = '\0';
+ spl_params.images[i].file += 1;
}
- size = rkcommon_get_aligned_filesize(params, spl_params.init_file);
- if (size < 0)
- return EXIT_FAILURE;
- spl_params.init_size = size;
+ for (i = 0; i < ARRAY_SIZE(spl_params.images); i++) {
+ if (!spl_params.images[i].file)
+ break;
- /* Boot file is optional, and only for back-to-bootrom functionality. */
- if (spl_params.boot_file) {
- size = rkcommon_get_aligned_filesize(params, spl_params.boot_file);
+ size = rkcommon_get_aligned_filesize(params,
+ spl_params.images[i].file);
if (size < 0)
return EXIT_FAILURE;
- spl_params.boot_size = size;
+ spl_params.images[i].size = size;
}
- if (spl_params.init_size > rkcommon_get_spl_size(params)) {
+ if (spl_params.images[0].size > rkcommon_get_spl_size(params)) {
fprintf(stderr,
"Error: SPL image is too large (size %#x than %#x)\n",
- spl_params.init_size, rkcommon_get_spl_size(params));
+ spl_params.images[0].size, rkcommon_get_spl_size(params));
return EXIT_FAILURE;
}
@@ -331,7 +330,7 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
hdr->magic = cpu_to_le32(RK_MAGIC);
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
hdr->init_offset = cpu_to_le16(init_offset);
- hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
+ hdr->init_size = cpu_to_le16(spl_params.images[0].size / RK_BLK_SIZE);
/*
* init_boot_size needs to be set, as it is read by the BootROM
@@ -341,10 +340,11 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
* see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html
* for a more detailed explanation by Andy Yan
*/
- if (spl_params.boot_file)
- init_boot_size = spl_params.init_size + spl_params.boot_size;
+ if (spl_params.images[1].file)
+ init_boot_size = spl_params.images[0].size +
+ spl_params.images[1].size;
else
- init_boot_size = spl_params.init_size + RK_MAX_BOOT_SIZE;
+ init_boot_size = spl_params.images[0].size + RK_MAX_BOOT_SIZE;
hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE);
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
@@ -354,7 +354,6 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
{
struct header0_info_v2 *hdr = buf;
uint32_t sector_offset, image_sector_count;
- uint32_t image_size_array[2];
uint8_t *image_ptr = NULL;
int i;
@@ -362,19 +361,17 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
memset(buf, '\0', sector_offset * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
- image_size_array[0] = spl_params.init_size;
- image_size_array[1] = spl_params.boot_size;
- for (i = 0; i < 2; i++) {
- if (!image_size_array[i])
+ for (i = 0; i < ARRAY_SIZE(spl_params.images); i++) {
+ if (!spl_params.images[i].size)
break;
- image_sector_count = image_size_array[i] / RK_BLK_SIZE;
+ image_sector_count = spl_params.images[i].size / RK_BLK_SIZE;
hdr->images[i].offset = cpu_to_le16(sector_offset);
hdr->images[i].size = cpu_to_le16(image_sector_count);
hdr->images[i].address = 0xFFFFFFFF;
hdr->images[i].counter = cpu_to_le32(i + 1);
image_ptr = buf + sector_offset * RK_BLK_SIZE;
- do_sha256_hash(image_ptr, image_size_array[i],
+ do_sha256_hash(image_ptr, spl_params.images[i].size,
hdr->images[i].hash);
sector_offset = sector_offset + image_sector_count;
}
@@ -401,13 +398,13 @@ void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
if (rkcommon_need_rc4_spl(params))
rkcommon_rc4_encode_spl(buf, header_size,
- spl_params.init_size);
+ spl_params.images[0].size);
- if (spl_params.boot_file) {
+ if (spl_params.images[1].file) {
if (rkcommon_need_rc4_spl(params))
rkcommon_rc4_encode_spl(buf + header_size,
- spl_params.init_size,
- spl_params.boot_size);
+ spl_params.images[0].size,
+ spl_params.images[1].size);
}
}
}
@@ -645,8 +642,9 @@ int rkcommon_vrec_header(struct image_tool_params *params,
* We need to store the original file-size (i.e. before padding), as
* imagetool does not set this during its adjustment of file_size.
*/
- params->orig_file_size = tparams->header_size +
- spl_params.init_size + spl_params.boot_size;
+ params->orig_file_size = tparams->header_size;
+ for (int i = 0; i < ARRAY_SIZE(spl_params.images); i++)
+ params->orig_file_size += spl_params.images[i].size;
params->file_size = rkcommon_get_aligned_size(params,
params->orig_file_size);
@@ -733,16 +731,13 @@ err_close:
int rockchip_copy_image(int ifd, struct image_tool_params *params)
{
- int ret;
-
- ret = copy_file(params, ifd, spl_params.init_file,
- spl_params.init_size);
- if (ret)
- return ret;
+ int i, ret;
- if (spl_params.boot_file) {
- ret = copy_file(params, ifd, spl_params.boot_file,
- spl_params.boot_size);
+ for (i = 0; i < ARRAY_SIZE(spl_params.images); i++) {
+ if (!spl_params.images[i].size)
+ break;
+ ret = copy_file(params, ifd, spl_params.images[i].file,
+ spl_params.images[i].size);
if (ret)
return ret;
}
--
2.34.1

54
projects/Rockchip/patches/u-boot/rockchip-0077-rockchip-mkimage-Add-option-for-image-load-address-a.patch Normal file
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@@ -0,0 +1,54 @@
From 5dc781bf680c34a57817b8ac1ab247497253c3d7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 29 Jan 2025 22:36:32 +0000
Subject: [PATCH 77/84] rockchip: mkimage: Add option for image load address
and flag
The v2 image format supports defining a load address and flag for each
embedded image.
Add initial support for writing the image load address and flag to the
v2 image format header.
This may later be used for RK3576 to embed a minimal initial image that
if required to fix booting from SD-card due to a BootROM issue.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
tools/rkcommon.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 8f0616375c1..8b57ba69cde 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -152,12 +152,16 @@ static struct spl_info spl_infos[] = {
*
* @file: image file path
* @size: aligned size of image in bytes
+ * @address: image load address
+ * @flag: no use
*/
struct spl_params {
struct {
char *file;
uint32_t size;
+ uint32_t address;
+ uint32_t flag;
} images[4];
};
@@ -368,7 +372,8 @@ static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
image_sector_count = spl_params.images[i].size / RK_BLK_SIZE;
hdr->images[i].offset = cpu_to_le16(sector_offset);
hdr->images[i].size = cpu_to_le16(image_sector_count);
- hdr->images[i].address = 0xFFFFFFFF;
+ hdr->images[i].address = spl_params.images[i].address ?: 0xFFFFFFFF;
+ hdr->images[i].flag = spl_params.images[i].flag;
hdr->images[i].counter = cpu_to_le32(i + 1);
image_ptr = buf + sector_offset * RK_BLK_SIZE;
do_sha256_hash(image_ptr, spl_params.images[i].size,
--
2.34.1

130
projects/Rockchip/patches/u-boot/rockchip-0078-WIP-rockchip-mkimage-Add-rk3576-align-and-sd-card-wo.patch Normal file
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@@ -0,0 +1,130 @@
From b07ffc8797bbd19fab705b46751957b5d2160d72 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 28 Jan 2025 01:30:12 +0000
Subject: [PATCH 78/84] WIP: rockchip: mkimage: Add rk3576 align and sd-card
workaround
The BootROM on RK3576 has an issue loading boot images from an SD-card.
This issue can be worked around by injecting an initial boot image
before TPL that:
writel(0x3ffff800, 0x3ff803b0)
Prepend an image containing binary code that does this and return to
BootROM to load next image, TPL.
TODO: embed the binary code into rkcommon.c
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
rk3576-boost.bin | Bin 0 -> 24 bytes
rk3576-boost.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++
tools/rkcommon.c | 18 ++++++++++++++++-
3 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644 rk3576-boost.bin
create mode 100644 rk3576-boost.c
diff --git a/rk3576-boost.bin b/rk3576-boost.bin
new file mode 100644
index 0000000000000000000000000000000000000000..de1618b1a162e5e5cfbbb35ef10fcbe76e07b257
GIT binary patch
literal 24
gcmZQ5Yq<2#Thxf*|ME|a3=BIN7#e~OFvnj50CxTfSO5S3
literal 0
HcmV?d00001
diff --git a/rk3576-boost.c b/rk3576-boost.c
new file mode 100644
index 00000000000..73ba22f8aa5
--- /dev/null
+++ b/rk3576-boost.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+/*
+ * Generate assembly code for the c code in this file:
+ * aarch64-linux-gnu-gcc -nostdlib -ffreestanding -Os -S -o rk3576-boost.S rk3576-boost.c
+ *
+ * Compile assembly code and extract the AArch64 binary code:
+ * aarch64-linux-gnu-as -o rk3576-boost.o rk3576-boost.S
+ * aarch64-linux-gnu-objcopy -O binary -j .text rk3576-boost.o rk3576-boost.bin
+ */
+
+#include <stdint.h>
+
+#define SYS_SRAM_BASE 0x3ff80000
+#define OFFSET 0x03b0
+
+int _start(void)
+{
+ uint32_t *sram = (void*)(SYS_SRAM_BASE + OFFSET);
+
+ /* set unknown value in sram to fix boot from sdmmc */
+ *(sram) = 0x3ffff800;
+
+ return 0;
+}
+
+/*
+ .arch armv8-a
+ .file "rk3576-boost.c"
+ .text
+ .align 2
+ .global _start
+ .type _start, %function
+_start:
+.LFB0:
+ .cfi_startproc
+ mov x0, 944
+ mov w1, 1073739776
+ movk x0, 0x3ff8, lsl 16
+ str w1, [x0]
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE0:
+ .size _start, .-_start
+ .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
+ .section .note.GNU-stack,"",@progbits
+*/
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 8b57ba69cde..7125b1de9fe 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -143,7 +143,7 @@ static struct spl_info spl_infos[] = {
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
- { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2, 8 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
@@ -271,6 +271,22 @@ int rkcommon_check_params(struct image_tool_params *params)
return EXIT_FAILURE;
}
+ if (!strcmp(params->imagename, "rk3576")) {
+ size = rkcommon_get_aligned_filesize(params, "rk3576-boost.bin");
+ if (size < 0)
+ return EXIT_SUCCESS;
+
+ for (i = ARRAY_SIZE(spl_params.images) - 1; i > 0; i--) {
+ spl_params.images[i] = spl_params.images[i - 1];
+ }
+
+ spl_params.images[0].file = "rk3576-boost.bin";
+ spl_params.images[0].size = size;
+
+ spl_params.images[0].address = 0x3ffc0000;
+ spl_params.images[1].address = 0x3ff81000;
+ }
+
return EXIT_SUCCESS;
err_spl_info:
--
2.34.1

2480
projects/Rockchip/patches/u-boot/rockchip-0079-HACK-rockchip-dts-upstream-use-v6.17-rockchip-dts64-.patch Normal file
View File

File diff suppressed because it is too large Load Diff

140
projects/Rockchip/patches/u-boot/rockchip-0080-WIP-board-rockchip-Add-Luckfox-Omni3576.patch Normal file
View File

@@ -0,0 +1,140 @@
From 3523f73954d4d6194739d1cd8b0e2e9c35889741 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 11:05:55 +0000
Subject: [PATCH 80/84] WIP: board: rockchip: Add Luckfox Omni3576
Features tested with a Core3576 Rev1.1 on a Omni3576 carrier board:
- SD-card boot
- eMMC boot
- LED
- PCIe/NVMe
- USB2.0 HOST
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../dts/rk3576-luckfox-omni3576-u-boot.dtsi | 11 ++++
arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
configs/omni3576-rk3576_defconfig | 63 +++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 81 insertions(+)
create mode 100644 arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi
create mode 100644 configs/omni3576-rk3576_defconfig
diff --git a/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi
new file mode 100644
index 00000000000..28773696b97
--- /dev/null
+++ b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+&green_led {
+ default-state = "on";
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+};
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
index 54c75f451f0..e236163992d 100644
--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -4,6 +4,12 @@ S: Maintained
F: arch/arm/dts/rk3576-generic*
F: configs/generic-rk3576_defconfig
+OMNI3576-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-luckfox-omni3576*
+F: configs/omni3576-rk3576_defconfig
+
ROCK-4D-RK3576
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/configs/omni3576-rk3576_defconfig b/configs/omni3576-rk3576_defconfig
new file mode 100644
index 00000000000..13ef3112f1b
--- /dev/null
+++ b/configs/omni3576-rk3576_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-luckfox-omni3576"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-luckfox-omni3576.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 97266d370bf..e751bac9ca7 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -141,6 +141,7 @@ List of mainline supported Rockchip boards:
- ArmSoM Sige5 (sige5-rk3576)
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
- Generic RK3576 (generic-rk3576)
+ - Luckfox Omni3576 (omni3576-rk3576)
- Radxa ROCK 4D (rock-4d-rk3576)
* rk3588
--
2.34.1

178
projects/Rockchip/patches/u-boot/rockchip-0081-WIP-board-rockchip-Add-FriendlyElec-NanoPi-M5.patch Normal file
View File

@@ -0,0 +1,178 @@
From d337711a255fd3c6953f2a86ac242fabc5d419c2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 11 Jul 2025 11:05:19 +0000
Subject: [PATCH 81/84] WIP: board: rockchip: Add FriendlyElec NanoPi M5
Features tested on a NanoPi M5 2411:
- SD-card boot
- SPI flash boot
- Ethernet
- LEDs
- PCIe/NVMe
- USB HOST/OTG
- USER button
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi | 32 ++++++++++
arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
configs/nanopi-m5-rk3576_defconfig | 78 +++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 117 insertions(+)
create mode 100644 arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi
create mode 100644 configs/nanopi-m5-rk3576_defconfig
diff --git a/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi
new file mode 100644
index 00000000000..977d48410f0
--- /dev/null
+++ b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+&fspi1m1_csn0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&fspi1m1_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&led1 {
+ default-state = "off";
+};
+
+&led2 {
+ default-state = "off";
+};
+
+&led_sys {
+ default-state = "on";
+};
+
+&sfc1 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
index e236163992d..393edd3984c 100644
--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -4,6 +4,12 @@ S: Maintained
F: arch/arm/dts/rk3576-generic*
F: configs/generic-rk3576_defconfig
+NANOPI-M5-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-nanopi-m5*
+F: configs/nanopi-m5-rk3576_defconfig
+
OMNI3576-RK3576
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/configs/nanopi-m5-rk3576_defconfig b/configs/nanopi-m5-rk3576_defconfig
new file mode 100644
index 00000000000..28427390a62
--- /dev/null
+++ b/configs/nanopi-m5-rk3576_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-m5"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_SF_DEFAULT_BUS=6
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-m5.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index e751bac9ca7..ffd8671bbc8 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -140,6 +140,7 @@ List of mainline supported Rockchip boards:
* rk3576
- ArmSoM Sige5 (sige5-rk3576)
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
+ - FriendlyElec NanoPi M5 (nanopi-m5-rk3576)
- Generic RK3576 (generic-rk3576)
- Luckfox Omni3576 (omni3576-rk3576)
- Radxa ROCK 4D (rock-4d-rk3576)
--
2.34.1

11
projects/Rockchip/patches/u-boot/0007-rockchip-rk3328-add-ddr4-1600-sdram-timing.patch → projects/Rockchip/patches/u-boot/rockchip-0082-FROMLIST-v1-ram-rk3328-add-ddr4-1600-sdram-timing.patch
View File

@@ -1,7 +1,7 @@
From 825863d08ce323ebcefc03af20fb1e37cdac0eaa Mon Sep 17 00:00:00 2001
From 04e581a594e65a6e401bdfc7458bb8b2de3ab6f0 Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Mon, 19 Sep 2022 13:40:01 -0400
Subject: [PATCH] ram: rk3328: add ddr4-1600 sdram timing
Date: Tue, 10 Jun 2025 19:08:19 +0000
Subject: [PATCH 82/84] FROMLIST(v1): ram: rk3328: add ddr4-1600 sdram timing
Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.
@@ -15,7 +15,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
new file mode 100644
index 000000000000..9594bb428399
index 00000000000..9594bb42839
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
@@ -0,0 +1,226 @@
@@ -245,3 +245,6 @@ index 000000000000..9594bb428399
+ 0x9
+ >;
+};
--
2.34.1

12
projects/Rockchip/patches/u-boot/0006-rockchip-roc-3328-cc-use-1600-ddr4-timing.patch → projects/Rockchip/patches/u-boot/rockchip-0083-FROMLIST-v1-arm64-dts-rockchip-roc-3328-cc-use-1600-.patch
View File

@@ -1,7 +1,8 @@
From 2e54840fd3de7a791669bf20fc7b576b806167b8 Mon Sep 17 00:00:00 2001
From 13151018751bf8ded0ed0148526106853a1a60ba Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Sun, 19 May 2024 18:48:57 -0400
Subject: [PATCH] arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
Date: Tue, 10 Jun 2025 19:08:20 +0000
Subject: [PATCH 83/84] FROMLIST(v1): arm64: dts: rockchip: roc-3328-cc: use
1600 ddr4 timing
Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
@@ -12,7 +13,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 582d6ba49b4e..c47d29c59de9 100644
index 582d6ba49b4..c47d29c59de 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -4,7 +4,7 @@
@@ -24,3 +25,6 @@ index 582d6ba49b4e..c47d29c59de9 100644
/ {
smbios {
--
2.34.1

16
projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch → projects/Rockchip/patches/u-boot/rockchip-0084-KNAERZCHE-rockchip-rk3288-Pick-SD-card-as-first-boot.patch
View File

@@ -1,10 +1,11 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 8220d7fe1068fbcca2d587e1315503a70c498961 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 31 Oct 2022 17:13:47 +0100
Subject: [PATCH 5/6] rockchip: rk3288: Pick SD card as first boot device
Subject: [PATCH 84/84] KNAERZCHE: rockchip: rk3288: Pick SD card as first boot
device
In order to be able to boot from SD card at SPL level, always check this first
and any other mmc device later.
In order to be able to boot from SD card at SPL level, always check
this first and any other mmc device later.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
@@ -12,10 +13,10 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index e411445ed6..17f2dd4d12 100644
index bb0078588fe..3ec97f07c37 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -25,7 +25,7 @@
@@ -15,7 +15,7 @@
chosen {
u-boot,spl-boot-order = \
@@ -24,3 +25,6 @@ index e411445ed6..17f2dd4d12 100644
};
dmc: dmc@ff610000 {
--
2.34.1