mirror of
https://github.com/LibreELEC/LibreELEC.tv
synced 2025-09-24 19:46:01 +07:00
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From 23b7834fa5265f7b4c14b84c454951783adb2156 Mon Sep 17 00:00:00 2001
|
|
From: Jonas Karlman <jonas@kwiboo.se>
|
|
Date: Sun, 20 Jul 2025 13:09:38 +0000
|
|
Subject: [PATCH 12/84] phy: rockchip: naneng-combphy: Enable U3 port for
|
|
USB3OTG on RK3568
|
|
|
|
The USB OTG U3 port may have been disabled early, add support to the
|
|
COMBPHY driver to re-enable the U3 port.
|
|
|
|
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
|
---
|
|
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
|
|
1 file changed, 8 insertions(+)
|
|
|
|
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
|
index 7f107a11606..81195de60bc 100644
|
|
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
|
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
|
@@ -301,6 +301,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
|
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
|
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
|
+ switch (priv->id) {
|
|
+ case 0:
|
|
+ param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
|
|
+ break;
|
|
+ case 1:
|
|
+ param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
|
|
+ break;
|
|
+ }
|
|
break;
|
|
case PHY_TYPE_SATA:
|
|
writel(0x41, priv->mmio + 0x38);
|
|
--
|
|
2.34.1
|
|
|