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linux: add Rockchip kernel and patches for Linux 6.16.y and 6.17.y

Browse Source 
Patches for RK356X, RK3576 and RK3588 are placed in a 'rockchip'
folder under the Linux package dir. Boards use a common aarch64
arch defconfig.

Patches for RK3288, RK3328 and RK3399 are moved to a 'rockchip-old'
folder under the Linux package dir. Boards continue to use device
level 6.16.y defconfigs to ensure all drivers are present, except
for RK3288 which has been moved to the project level folder to be
the common arm arch defconfig.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
This commit is contained in:
Christian Hewitt
2025-06-08 09:42:03 +00:00
parent c4af961996
commit 334b6a6e6b
173 changed files with 41735 additions and 4152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
packages/linux/package.mk
View File

@@ -29,11 +29,23 @@ case "${LINUX}" in
PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
PKG_PATCH_DIRS="raspberrypi rtlwifi/6.13 rtlwifi/6.14 rtlwifi/6.15 rtlwifi/6.17"
;;
rockchip)
PKG_VERSION="76eeb9b8de9880ca38696b2fb56ac45ac0a25c6c" # 6.17-rc5
PKG_SHA256="b2ff7ef05755dadd0cfc526ef59ec80954a89ec6dc71e978ea09cb0420551950"
PKG_URL="https://github.com/chewitt/linux/archive/${PKG_VERSION}.tar.gz"
PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
PKG_PATCH_DIRS="default rockchip rtlwifi/6.17"
;;
*)
PKG_VERSION="6.16.4"
PKG_SHA256="d6a5e3c71a10b533a756251387cc8bf48bbd5c76d842ba5e957d8b1c316ab622"
PKG_URL="https://www.kernel.org/pub/linux/kernel/v${PKG_VERSION/.*/}.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
PKG_PATCH_DIRS="default rtlwifi/6.17"
case ${DEVICE} in
RK3288|RK3328|RK3399)
PKG_PATCH_DIRS+=" rockchip-old"
;;
esac
;;
esac

33
packages/linux/patches/rockchip-old/rockchip-0001-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch Normal file
View File

@@ -0,0 +1,33 @@
From 4b43cee6fc356dc6ad47528ccdafa015bac834e0 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 13 Apr 2019 05:45:18 +0000
Subject: [PATCH 01/59] LOCAL: arm64: fix Kodi sysinfo CPU information
This allows the CPU information to show in the Kodi sysinfo screen, e.g.
"ARMv8 Processor rev 4 (v81)" on Amlogic devices
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/kernel/cpuinfo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index c1f2b6b04b41..8bbdb64ec3ec 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -221,9 +221,8 @@ static int c_show(struct seq_file *m, void *v)
* "processor". Give glibc what it expects.
*/
seq_printf(m, "processor\t: %d\n", cpu);
- if (compat)
- seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
- MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+ MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
loops_per_jiffy / (500000UL/HZ),
--
2.34.1

11
projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch → packages/linux/patches/rockchip-old/rockchip-0002-FROMLIST-v1-mmc-core-set-initial-signal-voltage-on-p.patch
View File

@@ -1,7 +1,8 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From fdf810f853ce77ca62c68689aad383651bbffcfb Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 17 Feb 2019 22:14:38 +0000
Subject: [PATCH] mmc: core: set initial signal voltage on power off
Subject: [PATCH 02/59] FROMLIST(v1): mmc: core: set initial signal voltage on
power off
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. If the card has not been power cycled, it may still be
@@ -23,10 +24,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index ef53a2578824..d4c53074154a 100644
index a0e2dce70434..25b5ac857a11 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1368,6 +1368,14 @@ void mmc_power_off(struct mmc_host *host)
@@ -1374,6 +1374,14 @@ void mmc_power_off(struct mmc_host *host)
if (host->ios.power_mode == MMC_POWER_OFF)
return;
@@ -41,4 +42,6 @@ index ef53a2578824..d4c53074154a 100644
mmc_pwrseq_power_off(host);
host->ios.clock = 0;
--
2.34.1

30
packages/linux/patches/rockchip-old/rockchip-0003-WIP-1000-drm-rockchip-vop-filter-interlaced-modes.patch Normal file
View File

@@ -0,0 +1,30 @@
From e94e5e51e9f5de58dfa6ef2c556117302003db54 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 20 Jul 2020 15:15:50 +0000
Subject: [PATCH 03/59] WIP/1000: drm/rockchip: vop: filter interlaced modes
The current version of the driver does not support interlaced modes,
lets filter any interlaced mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ba6b0528d1e5..4713a6a6a6fe 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1203,6 +1203,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)
return MODE_BAD_HVALUE;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ return MODE_NO_INTERLACE;
+
return MODE_OK;
}
--
2.34.1

49
packages/linux/patches/rockchip-old/rockchip-0004-WIP-1000-drm-rockchip-dw-hdmi-encoder-error-handling.patch Normal file
View File

@@ -0,0 +1,49 @@
From ad4a904ac2fb081ba0e389a4c09520e7b33ee63a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 10 Oct 2020 10:16:32 +0000
Subject: [PATCH 04/59] WIP/1000: drm/rockchip: dw-hdmi: encoder error handling
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index f737e7d46e66..d65409b84888 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -582,7 +582,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
if (ret != -EPROBE_DEFER)
- dev_err(hdmi->dev, "failed to get phy\n");
+ dev_err(hdmi->dev, "failed to get phy: %d\n", ret);
return ret;
}
@@ -604,7 +604,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
}
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+
+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret);
+ goto err_disable_clk;
+ }
platform_set_drvdata(pdev, hdmi);
@@ -623,7 +628,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
err_bind:
drm_encoder_cleanup(encoder);
-
+err_disable_clk:
return ret;
}
--
2.34.1

59
packages/linux/patches/rockchip-old/rockchip-0005-WIP-1000-drm-rockchip-vop-split-rk3288-vop.patch Normal file
View File

@@ -0,0 +1,59 @@
From ea062a001e32bafc832eb0d903f1dad0981d2f8a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 10 Oct 2020 14:32:21 +0000
Subject: [PATCH 05/59] WIP/1000: drm/rockchip: vop: split rk3288 vop
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index d1f788763318..be237c844c49 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -762,7 +762,7 @@ static const struct vop_intr rk3288_vop_intr = {
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
};
-static const struct vop_data rk3288_vop = {
+static const struct vop_data rk3288_vop_big = {
.version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = &rk3288_vop_intr,
@@ -780,6 +780,19 @@ static const struct vop_data rk3288_vop = {
.max_output = { 3840, 2160 },
};
+static const struct vop_data rk3288_vop_lit = {
+ .version = VOP_VERSION(3, 1),
+ .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 2560, 1600 },
+ .intr = &rk3288_vop_intr,
+ .common = &rk3288_common,
+ .modeset = &rk3288_modeset,
+ .output = &rk3288_output,
+ .win = rk3288_vop_win_data,
+ .win_size = ARRAY_SIZE(rk3288_vop_win_data),
+ .lut_size = 1024,
+};
+
static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
@@ -1245,8 +1258,10 @@ static const struct of_device_id vop_driver_dt_match[] = {
.data = &rk3066_vop },
{ .compatible = "rockchip,rk3188-vop",
.data = &rk3188_vop },
- { .compatible = "rockchip,rk3288-vop",
- .data = &rk3288_vop },
+ { .compatible = "rockchip,rk3288-vop-big",
+ .data = &rk3288_vop_big },
+ { .compatible = "rockchip,rk3288-vop-lit",
+ .data = &rk3288_vop_lit },
{ .compatible = "rockchip,rk3368-vop",
.data = &rk3368_vop },
{ .compatible = "rockchip,rk3366-vop",
--
2.34.1

35
packages/linux/patches/rockchip-old/rockchip-0006-WIP-1000-ARM-dts-rockchip-split-rk3288-vop.patch Normal file
View File

@@ -0,0 +1,35 @@
From 93bbd545a8d3226afddac5c556e55727c21cc93a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 10 Oct 2020 14:33:30 +0000
Subject: [PATCH 06/59] WIP/1000: ARM: dts: rockchip: split rk3288 vop
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 42d705b544ec..60ff3bf14efe 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1023,7 +1023,7 @@ rga: rga@ff920000 {
};
vopb: vop@ff930000 {
- compatible = "rockchip,rk3288-vop";
+ compatible = "rockchip,rk3288-vop-big";
reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
@@ -1072,7 +1072,7 @@ vopb_mmu: iommu@ff930300 {
};
vopl: vop@ff940000 {
- compatible = "rockchip,rk3288-vop";
+ compatible = "rockchip,rk3288-vop-lit";
reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
--
2.34.1

80
packages/linux/patches/rockchip-old/rockchip-0007-WIP-1000-drm-bridge-dw-hdmi-add-mtmdsclock-parameter.patch Normal file
View File

@@ -0,0 +1,80 @@
From 9083fb44e20e507b6182537a8fab356b540a3afe Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 20 Jul 2020 18:00:44 +0000
Subject: [PATCH 07/59] WIP/1000: drm/bridge: dw-hdmi: add mtmdsclock parameter
to phy configure ops
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++----
drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c | 3 ++-
include/drm/bridge/dw_hdmi.h | 3 ++-
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 8791408dd1ff..ac1886c7e967 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -125,7 +125,8 @@ struct dw_hdmi_phy_data {
bool has_svsret;
int (*configure)(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
- unsigned long mpixelclock);
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock);
};
struct dw_hdmi {
@@ -1568,7 +1569,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
*/
static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
- unsigned long mpixelclock)
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock)
{
const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
@@ -1643,9 +1645,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
/* Write to the PHY as configured by the platform */
if (pdata->configure_phy)
- ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock, mtmdsclock);
else
- ret = phy->configure(hdmi, pdata, mpixelclock);
+ ret = phy->configure(hdmi, pdata, mpixelclock, mtmdsclock);
if (ret) {
dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
mpixelclock);
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
index c0176e5de9a8..90ca280ecd65 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c
@@ -53,7 +53,8 @@ rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
}
static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
- unsigned long mpixelclock)
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock)
{
const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 6a46baa0737c..4c0f850ce3c7 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -159,7 +159,8 @@ struct dw_hdmi_plat_data {
const struct dw_hdmi_curr_ctrl *cur_ctr;
const struct dw_hdmi_phy_config *phy_config;
int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
- unsigned long mpixelclock);
+ unsigned long mpixelclock,
+ unsigned long mtmdsclock);
unsigned int disable_cec : 1;
};
--
2.34.1

63
packages/linux/patches/rockchip-old/rockchip-0008-WIP-1000-drm-bridge-dw-hdmi-support-configuring-phy-.patch Normal file
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@@ -0,0 +1,63 @@
From 3f5ec049285b42b587f67b7d06ae3dacad340443 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 20 Jul 2020 21:34:48 +0000
Subject: [PATCH 08/59] WIP/1000: drm/bridge: dw-hdmi: support configuring phy
for deep color
Q: Should we rename dw_hdmi_curr_ctrl and dw_hdmi_phy_config mpixelclock to mtmdsclock ?
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ac1886c7e967..c039bffef20d 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1575,6 +1575,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
+ int depth;
/* TOFIX Will need 420 specific PHY configuration tables */
@@ -1584,11 +1585,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
break;
for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
- if (mpixelclock <= curr_ctrl->mpixelclock)
+ if (mtmdsclock <= curr_ctrl->mpixelclock)
break;
for (; phy_config->mpixelclock != ~0UL; phy_config++)
- if (mpixelclock <= phy_config->mpixelclock)
+ if (mtmdsclock <= phy_config->mpixelclock)
break;
if (mpll_config->mpixelclock == ~0UL ||
@@ -1596,11 +1597,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
phy_config->mpixelclock == ~0UL)
return -EINVAL;
- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
+ depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
+ if (depth > 8 && mpixelclock != mtmdsclock)
+ depth = fls(depth - 8) - 1;
+ else
+ depth = 0;
+
+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce,
HDMI_3D_TX_PHY_CPCE_CTRL);
- dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
+ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp,
HDMI_3D_TX_PHY_GMPCTRL);
- dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
+ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth],
HDMI_3D_TX_PHY_CURRCTRL);
dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
--
2.34.1

42
packages/linux/patches/rockchip-old/rockchip-0009-WIP-1000-drm-bridge-dw-hdmi-add-mpll_cfg_420-for-ycb.patch Normal file
View File

@@ -0,0 +1,42 @@
From e607320d74784d71236d70e32b63fbf5f7a7b636 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 20 Jul 2020 22:25:15 +0000
Subject: [PATCH 09/59] WIP/1000: drm/bridge: dw-hdmi: add mpll_cfg_420 for
ycbcr420 mode
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++-
include/drm/bridge/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index c039bffef20d..6cc5410b26f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1577,7 +1577,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
int depth;
- /* TOFIX Will need 420 specific PHY configuration tables */
+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
+ pdata->mpll_cfg_420)
+ mpll_config = pdata->mpll_cfg_420;
/* PLL/MPLL Cfg - always match on final entry */
for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 4c0f850ce3c7..30313f6db44e 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -156,6 +156,7 @@ struct dw_hdmi_plat_data {
/* Synopsys PHY support */
const struct dw_hdmi_mpll_config *mpll_cfg;
+ const struct dw_hdmi_mpll_config *mpll_cfg_420;
const struct dw_hdmi_curr_ctrl *cur_ctr;
const struct dw_hdmi_phy_config *phy_config;
int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
--
2.34.1

73
packages/linux/patches/rockchip-old/rockchip-0010-WIP-1000-drm-rockchip-dw-hdmi-add-YCbCr420-mpll-cfg-.patch Normal file
View File

@@ -0,0 +1,73 @@
From aaf29a7a0aec22f0e4181824dbd3f813cb400ec4 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 20 Jul 2020 22:26:19 +0000
Subject: [PATCH 10/59] WIP/1000: drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg
for rk3399
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index d65409b84888..3310a0dd1c43 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -178,6 +178,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
}
};
+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
+ {
+ 30666000, {
+ { 0x00b7, 0x0000 },
+ { 0x2157, 0x0000 },
+ { 0x40f7, 0x0000 },
+ },
+ }, {
+ 92000000, {
+ { 0x00b7, 0x0000 },
+ { 0x2143, 0x0001 },
+ { 0x40a3, 0x0001 },
+ },
+ }, {
+ 184000000, {
+ { 0x0073, 0x0001 },
+ { 0x2146, 0x0002 },
+ { 0x4062, 0x0002 },
+ },
+ }, {
+ 340000000, {
+ { 0x0052, 0x0003 },
+ { 0x214d, 0x0003 },
+ { 0x4065, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x0041, 0x0003 },
+ { 0x3b4d, 0x0003 },
+ { 0x5a65, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
@@ -487,6 +527,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
+ .mpll_cfg_420 = rockchip_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.phy_data = &rk3399_chip_data,
--
2.34.1

74
packages/linux/patches/rockchip-old/rockchip-0011-WIP-1000-drm-rockchip-dw-hdmi-add-YCbCr420-mpll-cfg-.patch Normal file
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@@ -0,0 +1,74 @@
From debd69140c65ab39e3723c0a82865510763539de Mon Sep 17 00:00:00 2001
From: Shunqing Chen <csq@rock-chips.com>
Date: Wed, 15 Jul 2020 15:19:11 +0800
Subject: [PATCH 11/59] WIP/1000: drm/rockchip: dw-hdmi: add YCbCr420 mpll cfg
for rk3288w
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 3310a0dd1c43..c7841c7d5daf 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -218,6 +218,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
}
};
+static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = {
+ {
+ 30666000, {
+ { 0x00b7, 0x0000 },
+ { 0x2157, 0x0000 },
+ { 0x40f7, 0x0000 },
+ },
+ }, {
+ 92000000, {
+ { 0x00b7, 0x0000 },
+ { 0x2143, 0x0001 },
+ { 0x40a3, 0x0001 },
+ },
+ }, {
+ 184000000, {
+ { 0x0073, 0x0001 },
+ { 0x2146, 0x0002 },
+ { 0x4062, 0x0002 },
+ },
+ }, {
+ 340000000, {
+ { 0x0052, 0x0003 },
+ { 0x214d, 0x0003 },
+ { 0x4065, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a65, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
@@ -490,6 +530,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
+ .mpll_cfg_420 = rockchip_rk3288w_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.phy_data = &rk3288_chip_data,
--
2.34.1

232
packages/linux/patches/rockchip-old/rockchip-0012-WIP-1000-drm-rockchip-dw-hdmi-add-bridge-and-switch-.patch Normal file
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@@ -0,0 +1,232 @@
From 588d403becca3bbf4e6e32c9bab9d15a6967c9f7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 20 Dec 2019 08:12:42 +0000
Subject: [PATCH 12/59] WIP/1000: drm/rockchip: dw-hdmi: add bridge and switch
to drm_bridge_funcs
Switch the dw-hdmi driver to drm_bridge_funcs by implementing
a new local bridge, connecting it to the dw-hdmi bridge.
Also enable bridge format negotiation by implementing
atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------
1 file changed, 81 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index c7841c7d5daf..a50218412fb0 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
+#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
@@ -73,6 +74,7 @@ struct rockchip_hdmi_chip_data {
struct rockchip_hdmi {
struct device *dev;
struct regmap *regmap;
+ struct drm_bridge bridge;
struct rockchip_encoder encoder;
const struct rockchip_hdmi_chip_data *chip_data;
const struct dw_hdmi_plat_data *plat_data;
@@ -83,11 +85,9 @@ struct rockchip_hdmi {
struct phy *phy;
};
-static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge)
{
- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-
- return container_of(rkencoder, struct rockchip_hdmi, encoder);
+ return container_of(bridge, struct rockchip_hdmi, bridge);
}
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
@@ -343,31 +343,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
return MODE_OK;
}
-
-static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
+static void
+dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
{
-}
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
-static bool
-dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- return true;
+ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000);
}
-static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
+static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge)
{
- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_encoder *encoder = bridge->encoder;
- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
-}
-
-static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
-{
- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
u32 val;
int ret;
@@ -394,10 +384,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
dev_dbg(hdmi->dev, "vop %s output to hdmi\n", ret ? "LIT" : "BIG");
}
+static bool is_rgb(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int
-dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
+dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
@@ -407,12 +408,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
}
-static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
- .mode_set = dw_hdmi_rockchip_encoder_mode_set,
- .enable = dw_hdmi_rockchip_encoder_enable,
- .disable = dw_hdmi_rockchip_encoder_disable,
- .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
+static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmt;
+
+ *num_input_fmts = 0;
+
+ if (!is_rgb(output_fmt))
+ return NULL;
+
+ input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL);
+ if (!input_fmt)
+ return NULL;
+
+ *num_input_fmts = 1;
+ *input_fmt = output_fmt;
+
+ return input_fmt;
+}
+
+static const struct drm_bridge_funcs dw_hdmi_rockchip_bridge_funcs = {
+ .mode_set = dw_hdmi_rockchip_bridge_mode_set,
+ .enable = dw_hdmi_rockchip_bridge_enable,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_get_input_bus_fmts = dw_hdmi_rockchip_get_input_bus_fmts,
+ .atomic_check = dw_hdmi_rockchip_bridge_atomic_check,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
};
static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
@@ -616,6 +643,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
struct dw_hdmi_plat_data *plat_data;
const struct of_device_id *match;
struct drm_device *drm = data;
+ struct drm_bridge *next_bridge;
struct drm_encoder *encoder;
struct rockchip_hdmi *hdmi;
int ret;
@@ -685,20 +713,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
RK3568_HDMI_SCLIN_MSK));
}
- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
-
ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
if (ret) {
DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret);
goto err_disable_clk;
}
+ hdmi->bridge.funcs = &dw_hdmi_rockchip_bridge_funcs;
+ drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
+
platform_set_drvdata(pdev, hdmi);
- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
+ hdmi->hdmi = dw_hdmi_probe(pdev, plat_data);
/*
- * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(),
* which would have called the encoder cleanup. Do it manually.
*/
if (IS_ERR(hdmi->hdmi)) {
@@ -706,8 +735,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
goto err_bind;
}
+ next_bridge = of_drm_find_bridge(pdev->dev.of_node);
+ if (!next_bridge) {
+ ret = -EPROBE_DEFER;
+ goto err_dw_hdmi_remove;
+ }
+
+ ret = drm_bridge_attach(encoder, next_bridge, &hdmi->bridge, 0);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(hdmi->dev, "Failed to attach dw-hdmi bridge: %d\n", ret);
+ goto err_dw_hdmi_remove;
+ }
+
return 0;
+err_dw_hdmi_remove:
+ dw_hdmi_remove(hdmi->hdmi);
err_bind:
drm_encoder_cleanup(encoder);
err_disable_clk:
@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
{
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
- dw_hdmi_unbind(hdmi->hdmi);
+ dw_hdmi_remove(hdmi->hdmi);
drm_encoder_cleanup(&hdmi->encoder.encoder);
}
--
2.34.1

59
packages/linux/patches/rockchip-old/rockchip-0013-WIP-1000-drm-rockchip-vop-add-immutable-zpos-propert.patch Normal file
View File

@@ -0,0 +1,59 @@
From 530254cb68fb1733fa7d5908b411083bad418ae9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 9 Oct 2020 15:29:27 +0000
Subject: [PATCH 13/59] WIP/1000: drm/rockchip: vop: add immutable zpos
property
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 ++
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
index 5829ee061c61..856d2ce56239 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
@@ -81,6 +81,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev)
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
+ dev->mode_config.normalize_zpos = true;
+
dev->mode_config.funcs = &rockchip_drm_mode_config_funcs;
dev->mode_config.helper_private = &rockchip_mode_config_helpers;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4713a6a6a6fe..4d9326b28740 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1843,7 +1843,7 @@ static irqreturn_t vop_isr(int irq, void *data)
return ret;
}
-static void vop_plane_add_properties(struct drm_plane *plane,
+static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
const struct vop_win_data *win_data)
{
unsigned int flags = 0;
@@ -1853,6 +1853,8 @@ static void vop_plane_add_properties(struct drm_plane *plane,
if (flags)
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_0 | flags);
+
+ drm_plane_create_zpos_immutable_property(plane, zpos);
}
static int vop_create_crtc(struct vop *vop)
@@ -1893,7 +1895,7 @@ static int vop_create_crtc(struct vop *vop)
plane = &vop_win->base;
drm_plane_helper_add(plane, &plane_helper_funcs);
- vop_plane_add_properties(plane, win_data);
+ vop_plane_add_properties(plane, i, win_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
--
2.34.1

71
packages/linux/patches/rockchip-old/rockchip-0014-WIP-1000-drm-rockchip-vop-add-plane-color-properties.patch Normal file
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@@ -0,0 +1,71 @@
From 3578549f1b2797596ff3a04697918246ded5dcc7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 10 Oct 2020 09:20:44 +0000
Subject: [PATCH 14/59] WIP/1000: drm/rockchip: vop: add plane color properties
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4d9326b28740..ea6dd61b4c1c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1843,8 +1843,23 @@ static irqreturn_t vop_isr(int irq, void *data)
return ret;
}
+static bool plane_supports_yuv_format(const struct drm_plane *plane)
+{
+ const struct drm_format_info *info;
+ int i;
+
+ for (i = 0; i < plane->format_count; i++) {
+ info = drm_format_info(plane->format_types[i]);
+ if (info->is_yuv)
+ return true;
+ }
+
+ return false;
+}
+
static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
- const struct vop_win_data *win_data)
+ const struct vop_win_data *win_data,
+ const struct vop_data *vop_data)
{
unsigned int flags = 0;
@@ -1855,6 +1870,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos,
DRM_MODE_ROTATE_0 | flags);
drm_plane_create_zpos_immutable_property(plane, zpos);
+
+ if (!plane_supports_yuv_format(plane))
+ return;
+
+ flags = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
+ if (vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)
+ flags |= BIT(DRM_COLOR_YCBCR_BT2020);
+
+ drm_plane_create_color_properties(plane, flags,
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+ DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
}
static int vop_create_crtc(struct vop *vop)
@@ -1895,7 +1923,7 @@ static int vop_create_crtc(struct vop *vop)
plane = &vop_win->base;
drm_plane_helper_add(plane, &plane_helper_funcs);
- vop_plane_add_properties(plane, i, win_data);
+ vop_plane_add_properties(plane, i, win_data, vop_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
--
2.34.1

66
packages/linux/patches/rockchip-old/rockchip-0015-WIP-1000-HACK-clk-rockchip-rk3288-dedicate-npll-for-.patch Normal file
View File

@@ -0,0 +1,66 @@
From 56e811120c24e4c91bcb00948ea3fc6e39b90a74 Mon Sep 17 00:00:00 2001
From: Nickey Yang <nickey.yang@rock-chips.com>
Date: Mon, 17 Jul 2017 16:35:34 +0800
Subject: [PATCH 15/59] WIP/1000: HACK: clk: rockchip: rk3288: dedicate npll
for vopb and hdmi use
MINIARM: set npll be used for hdmi only
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 9 +++++----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 60ff3bf14efe..bf0416834a5d 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1032,6 +1032,8 @@ vopb: vop@ff930000 {
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
+ assigned-clocks = <&cru DCLK_VOP0>;
+ assigned-clock-parents = <&cru PLL_NPLL>;
status = "disabled";
vopb_out: port {
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 0a1e017df7c6..89141dbfd483 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
+PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" };
+PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" };
+PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" };
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
--
2.34.1

74
packages/linux/patches/rockchip-old/rockchip-0016-WIP-1000-HACK-clk-rockchip-rk3288-use-npll-table-to-.patch Normal file
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@@ -0,0 +1,74 @@
From bf04a56d11d5691a02576a23c555b3aed84fb03f Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 14:51:14 +0200
Subject: [PATCH 16/59] WIP/1000: HACK: clk: rockchip: rk3288: use npll table
to to improve HDMI compatibility
Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 89141dbfd483..1da21ac9aad9 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
+ RK3066_PLL_RATE(348500000, 8, 697, 6),
+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
+ RK3066_PLL_RATE(241500000, 2, 161, 8),
+ RK3066_PLL_RATE(162000000, 1, 81, 12),
+ RK3066_PLL_RATE(154000000, 6, 539, 14),
+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
+ RK3066_PLL_RATE(121750000, 6, 487, 16),
+ RK3066_PLL_RATE(119000000, 3, 238, 16),
+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
+ RK3066_PLL_RATE(101000000, 3, 202, 16),
+ RK3066_PLL_RATE(88750000, 6, 355, 16),
+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
+ RK3066_PLL_RATE(83500000, 3, 167, 16),
+ RK3066_PLL_RATE(79500000, 1, 53, 16),
+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
+ RK3066_PLL_RATE(72000000, 1, 48, 16),
+ RK3066_PLL_RATE(71000000, 3, 142, 16),
+ RK3066_PLL_RATE(68250000, 2, 91, 16),
+ RK3066_PLL_RATE(65000000, 3, 130, 16),
+ RK3066_PLL_RATE(40000000, 3, 80, 16),
+ RK3066_PLL_RATE(33750000, 2, 45, 16),
+ { /* sentinel */ },
+};
+
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
--
2.34.1

120
packages/linux/patches/rockchip-old/rockchip-0017-WIP-1000-HACK-clk-rockchip-rk3399-dedicate-vpll-for-.patch Normal file
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@@ -0,0 +1,120 @@
From 10c63cc34f478c0265233b4a9911287940d29b05 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 25 May 2020 20:36:45 +0000
Subject: [PATCH 17/59] WIP/1000: HACK: clk: rockchip: rk3399: dedicate vpll
for vopb and hdmi use
Rockchip PLLs are kown provide the least jitter for
vco rates between 800 MHz and 2 GHz. I added the
rates for VPLL which are used for VOPs dclk and there-
fore HDMI phy in that manner and used the rates which
require the lowest frac divs.
Additionally I added some rates which are useful to
provide additional VESA and non-VESA rates for HDMI
output.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++-----
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index c2b243d7a5e2..a7e397fa9893 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */
+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */
+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */
+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */
+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */
+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */
+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */
+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/
+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */
+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */
+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */
+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */
+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */
+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */
+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */
+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */
+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */
+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */
+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */
+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */
+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */
+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */
+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */
+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */
+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */
+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */
+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */
+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
- "vpll_aclk_cci_src" };
+ "prevent:vpll" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" };
+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" };
+
+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll",
"npll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
+ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 0, GFLAGS),
- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
--
2.34.1

68
packages/linux/patches/rockchip-old/rockchip-0018-WIP-1000-HACK-dts-rockchip-do-not-use-vopl-for-hdmi.patch Normal file
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@@ -0,0 +1,68 @@
From 157ab827903e68cfb141f5bc600096ca822fffdf Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 19 Jul 2020 16:35:11 +0000
Subject: [PATCH 18/59] WIP/1000: HACK: dts: rockchip: do not use vopl for hdmi
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 10 ----------
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 9 ---------
2 files changed, 19 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index bf0416834a5d..5f3e3cc8757c 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1089,11 +1089,6 @@ vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vopl>;
- };
-
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
@@ -1260,11 +1255,6 @@ hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
-
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
};
hdmi_out: port@1 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index 9d5f5b083e3c..ec5ca40b2159 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1846,11 +1846,6 @@ vopl_out_edp: endpoint@1 {
remote-endpoint = <&edp_in_vopl>;
};
- vopl_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_vopl>;
- };
-
vopl_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopl>;
@@ -2048,10 +2043,6 @@ hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
};
hdmi_out: port@1 {
--
2.34.1

148
packages/linux/patches/rockchip-old/rockchip-0019-WIP-1000-drm-bridge-dw-hdmi-limit-mode-and-bus-forma.patch Normal file
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@@ -0,0 +1,148 @@
From f0edc32c73f5f47c134dcd1f461f7e446fc67406 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 20 Dec 2019 08:12:43 +0000
Subject: [PATCH 19/59] WIP/1000: drm/bridge: dw-hdmi: limit mode and bus
format to max_tmds_clock
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 74 ++++++++++++++---------
1 file changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 6cc5410b26f5..d3227ba79977 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1986,6 +1986,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
}
+static unsigned int
+hdmi_get_tmdsclock(unsigned int bus_format, unsigned int pixelclock)
+{
+ int color_depth = hdmi_bus_fmt_color_depth(bus_format);
+ unsigned int tmdsclock = pixelclock;
+
+ if (!hdmi_bus_fmt_is_yuv422(bus_format) && color_depth > 8)
+ tmdsclock = (u64)pixelclock * color_depth / 8;
+
+ if (hdmi_bus_fmt_is_yuv420(bus_format))
+ tmdsclock /= 2;
+
+ return tmdsclock;
+}
+
static void hdmi_av_composer(struct dw_hdmi *hdmi,
const struct drm_display_info *display,
const struct drm_display_mode *mode)
@@ -1997,29 +2012,12 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
unsigned int vdisplay, hdisplay;
vmode->mpixelclock = mode->clock * 1000;
+ vmode->mtmdsclock =
+ hdmi_get_tmdsclock(hdmi->hdmi_data.enc_out_bus_format,
+ vmode->mpixelclock);
dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
- vmode->mtmdsclock = vmode->mpixelclock;
-
- if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
- switch (hdmi_bus_fmt_color_depth(
- hdmi->hdmi_data.enc_out_bus_format)) {
- case 16:
- vmode->mtmdsclock = vmode->mpixelclock * 2;
- break;
- case 12:
- vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
- break;
- case 10:
- vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
- break;
- }
- }
-
- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
- vmode->mtmdsclock /= 2;
-
dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
/* Set up HDMI_FC_INVIDCONF */
@@ -2645,8 +2643,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
* - MEDIA_BUS_FMT_YUV8_1X24,
*/
-/* Can return a maximum of 11 possible output formats for a mode/connector */
-#define MAX_OUTPUT_SEL_FORMATS 11
+/* Can return a maximum of 15 possible output formats for a mode/connector */
+#define MAX_OUTPUT_SEL_FORMATS 15
+
+static bool is_tmds_allowed(struct drm_display_info *info,
+ struct drm_display_mode *mode,
+ u32 bus_format)
+{
+ unsigned long tmdsclock = hdmi_get_tmdsclock(bus_format, mode->clock);
+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
+
+ if (max_tmds_clock >= tmdsclock)
+ return true;
+
+ return false;
+}
static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
@@ -2658,8 +2669,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_display_info *info = &conn->display_info;
struct drm_display_mode *mode = &crtc_state->mode;
u8 max_bpc = conn_state->max_requested_bpc;
- bool is_hdmi2_sink = info->hdmi.scdc.supported ||
- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
u32 *output_fmts;
unsigned int i = 0;
@@ -2683,9 +2692,8 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
* If the current mode enforces 4:2:0, force the output bus format
* to 4:2:0 and do not add the YUV422/444/RGB formats
*/
- if (conn->ycbcr_420_allowed &&
- (drm_mode_is_420_only(info, mode) ||
- (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
+ if (conn->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
/* Order bus formats from 16bit to 8bit if supported */
if (max_bpc >= 16 && info->bpc == 16 &&
@@ -2715,7 +2723,8 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
*/
/* Default 8bit RGB fallback */
- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
if (max_bpc >= 16 && info->bpc == 16) {
if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
@@ -2930,11 +2939,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
struct dw_hdmi *hdmi = bridge->driver_private;
const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
enum drm_mode_status mode_status = MODE_OK;
+ int max_tmds_clock = info->max_tmds_clock ? info->max_tmds_clock : 340000;
+ int clock = mode->clock;
/* We don't support double-clocked modes */
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
return MODE_BAD;
+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420))
+ clock /= 2;
+
+ if (clock > max_tmds_clock)
+ return MODE_CLOCK_HIGH;
+
if (pdata->mode_valid)
mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
mode);
--
2.34.1

114
packages/linux/patches/rockchip-old/rockchip-0020-WIP-1000-drm-rockchip-dw_hdmi-add-10-bit-rgb-bus-for.patch Normal file
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@@ -0,0 +1,114 @@
From 867633919b4c29eb75abf3b61099d59b946c6318 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 20 Dec 2019 08:12:42 +0000
Subject: [PATCH 20/59] WIP/1000: drm/rockchip: dw_hdmi: add 10-bit rgb bus
format
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 +++++++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 +
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index a50218412fb0..8134add505e0 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -85,6 +85,8 @@ struct rockchip_hdmi {
struct phy *phy;
};
+#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x)
+
static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge)
{
return container_of(bridge, struct rockchip_hdmi, bridge);
@@ -349,6 +351,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *adjusted_mode)
{
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_crtc_state *crtc_state = to_crtc_state(adjusted_mode);
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+
+ if (hdmi->phy)
+ phy_set_bus_width(hdmi->phy, s->bus_width);
clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000);
}
@@ -388,6 +395,17 @@ static bool is_rgb(u32 format)
{
switch (format) {
case MEDIA_BUS_FMT_RGB888_1X24:
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_10bit(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_RGB101010_1X30:
return true;
default:
return false;
@@ -401,9 +419,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_atomic_state *state = bridge_state->base.state;
+ struct drm_crtc_state *old_crtc_state;
+ struct rockchip_crtc_state *old_state;
+ u32 format = bridge_state->output_bus_cfg.format;
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+ s->output_bpc = 10;
+ s->bus_format = format;
+ s->bus_width = is_10bit(format) ? 10 : 8;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
+ if (old_crtc_state && !crtc_state->mode_changed) {
+ old_state = to_rockchip_crtc_state(old_crtc_state);
+ if (s->bus_format != old_state->bus_format ||
+ s->bus_width != old_state->bus_width)
+ crtc_state->mode_changed = true;
+ }
return 0;
}
@@ -415,10 +448,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
u32 output_fmt,
unsigned int *num_input_fmts)
{
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
+ struct drm_encoder *encoder = bridge->encoder;
u32 *input_fmt;
+ bool has_10bit = true;
*num_input_fmts = 0;
+ if (drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder))
+ has_10bit = false;
+
+ if (!has_10bit && is_10bit(output_fmt))
+ return NULL;
+
if (!is_rgb(output_fmt))
return NULL;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index c183e82a42a5..98040929412c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -53,6 +53,7 @@ struct rockchip_crtc_state {
u32 bus_format;
u32 bus_flags;
int color_space;
+ int bus_width;
};
#define to_rockchip_crtc_state(s) \
container_of(s, struct rockchip_crtc_state, base)
--
2.34.1

54
packages/linux/patches/rockchip-old/rockchip-0021-WIP-1000-drm-dw-hdmi-add-content-type-connector-prop.patch Normal file
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@@ -0,0 +1,54 @@
From 3f52eff8a27b76c970ad115392f7ec7ca66883d6 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 8 Dec 2019 23:42:44 +0000
Subject: [PATCH 21/59] WIP/1000: drm: dw-hdmi: add content type connector
property
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index d3227ba79977..e7677dcf28f4 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1773,6 +1773,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi,
const struct drm_connector *connector,
const struct drm_display_mode *mode)
{
+ const struct drm_connector_state *conn_state = connector->state;
struct hdmi_avi_infoframe frame;
u8 val;
@@ -1830,6 +1831,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi,
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
}
+ drm_hdmi_avi_infoframe_content_type(&frame, conn_state);
+
/*
* The Designware IP uses a different byte format from standard
* AVI info frames, though generally the bits are in the correct
@@ -2534,7 +2537,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
if (!crtc)
return 0;
- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
+ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) ||
+ old_state->content_type != new_state->content_type) {
crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
@@ -2602,6 +2606,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
drm_connector_attach_max_bpc_property(connector, 8, 16);
+ drm_connector_attach_content_type_property(connector);
+
if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
drm_connector_attach_hdr_output_metadata_property(connector);
--
2.34.1

226
packages/linux/patches/rockchip-old/rockchip-0022-WIP-1000-drm-rockchip-add-yuv444-support.patch Normal file
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@@ -0,0 +1,226 @@
From c5e477f27cb0d69f8f4e6c3c2c8209cbc6b54db5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 20 Dec 2019 08:12:43 +0000
Subject: [PATCH 22/59] WIP/1000: drm/rockchip: add yuv444 support
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 +++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++
4 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 8134add505e0..07a8796b1f47 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -69,6 +69,7 @@ struct rockchip_hdmi_chip_data {
u32 lcdsel_big;
u32 lcdsel_lit;
int max_tmds_clock;
+ bool ycbcr_444_allowed;
};
struct rockchip_hdmi {
@@ -402,10 +403,22 @@ static bool is_rgb(u32 format)
}
}
+static bool is_yuv444(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool is_10bit(u32 format)
{
switch (format) {
case MEDIA_BUS_FMT_RGB101010_1X30:
+ case MEDIA_BUS_FMT_YUV10_1X30:
return true;
default:
return false;
@@ -422,12 +435,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
struct drm_atomic_state *state = bridge_state->base.state;
struct drm_crtc_state *old_crtc_state;
struct rockchip_crtc_state *old_state;
+ struct drm_bridge *next_bridge;
+ struct drm_bridge_state *next_bridge_state;
u32 format = bridge_state->output_bus_cfg.format;
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
s->output_bpc = 10;
s->bus_format = format;
+
+ next_bridge = drm_bridge_get_next_bridge(bridge);
+ if (next_bridge) {
+ next_bridge_state = drm_atomic_get_new_bridge_state(state,
+ next_bridge);
+ format = next_bridge_state->output_bus_cfg.format;
+ }
+
s->bus_width = is_10bit(format) ? 10 : 8;
old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
@@ -461,7 +484,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
if (!has_10bit && is_10bit(output_fmt))
return NULL;
- if (!is_rgb(output_fmt))
+ if (is_yuv444(output_fmt)) {
+ if (!hdmi->chip_data->ycbcr_444_allowed)
+ return NULL;
+ } else if (!is_rgb(output_fmt))
return NULL;
input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL);
@@ -616,6 +642,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
static struct rockchip_hdmi_chip_data rk3328_chip_data = {
.lcdsel_grf_reg = -1,
.max_tmds_clock = 594000,
+ .ycbcr_444_allowed = true,
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ea6dd61b4c1c..784599231a6a 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -344,6 +344,17 @@ static int vop_convert_afbc_format(uint32_t format)
}
}
+static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
uint32_t dst, bool is_horizontal,
int vsu_mode, int *vskiplines)
@@ -1382,6 +1393,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
u16 vact_end = vact_st + vdisplay;
uint32_t pin_pol, val;
int dither_bpc = s->output_bpc ? s->output_bpc : 10;
+ bool yuv_output = is_yuv_output(s->bus_format);
int ret;
if (old_state && old_state->self_refresh_active) {
@@ -1447,6 +1459,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0);
+
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
VOP_REG_SET(vop, common, pre_dither_down, 1);
else
@@ -1462,6 +1476,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
VOP_REG_SET(vop, common, out_mode, s->output_mode);
+ VOP_REG_SET(vop, common, overlay_mode, yuv_output);
+ VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output);
+
+ /*
+ * Background color is 10bit depth if vop version >= 3.5
+ */
+ if (!yuv_output)
+ val = 0;
+ else if (VOP_MAJOR(vop_data->version) == 3 &&
+ VOP_MINOR(vop_data->version) >= 5)
+ val = 0x20010200;
+ else
+ val = 0x801080;
+ VOP_REG_SET(vop, common, dsp_background, val);
+
VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
val |= hact_end;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index f04c9731ae7b..1fa0ecdf734c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -125,10 +125,16 @@ struct vop_common {
struct vop_reg dma_stop;
struct vop_reg out_mode;
struct vop_reg standby;
+
+ struct vop_reg overlay_mode;
+ struct vop_reg dsp_data_swap;
+ struct vop_reg dsp_out_yuv;
+ struct vop_reg dsp_background;
};
struct vop_misc {
struct vop_reg global_regdone_en;
+ struct vop_reg win_channel[4];
};
struct vop_intr {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index be237c844c49..234e03edae12 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -727,6 +727,11 @@ static const struct vop_common rk3288_common = {
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16),
+ .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
};
/*
@@ -952,6 +957,11 @@ static const struct vop_common rk3399_common = {
.dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16),
+ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
};
static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
@@ -1146,6 +1156,10 @@ static const struct vop_output rk3328_output = {
static const struct vop_misc rk3328_misc = {
.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
+
+ .win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0),
+ .win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0),
+ .win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0),
};
static const struct vop_common rk3328_common = {
@@ -1158,6 +1172,11 @@ static const struct vop_common rk3328_common = {
.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
+
+ .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
+ .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
+ .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
+ .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
};
static const struct vop_intr rk3328_vop_intr = {
--
2.34.1

162
packages/linux/patches/rockchip-old/rockchip-0023-WIP-1000-drm-rockchip-add-yuv420-support.patch Normal file
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@@ -0,0 +1,162 @@
From cf6bdd17cce3027d0e77ffa46ff79fb6e5005e15 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 20 Dec 2019 08:12:43 +0000
Subject: [PATCH 23/59] WIP/1000: drm/rockchip: add yuv420 support
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 07a8796b1f47..a01586ad44a2 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -414,9 +414,21 @@ static bool is_yuv444(u32 format)
}
}
+static bool is_yuv420(u32 format)
+{
+ switch (format) {
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool is_10bit(u32 format)
{
switch (format) {
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
case MEDIA_BUS_FMT_RGB101010_1X30:
case MEDIA_BUS_FMT_YUV10_1X30:
return true;
@@ -453,6 +465,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge,
s->bus_width = is_10bit(format) ? 10 : 8;
+ if (is_yuv420(format)) {
+ s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
+ s->bus_width /= 2;
+ }
+
old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc);
if (old_crtc_state && !crtc_state->mode_changed) {
old_state = to_rockchip_crtc_state(old_crtc_state);
@@ -473,6 +490,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
{
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge);
struct drm_encoder *encoder = bridge->encoder;
+ struct drm_connector *connector = conn_state->connector;
u32 *input_fmt;
bool has_10bit = true;
@@ -487,6 +505,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge,
if (is_yuv444(output_fmt)) {
if (!hdmi->chip_data->ycbcr_444_allowed)
return NULL;
+ } else if (is_yuv420(output_fmt)) {
+ if (!connector->ycbcr_420_allowed)
+ return NULL;
} else if (!is_rgb(output_fmt))
return NULL;
@@ -652,6 +673,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
.phy_name = "inno_dw_hdmi_phy2",
.phy_force_vendor = true,
.use_drm_infoframe = true,
+ .ycbcr_420_allowed = true,
};
static struct rockchip_hdmi_chip_data rk3399_chip_data = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 784599231a6a..8d8a7e748def 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -10,6 +10,7 @@
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/log2.h>
+#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/overflow.h>
@@ -345,6 +346,19 @@ static int vop_convert_afbc_format(uint32_t format)
}
static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool bus_fmt_has_uv_swapped(uint32_t bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_YUV8_1X24:
@@ -1459,7 +1473,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
s->output_mode = ROCKCHIP_OUT_MODE_P888;
- VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0);
+ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0);
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
VOP_REG_SET(vop, common, pre_dither_down, 1);
@@ -1476,6 +1490,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
VOP_REG_SET(vop, common, out_mode, s->output_mode);
+ VOP_REG_SET(vop, common, dclk_ddr,
+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
+
VOP_REG_SET(vop, common, overlay_mode, yuv_output);
VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 1fa0ecdf734c..7e53eb3c1372 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -127,6 +127,7 @@ struct vop_common {
struct vop_reg standby;
struct vop_reg overlay_mode;
+ struct vop_reg dclk_ddr;
struct vop_reg dsp_data_swap;
struct vop_reg dsp_out_yuv;
struct vop_reg dsp_background;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 234e03edae12..c72ed63c3d1d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -729,6 +729,7 @@ static const struct vop_common rk3288_common = {
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
.overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16),
+ .dclk_ddr = VOP_REG(RK3288_DSP_CTRL0, 0x1, 8),
.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
.dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2),
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
@@ -1174,6 +1175,7 @@ static const struct vop_common rk3328_common = {
.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
.overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
+ .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8),
.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
.dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
.dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
--
2.34.1

59
packages/linux/patches/rockchip-old/rockchip-0024-WIP-1000-drm-rockchip-enable-ycbcr_420_allowed-and-y.patch Normal file
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@@ -0,0 +1,59 @@
From 69ef0f7cf190874d23b9b39ef978147f3d363938 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 15 Aug 2020 23:20:34 +0200
Subject: [PATCH 24/59] WIP/1000: drm/rockchip: enable ycbcr_420_allowed and
ycbcr_444_allowed for RK3228
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 8d8a7e748def..8e0fcc680115 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -957,6 +957,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
int format;
int is_yuv = fb->format->is_yuv;
int i;
+ int skiplines = 0;
/*
* can't update plane when vop is disabled.
@@ -975,8 +976,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
obj = fb->obj[0];
rk_obj = to_rockchip_obj(obj);
+ /*
+ * Force skip lines when image is yuv and 3840 width,
+ * fixes a "jumping" green lines issue on RK3328.
+ */
actual_w = drm_rect_width(src) >> 16;
- actual_h = drm_rect_height(src) >> 16;
+ if (actual_w == 3840 && is_yuv)
+ skiplines = 1;
+ actual_h = drm_rect_height(src) >> (16 + skiplines);
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
dsp_info = (drm_rect_height(dest) - 1) << 16;
@@ -1018,7 +1025,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
VOP_WIN_SET(vop, win, format, format);
VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
+ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines));
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
VOP_WIN_SET(vop, win, y_mir_en,
@@ -1039,7 +1046,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
- VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
+ VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines));
VOP_WIN_SET(vop, win, uv_mst, dma_addr);
for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
--
2.34.1

57
packages/linux/patches/rockchip-old/rockchip-0025-WIP-1000-drm-bridge-dw-hdmi-fix-RGB-to-YUV-color-spa.patch Normal file
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@@ -0,0 +1,57 @@
From f657ba02a56f7148c56fcc92d542949b7397a1b2 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 10 Apr 2021 16:54:26 +0200
Subject: [PATCH 25/59] WIP/1000: drm/bridge: dw-hdmi: fix RGB to YUV color
space conversion
We are currently providing color space conversion coefficents
for RGB to YUV conversion for full range to full range.
This is wrong, since we are hardcoding YCC quantization range
limited in the AVI infoframe (which is correct according to
HDMI specs). This results in to dark colors if this conversion
is used.
I verfied this by setting YCC quantization range to full in
AVI infoframe which resulted in correct colors. Doing this,
however, will be ignored by some (most) sinks.
This patch fixes this, by providing CSC coefficents which
convert RGB full range to YUV limited range for both BT601
and BT709 colorspaces.
Fixes: 9aaf880ed4ee ("imx-drm: Add mx6 hdmi transmitter support")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index e7677dcf28f4..40b2374f2515 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -69,15 +69,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
};
static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
- { 0x2591, 0x1322, 0x074b, 0x0000 },
- { 0x6535, 0x2000, 0x7acc, 0x0200 },
- { 0x6acd, 0x7534, 0x2000, 0x0200 }
+ { 0x2040, 0x1080, 0x0640, 0x0040 },
+ { 0xe880, 0x1c00, 0xfb80, 0x0200 },
+ { 0xed80, 0xf680, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
- { 0x62f0, 0x2000, 0x7d11, 0x0200 },
- { 0x6756, 0x78ab, 0x2000, 0x0200 }
+ { 0x2740, 0x0bc0, 0x0400, 0x0040 },
+ { 0xe680, 0x1c00, 0xfd80, 0x0200 },
+ { 0xea40, 0xf980, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
--
2.34.1

157
packages/linux/patches/rockchip-old/rockchip-0026-WIP-1000-media-cec-adap-add-debounce-support-when-se.patch Normal file
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@@ -0,0 +1,157 @@
From 47cfcb55dc96df812538b733a56a8ca5b9340cac Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 1 Oct 2019 20:52:42 +0000
Subject: [PATCH 26/59] WIP/1000: media: cec-adap: add debounce support when
setting an invalid phys addr
When EDID is refreshed, HDMI cable is unplugged/replugged or
an AVR is power cycled the CEC phys addr gets invalidated.
This can cause some disruption of CEC communication when
adapter is being reconfigured.
Add a debounce_ms module option that can be used to debounce setting
an invalid phys addr. Default is not to use debouncing.
Using a configured debounce_ms of e.g. 5000 ms, cec reconfiguring
could be avoided when AVR was power cycled on my setup.
Power off AVR (default cec.debounce_ms=0):
[ 101.536866] cec-dw_hdmi: new physical address f.f.f.f
[ 102.495686] cec-dw_hdmi: new physical address 2.1.0.0
[ 102.495913] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
[ 102.628574] cec-dw_hdmi: config: la 1 pa 2.1.0.0
[ 105.130115] cec-dw_hdmi: new physical address f.f.f.f
[ 106.979705] cec-dw_hdmi: new physical address 2.1.0.0
[ 106.979872] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
[ 107.112399] cec-dw_hdmi: config: la 1 pa 2.1.0.0
[ 108.979408] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
[ 109.205386] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
Power on AVR (default cec.debounce_ms=0):
[ 158.398447] cec-dw_hdmi: new physical address f.f.f.f
[ 161.977714] cec-dw_hdmi: new physical address 2.1.0.0
[ 161.978766] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
[ 162.115624] cec-dw_hdmi: config: la 1 pa 2.1.0.0
[ 162.402750] cec-dw_hdmi: new physical address f.f.f.f
[ 162.403389] cec-dw_hdmi: cec_transmit_msg_fh: adapter is unconfigured
[ 162.886757] cec-dw_hdmi: new physical address 2.1.0.0
[ 162.886964] cec-dw_hdmi: physical address: 2.1.0.0, claim 1 logical addresses
[ 163.510725] cec-dw_hdmi: config: la 1 pa 2.1.0.0
[ 173.034200] cec-dw_hdmi: message 10 89 02 05 timed out
Power off AVR (cec.debounce_ms=5000):
[ 251.720471] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
[ 251.922432] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
Power on AVR (cec.debounce_ms=5000):
[ 291.154262] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 5
[ 291.296199] cec-dw_hdmi: reported physical address 2.0.0.0 for logical address 11
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/media/cec/core/cec-adap.c | 9 ++++++++-
drivers/media/cec/core/cec-core.c | 18 ++++++++++++++++++
drivers/media/cec/core/cec-priv.h | 1 +
include/media/cec.h | 2 ++
4 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c
index ba6828ef540e..ee6f0f706f95 100644
--- a/drivers/media/cec/core/cec-adap.c
+++ b/drivers/media/cec/core/cec-adap.c
@@ -1734,8 +1734,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block)
if (IS_ERR_OR_NULL(adap))
return;
+ cancel_delayed_work_sync(&adap->debounce_work);
+
mutex_lock(&adap->lock);
- __cec_s_phys_addr(adap, phys_addr, block);
+ if (cec_debounce_ms > 0 && !block && phys_addr == CEC_PHYS_ADDR_INVALID &&
+ adap->phys_addr != phys_addr)
+ schedule_delayed_work(&adap->debounce_work,
+ msecs_to_jiffies(cec_debounce_ms));
+ else
+ __cec_s_phys_addr(adap, phys_addr, block);
mutex_unlock(&adap->lock);
}
EXPORT_SYMBOL_GPL(cec_s_phys_addr);
diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c
index e10bd588a586..effb4dd70b97 100644
--- a/drivers/media/cec/core/cec-core.c
+++ b/drivers/media/cec/core/cec-core.c
@@ -41,6 +41,10 @@ static bool debug_phys_addr;
module_param(debug_phys_addr, bool, 0644);
MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set");
+int cec_debounce_ms;
+module_param_named(debounce_ms, cec_debounce_ms, int, 0644);
+MODULE_PARM_DESC(debounce_ms, "debounce invalid phys addr");
+
static dev_t cec_dev_t;
/* Active devices */
@@ -160,6 +164,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap)
mutex_unlock(&devnode->lock);
+ cancel_delayed_work_sync(&adap->debounce_work);
+
mutex_lock(&adap->lock);
__cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
__cec_s_log_addrs(adap, NULL, false);
@@ -220,6 +226,17 @@ static const struct file_operations cec_error_inj_fops = {
};
#endif
+static void cec_s_phys_addr_debounce(struct work_struct *work)
+{
+ struct delayed_work *delayed_work = to_delayed_work(work);
+ struct cec_adapter *adap =
+ container_of(delayed_work, struct cec_adapter, debounce_work);
+
+ mutex_lock(&adap->lock);
+ __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false);
+ mutex_unlock(&adap->lock);
+}
+
struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
void *priv, const char *name, u32 caps,
u8 available_las)
@@ -257,6 +274,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
INIT_LIST_HEAD(&adap->transmit_queue);
INIT_LIST_HEAD(&adap->wait_queue);
init_waitqueue_head(&adap->kthread_waitq);
+ INIT_DELAYED_WORK(&adap->debounce_work, cec_s_phys_addr_debounce);
/* adap->devnode initialization */
INIT_LIST_HEAD(&adap->devnode.fhs);
diff --git a/drivers/media/cec/core/cec-priv.h b/drivers/media/cec/core/cec-priv.h
index ce42a37c4ac0..24856163e295 100644
--- a/drivers/media/cec/core/cec-priv.h
+++ b/drivers/media/cec/core/cec-priv.h
@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg)
/* cec-core.c */
extern int cec_debug;
+extern int cec_debounce_ms;
/* cec-adap.c */
int cec_monitor_all_cnt_inc(struct cec_adapter *adap);
diff --git a/include/media/cec.h b/include/media/cec.h
index 0c8e86115b6f..b35212bebf9c 100644
--- a/include/media/cec.h
+++ b/include/media/cec.h
@@ -252,6 +252,8 @@ struct cec_adapter {
struct task_struct *kthread;
wait_queue_head_t kthread_waitq;
+ struct delayed_work debounce_work;
+
const struct cec_adap_ops *ops;
void *priv;
u32 capabilities;
--
2.34.1

54
packages/linux/patches/rockchip-old/rockchip-0027-WIP-1000-drm-bridge-synopsys-Fix-CEC-not-working-aft.patch Normal file
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@@ -0,0 +1,54 @@
From c8c43f15ad546daaf3d2cbd13c3ca4e4fa6604af Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Fri, 22 Oct 2021 11:17:30 +0200
Subject: [PATCH 27/59] WIP/1000: drm/bridge: synopsys: Fix CEC not working
after power-cyclying
This fixes standby -> power-on on Rockchip platform for, at least,
RK3288/RK3328/RK3399 where CEC wasn't working after powering on again.
It might differ for other phy implementations:
The whole HPD-detection part shoud be reworked and we should in general
avoid to rely in RX_SENSE phy status (at least for HDMI), since it differs
depending on sink's implementation.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 40b2374f2515..7b0aa5d0765d 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -3150,12 +3150,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
phy_stat & HDMI_PHY_HPD,
phy_stat & HDMI_PHY_RX_SENSE);
- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
- mutex_lock(&hdmi->cec_notifier_mutex);
- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
- mutex_unlock(&hdmi->cec_notifier_mutex);
- }
-
if (phy_stat & HDMI_PHY_HPD)
status = connector_status_connected;
@@ -3172,6 +3166,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
drm_helper_hpd_irq_event(hdmi->bridge.dev);
drm_bridge_hpd_notify(&hdmi->bridge, status);
}
+
+ if (status == connector_status_disconnected &&
+ (phy_stat & HDMI_PHY_RX_SENSE) &&
+ (phy_int_pol & HDMI_PHY_RX_SENSE)) {
+ mutex_lock(&hdmi->cec_notifier_mutex);
+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
+ mutex_unlock(&hdmi->cec_notifier_mutex);
+ }
}
hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
--
2.34.1

75
packages/linux/patches/rockchip-old/rockchip-0028-WIP-1000-drm-rockchip-vop-create-planes-in-window-or.patch Normal file
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@@ -0,0 +1,75 @@
From d0cb5362ec2336f048606ebae2dcb05a53d9dd3a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 9 Oct 2020 15:24:53 +0000
Subject: [PATCH 28/59] WIP/1000: drm/rockchip: vop: create planes in window
order
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------
1 file changed, 4 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 8e0fcc680115..ac90ceb894ca 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1949,19 +1949,10 @@ static int vop_create_crtc(struct vop *vop)
int ret;
int i;
- /*
- * Create drm_plane for primary and cursor planes first, since we need
- * to pass them to drm_crtc_init_with_planes, which sets the
- * "possible_crtcs" to the newly initialized crtc.
- */
for (i = 0; i < vop_data->win_size; i++) {
struct vop_win *vop_win = &vop->win[i];
const struct vop_win_data *win_data = vop_win->data;
- if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
- win_data->type != DRM_PLANE_TYPE_CURSOR)
- continue;
-
ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
0, &vop_plane_funcs,
win_data->phy->data_formats,
@@ -1994,32 +1985,13 @@ static int vop_create_crtc(struct vop *vop)
drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
}
- /*
- * Create drm_planes for overlay windows with possible_crtcs restricted
- * to the newly created crtc.
- */
+ /* Set possible_crtcs to the newly created crtc for overlay windows */
for (i = 0; i < vop_data->win_size; i++) {
struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
- unsigned long possible_crtcs = drm_crtc_mask(crtc);
-
- if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
- continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- possible_crtcs,
- &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->phy->format_modifiers,
- win_data->type, NULL);
- if (ret) {
- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
- ret);
- goto err_cleanup_crtc;
- }
- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
- vop_plane_add_properties(&vop_win->base, win_data);
+ plane = &vop_win->base;
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY)
+ plane->possible_crtcs = drm_crtc_mask(crtc);
}
port = of_get_child_by_name(dev->of_node, "port");
--
2.34.1

30
packages/linux/patches/rockchip-old/rockchip-0029-WIP-1001-media-rkvdec-pm-runtime-dont-use-autosuspen.patch Normal file
View File

@@ -0,0 +1,30 @@
From f0fa00d4cd4f08067189713707ce9012a4a9e7b7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 10:16:01 +0000
Subject: [PATCH 29/59] WIP/1001: media: rkvdec: pm runtime dont use
autosuspend before disable and cleanup
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 3367902f22de..7747e8396626 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1176,9 +1176,9 @@ static void rkvdec_remove(struct platform_device *pdev)
cancel_delayed_work_sync(&rkvdec->watchdog_work);
- rkvdec_v4l2_cleanup(rkvdec);
- pm_runtime_disable(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ rkvdec_v4l2_cleanup(rkvdec);
}
#ifdef CONFIG_PM
--
2.34.1

103
packages/linux/patches/rockchip-old/rockchip-0030-WIP-1001-soc-rockchip-power-domain-export-idle-reque.patch Normal file
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@@ -0,0 +1,103 @@
From 6c3752e2e7a3b8204cb8f5c6fa884c7ec089cf84 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 6 Jan 2019 01:48:37 +0800
Subject: [PATCH 30/59] WIP/1001: soc: rockchip: power-domain: export idle
request
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/pmdomain/rockchip/pm-domains.c | 23 +++++++++++++++++++++++
include/linux/rockchip_pmu.h | 15 +++++++++++++++
include/soc/rockchip/pm_domains.h | 6 ++++++
3 files changed, 44 insertions(+)
create mode 100644 include/linux/rockchip_pmu.h
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 4cce407bb1eb..ead8b1e380d5 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -417,6 +417,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
return 0;
}
+int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int ret;
+
+ if (IS_ERR_OR_NULL(dev))
+ return -EINVAL;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return -EINVAL;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ pd = to_rockchip_pd(genpd);
+
+ mutex_lock(&pd->pmu->mutex);
+ ret = rockchip_pmu_set_idle_request(pd, idle);
+ mutex_unlock(&pd->pmu->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_pmu_idle_request);
+
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
int i;
diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
new file mode 100644
index 000000000000..720b3314e71a
--- /dev/null
+++ b/include/linux/rockchip_pmu.h
@@ -0,0 +1,15 @@
+/*
+ * pm_domain.h - Definitions and headers related to device power domains.
+ *
+ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#ifndef _LINUX_ROCKCHIP_PM_H
+#define _LINUX_ROCKCHIP_PM_H
+#include <linux/device.h>
+
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+
+#endif /* _LINUX_ROCKCHIP_PM_H */
diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h
index 7dbd941fc937..c5a59dd71754 100644
--- a/include/soc/rockchip/pm_domains.h
+++ b/include/soc/rockchip/pm_domains.h
@@ -10,6 +10,7 @@
int rockchip_pmu_block(void);
void rockchip_pmu_unblock(void);
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
#else /* CONFIG_ROCKCHIP_PM_DOMAINS */
@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void)
static inline void rockchip_pmu_unblock(void) { }
+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ return -ENOTSUPP;
+}
+
#endif /* CONFIG_ROCKCHIP_PM_DOMAINS */
#endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */
--
2.34.1

219
packages/linux/patches/rockchip-old/rockchip-0031-WIP-1001-media-rkvdec-implement-reset-controls.patch Normal file
View File

@@ -0,0 +1,219 @@
From e820bdd484faa4af32620e4c8a07c92de3d1d096 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 20 May 2020 17:04:47 +0200
Subject: [PATCH 31/59] WIP/1001: media: rkvdec: implement reset controls
---
.../bindings/media/rockchip,vdec.yaml | 19 +++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++
drivers/staging/media/rkvdec/rkvdec.c | 53 +++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec.h | 11 +++-
4 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
index 08b02ec16755..828d085b0ad3 100644
--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
@@ -53,6 +53,18 @@ properties:
iommus:
maxItems: 1
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: video_h
+ - const: video_a
+ - const: video_core
+ - const: video_cabac
+ - const: niu_a
+ - const: niu_h
+
required:
- compatible
- reg
@@ -60,6 +72,8 @@ required:
- clocks
- clock-names
- power-domains
+ - resets
+ - reset-names
additionalProperties: false
@@ -78,6 +92,11 @@ examples:
clock-names = "axi", "ahb", "cabac", "core";
power-domains = <&power RK3399_PD_VDU>;
iommus = <&vdec_mmu>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
...
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 15b9bee92016..3acc914888f6 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -28,6 +28,11 @@
#define RKVDEC_SOFTRST_EN_P BIT(20)
#define RKVDEC_FORCE_SOFTRESET_VALID BIT(21)
#define RKVDEC_SOFTRESET_RDY BIT(22)
+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \
+ | RKVDEC_ERR_STA \
+ | RKVDEC_TIMEOUT_STA \
+ | RKVDEC_BUF_EMPTY_STA \
+ | RKVDEC_COLMV_REF_ERR_STA )
#define RKVDEC_REG_SYSCTRL 0x008
#define RKVDEC_IN_ENDIAN BIT(0)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 7747e8396626..c9c59d090bb3 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -10,12 +10,15 @@
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/rockchip_pmu.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
@@ -766,6 +769,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx,
pm_runtime_mark_last_busy(rkvdec->dev);
pm_runtime_put_autosuspend(rkvdec->dev);
+
+ if (result == VB2_BUF_STATE_ERROR &&
+ rkvdec->reset_mask == RESET_NONE)
+ rkvdec->reset_mask |= RESET_SOFT;
+
rkvdec_job_finish_no_pm(ctx, result);
}
@@ -803,6 +811,33 @@ static void rkvdec_device_run(void *priv)
if (WARN_ON(!desc))
return;
+ if (rkvdec->reset_mask != RESET_NONE) {
+
+ if (rkvdec->reset_mask & RESET_SOFT) {
+ writel(RKVDEC_SOFTRST_EN_P,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ udelay(RKVDEC_RESET_DELAY);
+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT)
+ & RKVDEC_SOFTRESET_RDY)
+ dev_info_ratelimited(rkvdec->dev,
+ "softreset failed\n");
+ }
+
+ if (rkvdec->reset_mask & RESET_HARD) {
+ rockchip_pmu_idle_request(rkvdec->dev, true);
+ ret = reset_control_assert(rkvdec->rstc);
+ if (!ret) {
+ udelay(RKVDEC_RESET_DELAY);
+ ret = reset_control_deassert(rkvdec->rstc);
+ }
+ rockchip_pmu_idle_request(rkvdec->dev, false);
+ if (ret)
+ dev_notice_ratelimited(rkvdec->dev,
+ "hardreset failed\n");
+ }
+ rkvdec->reset_mask = RESET_NONE;
+ pm_runtime_suspend(rkvdec->dev);
+ }
ret = pm_runtime_resume_and_get(rkvdec->dev);
if (ret < 0) {
@@ -1069,6 +1104,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
if (cancel_delayed_work(&rkvdec->watchdog_work)) {
struct rkvdec_ctx *ctx;
+ if (state == VB2_BUF_STATE_ERROR) {
+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ?
+ RESET_HARD : RESET_SOFT;
+ }
+
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
rkvdec_job_finish(ctx, state);
}
@@ -1086,6 +1126,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
if (ctx) {
dev_err(rkvdec->dev, "Frame processing timed out!\n");
+ rkvdec->reset_mask |= RESET_HARD;
writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
@@ -1154,6 +1195,18 @@ static int rkvdec_probe(struct platform_device *pdev)
return ret;
}
+
+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, RESET_CONTROL_OPTIONAL_EXCLUSIVE);
+ if (IS_ERR(rkvdec->rstc)) {
+ dev_err(&pdev->dev,
+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc));
+ return PTR_ERR(rkvdec->rstc);
+ } else {
+ dev_dbg(&pdev->dev,
+ "requested %d resets\n",
+ reset_control_get_count(&pdev->dev));
+ }
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 9a9f4fced7a1..101dfb4ec389 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -11,10 +11,11 @@
#ifndef RKVDEC_H_
#define RKVDEC_H_
+#include <linux/clk.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/videodev2.h>
#include <linux/wait.h>
-#include <linux/clk.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
@@ -22,6 +23,12 @@
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
+#define RESET_NONE 0
+#define RESET_SOFT BIT(0)
+#define RESET_HARD BIT(1)
+
+#define RKVDEC_RESET_DELAY 5
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -110,6 +117,8 @@ struct rkvdec_dev {
void __iomem *regs;
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
+ struct reset_control *rstc;
+ u8 reset_mask;
};
struct rkvdec_ctx {
--
2.34.1

28
packages/linux/patches/rockchip-old/rockchip-0032-WIP-1001-arm64-dts-add-resets-to-vdec-for-RK3399.patch Normal file
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@@ -0,0 +1,28 @@
From c5ccfb8981662498ead114cfc284c9d4f01ce78b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 18 Aug 2020 11:38:04 +0200
Subject: [PATCH 32/59] WIP/1001: arm64: dts: add resets to vdec for RK3399
---
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index ec5ca40b2159..b031d77f3763 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1463,6 +1463,11 @@ vdec: video-codec@ff660000 {
clock-names = "axi", "ahb", "cabac", "core";
iommus = <&vdec_mmu>;
power-domains = <&power RK3399_PD_VDU>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
vdec_mmu: iommu@ff660480 {
--
2.34.1

61
packages/linux/patches/rockchip-old/rockchip-0033-WIP-1001-media-hantro-rockchip-Increase-RK3288-s-max.patch Normal file
View File

@@ -0,0 +1,61 @@
From 00bb174583f859081e899ed397df0b5939553730 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 21 Aug 2021 16:12:36 +0200
Subject: [PATCH 33/59] WIP/1001: media: hantro: rockchip: Increase RK3288's
max ACLK
Required to proper decode H.264@4K
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
.../media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
index 02673be9878e..0e243c9cf894 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
@@ -16,7 +16,8 @@
#include "rockchip_vpu981_regs.h"
#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000)
+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
#define ROCKCHIP_VPU981_MIN_SIZE 64
@@ -453,13 +454,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
return 0;
}
-static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
+static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLK to max. possible freq. to improve performance. */
clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
return 0;
}
+static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
+{
+ /* Bump ACLK to max. possible freq. to improve performance. */
+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
+ return 0;
+}
+
static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
@@ -715,7 +723,7 @@ const struct hantro_variant rk3288_vpu_variant = {
.codec_ops = rk3288_vpu_codec_ops,
.irqs = rockchip_vpu1_irqs,
.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
- .init = rockchip_vpu_hw_init,
+ .init = rk3288_vpu_hw_init,
.clk_names = rockchip_vpu_clk_names,
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
};
--
2.34.1

54
packages/linux/patches/rockchip-old/rockchip-0034-WIP-1001-media-rkvdec-disable-QoS-for-VP9-corruption.patch Normal file
View File

@@ -0,0 +1,54 @@
From ff4a4fce9ca0066d67e4b88bd24f9e5afff16652 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 4 Jul 2021 15:19:44 +0200
Subject: [PATCH 34/59] WIP/1001: media: rkvdec: disable QoS for VP9
(corruptions on RK3328 otherwise)
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
drivers/staging/media/rkvdec/rkvdec-vp9.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 3acc914888f6..265f5234f4eb 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -222,6 +222,8 @@
#define RKVDEC_REG_H264_ERR_E 0x134
#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff)
+#define RKVDEC_QOS_CTRL 0x18C
+
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
index 0e7e16f20eeb..b7bc07493cea 100644
--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
@@ -803,6 +803,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
struct rkvdec_dev *rkvdec = ctx->dev;
struct rkvdec_vp9_run run = { };
int ret;
+ u32 reg;
ret = rkvdec_vp9_run_preamble(ctx, &run);
if (ret) {
@@ -824,6 +825,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+
+ /* disable QOS for RK3328 - no effect on other SoCs */
+ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= (~BIT(12));
+ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL);
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
--
2.34.1

28
packages/linux/patches/rockchip-old/rockchip-0035-WIP-1001-arm64-dts-add-resets-to-vdec-for-RK3328.patch Normal file
View File

@@ -0,0 +1,28 @@
From 128a568ff04e52754baa359ce62446777745f6e4 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Thu, 16 Jun 2022 13:18:22 +0200
Subject: [PATCH 35/59] WIP/1001: arm64: dts: add resets to vdec for RK3328
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7d992c3c01ce..48d1a6292818 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -705,6 +705,11 @@ vdec: video-codec@ff360000 {
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
<&cru SCLK_VDEC_CORE>;
assigned-clock-rates = <400000000>, <400000000>, <300000000>;
+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
iommus = <&vdec_mmu>;
power-domains = <&power RK3328_PD_VIDEO>;
};
--
2.34.1

112
packages/linux/patches/rockchip-old/rockchip-0036-WIP-1002-arm64-dts-rockchip-add-gpu-powerdomain-gpu-.patch Normal file
View File

@@ -0,0 +1,112 @@
From bce0ff837523f2cde25f52812d09415d556b6dac Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 2 Sep 2020 19:52:02 +0200
Subject: [PATCH 36/59] WIP/1002: arm64: dts: rockchip: add gpu powerdomain,
gpu opp-table and cooling cell for RK3328
Note: since the regulator that supplies the GPU usually also supplies
other SoC components, we have to make sure voltage is never lower then
1075 mV - also disable 500 MHz for now, since it will crash if rkvdec
is running at the same time (voltage too high)
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 4 +++
.../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
index b5bd5e7d5748..7eef6f7f108f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
@@ -160,6 +160,10 @@ &gmac2io {
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 5367e5fa9232..592fd8ca21df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -152,6 +152,10 @@ &gmac2io {
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
avdd-0v9-supply = <&vdd_10>;
avdd-1v8-supply = <&vcc_18>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 48d1a6292818..e3beadde6c07 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -331,6 +331,11 @@ power: power-controller {
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ #power-domain-cells = <0>;
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
clocks = <&cru SCLK_VENC_CORE>;
@@ -570,6 +575,11 @@ map0 {
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
+ map1 {
+ trip = <&target>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
};
};
@@ -651,7 +661,32 @@ gpu: gpu@ff300000 {
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ status = "disabled";
+ };
};
h265e_mmu: iommu@ff330200 {
--
2.34.1

51
packages/linux/patches/rockchip-old/rockchip-0037-WIP-1002-ARM-dts-RK3288-miqi-add-hdmi-sound-nodes.patch Normal file
View File

@@ -0,0 +1,51 @@
From b5d839cc33801f7d4793a8eb40c2bd3bc90e71cf Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 2 Feb 2021 17:22:21 +0200
Subject: [PATCH 37/59] WIP/1002: ARM: dts: RK3288 miqi add hdmi sound nodes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index dd42f8d31f70..20df626547bd 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -78,6 +78,21 @@ vcc_sys: regulator-vsys {
regulator-always-on;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+ };
};
&cpu0 {
@@ -283,6 +298,11 @@ &i2c5 {
status = "okay";
};
+&i2s {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&io_domains {
status = "okay";
--
2.34.1

41
packages/linux/patches/rockchip-old/rockchip-0038-WIP-1002-ARM-arm64-dts-rockchip-align-sound-card-nam.patch Normal file
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@@ -0,0 +1,41 @@
From ca832abe5bd81104aa5d2d193f9c279be4b15ee4 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Fri, 2 Apr 2021 17:54:22 +0200
Subject: [PATCH 38/59] WIP/1002: ARM/arm64: dts: rockchip: align sound card
names
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
index 8e27a20f2845..b83b122d00f1 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq {
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
- simple-audio-card,name = "rockchip,tinker-codec";
+ simple-audio-card,name = "HDMI";
simple-audio-card,mclk-fs = <512>;
simple-audio-card,codec {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index b031d77f3763..d27e3fa9ff80 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -2008,7 +2008,7 @@ hdmi_sound: hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "hdmi-sound";
+ simple-audio-card,name = "HDMI";
status = "disabled";
simple-audio-card,cpu {
--
2.34.1

55
packages/linux/patches/rockchip-old/rockchip-0039-WIP-1002-arm64-dts-rockchip-add-SPDIF-nodes-for-RK33.patch Normal file
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@@ -0,0 +1,55 @@
From 4c6ede1bdbe16a4bb6ce2518c55b9612477db966 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 27 Feb 2021 17:52:02 +0100
Subject: [PATCH 39/59] WIP/1002: arm64: dts: rockchip: add SPDIF nodes for
RK3328 A1 board
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index f7c4578865c5..b276a29bdd85 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -58,6 +58,24 @@ ir-receiver {
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
linux,rc-map-name = "rc-beelink-gs1";
};
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
};
&analog_sound {
@@ -325,6 +343,11 @@ &sdmmc {
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
--
2.34.1

46
packages/linux/patches/rockchip-old/rockchip-0040-WIP-1002-arm64-dts-rockchip-Add-ir-receiver-node-for.patch Normal file
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@@ -0,0 +1,46 @@
From 3bd9c85894e889f86176850f5f31e3009b637037 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 27 Feb 2021 18:01:13 +0100
Subject: [PATCH 40/59] WIP/1002: arm64: dts: rockchip: Add ir-receiver node
for RK3328 ROC CC
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
index 7eef6f7f108f..3fe0c17fd2b1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
@@ -84,6 +84,13 @@ vcc_phy: regulator-vcc-phy {
regulator-boot-on;
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
leds {
compatible = "gpio-leds";
@@ -304,6 +311,13 @@ &io_domains {
};
&pinctrl {
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.34.1

26
packages/linux/patches/rockchip-old/rockchip-0041-WIP-1002-ARM-dts-add-cec-pinctrl-for-RK3288-miqi-boa.patch Normal file
View File

@@ -0,0 +1,26 @@
From 5d0117163c35c896fca347fb2391b1f16251a35b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 1 Mar 2021 21:24:15 +0100
Subject: [PATCH 41/59] WIP/1002: ARM: dts: add cec pinctrl for RK3288 miqi
board
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index 20df626547bd..a5f5c6d38f80 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -145,6 +145,8 @@ &gpu {
&hdmi {
ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
status = "okay";
};
--
2.34.1

32
packages/linux/patches/rockchip-old/rockchip-0042-WIP-1002-HACK-arm64-dts-enable-FE-phy-for-Beelink-A1.patch Normal file
View File

@@ -0,0 +1,32 @@
From a5b67cd0fd28b9557c9b9011a98e2c0a85b4c90f Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 1 Mar 2021 19:22:15 +0100
Subject: [PATCH 42/59] WIP/1002: HACK: arm64: dts: enable FE phy for Beelink
A1 also
---
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index b276a29bdd85..962c3b3b804e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 {
};
};
+&gmac2phy {
+ clock_in_out = "output";
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "okay";
+};
+
&gpu {
mali-supply = <&vdd_logic>;
};
--
2.34.1

62
packages/linux/patches/rockchip-old/rockchip-0043-WIP-1002-dw-hdmi-cec-sleep-100ms-on-error.patch Normal file
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@@ -0,0 +1,62 @@
From 5f75e2b8b93aa36a3ef563220e05012bf6ee1637 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 26 Feb 2019 20:45:14 +0000
Subject: [PATCH 43/59] WIP/1002: dw-hdmi-cec: sleep 100ms on error
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
index 9549dabde941..b34eb025c1ef 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
@@ -4,6 +4,7 @@
*
* Copyright (C) 2015-2017 Russell King.
*/
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -133,8 +134,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
- if (stat & CEC_STAT_ERROR_INIT) {
- cec->tx_status = CEC_TX_STATUS_ERROR;
+ /* Status with both done and error_initiator bits have been seen
+ * on Rockchip RK3328 devices, transmit attempt seems to have failed
+ * when this happens, report as low drive and block cec-framework
+ * 100ms before core retransmits the failed message, this seems to
+ * mitigate the issue with failed transmit attempts.
+ */
+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
cec->tx_done = true;
ret = IRQ_WAKE_THREAD;
} else if (stat & CEC_STAT_DONE) {
@@ -149,6 +157,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
cec->tx_status = CEC_TX_STATUS_ARB_LOST;
cec->tx_done = true;
ret = IRQ_WAKE_THREAD;
+ } else if (stat & CEC_STAT_ERROR_INIT) {
+ cec->tx_status = CEC_TX_STATUS_ERROR;
+ cec->tx_done = true;
+ ret = IRQ_WAKE_THREAD;
}
if (stat & CEC_STAT_EOM) {
@@ -181,6 +193,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data)
if (cec->tx_done) {
cec->tx_done = false;
+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
+ msleep(100);
cec_transmit_attempt_done(adap, cec->tx_status);
}
if (cec->rx_done) {
--
2.34.1

30
packages/linux/patches/rockchip-old/rockchip-0044-WIP-1002-arm64-boot-dts-Increase-ACLK_PERILP0-clock-.patch Normal file
View File

@@ -0,0 +1,30 @@
From d3f81ed48b5f275372fc0a7f083dd1af0b5bef0a Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 5 May 2021 19:11:12 +0200
Subject: [PATCH 44/59] WIP/1002: arm64: boot: dts: Increase ACLK_PERILP0 clock
rate for RK3399
As per vendor kernel. Leaving this clock at the lower rate will
result in poor DMA controller performance
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index d27e3fa9ff80..f06147581fab 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1592,7 +1592,7 @@ cru: clock-controller@ff760000 {
<1000000000>,
<150000000>, <75000000>,
<37500000>,
- <100000000>, <100000000>,
+ <300000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
<400000000>, <400000000>,
--
2.34.1

30
packages/linux/patches/rockchip-old/rockchip-0045-WIP-1002-arm64-dts-rockchip-Enable-USB3-for-rk3328-B.patch Normal file
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@@ -0,0 +1,30 @@
From a11c3b6c96c3be4f3dc6d14eca1c6f6f41297da7 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 21 Aug 2021 17:04:46 +0200
Subject: [PATCH 45/59] WIP/1002: arm64: dts: rockchip: Enable USB3 for rk3328
Beelink A1
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index 962c3b3b804e..4feba4ae7a29 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -389,6 +389,11 @@ &usb_host0_ehci {
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&vop {
status = "okay";
};
--
2.34.1

44
packages/linux/patches/rockchip-old/rockchip-0046-WIP-1002-drm-bridge-dw-hdmi-switch-from-.hw_parmas-t.patch Normal file
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@@ -0,0 +1,44 @@
From 81a61b1534afbfa6805c40df3e8e1b0635b05fb2 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Oct 2021 12:19:19 +0200
Subject: [PATCH 46/59] WIP/1002: drm: bridge: dw-hdmi: switch from .hw_parmas
to .prepare for i2s
Seems to be the only way to get AES bits correctly as set by
userspace.
TODO: check other consequences.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
index 2c903c9fe805..7476690b889b 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
return audio->read(hdmi, offset);
}
-static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
- struct hdmi_codec_daifmt *fmt,
- struct hdmi_codec_params *hparms)
+static int dw_hdmi_i2s_prepare(struct device *dev, void *data,
+ struct hdmi_codec_daifmt *fmt,
+ struct hdmi_codec_params *hparms)
{
struct dw_hdmi_i2s_audio_data *audio = data;
struct dw_hdmi *hdmi = audio->hdmi;
@@ -179,7 +179,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data,
}
static const struct hdmi_codec_ops dw_hdmi_i2s_ops = {
- .hw_params = dw_hdmi_i2s_hw_params,
+ .prepare = dw_hdmi_i2s_prepare,
.audio_startup = dw_hdmi_i2s_audio_startup,
.audio_shutdown = dw_hdmi_i2s_audio_shutdown,
.get_eld = dw_hdmi_i2s_get_eld,
--
2.34.1

48
packages/linux/patches/rockchip-old/rockchip-0047-WIP-1002-arm64-dts-rockchip-disable-fusb-for-rk3399-.patch Normal file
View File

@@ -0,0 +1,48 @@
From 0202435665464cbf0bf9a3bb59e0da36aab17385 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 18 Sep 2022 10:35:52 +0200
Subject: [PATCH 47/59] WIP/1002: arm64: dts: rockchip: disable fusb for
rk3399-roc-pc
As it will lead to an unbootable device in case one if those ports
is used to power up the device.
See https://lkml.org/lkml/2022/6/20/413
---
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index fc9279627ef6..610518ff30ee 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -215,7 +215,7 @@ vdd_log: regulator-vdd-log {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <450000>;
+ regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
pwm-supply = <&vcc3v3_sys>;
};
@@ -536,7 +536,7 @@ fusb1: usb-typec@22 {
pinctrl-names = "default";
pinctrl-0 = <&fusb1_int>;
vbus-supply = <&vcc_vbus_typec1>;
- status = "okay";
+ status = "disabled";
};
};
@@ -553,7 +553,7 @@ fusb0: usb-typec@22 {
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc_vbus_typec0>;
- status = "okay";
+ status = "disabled";
};
mp8859: regulator@66 {
--
2.34.1

557
projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch → packages/linux/patches/rockchip-old/rockchip-0048-WIP-2000-media-rkvdec-add-HEVC-backend.patch
View File

@@ -1,7 +1,7 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From f17202a6531a100aaddc67dd8f9dba365bf0c231 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 15:17:45 +0000
Subject: [PATCH] WIP: media: rkvdec: add HEVC backend
Subject: [PATCH 48/59] WIP/2000: media: rkvdec: add HEVC backend
NOTE: cabac table and scailing list code is copied 1:1 from mpp
TODO: fix lowdelay flag and rework the scaling list part
@@ -10,11 +10,11 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 2585 ++++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 73 +-
drivers/staging/media/rkvdec/rkvdec.c | 77 +
drivers/staging/media/rkvdec/rkvdec.h | 1 +
5 files changed, 2647 insertions(+), 2 deletions(-)
5 files changed, 2665 insertions(+), 1 deletion(-)
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
@@ -28,10 +28,10 @@ index cb86b429cfaa..a77122641d14 100644
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
new file mode 100644
index 000000000000..7a375a23eaf1
index 000000000000..5454d2d5e147
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -0,0 +1,2571 @@
@@ -0,0 +1,2585 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
@@ -2448,6 +2448,29 @@ index 000000000000..7a375a23eaf1
+ return 0;
+}
+
+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS)
+ return RKVDEC_IMG_FMT_ANY;
+
+ if (sps->bit_depth_luma_minus8 == 0) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_8BIT;
+ else
+ return RKVDEC_IMG_FMT_420_8BIT;
+ } else if (sps->bit_depth_luma_minus8 == 2) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_10BIT;
+ else
+ return RKVDEC_IMG_FMT_420_10BIT;
+ }
+
+ return RKVDEC_IMG_FMT_ANY;
+}
+
+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
+ const struct v4l2_ctrl_hevc_sps *sps)
+{
@@ -2468,16 +2491,6 @@ index 000000000000..7a375a23eaf1
+ return 0;
+}
+
+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (sps->bit_depth_luma_minus8 == 2)
+ return V4L2_PIX_FMT_NV15;
+ else
+ return V4L2_PIX_FMT_NV12;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
@@ -2602,6 +2615,7 @@ index 000000000000..7a375a23eaf1
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+ .try_ctrl = rkvdec_hevc_try_ctrl,
+ .get_image_fmt = rkvdec_hevc_get_image_fmt,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 265f5234f4eb..4319ee3ccbbc 100644
@@ -2616,10 +2630,10 @@ index 265f5234f4eb..4319ee3ccbbc 100644
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index f55abb7c377f..00a9bf583596 100644
index c9c59d090bb3..1f4693cbc330 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -134,6 +134,68 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
@@ -202,6 +202,68 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
},
};
@@ -2688,7 +2702,7 @@ index f55abb7c377f..00a9bf583596 100644
static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.ctrls = rkvdec_h264_ctrl_descs,
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
@@ -270,6 +332,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.decoded_fmts = rkvdec_h264_decoded_fmts,
.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
},
@@ -2711,10 +2725,10 @@ index f55abb7c377f..00a9bf583596 100644
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
.frmsize = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index f02f79c405f0..d6222a2588be 100644
index 101dfb4ec389..6afbd40450b2 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
@@ -147,6 +147,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
@@ -2722,501 +2736,6 @@ index f02f79c405f0..d6222a2588be 100644
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
#endif /* RKVDEC_H_ */
--
2.34.1
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:16:39 +0100
Subject: [PATCH] media: rkvdec: add variants support
rkvdec IP has different versions which among others differ in
the supported decoding formats.
This adds an variant implementation in order support other
than the currently supported RK3399 version.
Note: Since matching of supported codecs is index-based the
available codec options have been reordered here: from
supported by all versions to not commonly supported. This seems
the better soultion than duplicatiing code for every newly added IP.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++--------
drivers/staging/media/rkvdec/rkvdec.h | 10 +++
2 files changed, 85 insertions(+), 30 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 00a9bf583596..955c53afe20f 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -14,6 +14,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = {
};
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_HEVC,
+ },
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
.decoded_fmts = rkvdec_h264_decoded_fmts,
.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
- },
- {
- .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
- .frmsize = {
- .min_width = 64,
- .max_width = 4096,
- .step_width = 64,
- .min_height = 64,
- .max_height = 2304,
- .step_height = 16,
- },
- .ctrls = &rkvdec_hevc_ctrls,
- .ops = &rkvdec_hevc_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
- .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_H264,
},
{
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.ops = &rkvdec_vp9_fmt_ops,
.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
.decoded_fmts = rkvdec_vp9_decoded_fmts,
- }
+ .capability = RKVDEC_CAPABILITY_VP9,
+ },
};
static const struct rkvdec_coded_fmt_desc *
-rkvdec_find_coded_fmt_desc(u32 fourcc)
+rkvdec_default_coded_fmt_desc(unsigned int capabilities)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+ if (rkvdec_coded_fmts[i].capability & capabilities)
+ return &rkvdec_coded_fmts[i];
+ }
+
+ return NULL;
+}
+
+static const struct rkvdec_coded_fmt_desc *
+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- if (rkvdec_coded_fmts[i].fourcc == fourcc)
+ if (rkvdec_coded_fmts[i].fourcc == fourcc &&
+ (rkvdec_coded_fmts[i].capability & capabilities))
return &rkvdec_coded_fmts[i];
}
@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->coded_fmt;
- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
const struct rkvdec_coded_fmt_desc *fmt;
+ struct rkvdec_dev *rkvdec = video_drvdata(file);
if (fsize->index != 0)
return -EINVAL;
- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
+ rkvdec->capabilities);
if (!fmt)
return -EINVAL;
@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
const struct rkvdec_coded_fmt_desc *desc;
- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
+ ctx->dev->capabilities);
if (!desc) {
- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
- desc = &rkvdec_coded_fmts[0];
+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
+ pix_mp->pixelformat = desc->fourcc;
}
v4l2_apply_frmsize_constraints(&pix_mp->width,
@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
if (ret)
return ret;
- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
+ ctx->dev->capabilities);
if (!desc)
return -EINVAL;
ctx->coded_fmt_desc = desc;
@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
static int rkvdec_enum_output_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+
+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
return -EINVAL;
f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
int ret;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
- if (ret)
- goto err_free_handler;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+ if (ret)
+ goto err_free_handler;
+ }
}
ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
}
}
+static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_VP9
+};
+
static const struct of_device_id of_rkvdec_match[] = {
- { .compatible = "rockchip,rk3399-vdec" },
+ {
+ .compatible = "rockchip,rk3399-vdec",
+ .data = &rk3399_rkvdec_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = {
static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;
@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev)
if (ret)
return ret;
+ variant = of_device_get_match_data(rkvdec->dev);
+ if (!variant)
+ return -EINVAL;
+
+ rkvdec->capabilities = variant->capabilities;
+
+
rkvdec->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rkvdec->regs))
return PTR_ERR(rkvdec->regs);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index d6222a2588be..ad8e83884121 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -29,6 +29,10 @@
#define RKVDEC_RESET_DELAY 5
+#define RKVDEC_CAPABILITY_H264 BIT(0)
+#define RKVDEC_CAPABILITY_HEVC BIT(1)
+#define RKVDEC_CAPABILITY_VP9 BIT(2)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
base.vb.vb2_buf);
}
+struct rkvdec_variant {
+ unsigned int capabilities;
+};
+
struct rkvdec_coded_fmt_ops {
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
struct v4l2_format *f);
@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc {
unsigned int num_decoded_fmts;
const u32 *decoded_fmts;
u32 subsystem_flags;
+ unsigned int capability;
};
struct rkvdec_dev {
@@ -105,6 +114,7 @@ struct rkvdec_dev {
struct delayed_work watchdog_work;
struct reset_control *rstc;
u8 reset_mask;
+ unsigned int capabilities;
};
struct rkvdec_ctx {
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:21:59 +0100
Subject: [PATCH] media: rkvdec: add RK3288 variant
This adds RK3288 variant to rkvdec driver. In this earlier version
of the IP only HEVC decoding is supported.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 955c53afe20f..4e228cd82f21 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
RKVDEC_CAPABILITY_VP9
};
+static const struct rkvdec_variant rk3288_hevc_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC
+};
+
static const struct of_device_id of_rkvdec_match[] = {
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
},
+ {
+ .compatible = "rockchip,rk3288-hevc",
+ .data = &rk3288_hevc_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:27:30 +0100
Subject: [PATCH] ARM: dts: RK3288: add hevc node
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 7b2cde230b87..59fba3ac6aae 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 {
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: hevc@ff9c0000 {
+ compatible = "rockchip,rk3288-hevc";
+ reg = <0x0 0xff9c0000 0x0 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video_core";
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 {
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Date: Tue, 10 May 2022 14:37:29 -0400
Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets
The offsets from the uAPI need to be extended to include some bits
that can be calculated from the parameters. This has been compared
to match with the vendor bit sizes (which simply parse again the
data to calcualte it).
Fixed by this change:
- LTRPSPS_A_Qualcomm_1
- RPS_C_ericsson_5
- RPS_D_ericsson_6
- RPS_E_qualcomm_5
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 7a375a23eaf1..580073d49b6a 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -10,6 +10,7 @@
*/
#include <media/v4l2-mem2mem.h>
+#include <linux/bitops.h>
#include "rkvdec.h"
#include "rkvdec-regs.h"
@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
struct rkvdec_hevc_run *run)
{
const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
const struct v4l2_ctrl_hevc_slice_params *sl_params;
const struct v4l2_hevc_dpb_entry *dpb;
struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
#define NUM_RPS_POC PS_FIELD(202, 4)
for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+
sl_params = &run->slices_params[j];
dpb = decode_params->dpb;
- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
hw_ps = &priv_tbl->rps[j];
memset(hw_ps, 0, sizeof(*hw_ps));
@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
WRITE_RPS(lowdelay, LOWDELAY);
- WRITE_RPS(sl_params->long_term_ref_pic_set_size +
- sl_params->short_term_ref_pic_set_size,
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
LONG_TERM_RPS_BIT_OFFSET);
WRITE_RPS(sl_params->short_term_ref_pic_set_size,
SHORT_TERM_RPS_BIT_OFFSET);
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Date: Tue, 10 May 2022 15:12:03 -0400
Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS
The numbers from the bitstream are values between 1 - 16 (as they are
the number - 1). The difference between 0 and 1 needs to be determined
base on the slice type. I frames have no reference, P frames only have
L0 reference, and B frames have both.
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 580073d49b6a..ce15028918b2 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < run->num_slices; j++) {
uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
sl_params = &run->slices_params[j];
dpb = decode_params->dpb;
@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
hw_ps = &priv_tbl->rps[j];
memset(hw_ps, 0, sizeof(*hw_ps));
- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
+ for (i = 0; i < num_l0_refs; i++) {
WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
REF_PIC_LONG_TERM_L0(i));
WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
}
- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
+ for (i = 0; i < num_l1_refs; i++) {
WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
REF_PIC_LONG_TERM_L1(i));
WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));

290
packages/linux/patches/rockchip-old/rockchip-0049-WIP-2000-media-rkvdec-add-variants-support.patch Normal file
View File

@@ -0,0 +1,290 @@
From 0166134b07694d9256193f254932fc92f282bc03 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:16:39 +0100
Subject: [PATCH 49/59] WIP/2000: media: rkvdec: add variants support
rkvdec IP has different versions which among others differ in
the supported decoding formats.
This adds an variant implementation in order support other
than the currently supported RK3399 version.
Note: Since matching of supported codecs is index-based the
available codec options have been reordered here: from
supported by all versions to not commonly supported. This seems
the better soultion than duplicatiing code for every newly added IP.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++--------
drivers/staging/media/rkvdec/rkvdec.h | 10 +++
2 files changed, 85 insertions(+), 30 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 1f4693cbc330..3bded553872e 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -14,6 +14,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
@@ -317,35 +318,37 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = {
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
{
- .fourcc = V4L2_PIX_FMT_H264_SLICE,
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
.frmsize = {
.min_width = 64,
.max_width = 4096,
.step_width = 64,
- .min_height = 48,
- .max_height = 2560,
+ .min_height = 64,
+ .max_height = 2304,
.step_height = 16,
},
- .ctrls = &rkvdec_h264_ctrls,
- .ops = &rkvdec_h264_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
- .decoded_fmts = rkvdec_h264_decoded_fmts,
- .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_HEVC,
},
{
- .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
.min_width = 64,
.max_width = 4096,
.step_width = 64,
- .min_height = 64,
- .max_height = 2304,
+ .min_height = 48,
+ .max_height = 2560,
.step_height = 16,
},
- .ctrls = &rkvdec_hevc_ctrls,
- .ops = &rkvdec_hevc_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
- .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .ctrls = &rkvdec_h264_ctrls,
+ .ops = &rkvdec_h264_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ .decoded_fmts = rkvdec_h264_decoded_fmts,
+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .capability = RKVDEC_CAPABILITY_H264,
},
{
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
@@ -361,16 +364,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.ops = &rkvdec_vp9_fmt_ops,
.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
.decoded_fmts = rkvdec_vp9_decoded_fmts,
- }
+ .capability = RKVDEC_CAPABILITY_VP9,
+ },
};
static const struct rkvdec_coded_fmt_desc *
-rkvdec_find_coded_fmt_desc(u32 fourcc)
+rkvdec_default_coded_fmt_desc(unsigned int capabilities)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+ if (rkvdec_coded_fmts[i].capability & capabilities)
+ return &rkvdec_coded_fmts[i];
+ }
+
+ return NULL;
+}
+
+static const struct rkvdec_coded_fmt_desc *
+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- if (rkvdec_coded_fmts[i].fourcc == fourcc)
+ if (rkvdec_coded_fmts[i].fourcc == fourcc &&
+ (rkvdec_coded_fmts[i].capability & capabilities))
return &rkvdec_coded_fmts[i];
}
@@ -381,7 +399,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->coded_fmt;
- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
@@ -396,11 +414,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
const struct rkvdec_coded_fmt_desc *fmt;
+ struct rkvdec_dev *rkvdec = video_drvdata(file);
if (fsize->index != 0)
return -EINVAL;
- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
+ rkvdec->capabilities);
if (!fmt)
return -EINVAL;
@@ -469,10 +489,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
const struct rkvdec_coded_fmt_desc *desc;
- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
+ ctx->dev->capabilities);
if (!desc) {
- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
- desc = &rkvdec_coded_fmts[0];
+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
+ pix_mp->pixelformat = desc->fourcc;
}
v4l2_apply_frmsize_constraints(&pix_mp->width,
@@ -549,7 +570,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
if (ret)
return ret;
- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
+ ctx->dev->capabilities);
if (!desc)
return -EINVAL;
ctx->coded_fmt_desc = desc;
@@ -601,7 +623,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
static int rkvdec_enum_output_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+
+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
return -EINVAL;
f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
@@ -1001,14 +1026,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
int ret;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
- if (ret)
- goto err_free_handler;
+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+ if (ret)
+ goto err_free_handler;
+ }
}
ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
@@ -1210,8 +1238,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
}
}
+static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_VP9
+};
+
static const struct of_device_id of_rkvdec_match[] = {
- { .compatible = "rockchip,rk3399-vdec" },
+ {
+ .compatible = "rockchip,rk3399-vdec",
+ .data = &rk3399_rkvdec_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1223,6 +1260,7 @@ static const char * const rkvdec_clk_names[] = {
static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;
@@ -1248,6 +1286,13 @@ static int rkvdec_probe(struct platform_device *pdev)
if (ret)
return ret;
+ variant = of_device_get_match_data(rkvdec->dev);
+ if (!variant)
+ return -EINVAL;
+
+ rkvdec->capabilities = variant->capabilities;
+
+
rkvdec->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rkvdec->regs))
return PTR_ERR(rkvdec->regs);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 6afbd40450b2..728cdc5ba729 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -29,6 +29,10 @@
#define RKVDEC_RESET_DELAY 5
+#define RKVDEC_CAPABILITY_H264 BIT(0)
+#define RKVDEC_CAPABILITY_HEVC BIT(1)
+#define RKVDEC_CAPABILITY_VP9 BIT(2)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
base.vb.vb2_buf);
}
+struct rkvdec_variant {
+ unsigned int capabilities;
+};
+
struct rkvdec_coded_fmt_ops {
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
struct v4l2_format *f);
@@ -105,6 +113,7 @@ struct rkvdec_coded_fmt_desc {
unsigned int num_decoded_fmts;
const struct rkvdec_decoded_fmt_desc *decoded_fmts;
u32 subsystem_flags;
+ unsigned int capability;
};
struct rkvdec_dev {
@@ -119,6 +128,7 @@ struct rkvdec_dev {
struct delayed_work watchdog_work;
struct reset_control *rstc;
u8 reset_mask;
+ unsigned int capabilities;
};
struct rkvdec_ctx {
--
2.34.1

40
packages/linux/patches/rockchip-old/rockchip-0050-WIP-2000-media-rkvdec-add-RK3288-variant.patch Normal file
View File

@@ -0,0 +1,40 @@
From df2c88e56a2d2e2cae8689e2fe3a60375aa1c31b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:21:59 +0100
Subject: [PATCH 50/59] WIP/2000: media: rkvdec: add RK3288 variant
This adds RK3288 variant to rkvdec driver. In this earlier version
of the IP only HEVC decoding is supported.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 3bded553872e..72a5e814dd19 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1244,11 +1244,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
RKVDEC_CAPABILITY_VP9
};
+static const struct rkvdec_variant rk3288_hevc_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC
+};
+
static const struct of_device_id of_rkvdec_match[] = {
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
},
+ {
+ .compatible = "rockchip,rk3288-hevc",
+ .data = &rk3288_hevc_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
--
2.34.1

52
packages/linux/patches/rockchip-old/rockchip-0051-WIP-2000-ARM-dts-RK3288-add-hevc-node.patch Normal file
View File

@@ -0,0 +1,52 @@
From d3a694f344c3a2aa600a47cb44cb95827d95d23f Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 30 Jan 2021 18:27:30 +0100
Subject: [PATCH 51/59] WIP/2000: ARM: dts: RK3288: add hevc node
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 5f3e3cc8757c..64e9d757d712 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1285,6 +1285,25 @@ vpu_mmu: iommu@ff9a0800 {
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: hevc@ff9c0000 {
+ compatible = "rockchip,rk3288-hevc";
+ reg = <0x0 0xff9c0000 0x0 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video_core";
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1292,7 +1311,7 @@ hevc_mmu: iommu@ff9c0440 {
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
--
2.34.1

84
packages/linux/patches/rockchip-old/rockchip-0052-WIP-2000-media-rkvdec-Fix-HEVC-RPS-bit-offsets.patch Normal file
View File

@@ -0,0 +1,84 @@
From 70843319d3ed20b0621011355f0bc2db625ffd4a Mon Sep 17 00:00:00 2001
From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Date: Tue, 10 May 2022 14:37:29 -0400
Subject: [PATCH 52/59] WIP/2000: media: rkvdec: Fix HEVC RPS bit offsets
The offsets from the uAPI need to be extended to include some bits
that can be calculated from the parameters. This has been compared
to match with the vendor bit sizes (which simply parse again the
data to calcualte it).
Fixed by this change:
- LTRPSPS_A_Qualcomm_1
- RPS_C_ericsson_5
- RPS_D_ericsson_6
- RPS_E_qualcomm_5
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 5454d2d5e147..39b656d3e101 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -10,6 +10,7 @@
*/
#include <media/v4l2-mem2mem.h>
+#include <linux/bitops.h>
#include "rkvdec.h"
#include "rkvdec-regs.h"
@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
struct rkvdec_hevc_run *run)
{
const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
const struct v4l2_ctrl_hevc_slice_params *sl_params;
const struct v4l2_hevc_dpb_entry *dpb;
struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
#define NUM_RPS_POC PS_FIELD(202, 4)
for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+
sl_params = &run->slices_params[j];
dpb = decode_params->dpb;
- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
hw_ps = &priv_tbl->rps[j];
memset(hw_ps, 0, sizeof(*hw_ps));
@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
WRITE_RPS(lowdelay, LOWDELAY);
- WRITE_RPS(sl_params->long_term_ref_pic_set_size +
- sl_params->short_term_ref_pic_set_size,
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
LONG_TERM_RPS_BIT_OFFSET);
WRITE_RPS(sl_params->short_term_ref_pic_set_size,
SHORT_TERM_RPS_BIT_OFFSET);
--
2.34.1

50
packages/linux/patches/rockchip-old/rockchip-0053-WIP-2000-media-rkvdec-Fix-number-of-HEVC-references-.patch Normal file
View File

@@ -0,0 +1,50 @@
From 926527e77cc261449875af78e9e52c0b20af7f46 Mon Sep 17 00:00:00 2001
From: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Date: Tue, 10 May 2022 15:12:03 -0400
Subject: [PATCH 53/59] WIP/2000: media: rkvdec: Fix number of HEVC references
being set in RPS
The numbers from the bitstream are values between 1 - 16 (as they are
the number - 1). The difference between 0 and 1 needs to be determined
base on the slice type. I frames have no reference, P frames only have
L0 reference, and B frames have both.
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 39b656d3e101..7c74981953ea 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < run->num_slices; j++) {
uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
sl_params = &run->slices_params[j];
dpb = decode_params->dpb;
@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
hw_ps = &priv_tbl->rps[j];
memset(hw_ps, 0, sizeof(*hw_ps));
- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
+ for (i = 0; i < num_l0_refs; i++) {
WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
REF_PIC_LONG_TERM_L0(i));
WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
}
- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
+ for (i = 0; i < num_l1_refs; i++) {
WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
REF_PIC_LONG_TERM_L1(i));
WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
--
2.34.1

93
packages/linux/patches/rockchip-old/rockchip-0054-WIP-2001-dt-bindings-media-Add-Rockchip-IEP-binding.patch Normal file
View File

@@ -0,0 +1,93 @@
From 73427ab019d92c8063dbc55766a659be3c61c97c Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 17:03:12 +0200
Subject: [PATCH 54/59] WIP/2001: dt-bindings: media: Add Rockchip IEP binding
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
.../bindings/media/rockchip-iep.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml
diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
new file mode 100644
index 000000000000..a9efcda13fc1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Image Enhancement Processor (IEP)
+
+description:
+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the
+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3228-iep
+ - items:
+ - enum:
+ - rockchip,rk3288-iep
+ - rockchip,rk3328-iep
+ - rockchip,rk3368-iep
+ - rockchip,rk3399-iep
+ - const: rockchip,rk3228-iep
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: axi
+ - const: ahb
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3228-power.h>
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ iommus = <&iep_mmu>;
+ power-domains = <&power RK3228_PD_VIO>;
+ };
--
2.34.1

232
projects/Rockchip/patches/linux/default/linux-2001-v4l2-wip-iep-driver.patch → packages/linux/patches/rockchip-old/rockchip-0055-WIP-2001-media-rockchip-Add-Rockchip-IEP-driver.patch
View File

@@ -1,98 +1,7 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 17:03:12 +0200
Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
.../bindings/media/rockchip-iep.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml
diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
new file mode 100644
index 000000000000..a9efcda13fc1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Image Enhancement Processor (IEP)
+
+description:
+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the
+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3228-iep
+ - items:
+ - enum:
+ - rockchip,rk3288-iep
+ - rockchip,rk3328-iep
+ - rockchip,rk3368-iep
+ - rockchip,rk3399-iep
+ - const: rockchip,rk3228-iep
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: axi
+ - const: ahb
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3228-power.h>
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ iommus = <&iep_mmu>;
+ power-domains = <&power RK3228_PD_VIO>;
+ };
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From ed377549c4b8c1cacc4146e3b47cda38fa3df5da Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 21:24:10 +0200
Subject: [PATCH] media: rockchip: Add Rockchip IEP driver
Subject: [PATCH 55/59] WIP/2001: media: rockchip: Add Rockchip IEP driver
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
@@ -101,9 +10,9 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
drivers/media/platform/rockchip/iep/Kconfig | 16 +
drivers/media/platform/rockchip/iep/Makefile | 5 +
.../media/platform/rockchip/iep/iep-regs.h | 291 +++++
drivers/media/platform/rockchip/iep/iep.c | 1089 +++++++++++++++++
drivers/media/platform/rockchip/iep/iep.c | 1087 +++++++++++++++++
drivers/media/platform/rockchip/iep/iep.h | 112 ++
7 files changed, 1515 insertions(+)
7 files changed, 1513 insertions(+)
create mode 100644 drivers/media/platform/rockchip/iep/Kconfig
create mode 100644 drivers/media/platform/rockchip/iep/Makefile
create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h
@@ -462,7 +371,7 @@ index 000000000000..a68685ef3604
+#endif
diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c
new file mode 100644
index 000000000000..f4b9320733be
index 000000000000..2e547133c3be
--- /dev/null
+++ b/drivers/media/platform/rockchip/iep/iep.c
@@ -0,0 +1,1087 @@
@@ -1671,133 +1580,6 @@ index 000000000000..7d9fc61624b6
+};
+
+#endif
--
2.34.1
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:22:38 +0200
Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328
while at that also add the mmu required
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index eec03adf0902..5455a46c9a6b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 {
status = "disabled";
};
+ iep: iep@ff3a0000 {
+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff3a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ iommus = <&iep_mmu>;
+ };
+
+ iep_mmu: iommu@ff3a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff3a0800 0x0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ #iommu-cells = <0>;
+ };
+
hdmi: hdmi@ff3c0000 {
compatible = "rockchip,rk3328-dw-hdmi";
reg = <0x0 0xff3c0000 0x0 0x20000>;
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:43:12 +0200
Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index dbe6a9cb98a5..f0629b7a81c6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 {
#iommu-cells = <0>;
};
+ iep: iep@ff670000 {
+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3399_PD_IEP>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff670800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3399_PD_IEP>;
#iommu-cells = <0>;
- status = "disabled";
};
rga: rga@ff680000 {
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:53:56 +0200
Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 59fba3ac6aae..06545f423de2 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 {
reset-names = "crypto-rst";
};
+ iep: iep@ff90000 {
+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3288_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x40>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
};
isp_mmu: iommu@ff914000 {

48
packages/linux/patches/rockchip-old/rockchip-0056-WIP-2001-ARM64-dts-rockchip-Add-IEP-node-for-RK3328.patch Normal file
View File

@@ -0,0 +1,48 @@
From b489e58fe7cbc0cd2432314447b59316ec3a8ab5 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:22:38 +0200
Subject: [PATCH 56/59] WIP/2001: ARM64: dts: rockchip: Add IEP node for RK3328
while at that also add the mmu required
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index e3beadde6c07..bb8093eb163c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -791,6 +791,28 @@ vop_mmu: iommu@ff373f00 {
status = "disabled";
};
+ iep: iep@ff3a0000 {
+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff3a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ iommus = <&iep_mmu>;
+ };
+
+ iep_mmu: iommu@ff3a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff3a0800 0x0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3328_PD_VIDEO>;
+ #iommu-cells = <0>;
+ };
+
hdmi: hdmi@ff3c0000 {
compatible = "rockchip,rk3328-dw-hdmi";
reg = <0x0 0xff3c0000 0x0 0x20000>;
--
2.34.1

44
packages/linux/patches/rockchip-old/rockchip-0057-WIP-2001-ARM64-dts-rockchip-Add-IEP-node-for-RK3399.patch Normal file
View File

@@ -0,0 +1,44 @@
From 319bec9d8c6e78d6caa2f31922c82cc188192635 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:43:12 +0200
Subject: [PATCH 57/59] WIP/2001: ARM64: dts: rockchip: Add IEP node for RK3399
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index f06147581fab..d088e484a02c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1480,14 +1480,25 @@ vdec_mmu: iommu@ff660480 {
#iommu-cells = <0>;
};
+ iep: iep@ff670000 {
+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3399_PD_IEP>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff670800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3399_PD_IEP>;
#iommu-cells = <0>;
- status = "disabled";
};
rga: rga@ff680000 {
--
2.34.1

44
packages/linux/patches/rockchip-old/rockchip-0058-WIP-2001-ARM-dts-rockchip-Add-IEP-node-for-RK3288.patch Normal file
View File

@@ -0,0 +1,44 @@
From 64554c7fe9941ce1896256e46155f1483ad0b4e8 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:53:56 +0200
Subject: [PATCH 58/59] WIP/2001: ARM: dts: rockchip: Add IEP node for RK3288
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 64e9d757d712..6f363eb14185 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -990,14 +990,25 @@ crypto: crypto@ff8a0000 {
reset-names = "crypto-rst";
};
+ iep: iep@ff90000 {
+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ power-domains = <&power RK3288_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x40>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
};
isp_mmu: iommu@ff914000 {
--
2.34.1

31
packages/linux/patches/rockchip-old/rockchip-0059-WIP-9000-arm64-rockchip-rk3288-disable-VPU-iommu.patch Normal file
View File

@@ -0,0 +1,31 @@
From 7febf2c5fa24b27be17a528e8d74a2ccd5759ab8 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 15 Dec 2024 12:53:18 +0100
Subject: [PATCH 59/59] WIP/9000: arm64: rockchip: rk3288: disable VPU iommu
Due to bug in either hantro, iommu or general dma management drivers for ARMv7
buffers are not correctly flushed when being re-used.
To work around that, disable VPU iommu and increase cma memory size to be
sufficient for 4K H.264 decoding.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 6f363eb14185..3af2cd4f78c3 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1294,6 +1294,7 @@ vpu_mmu: iommu@ff9a0800 {
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3288_PD_VIDEO>;
+ status = "disabled";
};
hevc: hevc@ff9c0000 {
--
2.34.1

33
packages/linux/patches/rockchip/rockchip-0001-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch Normal file
View File

@@ -0,0 +1,33 @@
From 1efb0ab46aeddce29687b942b118a5338d249c61 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 13 Apr 2019 05:45:18 +0000
Subject: [PATCH 001/108] LOCAL: arm64: fix Kodi sysinfo CPU information
This allows the CPU information to show in the Kodi sysinfo screen, e.g.
"ARMv8 Processor rev 4 (v81)" on Amlogic devices
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/kernel/cpuinfo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index ba834909a28b..4384c894bb0f 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -223,9 +223,8 @@ static int c_show(struct seq_file *m, void *v)
* "processor". Give glibc what it expects.
*/
seq_printf(m, "processor\t: %d\n", cpu);
- if (compat)
- seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
- MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+ MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
loops_per_jiffy / (500000UL/HZ),
--
2.34.1

43
packages/linux/patches/rockchip/rockchip-0002-LOCAL-arm64-dts-rockchip-rock5b-disable-sdio-node.patch Normal file
View File

@@ -0,0 +1,43 @@
From 9f9d1e1535f8004247aca088d83f964c66a81155 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 16 Jul 2025 11:03:09 +0000
Subject: [PATCH 002/108] LOCAL: arm64: dts: rockchip: rock5b: disable sdio
node
Radxa ships an M2 compatible WiFi module with PCIe wired RTL8852BE
chip, so leave the SDIO node described in device-tree, but disable
it by default to avoid mmc2 failures in the system log:
ROCK5B:~ # dmesg | grep mmc2
[ 0.790097] mmc_host mmc2: card is non-removable.
[ 0.804379] mmc_host mmc2: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 1.968538] mmc_host mmc2: Timeout sending command (cmd 0x202000 arg 0x0 status 0x80202000)
[ 1.992757] mmc_host mmc2: Bus speed (slot 0) = 300000Hz (slot req 300000Hz, actual 300000HZ div = 0)
[ 3.163937] mmc_host mmc2: Timeout sending command (cmd 0x202000 arg 0x0 status 0x80202000)
[ 3.177872] mmc_host mmc2: Bus speed (slot 0) = 200000Hz (slot req 200000Hz, actual 200000HZ div = 0)
[ 4.359405] mmc_host mmc2: Timeout sending command (cmd 0x202000 arg 0x0 status 0x80202000)
[ 4.373304] mmc_host mmc2: Bus speed (slot 0) = 187500Hz (slot req 187500Hz, actual 187500HZ div = 0)
[ 5.538223] mmc_host mmc2: Timeout sending command (cmd 0x202000 arg 0x0 status 0x80202000)
[ 5.539621] mmc2: Failed to initialize a non-removable card
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 9407a7c9910a..ba82c89201ea 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -27,7 +27,7 @@ &sdio {
vqmmc-supply = <&vcc_1v8_s3>;
pinctrl-names = "default";
pinctrl-0 = <&sdiom0_pins>;
- status = "okay";
+ status = "disabled";
};
&uart6 {
--
2.34.1

173
packages/linux/patches/rockchip/rockchip-0003-LOCAL-drm-rockchip-vop2-rk3588-change-Esmart-Cluster.patch Normal file
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@@ -0,0 +1,173 @@
From 5f3225643ae70aa456d1cc3ea4b42a2a1556ad0d Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 16 Jul 2025 05:09:07 +0000
Subject: [PATCH 003/108] LOCAL: drm/rockchip: vop2: rk3588: change
Esmart/Cluster ordering
Order Esmart planes before Cluster planes so Kodi (which currently
lacks the ability to dymanically order planes using zpos) can show
the OSD on-top of Video rather then behind.
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 136 +++++++++----------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
index 45c5e3987813..42a4833a90a3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -1119,6 +1119,74 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
*/
static const struct vop2_win_data rk3588_vop_win_data[] = {
{
+ .name = "Esmart0-win0",
+ .phys_id = ROCKCHIP_VOP2_ESMART0,
+ .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
+ .formats = formats_esmart,
+ .nformats = ARRAY_SIZE(formats_esmart),
+ .format_modifiers = format_modifiers,
+ .base = 0x1800,
+ .layer_sel_id = { 2, 2, 2, 2 },
+ .supported_rotations = DRM_MODE_REFLECT_Y,
+ .type = DRM_PLANE_TYPE_OVERLAY,
+ .axi_bus_id = 0,
+ .axi_yrgb_r_id = 0x0a,
+ .axi_uv_r_id = 0x0b,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ .dly = { 23, 45, 48 },
+ }, {
+ .name = "Esmart1-win0",
+ .phys_id = ROCKCHIP_VOP2_ESMART1,
+ .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
+ .formats = formats_esmart,
+ .nformats = ARRAY_SIZE(formats_esmart),
+ .format_modifiers = format_modifiers,
+ .base = 0x1a00,
+ .layer_sel_id = { 3, 3, 3, 3 },
+ .supported_rotations = DRM_MODE_REFLECT_Y,
+ .type = DRM_PLANE_TYPE_OVERLAY,
+ .axi_bus_id = 0,
+ .axi_yrgb_r_id = 0x0c,
+ .axi_uv_r_id = 0x01,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ .dly = { 23, 45, 48 },
+ }, {
+ .name = "Esmart2-win0",
+ .phys_id = ROCKCHIP_VOP2_ESMART2,
+ .base = 0x1c00,
+ .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
+ .formats = formats_esmart,
+ .nformats = ARRAY_SIZE(formats_esmart),
+ .format_modifiers = format_modifiers,
+ .layer_sel_id = { 6, 6, 6, 6 },
+ .supported_rotations = DRM_MODE_REFLECT_Y,
+ .type = DRM_PLANE_TYPE_OVERLAY,
+ .axi_bus_id = 1,
+ .axi_yrgb_r_id = 0x0a,
+ .axi_uv_r_id = 0x0b,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ .dly = { 23, 45, 48 },
+ }, {
+ .name = "Esmart3-win0",
+ .phys_id = ROCKCHIP_VOP2_ESMART3,
+ .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
+ .formats = formats_esmart,
+ .nformats = ARRAY_SIZE(formats_esmart),
+ .format_modifiers = format_modifiers,
+ .base = 0x1e00,
+ .layer_sel_id = { 7, 7, 7, 7 },
+ .supported_rotations = DRM_MODE_REFLECT_Y,
+ .type = DRM_PLANE_TYPE_OVERLAY,
+ .axi_bus_id = 1,
+ .axi_yrgb_r_id = 0x0c,
+ .axi_uv_r_id = 0x0d,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ .dly = { 23, 45, 48 },
+ }, {
.name = "Cluster0-win0",
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
.base = 0x1000,
@@ -1194,74 +1262,6 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.max_downscale_factor = 4,
.dly = { 4, 26, 29 },
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER,
- }, {
- .name = "Esmart0-win0",
- .phys_id = ROCKCHIP_VOP2_ESMART0,
- .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- .formats = formats_esmart,
- .nformats = ARRAY_SIZE(formats_esmart),
- .format_modifiers = format_modifiers,
- .base = 0x1800,
- .layer_sel_id = { 2, 2, 2, 2 },
- .supported_rotations = DRM_MODE_REFLECT_Y,
- .type = DRM_PLANE_TYPE_OVERLAY,
- .axi_bus_id = 0,
- .axi_yrgb_r_id = 0x0a,
- .axi_uv_r_id = 0x0b,
- .max_upscale_factor = 8,
- .max_downscale_factor = 8,
- .dly = { 23, 45, 48 },
- }, {
- .name = "Esmart1-win0",
- .phys_id = ROCKCHIP_VOP2_ESMART1,
- .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- .formats = formats_esmart,
- .nformats = ARRAY_SIZE(formats_esmart),
- .format_modifiers = format_modifiers,
- .base = 0x1a00,
- .layer_sel_id = { 3, 3, 3, 3 },
- .supported_rotations = DRM_MODE_REFLECT_Y,
- .type = DRM_PLANE_TYPE_OVERLAY,
- .axi_bus_id = 0,
- .axi_yrgb_r_id = 0x0c,
- .axi_uv_r_id = 0x01,
- .max_upscale_factor = 8,
- .max_downscale_factor = 8,
- .dly = { 23, 45, 48 },
- }, {
- .name = "Esmart2-win0",
- .phys_id = ROCKCHIP_VOP2_ESMART2,
- .base = 0x1c00,
- .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- .formats = formats_esmart,
- .nformats = ARRAY_SIZE(formats_esmart),
- .format_modifiers = format_modifiers,
- .layer_sel_id = { 6, 6, 6, 6 },
- .supported_rotations = DRM_MODE_REFLECT_Y,
- .type = DRM_PLANE_TYPE_OVERLAY,
- .axi_bus_id = 1,
- .axi_yrgb_r_id = 0x0a,
- .axi_uv_r_id = 0x0b,
- .max_upscale_factor = 8,
- .max_downscale_factor = 8,
- .dly = { 23, 45, 48 },
- }, {
- .name = "Esmart3-win0",
- .phys_id = ROCKCHIP_VOP2_ESMART3,
- .possible_vp_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
- .formats = formats_esmart,
- .nformats = ARRAY_SIZE(formats_esmart),
- .format_modifiers = format_modifiers,
- .base = 0x1e00,
- .layer_sel_id = { 7, 7, 7, 7 },
- .supported_rotations = DRM_MODE_REFLECT_Y,
- .type = DRM_PLANE_TYPE_OVERLAY,
- .axi_bus_id = 1,
- .axi_yrgb_r_id = 0x0c,
- .axi_uv_r_id = 0x0d,
- .max_upscale_factor = 8,
- .max_downscale_factor = 8,
- .dly = { 23, 45, 48 },
},
};
--
2.34.1

182
packages/linux/patches/rockchip/rockchip-0004-FROMGIT-6.18-media-uapi-HEVC-Add-v4l2_ctrl_hevc_ext_.patch Normal file
View File

@@ -0,0 +1,182 @@
From ba2f7791641e70ab3a6ad8605622a46a99f4b667 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Thu, 24 Jul 2025 14:10:18 -0400
Subject: [PATCH 004/108] FROMGIT(6.18): media: uapi: HEVC: Add
v4l2_ctrl_hevc_ext_sps_[ls]t_rps controls
Some hardware (e.g.: Rockchip's rk3588 hevc decoder) need the
long and short term reference information for HEVC decoding.
Add controls to provide it as the raw data form the stream.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
.../media/v4l/ext-ctrls-codec-stateless.rst | 114 ++++++++++++++++++
.../media/v4l/vidioc-queryctrl.rst | 12 ++
.../media/videodev2.h.rst.exceptions | 2 +
3 files changed, 128 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
index 0da635691fdc..bb6772cf3cee 100644
--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
@@ -2958,6 +2958,120 @@ This structure contains all loop filter related parameters. See sections
- 0x00000004
-
+``V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (struct)``
+ Specifies the list of Long-Term reference sets parameters from the SPS.
+ These parameters are defined according to :ref:`hevc`.
+ They are described in section 7.4.3.2.1 "General sequence parameter set
+ RBSP semantics" of the specification.
+ This control is a dynamically sized 1-dimensional array,
+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it.
+
+.. c:type:: v4l2_ctrl_hevc_ext_sps_lt_rps
+
+.. cssclass:: longtable
+
+.. flat-table:: struct v4l2_ctrl_hevc_ext_sps_lt_rps
+ :header-rows: 0
+ :stub-columns: 0
+ :widths: 1 1 2
+
+ * - __u16
+ - ``lt_ref_pic_poc_lsb_sps``
+ - Long term reference picture order count as described in section 7.4.3.2.1
+ "General sequence parameter set RBSP semantics" of the specification.
+ * - __u8
+ - ``flags``
+ - See :ref:`Extended Long-Term RPS Flags <hevc_ext_sps_lt_rps_flags>`
+
+.. _hevc_ext_sps_lt_rps_flags:
+
+``Extended SPS Long-Term RPS Flags``
+
+.. cssclass:: longtable
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+ :widths: 1 1 2
+
+ * - ``V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT``
+ - 0x00000001
+ - Specifies if the long-term reference picture is used 7.4.3.2.1 "General sequence parameter
+ set RBSP semantics" of the specification.
+
+``V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (struct)``
+ Specifies the list of Short-Term reference sets parameters from the SPS.
+ These parameters are defined according to :ref:`hevc`.
+ They are described in section 7.4.8 "Short-term reference picture set
+ semantics" of the specification.
+ This control is a dynamically sized 1-dimensional array,
+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it.
+
+.. c:type:: v4l2_ctrl_hevc_ext_sps_st_rps
+
+.. cssclass:: longtable
+
+.. flat-table:: struct v4l2_ctrl_hevc_ext_sps_st_rps
+ :header-rows: 0
+ :stub-columns: 0
+ :widths: 1 1 2
+
+ * - __u8
+ - ``delta_idx_minus1``
+ - Specifies the delta compare to the index. See details in section 7.4.8 "Short-term
+ reference picture set semantics" of the specification.
+ * - __u8
+ - ``delta_rps_sign``
+ - Sign of the delta as specified in section 7.4.8 "Short-term reference picture set
+ semantics" of the specification.
+ * - __u16
+ - ``abs_delta_rps_minus1``
+ - Absolute delta RPS as specified in section 7.4.8 "Short-term reference picture set
+ semantics" of the specification.
+ * - __u8
+ - ``num_negative_pics``
+ - Number of short-term RPS entries that have picture order count values less than the
+ picture order count value of the current picture.
+ * - __u8
+ - ``num_positive_pics``
+ - Number of short-term RPS entries that have picture order count values greater than the
+ picture order count value of the current picture.
+ * - __u32
+ - ``used_by_curr_pic``
+ - Bit i specifies if short-term RPS i is used by the current picture.
+ * - __u32
+ - ``use_delta_flag``
+ - Bit i specifies if short-term RPS i is included in the short-term RPS entries.
+ * - __u16
+ - ``delta_poc_s0_minus1[16]``
+ - Specifies the negative picture order count delta for the i-th entry in the short-term RPS.
+ See details in section 7.4.8 "Short-term reference picture set semantics" of the
+ specification.
+ * - __u16
+ - ``delta_poc_s1_minus1[16]``
+ - Specifies the positive picture order count delta for the i-th entry in the short-term RPS.
+ See details in section 7.4.8 "Short-term reference picture set semantics" of the
+ specification.
+ * - __u8
+ - ``flags``
+ - See :ref:`Extended Short-Term RPS Flags <hevc_ext_sps_st_rps_flags>`
+
+.. _hevc_ext_sps_st_rps_flags:
+
+``Extended SPS Short-Term RPS Flags``
+
+.. cssclass:: longtable
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+ :widths: 1 1 2
+
+ * - ``V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED``
+ - 0x00000001
+ - Specifies if the short-term RPS is predicted from another short term RPS. See details in
+ section 7.4.8 "Short-term reference picture set semantics" of the specification.
+
.. _v4l2-codec-stateless-av1:
``V4L2_CID_STATELESS_AV1_SEQUENCE (struct)``
diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst
index 3549417c7feb..128c044d2e3c 100644
--- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst
+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst
@@ -523,6 +523,18 @@ See also the examples in :ref:`control`.
- n/a
- A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC
decoding parameters for stateless video decoders.
+ * - ``V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS``
+ - n/a
+ - n/a
+ - n/a
+ - A struct :c:type:`v4l2_ctrl_hevc_ext_sps_lt_rps`, containing HEVC
+ extended Long-Term RPS for stateless video decoders.
+ * - ``V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS``
+ - n/a
+ - n/a
+ - n/a
+ - A struct :c:type:`v4l2_ctrl_hevc_ext_sps_st_rps`, containing HEVC
+ extended Short-Term RPS for stateless video decoders.
* - ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR``
- n/a
- n/a
diff --git a/Documentation/userspace-api/media/videodev2.h.rst.exceptions b/Documentation/userspace-api/media/videodev2.h.rst.exceptions
index 35d3456cc812..1663fdf8444c 100644
--- a/Documentation/userspace-api/media/videodev2.h.rst.exceptions
+++ b/Documentation/userspace-api/media/videodev2.h.rst.exceptions
@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type`
+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS :c:type:`v4l2_ctrl_type`
+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_RECT :c:type:`v4l2_ctrl_type`
replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type`
--
2.34.1

192
packages/linux/patches/rockchip/rockchip-0005-FROMGIT-6.18-media-v4l2-ctrls-Add-hevc_ext_sps_-ls-t.patch Normal file
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@@ -0,0 +1,192 @@
From 09f7bf034d1a5608cd1992db1e582c1352a10dbf Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Thu, 24 Jul 2025 14:10:19 -0400
Subject: [PATCH 005/108] FROMGIT(6.18): media: v4l2-ctrls: Add
hevc_ext_sps_[ls]t_rps controls
The vdpu381 decoder found on newer Rockchip SoC need the information
from the long term and short term ref pic sets from the SPS.
So far, it wasn't included in the v4l2 API, so add it with new dynamic
sized controls.
Each element of the hevc_ext_sps_lt_rps array contains the long term ref
pic set at that index.
Each element of the hevc_ext_sps_st_rps contains the short term ref pic
set at that index, as the raw data.
It is the role of the drivers to calculate the reference sets values.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
drivers/media/v4l2-core/v4l2-ctrls-core.c | 18 +++++++
drivers/media/v4l2-core/v4l2-ctrls-defs.c | 10 ++++
include/uapi/linux/v4l2-controls.h | 61 +++++++++++++++++++++++
include/uapi/linux/videodev2.h | 2 +
4 files changed, 91 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c
index 98b960775e87..142e26134ef0 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c
@@ -418,6 +418,12 @@ void v4l2_ctrl_type_op_log(const struct v4l2_ctrl *ctrl)
case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
pr_cont("HEVC_SLICE_PARAMS");
break;
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS:
+ pr_cont("HEVC_EXT_SPS_ST_RPS");
+ break;
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS:
+ pr_cont("HEVC_EXT_SPS_LT_RPS");
+ break;
case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:
pr_cont("HEVC_SCALING_MATRIX");
break;
@@ -1173,6 +1179,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
break;
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS:
+ break;
+
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS:
+ break;
+
case V4L2_CTRL_TYPE_HDR10_CLL_INFO:
break;
@@ -1925,6 +1937,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params);
break;
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS:
+ elem_size = sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps);
+ break;
+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS:
+ elem_size = sizeof(struct v4l2_ctrl_hevc_ext_sps_lt_rps);
+ break;
case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:
elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix);
break;
diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index 1ea52011247a..86c7ee224b66 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
@@ -1233,6 +1233,8 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_STATELESS_HEVC_DECODE_MODE: return "HEVC Decode Mode";
case V4L2_CID_STATELESS_HEVC_START_CODE: return "HEVC Start Code";
case V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS: return "HEVC Entry Point Offsets";
+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS: return "HEVC Short Term Ref Sets";
+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS: return "HEVC Long Term Ref Sets";
case V4L2_CID_STATELESS_AV1_SEQUENCE: return "AV1 Sequence Parameters";
case V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY: return "AV1 Tile Group Entry";
case V4L2_CID_STATELESS_AV1_FRAME: return "AV1 Frame Parameters";
@@ -1578,6 +1580,14 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
*type = V4L2_CTRL_TYPE_U32;
*flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY;
break;
+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS:
+ *type = V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS;
+ *flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY;
+ break;
+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS:
+ *type = V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS;
+ *flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY;
+ break;
case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR:
*type = V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR;
break;
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index f836512e9deb..08f869124474 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -2094,6 +2094,8 @@ struct v4l2_ctrl_mpeg2_quantisation {
#define V4L2_CID_STATELESS_HEVC_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 405)
#define V4L2_CID_STATELESS_HEVC_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 406)
#define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407)
+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (V4L2_CID_CODEC_STATELESS_BASE + 408)
+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (V4L2_CID_CODEC_STATELESS_BASE + 409)
enum v4l2_stateless_hevc_decode_mode {
V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,
@@ -2549,6 +2551,65 @@ struct v4l2_ctrl_hevc_scaling_matrix {
__u8 scaling_list_dc_coef_32x32[2];
};
+#define V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED 0x1
+
+/*
+ * struct v4l2_ctrl_hevc_ext_sps_st_rps - HEVC short term RPS parameters
+ *
+ * Dynamic size 1-dimension array for short term RPS. The number of elements
+ * is v4l2_ctrl_hevc_sps::num_short_term_ref_pic_sets. It can contain up to 65 elements.
+ *
+ * @delta_idx_minus1: Specifies the delta compare to the index. See details in section 7.4.8
+ * "Short-term reference picture set semantics" of the specification.
+ * @delta_rps_sign: Sign of the delta as specified in section 7.4.8 "Short-term reference picture
+ * set semantics" of the specification.
+ * @abs_delta_rps_minus1: Absolute delta RPS as specified in section 7.4.8 "Short-term reference
+ * picture set semantics" of the specification.
+ * @num_negative_pics: Number of short-term RPS entries that have picture order count values less
+ * than the picture order count value of the current picture.
+ * @num_positive_pics: Number of short-term RPS entries that have picture order count values
+ * greater than the picture order count value of the current picture.
+ * @used_by_curr_pic: Bit j specifies if short-term RPS j is used by the current picture.
+ * @use_delta_flag: Bit j equals to 1 specifies that the j-th entry in the source candidate
+ * short-term RPS is included in this candidate short-term RPS.
+ * @delta_poc_s0_minus1: Specifies the negative picture order count delta for the i-th entry in
+ * the short-term RPS. See details in section 7.4.8 "Short-term reference
+ * picture set semantics" of the specification.
+ * @delta_poc_s1_minus1: Specifies the positive picture order count delta for the i-th entry in
+ * the short-term RPS. See details in section 7.4.8 "Short-term reference
+ * picture set semantics" of the specification.
+ * @flags: See V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_{}
+ */
+struct v4l2_ctrl_hevc_ext_sps_st_rps {
+ __u8 delta_idx_minus1;
+ __u8 delta_rps_sign;
+ __u16 abs_delta_rps_minus1;
+ __u8 num_negative_pics;
+ __u8 num_positive_pics;
+ __u32 used_by_curr_pic;
+ __u32 use_delta_flag;
+ __u16 delta_poc_s0_minus1[16];
+ __u16 delta_poc_s1_minus1[16];
+ __u8 flags;
+};
+
+#define V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT 0x1
+
+/*
+ * struct v4l2_ctrl_hevc_ext_sps_lt_rps - HEVC long term RPS parameters
+ *
+ * Dynamic size 1-dimension array for long term RPS. The number of elements
+ * is v4l2_ctrl_hevc_sps::num_long_term_ref_pics_sps. It can contain up to 65 elements.
+ *
+ * @lt_ref_pic_poc_lsb_sps: picture order count modulo MaxPicOrderCntLsb of the i-th candidate
+ * long-term reference picture.
+ * @flags: See V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_{}
+ */
+struct v4l2_ctrl_hevc_ext_sps_lt_rps {
+ __u16 lt_ref_pic_poc_lsb_sps;
+ __u8 flags;
+};
+
#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900)
#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1)
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 3dd9fa45dde1..a3aa1f8c3894 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1981,6 +1981,8 @@ enum v4l2_ctrl_type {
V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS = 0x0272,
V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX = 0x0273,
V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS = 0x0274,
+ V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS = 0x0275,
+ V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS = 0x0276,
V4L2_CTRL_TYPE_AV1_SEQUENCE = 0x280,
V4L2_CTRL_TYPE_AV1_TILE_GROUP_ENTRY = 0x281,
--
2.34.1

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@@ -0,0 +1,111 @@
From fab7fe918af46b99bdd05a9a32c16d488ac8050b Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 23 Jun 2025 12:07:17 -0400
Subject: [PATCH 006/108] FROMGIT(6.18): arm64: dts: rockchip: Add the vdpu381
Video Decoders on RK3588
Add the vdpu381 Video Decoders to the rk3588-base devicetree.
The RK3588 based SoCs all embed 2 vdpu381 decoders.
This also adds the dedicated IOMMU controllers.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 70f03e68ba55..c1eaff86d5b7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 {
#iommu-cells = <0>;
};
+ vdec0: video-codec@fdc38000 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc38100 0x0 0x500>,
+ <0x0 0xfdc38000 0x0 0x100>,
+ <0x0 0xfdc38600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec0_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec0_sram>;
+ };
+
+ vdec0_mmu: iommu@fdc38700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ #iommu-cells = <0>;
+ };
+
+ vdec1: video-codec@fdc40000 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc40100 0x0 0x500>,
+ <0x0 0xfdc40000 0x0 0x100>,
+ <0x0 0xfdc40600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec1_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec1_sram>;
+ };
+
+ vdec1_mmu: iommu@fdc40700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
@@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 {
ranges = <0x0 0x0 0xff001000 0xef000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ vdec0_sram: codec-sram@0 {
+ reg = <0x0 0x78000>;
+ pool;
+ };
+
+ vdec1_sram: codec-sram@78000 {
+ reg = <0x78000 0x77000>;
+ pool;
+ };
};
pinctrl: pinctrl {
--
2.34.1

72
packages/linux/patches/rockchip/rockchip-0007-FROMGIT-6.18-arm64-dts-rockchip-Add-the-vdpu383-Vide.patch Normal file
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@@ -0,0 +1,72 @@
From f2641077e6f20acb152e9cdb439a0475662538fa Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 23 Jun 2025 12:07:18 -0400
Subject: [PATCH 007/108] FROMGIT(6.18): arm64: dts: rockchip: Add the vdpu383
Video Decoder on rk3576
Add the vdpu383 Video Decoder variant to the RK3576 device tree.
Also allow using the dedicated SRAM as a pool.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index c3cdae8a5494..b99f4bd4c9d9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1139,6 +1139,41 @@ gpu: gpu@27800000 {
status = "disabled";
};
+ vdec: video-codec@27b00000 {
+ compatible = "rockchip,rk3576-vdec";
+ reg = <0x0 0x27b00100 0x0 0x500>,
+ <0x0 0x27b00000 0x0 0x100>,
+ <0x0 0x27b00600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
+ <&cru CLK_RKVDEC_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>,
+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>;
+ assigned-clock-rates = <600000000>, <600000000>,
+ <500000000>, <1000000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3576_PD_VDEC>;
+ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>,
+ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>,
+ <&cru SRST_RKVDEC_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&rkvdec_sram>;
+ };
+
+ vdec_mmu: iommu@27b00800 {
+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3576_PD_VDEC>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ };
+
vop: vop@27d00000 {
compatible = "rockchip,rk3576-vop";
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
@@ -2428,6 +2463,7 @@ sram: sram@3ff88000 {
/* start address and size should be 4k align */
rkvdec_sram: rkvdec-sram@0 {
reg = <0x0 0x78000>;
+ pool;
};
};
--
2.34.1

42
packages/linux/patches/rockchip/rockchip-0008-FROMGIT-6.18-arm64-dts-rockchip-Enable-HDMI-audio-ou.patch Normal file
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@@ -0,0 +1,42 @@
From ea91dcbaa188e57990e25d381aa855d59ff9f1e9 Mon Sep 17 00:00:00 2001
From: Anton Kirilov <anton.kirilov@arm.com>
Date: Thu, 7 Aug 2025 18:00:11 +0100
Subject: [PATCH 008/108] FROMGIT(6.18): arm64: dts: rockchip: Enable HDMI
audio output for NanoPi R6C/R6S
Enable HDMI audio output for FriendlyElec NanoPi R6C/R6S boards.
Signed-off-by: Anton Kirilov <anton.kirilov@arm.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
index fbf062ec3bf1..2e9d5143476d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
@@ -251,6 +251,10 @@ hdmi0_out_con: endpoint {
};
};
+&hdmi0_sound {
+ status = "okay";
+};
+
&hdptxphy0 {
status = "okay";
};
@@ -335,6 +339,10 @@ hym8563: rtc@51 {
};
};
+&i2s5_8ch {
+ status = "okay";
+};
+
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
--
2.34.1

68
packages/linux/patches/rockchip/rockchip-0009-FROMGIT-6.18-arm64-dts-rockchip-Enable-the-NPU-on-Na.patch Normal file
View File

@@ -0,0 +1,68 @@
From 4105b87fae397b898acc67b05019c7e8801bc582 Mon Sep 17 00:00:00 2001
From: Anton Kirilov <anton.kirilov@arm.com>
Date: Wed, 27 Aug 2025 15:22:10 +0100
Subject: [PATCH 009/108] FROMGIT(6.18): arm64: dts: rockchip: Enable the NPU
on NanoPi R6C/R6S
Enable the NPU on FriendlyElec NanoPi R6C/R6S boards.
Signed-off-by: Anton Kirilov <anton.kirilov@arm.com>
---
.../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
index 2e9d5143476d..1b6a59f7cabc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
@@ -371,6 +371,10 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
gpio-key {
key1_pin: key1-pin {
@@ -429,6 +433,36 @@ rtl8211f_rst: rtl8211f-rst {
};
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
--
2.34.1

4432
packages/linux/patches/rockchip/rockchip-0010-FROMGIT-6.18-accel-rocket-Add-registers-header.patch Normal file
View File

File diff suppressed because it is too large Load Diff

722
packages/linux/patches/rockchip/rockchip-0011-FROMGIT-6.18-accel-rocket-Add-a-new-driver-for-Rockc.patch Normal file
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@@ -0,0 +1,722 @@
From c588f2f877ff0081119607f5fbfca3b130d6af66 Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:29 +0200
Subject: [PATCH 011/108] FROMGIT(6.18): accel/rocket: Add a new driver for
Rockchip's NPU
This initial version supports the NPU as shipped in the RK3588 SoC and
described in the first part of its TRM, in Chapter 36.
This NPU contains 3 independent cores that the driver can submit jobs
to.
This commit adds just hardware initialization and power management.
Reviewed-by: Robert Foss <rfoss@kernel.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
Documentation/accel/index.rst | 1 +
Documentation/accel/rocket/index.rst | 19 ++
MAINTAINERS | 10 +
drivers/accel/Kconfig | 1 +
drivers/accel/Makefile | 1 +
drivers/accel/rocket/Kconfig | 24 +++
drivers/accel/rocket/Makefile | 8 +
drivers/accel/rocket/rocket_core.c | 100 ++++++++++
drivers/accel/rocket/rocket_core.h | 49 +++++
drivers/accel/rocket/rocket_device.c | 56 ++++++
drivers/accel/rocket/rocket_device.h | 28 +++
drivers/accel/rocket/rocket_drv.c | 261 +++++++++++++++++++++++++++
drivers/accel/rocket/rocket_drv.h | 23 +++
13 files changed, 581 insertions(+)
create mode 100644 Documentation/accel/rocket/index.rst
create mode 100644 drivers/accel/rocket/Kconfig
create mode 100644 drivers/accel/rocket/Makefile
create mode 100644 drivers/accel/rocket/rocket_core.c
create mode 100644 drivers/accel/rocket/rocket_core.h
create mode 100644 drivers/accel/rocket/rocket_device.c
create mode 100644 drivers/accel/rocket/rocket_device.h
create mode 100644 drivers/accel/rocket/rocket_drv.c
create mode 100644 drivers/accel/rocket/rocket_drv.h
diff --git a/Documentation/accel/index.rst b/Documentation/accel/index.rst
index bc85f26533d8..d8fa332d60a8 100644
--- a/Documentation/accel/index.rst
+++ b/Documentation/accel/index.rst
@@ -10,6 +10,7 @@ Compute Accelerators
introduction
amdxdna/index
qaic/index
+ rocket/index
.. only:: subproject and html
diff --git a/Documentation/accel/rocket/index.rst b/Documentation/accel/rocket/index.rst
new file mode 100644
index 000000000000..70f97bccf100
--- /dev/null
+++ b/Documentation/accel/rocket/index.rst
@@ -0,0 +1,19 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+
+=====================================
+ accel/rocket Rockchip NPU driver
+=====================================
+
+The accel/rocket driver supports the Neural Processing Units (NPUs) inside some
+Rockchip SoCs such as the RK3588. Rockchip calls it RKNN and sometimes RKNPU.
+
+The hardware is described in chapter 36 in the RK3588 TRM.
+
+This driver just powers the hardware on and off, allocates and maps buffers to
+the device and submits jobs to the frontend unit. Everything else is done in
+userspace, as a Gallium driver (also called rocket) that is part of the Mesa3D
+project.
+
+Hardware currently supported:
+
+* RK3588
diff --git a/MAINTAINERS b/MAINTAINERS
index cd7ff55b5d32..a19231134b01 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7499,6 +7499,16 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/accel/ivpu/
F: include/uapi/drm/ivpu_accel.h
+DRM ACCEL DRIVER FOR ROCKCHIP NPU
+M: Tomeu Vizoso <tomeu@tomeuvizoso.net>
+L: dri-devel@lists.freedesktop.org
+S: Supported
+T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F: Documentation/accel/rocket/
+F: Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
+F: drivers/accel/rocket/
+F: include/uapi/drm/rocket_accel.h
+
DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
M: Oded Gabbay <ogabbay@kernel.org>
L: dri-devel@lists.freedesktop.org
diff --git a/drivers/accel/Kconfig b/drivers/accel/Kconfig
index 5b9490367a39..bb01cebc42bf 100644
--- a/drivers/accel/Kconfig
+++ b/drivers/accel/Kconfig
@@ -28,5 +28,6 @@ source "drivers/accel/amdxdna/Kconfig"
source "drivers/accel/habanalabs/Kconfig"
source "drivers/accel/ivpu/Kconfig"
source "drivers/accel/qaic/Kconfig"
+source "drivers/accel/rocket/Kconfig"
endif
diff --git a/drivers/accel/Makefile b/drivers/accel/Makefile
index a301fb6089d4..ffc3fa588666 100644
--- a/drivers/accel/Makefile
+++ b/drivers/accel/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_ACCEL_AMDXDNA) += amdxdna/
obj-$(CONFIG_DRM_ACCEL_HABANALABS) += habanalabs/
obj-$(CONFIG_DRM_ACCEL_IVPU) += ivpu/
obj-$(CONFIG_DRM_ACCEL_QAIC) += qaic/
+obj-$(CONFIG_DRM_ACCEL_ROCKET) += rocket/
\ No newline at end of file
diff --git a/drivers/accel/rocket/Kconfig b/drivers/accel/rocket/Kconfig
new file mode 100644
index 000000000000..43d6cd98ec8e
--- /dev/null
+++ b/drivers/accel/rocket/Kconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_ACCEL_ROCKET
+ tristate "Rocket (support for Rockchip NPUs)"
+ depends on DRM
+ depends on (ARCH_ROCKCHIP && ARM64) || COMPILE_TEST
+ depends on ROCKCHIP_IOMMU || COMPILE_TEST
+ depends on MMU
+ select DRM_SCHED
+ select DRM_GEM_SHMEM_HELPER
+ help
+ Choose this option if you have a Rockchip SoC that contains a
+ compatible Neural Processing Unit (NPU), such as the RK3588. Called by
+ Rockchip either RKNN or RKNPU, it accelerates inference of neural
+ networks.
+
+ The interface exposed to userspace is described in
+ include/uapi/drm/rocket_accel.h and is used by the Rocket userspace
+ driver in Mesa3D.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called rocket.
diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
new file mode 100644
index 000000000000..abdd75f2492e
--- /dev/null
+++ b/drivers/accel/rocket/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_DRM_ACCEL_ROCKET) := rocket.o
+
+rocket-y := \
+ rocket_core.o \
+ rocket_device.o \
+ rocket_drv.o
diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
new file mode 100644
index 000000000000..9be964b5fbae
--- /dev/null
+++ b/drivers/accel/rocket/rocket_core.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dev_printk.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "rocket_core.h"
+
+int rocket_core_init(struct rocket_core *core)
+{
+ struct device *dev = core->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ u32 version;
+ int err = 0;
+
+ core->resets[0].id = "srst_a";
+ core->resets[1].id = "srst_h";
+ err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
+ core->resets);
+ if (err)
+ return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
+
+ err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
+ if (err)
+ return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
+
+ core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc");
+ if (IS_ERR(core->pc_iomem)) {
+ dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem));
+ return PTR_ERR(core->pc_iomem);
+ }
+
+ core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna");
+ if (IS_ERR(core->cna_iomem)) {
+ dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem));
+ return PTR_ERR(core->cna_iomem);
+ }
+
+ core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core");
+ if (IS_ERR(core->core_iomem)) {
+ dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem));
+ return PTR_ERR(core->core_iomem);
+ }
+
+ dma_set_max_seg_size(dev, UINT_MAX);
+
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+ if (err)
+ return err;
+
+ core->iommu_group = iommu_group_get(dev);
+
+ pm_runtime_use_autosuspend(dev);
+
+ /*
+ * As this NPU will be most often used as part of a media pipeline that
+ * ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an
+ * autosuspend delay as that will keep the device powered up while the
+ * pipeline is running.
+ */
+ pm_runtime_set_autosuspend_delay(dev, 50);
+
+ pm_runtime_enable(dev);
+
+ err = pm_runtime_get_sync(dev);
+
+ version = rocket_pc_readl(core, VERSION);
+ version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
+
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
+
+ return 0;
+}
+
+void rocket_core_fini(struct rocket_core *core)
+{
+ pm_runtime_dont_use_autosuspend(core->dev);
+ pm_runtime_disable(core->dev);
+ iommu_group_put(core->iommu_group);
+ core->iommu_group = NULL;
+}
+
+void rocket_core_reset(struct rocket_core *core)
+{
+ reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
+
+ udelay(10);
+
+ reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
+}
diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
new file mode 100644
index 000000000000..660de2d70f7d
--- /dev/null
+++ b/drivers/accel/rocket/rocket_core.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_CORE_H__
+#define __ROCKET_CORE_H__
+
+#include <drm/gpu_scheduler.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mutex_types.h>
+#include <linux/reset.h>
+
+#include "rocket_registers.h"
+
+#define rocket_pc_readl(core, reg) \
+ readl((core)->pc_iomem + (REG_PC_##reg))
+#define rocket_pc_writel(core, reg, value) \
+ writel(value, (core)->pc_iomem + (REG_PC_##reg))
+
+#define rocket_cna_readl(core, reg) \
+ readl((core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
+#define rocket_cna_writel(core, reg, value) \
+ writel(value, (core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
+
+#define rocket_core_readl(core, reg) \
+ readl((core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
+#define rocket_core_writel(core, reg, value) \
+ writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
+
+struct rocket_core {
+ struct device *dev;
+ struct rocket_device *rdev;
+ unsigned int index;
+
+ int irq;
+ void __iomem *pc_iomem;
+ void __iomem *cna_iomem;
+ void __iomem *core_iomem;
+ struct clk_bulk_data clks[4];
+ struct reset_control_bulk_data resets[2];
+
+ struct iommu_group *iommu_group;
+};
+
+int rocket_core_init(struct rocket_core *core);
+void rocket_core_fini(struct rocket_core *core);
+void rocket_core_reset(struct rocket_core *core);
+
+#endif
diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
new file mode 100644
index 000000000000..b05a0df91d48
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_drv.h>
+#include <linux/array_size.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+
+#include "rocket_device.h"
+
+struct rocket_device *rocket_device_init(struct platform_device *pdev,
+ const struct drm_driver *rocket_drm_driver)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *core_node;
+ struct rocket_device *rdev;
+ struct drm_device *ddev;
+ unsigned int num_cores = 0;
+ int err;
+
+ rdev = devm_drm_dev_alloc(dev, rocket_drm_driver, struct rocket_device, ddev);
+ if (IS_ERR(rdev))
+ return rdev;
+
+ ddev = &rdev->ddev;
+ dev_set_drvdata(dev, rdev);
+
+ for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
+ if (of_device_is_available(core_node))
+ num_cores++;
+
+ rdev->cores = devm_kcalloc(dev, num_cores, sizeof(*rdev->cores), GFP_KERNEL);
+ if (!rdev->cores)
+ return ERR_PTR(-ENOMEM);
+
+ dma_set_max_seg_size(dev, UINT_MAX);
+
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+ if (err)
+ return ERR_PTR(err);
+
+ err = drm_dev_register(ddev, 0);
+ if (err)
+ return ERR_PTR(err);
+
+ return rdev;
+}
+
+void rocket_device_fini(struct rocket_device *rdev)
+{
+ WARN_ON(rdev->num_cores > 0);
+
+ drm_dev_unregister(&rdev->ddev);
+}
diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h
new file mode 100644
index 000000000000..a5a5857bb199
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_DEVICE_H__
+#define __ROCKET_DEVICE_H__
+
+#include <drm/drm_device.h>
+#include <linux/clk.h>
+#include <linux/container_of.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+
+#include "rocket_core.h"
+
+struct rocket_device {
+ struct drm_device ddev;
+
+ struct rocket_core *cores;
+ unsigned int num_cores;
+};
+
+struct rocket_device *rocket_device_init(struct platform_device *pdev,
+ const struct drm_driver *rocket_drm_driver);
+void rocket_device_fini(struct rocket_device *rdev);
+#define to_rocket_device(drm_dev) \
+ ((struct rocket_device *)(container_of((drm_dev), struct rocket_device, ddev)))
+
+#endif /* __ROCKET_DEVICE_H__ */
diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
new file mode 100644
index 000000000000..a5df94f6b125
--- /dev/null
+++ b/drivers/accel/rocket/rocket_drv.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_ioctl.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/iommu.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "rocket_drv.h"
+
+/*
+ * Facade device, used to expose a single DRM device to userspace, that
+ * schedules jobs to any RKNN cores in the system.
+ */
+static struct platform_device *drm_dev;
+static struct rocket_device *rdev;
+
+static void
+rocket_iommu_domain_destroy(struct kref *kref)
+{
+ struct rocket_iommu_domain *domain = container_of(kref, struct rocket_iommu_domain, kref);
+
+ iommu_domain_free(domain->domain);
+ domain->domain = NULL;
+ kfree(domain);
+}
+
+static struct rocket_iommu_domain*
+rocket_iommu_domain_create(struct device *dev)
+{
+ struct rocket_iommu_domain *domain = kmalloc(sizeof(*domain), GFP_KERNEL);
+ void *err;
+
+ if (!domain)
+ return ERR_PTR(-ENOMEM);
+
+ domain->domain = iommu_paging_domain_alloc(dev);
+ if (IS_ERR(domain->domain)) {
+ err = ERR_CAST(domain->domain);
+ kfree(domain);
+ return err;
+ }
+ kref_init(&domain->kref);
+
+ return domain;
+}
+
+struct rocket_iommu_domain *
+rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv)
+{
+ kref_get(&rocket_priv->domain->kref);
+ return rocket_priv->domain;
+}
+
+void
+rocket_iommu_domain_put(struct rocket_iommu_domain *domain)
+{
+ kref_put(&domain->kref, rocket_iommu_domain_destroy);
+}
+
+static int
+rocket_open(struct drm_device *dev, struct drm_file *file)
+{
+ struct rocket_device *rdev = to_rocket_device(dev);
+ struct rocket_file_priv *rocket_priv;
+ int ret;
+
+ if (!try_module_get(THIS_MODULE))
+ return -EINVAL;
+
+ rocket_priv = kzalloc(sizeof(*rocket_priv), GFP_KERNEL);
+ if (!rocket_priv) {
+ ret = -ENOMEM;
+ goto err_put_mod;
+ }
+
+ rocket_priv->rdev = rdev;
+ rocket_priv->domain = rocket_iommu_domain_create(rdev->cores[0].dev);
+ if (IS_ERR(rocket_priv->domain)) {
+ ret = PTR_ERR(rocket_priv->domain);
+ goto err_free;
+ }
+
+ file->driver_priv = rocket_priv;
+
+ return 0;
+
+err_free:
+ kfree(rocket_priv);
+err_put_mod:
+ module_put(THIS_MODULE);
+ return ret;
+}
+
+static void
+rocket_postclose(struct drm_device *dev, struct drm_file *file)
+{
+ struct rocket_file_priv *rocket_priv = file->driver_priv;
+
+ rocket_iommu_domain_put(rocket_priv->domain);
+ kfree(rocket_priv);
+ module_put(THIS_MODULE);
+}
+
+static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
+#define ROCKET_IOCTL(n, func) \
+ DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
+};
+
+DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
+
+/*
+ * Rocket driver version:
+ * - 1.0 - initial interface
+ */
+static const struct drm_driver rocket_drm_driver = {
+ .driver_features = DRIVER_COMPUTE_ACCEL,
+ .open = rocket_open,
+ .postclose = rocket_postclose,
+ .ioctls = rocket_drm_driver_ioctls,
+ .num_ioctls = ARRAY_SIZE(rocket_drm_driver_ioctls),
+ .fops = &rocket_accel_driver_fops,
+ .name = "rocket",
+ .desc = "rocket DRM",
+};
+
+static int rocket_probe(struct platform_device *pdev)
+{
+ if (rdev == NULL) {
+ /* First core probing, initialize DRM device. */
+ rdev = rocket_device_init(drm_dev, &rocket_drm_driver);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to initialize rocket device\n");
+ return PTR_ERR(rdev);
+ }
+ }
+
+ unsigned int core = rdev->num_cores;
+
+ dev_set_drvdata(&pdev->dev, rdev);
+
+ rdev->cores[core].rdev = rdev;
+ rdev->cores[core].dev = &pdev->dev;
+ rdev->cores[core].index = core;
+
+ rdev->num_cores++;
+
+ return rocket_core_init(&rdev->cores[core]);
+}
+
+static void rocket_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ for (unsigned int core = 0; core < rdev->num_cores; core++) {
+ if (rdev->cores[core].dev == dev) {
+ rocket_core_fini(&rdev->cores[core]);
+ rdev->num_cores--;
+ break;
+ }
+ }
+
+ if (rdev->num_cores == 0) {
+ /* Last core removed, deinitialize DRM device. */
+ rocket_device_fini(rdev);
+ rdev = NULL;
+ }
+}
+
+static const struct of_device_id dt_match[] = {
+ { .compatible = "rockchip,rk3588-rknn-core" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
+static int find_core_for_dev(struct device *dev)
+{
+ struct rocket_device *rdev = dev_get_drvdata(dev);
+
+ for (unsigned int core = 0; core < rdev->num_cores; core++) {
+ if (dev == rdev->cores[core].dev)
+ return core;
+ }
+
+ return -1;
+}
+
+static int rocket_device_runtime_resume(struct device *dev)
+{
+ struct rocket_device *rdev = dev_get_drvdata(dev);
+ int core = find_core_for_dev(dev);
+ int err = 0;
+
+ if (core < 0)
+ return -ENODEV;
+
+ err = clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
+ if (err) {
+ dev_err(dev, "failed to enable (%d) clocks for core %d\n", err, core);
+ return err;
+ }
+
+ return 0;
+}
+
+static int rocket_device_runtime_suspend(struct device *dev)
+{
+ struct rocket_device *rdev = dev_get_drvdata(dev);
+ int core = find_core_for_dev(dev);
+
+ if (core < 0)
+ return -ENODEV;
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
+
+ return 0;
+}
+
+EXPORT_GPL_DEV_PM_OPS(rocket_pm_ops) = {
+ RUNTIME_PM_OPS(rocket_device_runtime_suspend, rocket_device_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
+static struct platform_driver rocket_driver = {
+ .probe = rocket_probe,
+ .remove = rocket_remove,
+ .driver = {
+ .name = "rocket",
+ .pm = pm_ptr(&rocket_pm_ops),
+ .of_match_table = dt_match,
+ },
+};
+
+static int __init rocket_register(void)
+{
+ drm_dev = platform_device_register_simple("rknn", -1, NULL, 0);
+ if (IS_ERR(drm_dev))
+ return PTR_ERR(drm_dev);
+
+ return platform_driver_register(&rocket_driver);
+}
+
+static void __exit rocket_unregister(void)
+{
+ platform_driver_unregister(&rocket_driver);
+
+ platform_device_unregister(drm_dev);
+}
+
+module_init(rocket_register);
+module_exit(rocket_unregister);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DRM driver for the Rockchip NPU IP");
+MODULE_AUTHOR("Tomeu Vizoso");
diff --git a/drivers/accel/rocket/rocket_drv.h b/drivers/accel/rocket/rocket_drv.h
new file mode 100644
index 000000000000..36b1291b0ead
--- /dev/null
+++ b/drivers/accel/rocket/rocket_drv.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_DRV_H__
+#define __ROCKET_DRV_H__
+
+#include "rocket_device.h"
+
+struct rocket_iommu_domain {
+ struct iommu_domain *domain;
+ struct kref kref;
+};
+
+struct rocket_file_priv {
+ struct rocket_device *rdev;
+
+ struct rocket_iommu_domain *domain;
+};
+
+struct rocket_iommu_domain *rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv);
+void rocket_iommu_domain_put(struct rocket_iommu_domain *domain);
+
+#endif
--
2.34.1

347
packages/linux/patches/rockchip/rockchip-0012-FROMGIT-6.18-accel-rocket-Add-IOCTL-for-BO-creation.patch Normal file
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@@ -0,0 +1,347 @@
From 020bd1d28e4774d8beccc90bbfdad391d535cedc Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:30 +0200
Subject: [PATCH 012/108] FROMGIT(6.18): accel/rocket: Add IOCTL for BO
creation
This uses the SHMEM DRM helpers and we map right away to the CPU and NPU
sides, as all buffers are expected to be accessed from both.
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
drivers/accel/rocket/Makefile | 3 +-
drivers/accel/rocket/rocket_drv.c | 15 +++-
drivers/accel/rocket/rocket_drv.h | 4 +
drivers/accel/rocket/rocket_gem.c | 125 ++++++++++++++++++++++++++++++
drivers/accel/rocket/rocket_gem.h | 30 +++++++
include/uapi/drm/rocket_accel.h | 44 +++++++++++
6 files changed, 219 insertions(+), 2 deletions(-)
create mode 100644 drivers/accel/rocket/rocket_gem.c
create mode 100644 drivers/accel/rocket/rocket_gem.h
create mode 100644 include/uapi/drm/rocket_accel.h
diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
index abdd75f2492e..4deef267f9e1 100644
--- a/drivers/accel/rocket/Makefile
+++ b/drivers/accel/rocket/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_DRM_ACCEL_ROCKET) := rocket.o
rocket-y := \
rocket_core.o \
rocket_device.o \
- rocket_drv.o
+ rocket_drv.o \
+ rocket_gem.o
diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
index a5df94f6b125..8b7fbe9226f4 100644
--- a/drivers/accel/rocket/rocket_drv.c
+++ b/drivers/accel/rocket/rocket_drv.c
@@ -5,6 +5,7 @@
#include <drm/drm_drv.h>
#include <drm/drm_gem.h>
#include <drm/drm_ioctl.h>
+#include <drm/rocket_accel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/iommu.h>
@@ -13,6 +14,7 @@
#include <linux/pm_runtime.h>
#include "rocket_drv.h"
+#include "rocket_gem.h"
/*
* Facade device, used to expose a single DRM device to userspace, that
@@ -69,6 +71,7 @@ rocket_open(struct drm_device *dev, struct drm_file *file)
{
struct rocket_device *rdev = to_rocket_device(dev);
struct rocket_file_priv *rocket_priv;
+ u64 start, end;
int ret;
if (!try_module_get(THIS_MODULE))
@@ -89,6 +92,11 @@ rocket_open(struct drm_device *dev, struct drm_file *file)
file->driver_priv = rocket_priv;
+ start = rocket_priv->domain->domain->geometry.aperture_start;
+ end = rocket_priv->domain->domain->geometry.aperture_end;
+ drm_mm_init(&rocket_priv->mm, start, end - start + 1);
+ mutex_init(&rocket_priv->mm_lock);
+
return 0;
err_free:
@@ -103,6 +111,8 @@ rocket_postclose(struct drm_device *dev, struct drm_file *file)
{
struct rocket_file_priv *rocket_priv = file->driver_priv;
+ mutex_destroy(&rocket_priv->mm_lock);
+ drm_mm_takedown(&rocket_priv->mm);
rocket_iommu_domain_put(rocket_priv->domain);
kfree(rocket_priv);
module_put(THIS_MODULE);
@@ -111,6 +121,8 @@ rocket_postclose(struct drm_device *dev, struct drm_file *file)
static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
#define ROCKET_IOCTL(n, func) \
DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
+
+ ROCKET_IOCTL(CREATE_BO, create_bo),
};
DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
@@ -120,9 +132,10 @@ DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
* - 1.0 - initial interface
*/
static const struct drm_driver rocket_drm_driver = {
- .driver_features = DRIVER_COMPUTE_ACCEL,
+ .driver_features = DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
.open = rocket_open,
.postclose = rocket_postclose,
+ .gem_create_object = rocket_gem_create_object,
.ioctls = rocket_drm_driver_ioctls,
.num_ioctls = ARRAY_SIZE(rocket_drm_driver_ioctls),
.fops = &rocket_accel_driver_fops,
diff --git a/drivers/accel/rocket/rocket_drv.h b/drivers/accel/rocket/rocket_drv.h
index 36b1291b0ead..2944e0136ab9 100644
--- a/drivers/accel/rocket/rocket_drv.h
+++ b/drivers/accel/rocket/rocket_drv.h
@@ -4,6 +4,8 @@
#ifndef __ROCKET_DRV_H__
#define __ROCKET_DRV_H__
+#include <drm/drm_mm.h>
+
#include "rocket_device.h"
struct rocket_iommu_domain {
@@ -15,6 +17,8 @@ struct rocket_file_priv {
struct rocket_device *rdev;
struct rocket_iommu_domain *domain;
+ struct drm_mm mm;
+ struct mutex mm_lock;
};
struct rocket_iommu_domain *rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv);
diff --git a/drivers/accel/rocket/rocket_gem.c b/drivers/accel/rocket/rocket_gem.c
new file mode 100644
index 000000000000..05cf46040865
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_device.h>
+#include <drm/drm_utils.h>
+#include <drm/rocket_accel.h>
+#include <linux/dma-mapping.h>
+#include <linux/iommu.h>
+
+#include "rocket_drv.h"
+#include "rocket_gem.h"
+
+static void rocket_gem_bo_free(struct drm_gem_object *obj)
+{
+ struct rocket_gem_object *bo = to_rocket_bo(obj);
+ struct rocket_file_priv *rocket_priv = bo->driver_priv;
+ size_t unmapped;
+
+ drm_WARN_ON(obj->dev, refcount_read(&bo->base.pages_use_count) > 1);
+
+ unmapped = iommu_unmap(bo->domain->domain, bo->mm.start, bo->size);
+ drm_WARN_ON(obj->dev, unmapped != bo->size);
+
+ mutex_lock(&rocket_priv->mm_lock);
+ drm_mm_remove_node(&bo->mm);
+ mutex_unlock(&rocket_priv->mm_lock);
+
+ rocket_iommu_domain_put(bo->domain);
+ bo->domain = NULL;
+
+ drm_gem_shmem_free(&bo->base);
+}
+
+static const struct drm_gem_object_funcs rocket_gem_funcs = {
+ .free = rocket_gem_bo_free,
+ .print_info = drm_gem_shmem_object_print_info,
+ .pin = drm_gem_shmem_object_pin,
+ .unpin = drm_gem_shmem_object_unpin,
+ .get_sg_table = drm_gem_shmem_object_get_sg_table,
+ .vmap = drm_gem_shmem_object_vmap,
+ .vunmap = drm_gem_shmem_object_vunmap,
+ .mmap = drm_gem_shmem_object_mmap,
+ .vm_ops = &drm_gem_shmem_vm_ops,
+};
+
+struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size)
+{
+ struct rocket_gem_object *obj;
+
+ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+ if (!obj)
+ return ERR_PTR(-ENOMEM);
+
+ obj->base.base.funcs = &rocket_gem_funcs;
+
+ return &obj->base.base;
+}
+
+int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct rocket_file_priv *rocket_priv = file->driver_priv;
+ struct drm_rocket_create_bo *args = data;
+ struct drm_gem_shmem_object *shmem_obj;
+ struct rocket_gem_object *rkt_obj;
+ struct drm_gem_object *gem_obj;
+ struct sg_table *sgt;
+ int ret;
+
+ shmem_obj = drm_gem_shmem_create(dev, args->size);
+ if (IS_ERR(shmem_obj))
+ return PTR_ERR(shmem_obj);
+
+ gem_obj = &shmem_obj->base;
+ rkt_obj = to_rocket_bo(gem_obj);
+
+ rkt_obj->driver_priv = rocket_priv;
+ rkt_obj->domain = rocket_iommu_domain_get(rocket_priv);
+ rkt_obj->size = args->size;
+ rkt_obj->offset = 0;
+
+ ret = drm_gem_handle_create(file, gem_obj, &args->handle);
+ drm_gem_object_put(gem_obj);
+ if (ret)
+ goto err;
+
+ sgt = drm_gem_shmem_get_pages_sgt(shmem_obj);
+ if (IS_ERR(sgt)) {
+ ret = PTR_ERR(sgt);
+ goto err;
+ }
+
+ mutex_lock(&rocket_priv->mm_lock);
+ ret = drm_mm_insert_node_generic(&rocket_priv->mm, &rkt_obj->mm,
+ rkt_obj->size, PAGE_SIZE,
+ 0, 0);
+ mutex_unlock(&rocket_priv->mm_lock);
+
+ ret = iommu_map_sgtable(rocket_priv->domain->domain,
+ rkt_obj->mm.start,
+ shmem_obj->sgt,
+ IOMMU_READ | IOMMU_WRITE);
+ if (ret < 0 || ret < args->size) {
+ drm_err(dev, "failed to map buffer: size=%d request_size=%u\n",
+ ret, args->size);
+ ret = -ENOMEM;
+ goto err_remove_node;
+ }
+
+ /* iommu_map_sgtable might have aligned the size */
+ rkt_obj->size = ret;
+ args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
+ args->dma_address = rkt_obj->mm.start;
+
+ return 0;
+
+err_remove_node:
+ mutex_lock(&rocket_priv->mm_lock);
+ drm_mm_remove_node(&rkt_obj->mm);
+ mutex_unlock(&rocket_priv->mm_lock);
+
+err:
+ drm_gem_shmem_object_free(gem_obj);
+
+ return ret;
+}
diff --git a/drivers/accel/rocket/rocket_gem.h b/drivers/accel/rocket/rocket_gem.h
new file mode 100644
index 000000000000..91a1fc09c56c
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_GEM_H__
+#define __ROCKET_GEM_H__
+
+#include <drm/drm_gem_shmem_helper.h>
+
+struct rocket_gem_object {
+ struct drm_gem_shmem_object base;
+
+ struct rocket_file_priv *driver_priv;
+
+ struct rocket_iommu_domain *domain;
+ struct drm_mm_node mm;
+ size_t size;
+ u32 offset;
+};
+
+struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size);
+
+int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
+static inline
+struct rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
+{
+ return container_of(to_drm_gem_shmem_obj(obj), struct rocket_gem_object, base);
+}
+
+#endif
diff --git a/include/uapi/drm/rocket_accel.h b/include/uapi/drm/rocket_accel.h
new file mode 100644
index 000000000000..95720702b7c4
--- /dev/null
+++ b/include/uapi/drm/rocket_accel.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Tomeu Vizoso
+ */
+#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
+#define __DRM_UAPI_ROCKET_ACCEL_H__
+
+#include "drm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define DRM_ROCKET_CREATE_BO 0x00
+
+#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
+
+/**
+ * struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
+ *
+ */
+struct drm_rocket_create_bo {
+ /** Input: Size of the requested BO. */
+ __u32 size;
+
+ /** Output: GEM handle for the BO. */
+ __u32 handle;
+
+ /**
+ * Output: DMA address for the BO in the NPU address space. This address
+ * is private to the DRM fd and is valid for the lifetime of the GEM
+ * handle.
+ */
+ __u64 dma_address;
+
+ /** Output: Offset into the drm node to use for subsequent mmap call. */
+ __u64 offset;
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */
--
2.34.1

1001
packages/linux/patches/rockchip/rockchip-0013-FROMGIT-6.18-accel-rocket-Add-job-submission-IOCTL.patch Normal file
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File diff suppressed because it is too large Load Diff

175
packages/linux/patches/rockchip/rockchip-0014-FROMGIT-6.18-accel-rocket-Add-IOCTLs-for-synchronizi.patch Normal file
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@@ -0,0 +1,175 @@
From 2be26c65a61588e349d57fa84461aa7d0e9ce96e Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:32 +0200
Subject: [PATCH 014/108] FROMGIT(6.18): accel/rocket: Add IOCTLs for
synchronizing memory accesses
The NPU cores have their own access to the memory bus, and this isn't
cache coherent with the CPUs.
Add IOCTLs so userspace can mark when the caches need to be flushed, and
also when a writer job needs to be waited for before the buffer can be
accessed from the CPU.
Initially based on the same IOCTLs from the Etnaviv driver.
Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
drivers/accel/rocket/rocket_drv.c | 2 ++
drivers/accel/rocket/rocket_gem.c | 56 +++++++++++++++++++++++++++++++
drivers/accel/rocket/rocket_gem.h | 4 +++
include/uapi/drm/rocket_accel.h | 34 +++++++++++++++++++
4 files changed, 96 insertions(+)
diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
index a21aa9aa189b..5c0b63f0a8f0 100644
--- a/drivers/accel/rocket/rocket_drv.c
+++ b/drivers/accel/rocket/rocket_drv.c
@@ -134,6 +134,8 @@ static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
ROCKET_IOCTL(CREATE_BO, create_bo),
ROCKET_IOCTL(SUBMIT, submit),
+ ROCKET_IOCTL(PREP_BO, prep_bo),
+ ROCKET_IOCTL(FINI_BO, fini_bo),
};
DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
diff --git a/drivers/accel/rocket/rocket_gem.c b/drivers/accel/rocket/rocket_gem.c
index 05cf46040865..0551e11cc184 100644
--- a/drivers/accel/rocket/rocket_gem.c
+++ b/drivers/accel/rocket/rocket_gem.c
@@ -123,3 +123,59 @@ int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *
return ret;
}
+
+int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_rocket_prep_bo *args = data;
+ unsigned long timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
+ struct drm_gem_object *gem_obj;
+ struct drm_gem_shmem_object *shmem_obj;
+ long ret = 0;
+
+ if (args->reserved != 0) {
+ drm_dbg(dev, "Reserved field in drm_rocket_prep_bo struct should be 0.\n");
+ return -EINVAL;
+ }
+
+ gem_obj = drm_gem_object_lookup(file, args->handle);
+ if (!gem_obj)
+ return -ENOENT;
+
+ ret = dma_resv_wait_timeout(gem_obj->resv, DMA_RESV_USAGE_WRITE, true, timeout);
+ if (!ret)
+ ret = timeout ? -ETIMEDOUT : -EBUSY;
+
+ shmem_obj = &to_rocket_bo(gem_obj)->base;
+
+ dma_sync_sgtable_for_cpu(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
+
+ drm_gem_object_put(gem_obj);
+
+ return ret;
+}
+
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_rocket_fini_bo *args = data;
+ struct drm_gem_shmem_object *shmem_obj;
+ struct rocket_gem_object *rkt_obj;
+ struct drm_gem_object *gem_obj;
+
+ if (args->reserved != 0) {
+ drm_dbg(dev, "Reserved field in drm_rocket_fini_bo struct should be 0.\n");
+ return -EINVAL;
+ }
+
+ gem_obj = drm_gem_object_lookup(file, args->handle);
+ if (!gem_obj)
+ return -ENOENT;
+
+ rkt_obj = to_rocket_bo(gem_obj);
+ shmem_obj = &rkt_obj->base;
+
+ dma_sync_sgtable_for_device(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
+
+ drm_gem_object_put(gem_obj);
+
+ return 0;
+}
diff --git a/drivers/accel/rocket/rocket_gem.h b/drivers/accel/rocket/rocket_gem.h
index 91a1fc09c56c..240430334509 100644
--- a/drivers/accel/rocket/rocket_gem.h
+++ b/drivers/accel/rocket/rocket_gem.h
@@ -21,6 +21,10 @@ struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t s
int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
+int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
static inline
struct rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
{
diff --git a/include/uapi/drm/rocket_accel.h b/include/uapi/drm/rocket_accel.h
index 374f8370ac9d..14b2e12b7c49 100644
--- a/include/uapi/drm/rocket_accel.h
+++ b/include/uapi/drm/rocket_accel.h
@@ -13,9 +13,13 @@ extern "C" {
#define DRM_ROCKET_CREATE_BO 0x00
#define DRM_ROCKET_SUBMIT 0x01
+#define DRM_ROCKET_PREP_BO 0x02
+#define DRM_ROCKET_FINI_BO 0x03
#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
+#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
+#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
/**
* struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
@@ -39,6 +43,36 @@ struct drm_rocket_create_bo {
__u64 offset;
};
+/**
+ * struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
+ *
+ * Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
+ * synchronization.
+ */
+struct drm_rocket_prep_bo {
+ /** Input: GEM handle of the buffer object. */
+ __u32 handle;
+
+ /** Reserved, must be zero. */
+ __u32 reserved;
+
+ /** Input: Amount of time to wait for NPU jobs. */
+ __s64 timeout_ns;
+};
+
+/**
+ * struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
+ *
+ * Synchronize caches for NPU access.
+ */
+struct drm_rocket_fini_bo {
+ /** Input: GEM handle of the buffer object. */
+ __u32 handle;
+
+ /** Reserved, must be zero. */
+ __u32 reserved;
+};
+
/**
* struct drm_rocket_task - A task to be run on the NPU
*
--
2.34.1

139
packages/linux/patches/rockchip/rockchip-0015-FROMGIT-6.18-dt-bindings-npu-rockchip-rknn-Add-bindi.patch Normal file
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@@ -0,0 +1,139 @@
From 2a4747ba6fab4596a99366cea799aa992e262ce6 Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:33 +0200
Subject: [PATCH 015/108] FROMGIT(6.18): dt-bindings: npu: rockchip,rknn: Add
bindings
Add the bindings for the Neural Processing Unit IP from Rockchip.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../npu/rockchip,rk3588-rknn-core.yaml | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
new file mode 100644
index 000000000000..caca2a4903cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Neural Processing Unit IP from Rockchip
+
+maintainers:
+ - Tomeu Vizoso <tomeu@tomeuvizoso.net>
+
+description:
+ Rockchip IP for accelerating inference of neural networks.
+
+ There is to be a node per each NPU core in the SoC, and each core should reference all the
+ resources that it needs to function, such as clocks, power domains, and resets.
+
+properties:
+ $nodename:
+ pattern: '^npu@[a-f0-9]+$'
+
+ compatible:
+ enum:
+ - rockchip,rk3588-rknn-core
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: pc # Program Control-related registers
+ - const: cna # Convolution Neural Network Accelerator registers
+ - const: core # Main NPU core processing unit registers
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: hclk
+ - const: npu
+ - const: pclk
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ npu-supply: true
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: srst_a
+ - const: srst_h
+
+ sram-supply: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - iommus
+ - power-domains
+ - resets
+ - reset-names
+ - npu-supply
+ - sram-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ npu@fdab0000 {
+ compatible = "rockchip,rk3588-rknn-core";
+ reg = <0x0 0xfdab0000 0x0 0x1000>,
+ <0x0 0xfdab1000 0x0 0x1000>,
+ <0x0 0xfdab3000 0x0 0x1000>;
+ reg-names = "pc", "cna", "core";
+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&rknn_mmu_0>;
+ npu-supply = <&vdd_npu_s0>;
+ power-domains = <&power RK3588_PD_NPUTOP>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
+ reset-names = "srst_a", "srst_h";
+ sram-supply = <&vdd_npu_mem_s0>;
+ };
+ };
+...
--
2.34.1

35
packages/linux/patches/rockchip/rockchip-0016-FROMGIT-6.18-arm64-dts-rockchip-add-pd_npu-label-for.patch Normal file
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@@ -0,0 +1,35 @@
From 960534f564d80801fead4231c1e528e8e437ed87 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Mon, 21 Jul 2025 11:17:34 +0200
Subject: [PATCH 016/108] FROMGIT(6.18): arm64: dts: rockchip: add pd_npu label
for RK3588 power domains
The NPU of the RK3588 has an external supply. This supply also affects
the power domain of the NPU, not just the NPU device nodes themselves.
Since correctly modelled boards will want the power domain to be aware
of the regulator so that it doesn't always have to be on, add a label to
the NPU power domain node so board files can reference it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index c1eaff86d5b7..3707aa1af785 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -841,7 +841,7 @@ power: power-controller {
status = "okay";
/* These power domains are grouped by VD_NPU */
- power-domain@RK3588_PD_NPU {
+ pd_npu: power-domain@RK3588_PD_NPU {
reg = <RK3588_PD_NPU>;
#power-domain-cells = <0>;
#address-cells = <1>;
--
2.34.1

125
packages/linux/patches/rockchip/rockchip-0017-FROMGIT-6.18-arm64-dts-rockchip-Add-nodes-for-NPU-an.patch Normal file
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@@ -0,0 +1,125 @@
From 2f38aadba79e366bfbbb4e98bdf01b2fa0b4667d Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:35 +0200
Subject: [PATCH 017/108] FROMGIT(6.18): arm64: dts: rockchip: Add nodes for
NPU and its MMU to rk3588-base
See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
The IP is divided in three cores, programmed independently. The first
core though is special, being able to delegate work to the other cores.
The IOMMU of the first core is also special in that it has two subunits
(read/write?) that need to be programmed in sync.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 3707aa1af785..56bf903eb04f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1140,6 +1140,97 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ rknn_core_0: npu@fdab0000 {
+ compatible = "rockchip,rk3588-rknn-core";
+ reg = <0x0 0xfdab0000 0x0 0x1000>,
+ <0x0 0xfdab1000 0x0 0x1000>,
+ <0x0 0xfdab3000 0x0 0x1000>;
+ reg-names = "pc", "cna", "core";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
+ reset-names = "srst_a", "srst_h";
+ power-domains = <&power RK3588_PD_NPUTOP>;
+ iommus = <&rknn_mmu_0>;
+ status = "disabled";
+ };
+
+ rknn_mmu_0: iommu@fdab9000 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdab9000 0x0 0x100>,
+ <0x0 0xfdaba000 0x0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_NPUTOP>;
+ status = "disabled";
+ };
+
+ rknn_core_1: npu@fdac0000 {
+ compatible = "rockchip,rk3588-rknn-core";
+ reg = <0x0 0xfdac0000 0x0 0x1000>,
+ <0x0 0xfdac1000 0x0 0x1000>,
+ <0x0 0xfdac3000 0x0 0x1000>;
+ reg-names = "pc", "cna", "core";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>;
+ reset-names = "srst_a", "srst_h";
+ power-domains = <&power RK3588_PD_NPU1>;
+ iommus = <&rknn_mmu_1>;
+ status = "disabled";
+ };
+
+ rknn_mmu_1: iommu@fdac9000 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdaca000 0x0 0x100>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_NPU1>;
+ status = "disabled";
+ };
+
+ rknn_core_2: npu@fdad0000 {
+ compatible = "rockchip,rk3588-rknn-core";
+ reg = <0x0 0xfdad0000 0x0 0x1000>,
+ <0x0 0xfdad1000 0x0 0x1000>,
+ <0x0 0xfdad3000 0x0 0x1000>;
+ reg-names = "pc", "cna", "core";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>;
+ reset-names = "srst_a", "srst_h";
+ power-domains = <&power RK3588_PD_NPU2>;
+ iommus = <&rknn_mmu_2>;
+ status = "disabled";
+ };
+
+ rknn_mmu_2: iommu@fdad9000 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdada000 0x0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_NPU2>;
+ status = "disabled";
+ };
+
vpu121: video-codec@fdb50000 {
compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
reg = <0x0 0xfdb50000 0x0 0x800>;
--
2.34.1

58
packages/linux/patches/rockchip/rockchip-0018-FROMGIT-6.18-arm64-dts-rockchip-Enable-the-NPU-on-qu.patch Normal file
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@@ -0,0 +1,58 @@
From 96fa1545d6e230d6253eb3f74b0eeb20b43cfa56 Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 21 Jul 2025 11:17:36 +0200
Subject: [PATCH 018/108] FROMGIT(6.18): arm64: dts: rockchip: Enable the NPU
on quartzpro64
Enable the nodes added in a previous commit to the rk3588s device tree.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
.../boot/dts/rockchip/rk3588-quartzpro64.dts | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
index 78aaa6635b5d..b2336c36da01 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
@@ -415,6 +415,36 @@ &pcie3x4 {
status = "okay";
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_1v8_s0>;
status = "okay";
--
2.34.1

104
packages/linux/patches/rockchip/rockchip-0019-FROMGIT-6.18-arm64-dts-rockchip-enable-NPU-on-ROCK-5.patch Normal file
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@@ -0,0 +1,104 @@
From 317cce80eb431cd7d4aaf4dc30b319b2b3d5ef92 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Mon, 21 Jul 2025 09:17:00 +0000
Subject: [PATCH 019/108] FROMGIT(6.18): arm64: dts: rockchip: enable NPU on
ROCK 5B/5B+/5T
The NPU on the ROCK5B uses the same regulator for both the sram-supply
and the npu's supply. Add this regulator, and enable all the NPU bits.
Also add the regulator as a domain-supply to the pd_npu power domain.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
[ relocate patch to rk3588-rock-5b-5bp-5t.dtsi ]
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index 973d39a7e0e0..612808d2b4c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -268,6 +268,29 @@ regulator-state-mem {
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m2_xfer>;
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <500>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
&i2c6 {
status = "okay";
@@ -392,6 +415,10 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
@@ -424,6 +451,36 @@ &pwm1 {
status = "okay";
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
--
2.34.1

55
packages/linux/patches/rockchip/rockchip-0020-FROMGIT-6.18-arm64-dts-rockchip-Enable-HDMI-receiver.patch Normal file
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@@ -0,0 +1,55 @@
From 29b7330ef561ae7007792b9282c05d4ca5a32cd4 Mon Sep 17 00:00:00 2001
From: Maud Spierings <maud_spierings@hotmail.com>
Date: Sat, 23 Aug 2025 14:43:51 +0200
Subject: [PATCH 020/108] FROMGIT(6.18): arm64: dts: rockchip: Enable HDMI
receiver on orangepi 5 plus
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enable support for the HDMI input port found on the orangepi 5 plus.
Signed-off-by: Maud Spierings <maud_spierings@hotmail.com>
Reviewed-by: Ondřej Jirman <megi@xff.cz>
---
.../dts/rockchip/rk3588-orangepi-5-plus.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
index 8222f1fae8fa..9950d1147e12 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
@@ -160,6 +160,17 @@ &hdmi1_sound {
status = "okay";
};
+&hdmi_receiver_cma {
+ status = "okay";
+};
+
+&hdmi_receiver {
+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&hdptxphy0 {
status = "okay";
};
@@ -279,6 +290,12 @@ blue_led_pin: blue-led {
};
};
+ hdmirx {
+ hdmirx_hpd: hdmirx-5v-detection {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
ir-receiver {
ir_receiver_pin: ir-receiver-pin {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.34.1

94
packages/linux/patches/rockchip/rockchip-0021-FROMGIT-6.18-arm64-dts-rockchip-Enable-the-NPU-on-th.patch Normal file
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@@ -0,0 +1,94 @@
From 17bad86ba250bb1a93bcc42333f0dc1bdee3ea9b Mon Sep 17 00:00:00 2001
From: Maud Spierings <maud_spierings@hotmail.com>
Date: Sat, 23 Aug 2025 14:43:52 +0200
Subject: [PATCH 021/108] FROMGIT(6.18): arm64: dts: rockchip: Enable the NPU
on the orangepi 5 boards
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enable the NPU and the PMIC that powers it.
Signed-off-by: Maud Spierings <maud_spierings@hotmail.com>
Reviewed-by: Ondřej Jirman <megi@xff.cz>
---
.../boot/dts/rockchip/rk3588-orangepi-5.dtsi | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
index 8a8f3b26754d..3bceee948458 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
@@ -258,6 +258,28 @@ regulator-state-mem {
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m2_xfer>;
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
&i2c6 {
clock-frequency = <400000>;
status = "okay";
@@ -352,6 +374,40 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_1v8_s0>;
status = "okay";
--
2.34.1

41
packages/linux/patches/rockchip/rockchip-0022-FROMGIT-6.18-arm64-dts-rockchip-rk3588s-rock-5a-Add-.patch Normal file
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@@ -0,0 +1,41 @@
From ee2f59492e51379da3fb11760c8b2d1bec7ebe48 Mon Sep 17 00:00:00 2001
From: "kylepzak@projectinitiative.io" <kylepzak@projectinitiative.io>
Date: Tue, 19 Aug 2025 21:30:12 -0500
Subject: [PATCH 022/108] FROMGIT(6.18): arm64: dts: rockchip: rk3588s-rock-5a:
Add green power LED
The Radxa ROCK 5A board includes a green power LED that is defined in
the vendor device tree but is missing from the upstream kernel DTS file.
This causes the LED to be uncontrollable from the operating system, as no
entry is created for it under /sys/class/leds.
This patch adds the missing node to the leds block, creating a
"green:power" device and allowing the LED to be controlled by the kernel.
Signed-off-by: Kyle Petryszak <kylepzak@projectinitiative.io>
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
index f894742b1ebe..f70b49d9361a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -52,6 +52,13 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&io_led>;
+ power-led {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
io-led {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
--
2.34.1

29
packages/linux/patches/rockchip/rockchip-0023-FROMGIT-6.18-arm64-dts-rockchip-Enable-RK3576-watchd.patch Normal file
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@@ -0,0 +1,29 @@
From be887c8e5e8938d694e75f8ceb3aa90f2e3aa769 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 18 Aug 2025 19:18:40 +0200
Subject: [PATCH 023/108] FROMGIT(6.18): arm64: dts: rockchip: Enable RK3576
watchdog
The RK3576 watchdog does not need any board specific resources, so
let's enable it by default just like we do for RK3588.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index b99f4bd4c9d9..552e825a96d3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2108,7 +2108,6 @@ wdt: watchdog@2ace0000 {
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
spi0: spi@2acf0000 {
--
2.34.1

59
packages/linux/patches/rockchip/rockchip-0024-FROMGIT-6.18-arm64-dts-rockchip-add-SPDIF-audio-to-B.patch Normal file
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@@ -0,0 +1,59 @@
From cfcdbeea880365e4217fede204f3516ef1869618 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 27 Feb 2021 17:52:02 +0100
Subject: [PATCH 024/108] FROMGIT(6.18): arm64: dts: rockchip: add SPDIF audio
to Beelink A1
Add the required nodes to enable SPDIF audio output on
the Beelink A1 set-top-box.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index f7c4578865c5..b276a29bdd85 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -58,6 +58,24 @@ ir-receiver {
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
linux,rc-map-name = "rc-beelink-gs1";
};
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
};
&analog_sound {
@@ -325,6 +343,11 @@ &sdmmc {
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
--
2.34.1

33
packages/linux/patches/rockchip/rockchip-0025-FROMGIT-6.18-arm64-dts-rockchip-add-USB3-on-Beelink-.patch Normal file
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@@ -0,0 +1,33 @@
From ea34273c334899f0a36894ec66eaebe1ab8ab4e3 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 21 Aug 2021 17:04:46 +0200
Subject: [PATCH 025/108] FROMGIT(6.18): arm64: dts: rockchip: add USB3 on
Beelink A1
Enable USB3 for the Beelink A1 set-top box.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index b276a29bdd85..632b0b22c52f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -381,6 +381,11 @@ &usb_host0_ehci {
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&vop {
status = "okay";
};
--
2.34.1

50
packages/linux/patches/rockchip/rockchip-0026-FROMGIT-6.18-arm64-dts-rockchip-add-IR-receiver-to-r.patch Normal file
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@@ -0,0 +1,50 @@
From 23521dedf7b946179c07ecd34eebc8d34f6f6409 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 27 Feb 2021 18:01:13 +0100
Subject: [PATCH 026/108] FROMGIT(6.18): arm64: dts: rockchip: add IR receiver
to rk3328-roc
Add the ir-receiver and ir pinctrl nodes to enable the IR receiver
on the ROC-RK3328-CC board.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
index b5bd5e7d5748..aa1d5a6d7fd5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
@@ -84,6 +84,13 @@ vcc_phy: regulator-vcc-phy {
regulator-boot-on;
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
leds {
compatible = "gpio-leds";
@@ -300,6 +307,13 @@ &io_domains {
};
&pinctrl {
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.34.1

88
packages/linux/patches/rockchip/rockchip-0027-FROMGIT-6.18-arm64-dts-rockchip-add-GPU-powerdomain-.patch Normal file
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@@ -0,0 +1,88 @@
From 5eb285a0a2db04a425b7198bf4ccad266646b7b0 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 2 Sep 2020 19:52:02 +0200
Subject: [PATCH 027/108] FROMGIT(6.18): arm64: dts: rockchip: add GPU
powerdomain, opps, and cooling to rk3328
Add GPU powerdomain, opp-table, and cooling map nodes for the Mali
GPU on the RK3328 SoC. Opp-table frequencies are sourced from the
Rockchip Linux v4.4 vendor kernel while voltages have been derived
from practical use and support work: keeping voltage above 1075mV
and disabling the 500MHz opp-point avoids instability and crashes.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 39 +++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 6438c969f9d7..cc93136422c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -331,6 +331,11 @@ power: power-controller {
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ #power-domain-cells = <0>;
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
clocks = <&cru SCLK_VENC_CORE>;
@@ -570,9 +575,13 @@ map0 {
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
+ map1 {
+ trip = <&target>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
};
};
-
};
tsadc: tsadc@ff250000 {
@@ -651,7 +660,35 @@ gpu: gpu@ff300000 {
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1075000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1075000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1075000>;
+ };
+
+ opp-500000000 {
+ /* causes stability issues */
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ status = "disabled";
+ };
};
h265e_mmu: iommu@ff330200 {
--
2.34.1

66
packages/linux/patches/rockchip/rockchip-0028-FROMGIT-6.18-arm64-dts-rockchip-enable-the-Mali-GPU-.patch Normal file
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@@ -0,0 +1,66 @@
From 4d3154e1151a869b20cca421792ed2237c75ff9f Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 2 Sep 2020 19:52:02 +0200
Subject: [PATCH 028/108] FROMGIT(6.18): arm64: dts: rockchip: enable the Mali
GPU on RK3328 boards
Add a gpu node to the rock64 board to enable the Mali GPU and
move the existing node from roc-pc to the shared roc dtsi to
enable it also for the roc-cc board.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 4 ----
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 4 ++++
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 ++++
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
index 329d03172433..c0b7b98ff788 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
@@ -44,10 +44,6 @@ &codec {
mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
};
-&gpu {
- mali-supply = <&vdd_logic>;
-};
-
&pinctrl {
ir {
ir_int: ir-int {
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
index aa1d5a6d7fd5..3fe0c17fd2b1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
@@ -167,6 +167,10 @@ &gmac2io {
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 5367e5fa9232..592fd8ca21df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -152,6 +152,10 @@ &gmac2io {
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
&hdmi {
avdd-0v9-supply = <&vdd_10>;
avdd-1v8-supply = <&vcc_18>;
--
2.34.1

56
packages/linux/patches/rockchip/rockchip-0029-FROMGIT-6.18-ARM-dts-rockchip-add-HDMI-audio-to-rk32.patch Normal file
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@@ -0,0 +1,56 @@
From 4898362d8fb614e726a5ae7df1d31b7ce3fb3119 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 2 Feb 2021 17:22:21 +0200
Subject: [PATCH 029/108] FROMGIT(6.18): ARM: dts: rockchip: add HDMI audio to
rk3288-miqi
Add the sound and i2s nodes to enable HDMI audio output on
the MiQi board.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index dd42f8d31f70..20df626547bd 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -78,6 +78,21 @@ vcc_sys: regulator-vsys {
regulator-always-on;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+ };
};
&cpu0 {
@@ -283,6 +298,11 @@ &i2c5 {
status = "okay";
};
+&i2s {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&io_domains {
status = "okay";
--
2.34.1

30
packages/linux/patches/rockchip/rockchip-0030-FROMGIT-6.18-ARM-dts-rockchip-add-CEC-pinctrl-to-rk3.patch Normal file
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@@ -0,0 +1,30 @@
From c0ab4f0e15e2e981996e4014196505b214f074cc Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 1 Mar 2021 21:24:15 +0100
Subject: [PATCH 030/108] FROMGIT(6.18): ARM: dts: rockchip: add CEC pinctrl to
rk3288-miqi
Enable CEC control on the HDMI port for MiQi.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index 20df626547bd..a5f5c6d38f80 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -145,6 +145,8 @@ &gpu {
&hdmi {
ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
status = "okay";
};
--
2.34.1

47
packages/linux/patches/rockchip/rockchip-0031-FROMLIST-v1-mmc-core-set-initial-signal-voltage-on-p.patch Normal file
View File

@@ -0,0 +1,47 @@
From 9a3ffa8a3b4c8755d57a5b18ad3e664e9cf0cd24 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 17 Feb 2019 22:14:38 +0000
Subject: [PATCH 031/108] FROMLIST(v1): mmc: core: set initial signal voltage
on power off
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. If the card has not been power cycled, it may still be
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
will fail to boot from a UHS card that continue to use 1.8V signaling.
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
same issue have been seen on some Rockchip RK3399 boards.
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
this change fix a re-boot issue on my boards and does not break emmc/sdio.
Is this an acceptable workaround? Any advice is appreciated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/core/core.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 874c6fe92855..7a8bede74cdd 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1373,6 +1373,14 @@ void mmc_power_off(struct mmc_host *host)
if (host->ios.power_mode == MMC_POWER_OFF)
return;
+ mmc_set_initial_signal_voltage(host);
+
+ /*
+ * This delay should be sufficient to allow the power supply
+ * to reach the minimum voltage.
+ */
+ mmc_delay(host->ios.power_delay_ms);
+
mmc_pwrseq_power_off(host);
host->ios.clock = 0;
--
2.34.1

35
packages/linux/patches/rockchip/rockchip-0032-FROMLIST-v7-dt-bindings-vendor-prefixes-Add-Verisili.patch Normal file
View File

@@ -0,0 +1,35 @@
From 2fe8271be434668d1da551357cd7a934d035e9ba Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 25 Aug 2025 17:34:40 +0200
Subject: [PATCH 032/108] FROMLIST(v7): dt-bindings: vendor-prefixes: Add
Verisilicon
Verisilicon Microelectronics is a company based in Shanghai, China,
developping hardware blocks for SoC.
https://verisilicon.com/
Add their name to the list of vendors.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 9ec8947dfcad..52b3495ff4db 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1656,6 +1656,8 @@ patternProperties:
description: Variscite Ltd.
"^vdl,.*":
description: Van der Laan b.v.
+ "^verisilicon,.*":
+ description: VeriSilicon Microelectronics
"^vertexcom,.*":
description: Vertexcom Technologies, Inc.
"^via,.*":
--
2.34.1

97
packages/linux/patches/rockchip/rockchip-0033-FROMLIST-v7-dt-bindings-iommu-verisilicon-Add-bindin.patch Normal file
View File

@@ -0,0 +1,97 @@
From 64fbd58f282af1be1ffdd94df94651baaf0b4f8e Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 25 Aug 2025 17:34:41 +0200
Subject: [PATCH 033/108] FROMLIST(v7): dt-bindings: iommu: verisilicon: Add
binding for VSI IOMMU
Add a device tree binding for the Verisilicon (VSI) IOMMU.
This IOMMU sits in front of hardware encoder and decoder
blocks on SoCs using Verisilicon IP, such as the Rockchip RK3588.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/iommu/verisilicon,iommu.yaml | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml
diff --git a/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml
new file mode 100644
index 000000000000..d3ce9e603b61
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/verisilicon,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Verisilicon IOMMU
+
+maintainers:
+ - Benjamin Gaignard <benjamin.gaignard@collabora.com>
+
+description: |+
+ A Versilicon iommu translates io virtual addresses to physical addresses for
+ its associated video decoder.
+
+properties:
+ compatible:
+ items:
+ - const: rockchip,rk3588-av1-iommu
+ - const: verisilicon,iommu-1.2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core clock
+ - description: Interface clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+
+ "#iommu-cells":
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#iommu-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ iommu@fdca0000 {
+ compatible = "rockchip,rk3588-av1-iommu","verisilicon,iommu-1.2";
+ reg = <0x0 0xfdca0000 0x0 0x600>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "core", "iface";
+ #iommu-cells = <0>;
+ };
+ };
--
2.34.1

836
packages/linux/patches/rockchip/rockchip-0034-FROMLIST-v7-iommu-Add-verisilicon-IOMMU-driver.patch Normal file
View File

@@ -0,0 +1,836 @@
From 1f06807df186c80abf4ec533df74c6ab07e030c6 Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 25 Aug 2025 17:34:42 +0200
Subject: [PATCH 034/108] FROMLIST(v7): iommu: Add verisilicon IOMMU driver
The Verisilicon IOMMU hardware block can be found in combination
with Verisilicon hardware video codecs (encoders or decoders) on
different SoCs.
Enable it will allow us to use non contiguous memory allocators
for Verisilicon video codecs.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/iommu/Kconfig | 11 +
drivers/iommu/Makefile | 1 +
drivers/iommu/vsi-iommu.c | 779 ++++++++++++++++++++++++++++++++++++++
3 files changed, 791 insertions(+)
create mode 100644 drivers/iommu/vsi-iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 70d29b14d851..d3731be630a2 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -383,4 +383,15 @@ config SPRD_IOMMU
Say Y here if you want to use the multimedia devices listed above.
+config VSI_IOMMU
+ tristate "Verisilicon IOMMU Support"
+ depends on (ARCH_ROCKCHIP && ARM64) || COMPILE_TEST
+ select IOMMU_API
+ help
+ Support for IOMMUs used by Verisilicon sub-systems like video
+ decoders or encoder hardware blocks.
+
+ Say Y here if you want to use this IOMMU in front of these
+ hardware blocks.
+
endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 355294fa9033..68aeff31af8b 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_IOMMU_SVA) += iommu-sva.o
obj-$(CONFIG_IOMMU_IOPF) += io-pgfault.o
obj-$(CONFIG_SPRD_IOMMU) += sprd-iommu.o
obj-$(CONFIG_APPLE_DART) += apple-dart.o
+obj-$(CONFIG_VSI_IOMMU) += vsi-iommu.o
diff --git a/drivers/iommu/vsi-iommu.c b/drivers/iommu/vsi-iommu.c
new file mode 100644
index 000000000000..69b5fcb910ef
--- /dev/null
+++ b/drivers/iommu/vsi-iommu.c
@@ -0,0 +1,779 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2025 Collabora Ltd.
+ *
+ * IOMMU API for Verisilicon
+ *
+ * Module Authors: Yandong Lin <yandong.lin@rock-chips.com>
+ * Simon Xue <xxm@rock-chips.com>
+ * Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iommu.h>
+#include <linux/list.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_iommu.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "iommu-pages.h"
+
+struct vsi_iommu {
+ struct device *dev;
+ void __iomem *regs;
+ struct clk_bulk_data *clocks;
+ int num_clocks;
+ struct iommu_device iommu;
+ struct list_head node; /* entry in vsi_iommu_domain.iommus */
+ struct iommu_domain *domain; /* domain to which iommu is attached */
+ spinlock_t lock;
+ int irq;
+};
+
+struct vsi_iommu_domain {
+ struct list_head iommus;
+ struct device *dev;
+ u32 *dt;
+ dma_addr_t dt_dma;
+ struct iommu_domain domain;
+ u64 *pta;
+ dma_addr_t pta_dma;
+ spinlock_t lock;
+};
+
+static struct iommu_domain vsi_identity_domain;
+
+#define NUM_DT_ENTRIES 1024
+#define NUM_PT_ENTRIES 1024
+#define PT_SIZE (NUM_PT_ENTRIES * sizeof(u32))
+
+#define SPAGE_SIZE BIT(12)
+
+/* vsi iommu regs address */
+#define VSI_MMU_CONFIG1_BASE 0x1ac
+#define VSI_MMU_AHB_EXCEPTION_BASE 0x380
+#define VSI_MMU_AHB_CONTROL_BASE 0x388
+#define VSI_MMU_AHB_TLB_ARRAY_BASE_L_BASE 0x38C
+
+/* MMU register offsets */
+#define VSI_MMU_FLUSH_BASE 0x184
+#define VSI_MMU_BIT_FLUSH BIT(4)
+
+#define VSI_MMU_PAGE_FAULT_ADDR 0x380
+#define VSI_MMU_STATUS_BASE 0x384 /* IRQ status */
+
+#define VSI_MMU_BIT_ENABLE BIT(0)
+
+#define VSI_MMU_OUT_OF_BOUND BIT(28)
+/* Irq mask */
+#define VSI_MMU_IRQ_MASK 0x7
+
+#define VSI_DTE_PT_ADDRESS_MASK 0xffffffc0
+#define VSI_DTE_PT_VALID BIT(0)
+
+#define VSI_PAGE_DESC_LO_MASK 0xfffff000
+#define VSI_PAGE_DESC_HI_MASK GENMASK_ULL(39, 32)
+#define VSI_PAGE_DESC_HI_SHIFT (32 - 4)
+
+static inline phys_addr_t vsi_dte_pt_address(u32 dte)
+{
+ return (phys_addr_t)dte & VSI_DTE_PT_ADDRESS_MASK;
+}
+
+static inline u32 vsi_mk_dte(u32 dte)
+{
+ return (phys_addr_t)dte | VSI_DTE_PT_VALID;
+}
+
+#define VSI_PTE_PAGE_WRITABLE BIT(2)
+#define VSI_PTE_PAGE_VALID BIT(0)
+
+static inline phys_addr_t vsi_pte_page_address(u64 pte)
+{
+ return pte << VSI_PAGE_DESC_HI_SHIFT;
+}
+
+static u32 vsi_mk_pte(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_WRITE) ? VSI_PTE_PAGE_WRITABLE : 0;
+ page = (page & VSI_PAGE_DESC_LO_MASK) |
+ ((page & VSI_PAGE_DESC_HI_MASK) >> VSI_PAGE_DESC_HI_SHIFT);
+
+ return page | flags | VSI_PTE_PAGE_VALID;
+}
+
+#define VSI_DTE_PT_VALID BIT(0)
+
+static inline bool vsi_dte_is_pt_valid(u32 dte)
+{
+ return dte & VSI_DTE_PT_VALID;
+}
+
+static inline bool vsi_pte_is_page_valid(u32 pte)
+{
+ return pte & VSI_PTE_PAGE_VALID;
+}
+
+static u32 vsi_mk_pte_invalid(u32 pte)
+{
+ return pte & ~VSI_PTE_PAGE_VALID;
+}
+
+#define VSI_MASTER_TLB_MASK GENMASK_ULL(31, 10)
+/* mode 0 : 4k */
+#define VSI_PTA_4K_MODE 0
+
+static u64 vsi_mk_pta(dma_addr_t dt_dma)
+{
+ u64 val = (dt_dma & VSI_MASTER_TLB_MASK) | VSI_PTA_4K_MODE;
+
+ return val;
+}
+
+static struct vsi_iommu_domain *to_vsi_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct vsi_iommu_domain, domain);
+}
+
+static inline void vsi_table_flush(struct vsi_iommu_domain *vsi_domain, dma_addr_t dma,
+ unsigned int count)
+{
+ size_t size = count * sizeof(u32); /* count of u32 entry */
+
+ dma_sync_single_for_device(vsi_domain->dev, dma, size, DMA_TO_DEVICE);
+}
+
+#define VSI_IOVA_DTE_MASK 0xffc00000
+#define VSI_IOVA_DTE_SHIFT 22
+#define VSI_IOVA_PTE_MASK 0x003ff000
+#define VSI_IOVA_PTE_SHIFT 12
+#define VSI_IOVA_PAGE_MASK 0x00000fff
+#define VSI_IOVA_PAGE_SHIFT 0
+
+static u32 vsi_iova_dte_index(u32 iova)
+{
+ return (iova & VSI_IOVA_DTE_MASK) >> VSI_IOVA_DTE_SHIFT;
+}
+
+static u32 vsi_iova_pte_index(u32 iova)
+{
+ return (iova & VSI_IOVA_PTE_MASK) >> VSI_IOVA_PTE_SHIFT;
+}
+
+static u32 vsi_iova_page_offset(u32 iova)
+{
+ return (iova & VSI_IOVA_PAGE_MASK) >> VSI_IOVA_PAGE_SHIFT;
+}
+
+static void vsi_iommu_flush_tlb_all(struct iommu_domain *domain)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ struct list_head *pos;
+ unsigned long flags;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+
+ list_for_each(pos, &vsi_domain->iommus) {
+ struct vsi_iommu *iommu;
+ int ret;
+
+ iommu = list_entry(pos, struct vsi_iommu, node);
+ ret = pm_runtime_resume_and_get(iommu->dev);
+ if (ret < 0)
+ continue;
+
+ spin_lock(&iommu->lock);
+
+ writel(VSI_MMU_BIT_FLUSH, iommu->regs + VSI_MMU_FLUSH_BASE);
+ writel(0, iommu->regs + VSI_MMU_FLUSH_BASE);
+
+ spin_unlock(&iommu->lock);
+ pm_runtime_put_autosuspend(iommu->dev);
+ }
+
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+
+}
+
+static irqreturn_t vsi_iommu_irq(int irq, void *dev_id)
+{
+ struct vsi_iommu *iommu = dev_id;
+ unsigned long flags;
+ dma_addr_t iova;
+ u32 status;
+
+ if (pm_runtime_resume_and_get(iommu->dev) < 0)
+ return IRQ_NONE;
+
+ spin_lock_irqsave(&iommu->lock, flags);
+
+ status = readl(iommu->regs + VSI_MMU_STATUS_BASE);
+ if (status & VSI_MMU_IRQ_MASK) {
+ dev_err(iommu->dev, "unexpected int_status=%08x\n", status);
+ iova = readl(iommu->regs + VSI_MMU_PAGE_FAULT_ADDR);
+ report_iommu_fault(iommu->domain, iommu->dev, iova, status);
+ }
+ writel(0, iommu->regs + VSI_MMU_STATUS_BASE);
+
+ spin_unlock_irqrestore(&iommu->lock, flags);
+ pm_runtime_put_autosuspend(iommu->dev);
+
+ return IRQ_HANDLED;
+}
+
+static struct vsi_iommu *vsi_iommu_get_from_dev(struct device *dev)
+{
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct device *iommu_dev = bus_find_device_by_fwnode(&platform_bus_type,
+ fwspec->iommu_fwnode);
+
+ put_device(iommu_dev);
+
+ return iommu_dev ? dev_get_drvdata(iommu_dev) : NULL;
+}
+
+static struct iommu_domain *vsi_iommu_domain_alloc_paging(struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_iommu_priv_get(dev);
+ struct vsi_iommu_domain *vsi_domain;
+
+ vsi_domain = kzalloc(sizeof(*vsi_domain), GFP_KERNEL);
+ if (!vsi_domain)
+ return NULL;
+
+ vsi_domain->dev = iommu->dev;
+ spin_lock_init(&vsi_domain->lock);
+
+ /*
+ * iommu use a 2 level pagetable.
+ * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
+ * Allocate one 4 KiB page for each table.
+ */
+ vsi_domain->dt = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32,
+ SPAGE_SIZE);
+ if (!vsi_domain->dt)
+ goto err_free_domain;
+
+ vsi_domain->dt_dma = dma_map_single(vsi_domain->dev, vsi_domain->dt,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+ if (dma_mapping_error(vsi_domain->dev, vsi_domain->dt_dma)) {
+ dev_err(dev, "DMA map error for DT\n");
+ goto err_free_dt;
+ }
+
+ vsi_domain->pta = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32,
+ SPAGE_SIZE);
+ if (!vsi_domain->pta)
+ goto err_unmap_dt;
+
+ vsi_domain->pta[0] = vsi_mk_pta(vsi_domain->dt_dma);
+ vsi_domain->pta_dma = dma_map_single(vsi_domain->dev, vsi_domain->pta,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+ if (dma_mapping_error(vsi_domain->dev, vsi_domain->pta_dma)) {
+ dev_err(dev, "DMA map error for PTA\n");
+ goto err_free_pta;
+ }
+
+ INIT_LIST_HEAD(&vsi_domain->iommus);
+
+ vsi_domain->domain.geometry.aperture_start = 0;
+ vsi_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
+ vsi_domain->domain.geometry.force_aperture = true;
+ vsi_domain->domain.pgsize_bitmap = SZ_4K;
+
+ return &vsi_domain->domain;
+
+err_free_pta:
+ iommu_free_pages(vsi_domain->pta);
+err_unmap_dt:
+ dma_unmap_single(vsi_domain->dev, vsi_domain->dt_dma,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+err_free_dt:
+ iommu_free_pages(vsi_domain->dt);
+err_free_domain:
+ kfree(vsi_domain);
+
+ return NULL;
+}
+
+static phys_addr_t vsi_iommu_iova_to_phys(struct iommu_domain *domain,
+ dma_addr_t iova)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ phys_addr_t pt_phys, phys = 0;
+ unsigned long flags;
+ u32 dte, pte;
+ u32 *page_table;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+ dte = vsi_domain->dt[vsi_iova_dte_index(iova)];
+ if (!vsi_dte_is_pt_valid(dte))
+ goto unlock;
+
+ pt_phys = vsi_dte_pt_address(dte);
+ page_table = (u32 *)phys_to_virt(pt_phys);
+ pte = page_table[vsi_iova_pte_index(iova)];
+ if (!vsi_pte_is_page_valid(pte))
+ goto unlock;
+
+ phys = vsi_pte_page_address(pte) + vsi_iova_page_offset(iova);
+
+unlock:
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+ return phys;
+}
+
+static size_t vsi_iommu_unmap_iova(struct vsi_iommu_domain *vsi_domain,
+ u32 *pte_addr, dma_addr_t pte_dma,
+ size_t size)
+{
+ unsigned int pte_count;
+ unsigned int pte_total = size / SPAGE_SIZE;
+
+ for (pte_count = 0;
+ pte_count < pte_total && pte_count < NUM_PT_ENTRIES; pte_count++) {
+ u32 pte = pte_addr[pte_count];
+
+ if (!vsi_pte_is_page_valid(pte))
+ break;
+
+ pte_addr[pte_count] = vsi_mk_pte_invalid(pte);
+ }
+
+ vsi_table_flush(vsi_domain, pte_dma, pte_count);
+
+ return pte_count * SPAGE_SIZE;
+}
+
+static int vsi_iommu_map_iova(struct vsi_iommu_domain *vsi_domain, u32 *pte_addr,
+ dma_addr_t pte_dma, dma_addr_t iova,
+ phys_addr_t paddr, size_t size, int prot)
+{
+ unsigned int pte_count;
+ unsigned int pte_total = size / SPAGE_SIZE;
+
+ for (pte_count = 0;
+ pte_count < pte_total && pte_count < NUM_PT_ENTRIES; pte_count++) {
+ u32 pte = pte_addr[pte_count];
+
+ if (vsi_pte_is_page_valid(pte))
+ return (pte_count - 1) * SPAGE_SIZE;
+
+ pte_addr[pte_count] = vsi_mk_pte(paddr, prot);
+
+ paddr += SPAGE_SIZE;
+ }
+
+ vsi_table_flush(vsi_domain, pte_dma, pte_total);
+
+ return 0;
+}
+
+static size_t vsi_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
+ size_t size, size_t count, struct iommu_iotlb_gather *gather)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
+ unsigned long flags;
+ phys_addr_t pt_phys;
+ u32 dte;
+ u32 *pte_addr;
+ size_t unmap_size = 0;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+
+ dte = vsi_domain->dt[vsi_iova_dte_index(iova)];
+ /* Just return 0 if iova is unmapped */
+ if (!vsi_dte_is_pt_valid(dte))
+ goto unlock;
+
+ pt_phys = vsi_dte_pt_address(dte);
+ pte_addr = (u32 *)phys_to_virt(pt_phys) + vsi_iova_pte_index(iova);
+ pte_dma = pt_phys + vsi_iova_pte_index(iova) * sizeof(u32);
+ unmap_size = vsi_iommu_unmap_iova(vsi_domain, pte_addr, pte_dma, size);
+
+unlock:
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+
+ return unmap_size;
+}
+
+static u32 *vsi_dte_get_page_table(struct vsi_iommu_domain *vsi_domain,
+ dma_addr_t iova, gfp_t gfp)
+{
+ u32 *page_table, *dte_addr;
+ u32 dte_index, dte;
+ phys_addr_t pt_phys;
+ dma_addr_t pt_dma;
+ gfp_t flags;
+
+ dte_index = vsi_iova_dte_index(iova);
+ dte_addr = &vsi_domain->dt[dte_index];
+ dte = *dte_addr;
+ if (vsi_dte_is_pt_valid(dte))
+ goto done;
+
+ /* Do not allow to sleep while allocating the buffer */
+ flags = (gfp & ~GFP_KERNEL) | GFP_ATOMIC | GFP_DMA32;
+ page_table = iommu_alloc_pages_sz(flags, PAGE_SIZE);
+ if (!page_table)
+ return ERR_PTR(-ENOMEM);
+
+ pt_dma = dma_map_single(vsi_domain->dev, page_table, PAGE_SIZE, DMA_TO_DEVICE);
+ if (dma_mapping_error(vsi_domain->dev, pt_dma)) {
+ dev_err(vsi_domain->dev, "DMA mapping error while allocating page table\n");
+ iommu_free_pages(page_table);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ dte = vsi_mk_dte(pt_dma);
+ *dte_addr = dte;
+
+ vsi_table_flush(vsi_domain,
+ vsi_domain->dt_dma + dte_index * sizeof(u32), 1);
+done:
+ pt_phys = vsi_dte_pt_address(dte);
+ return (u32 *)phys_to_virt(pt_phys);
+}
+
+static int vsi_iommu_map(struct iommu_domain *domain, unsigned long _iova,
+ phys_addr_t paddr, size_t size, size_t count,
+ int prot, gfp_t gfp, size_t *mapped)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
+ u32 *page_table, *pte_addr;
+ u32 dte, pte_index;
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+
+ page_table = vsi_dte_get_page_table(vsi_domain, iova, gfp);
+ if (IS_ERR(page_table)) {
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+ return PTR_ERR(page_table);
+ }
+
+ dte = vsi_domain->dt[vsi_iova_dte_index(iova)];
+ pte_index = vsi_iova_pte_index(iova);
+ pte_addr = &page_table[pte_index];
+ pte_dma = vsi_dte_pt_address(dte) + pte_index * sizeof(u32);
+ ret = vsi_iommu_map_iova(vsi_domain, pte_addr, pte_dma, iova,
+ paddr, size, prot);
+ if (!ret)
+ *mapped = size;
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+
+ return ret;
+}
+
+static void vsi_iommu_disable(struct vsi_iommu *iommu)
+{
+ writel(0, iommu->regs + VSI_MMU_AHB_CONTROL_BASE);
+}
+
+static int vsi_iommu_identity_attach(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_iommu_priv_get(dev);
+ unsigned long flags;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(iommu->dev);
+ if (ret < 0)
+ return ret;
+
+ spin_lock_irqsave(&iommu->lock, flags);
+ if (iommu->domain == domain)
+ goto unlock;
+
+ vsi_iommu_disable(iommu);
+ list_del_init(&iommu->node);
+
+ iommu->domain = domain;
+
+unlock:
+ spin_unlock_irqrestore(&iommu->lock, flags);
+ pm_runtime_put_autosuspend(iommu->dev);
+ return 0;
+}
+
+static const struct iommu_domain_ops vsi_identity_ops = {
+ .attach_dev = vsi_iommu_identity_attach,
+};
+
+static struct iommu_domain vsi_identity_domain = {
+ .type = IOMMU_DOMAIN_IDENTITY,
+ .ops = &vsi_identity_ops,
+};
+
+static void vsi_iommu_enable(struct vsi_iommu *iommu, struct iommu_domain *domain)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+
+ if (domain == &vsi_identity_domain)
+ return;
+
+ writel(vsi_domain->pta_dma, iommu->regs + VSI_MMU_AHB_TLB_ARRAY_BASE_L_BASE);
+ writel(VSI_MMU_OUT_OF_BOUND, iommu->regs + VSI_MMU_CONFIG1_BASE);
+ writel(VSI_MMU_BIT_ENABLE, iommu->regs + VSI_MMU_AHB_EXCEPTION_BASE);
+ writel(VSI_MMU_BIT_ENABLE, iommu->regs + VSI_MMU_AHB_CONTROL_BASE);
+}
+
+static int vsi_iommu_attach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_iommu_priv_get(dev);
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ unsigned long flags, flags2;
+ int ret = 0;
+
+ ret = pm_runtime_resume_and_get(iommu->dev);
+ if (ret < 0)
+ return ret;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+ spin_lock_irqsave(&iommu->lock, flags2);
+
+ vsi_iommu_enable(iommu, domain);
+ writel(VSI_MMU_BIT_FLUSH, iommu->regs + VSI_MMU_FLUSH_BASE);
+ writel(0, iommu->regs + VSI_MMU_FLUSH_BASE);
+
+ list_del_init(&iommu->node);
+ list_add_tail(&iommu->node, &vsi_domain->iommus);
+
+ iommu->domain = domain;
+
+ spin_unlock_irqrestore(&iommu->lock, flags2);
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+ pm_runtime_put_autosuspend(iommu->dev);
+ return ret;
+}
+
+static void vsi_iommu_domain_free(struct iommu_domain *domain)
+{
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(domain);
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+
+ WARN_ON(!list_empty(&vsi_domain->iommus));
+
+ for (i = 0; i < NUM_DT_ENTRIES; i++) {
+ u32 dte = vsi_domain->dt[i];
+
+ if (vsi_dte_is_pt_valid(dte)) {
+ phys_addr_t pt_phys = vsi_dte_pt_address(dte);
+ u32 *page_table = phys_to_virt(pt_phys);
+
+ dma_unmap_single(vsi_domain->dev, pt_phys,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+ iommu_free_pages(page_table);
+ }
+ }
+
+ dma_unmap_single(vsi_domain->dev, vsi_domain->dt_dma,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+ iommu_free_pages(vsi_domain->dt);
+
+ dma_unmap_single(vsi_domain->dev, vsi_domain->pta_dma,
+ SPAGE_SIZE, DMA_TO_DEVICE);
+ iommu_free_pages(vsi_domain->pta);
+
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+
+ kfree(vsi_domain);
+}
+
+static struct iommu_device *vsi_iommu_probe_device(struct device *dev)
+{
+ struct vsi_iommu *iommu = vsi_iommu_get_from_dev(dev);
+ struct device_link *link;
+
+ link = device_link_add(dev, iommu->dev,
+ DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
+ if (!link)
+ dev_err(dev, "Unable to link %s\n", dev_name(iommu->dev));
+
+ dev_iommu_priv_set(dev, iommu);
+ return &iommu->iommu;
+}
+
+static void vsi_iommu_release_device(struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_iommu_priv_get(dev);
+
+ device_link_remove(dev, iommu->dev);
+}
+
+static int vsi_iommu_of_xlate(struct device *dev, const struct of_phandle_args *args)
+{
+ return iommu_fwspec_add_ids(dev, args->args, 1);
+}
+
+static const struct iommu_ops vsi_iommu_ops = {
+ .identity_domain = &vsi_identity_domain,
+ .release_domain = &vsi_identity_domain,
+ .domain_alloc_paging = vsi_iommu_domain_alloc_paging,
+ .of_xlate = vsi_iommu_of_xlate,
+ .probe_device = vsi_iommu_probe_device,
+ .release_device = vsi_iommu_release_device,
+ .device_group = generic_single_device_group,
+ .owner = THIS_MODULE,
+ .default_domain_ops = &(const struct iommu_domain_ops) {
+ .attach_dev = vsi_iommu_attach_device,
+ .map_pages = vsi_iommu_map,
+ .unmap_pages = vsi_iommu_unmap,
+ .flush_iotlb_all = vsi_iommu_flush_tlb_all,
+ .iova_to_phys = vsi_iommu_iova_to_phys,
+ .free = vsi_iommu_domain_free,
+ }
+};
+
+static const struct of_device_id vsi_iommu_dt_ids[] = {
+ {
+ .compatible = "verisilicon,iommu-1.2",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, vsi_iommu_dt_ids);
+
+static int vsi_iommu_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct vsi_iommu *iommu;
+ int err;
+
+ iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
+ if (!iommu)
+ return -ENOMEM;
+
+ iommu->dev = dev;
+ spin_lock_init(&iommu->lock);
+ INIT_LIST_HEAD(&iommu->node);
+
+ iommu->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(iommu->regs))
+ return -ENOMEM;
+
+ iommu->num_clocks = devm_clk_bulk_get_all(dev, &iommu->clocks);
+ if (iommu->num_clocks < 0)
+ return iommu->num_clocks;
+
+ err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
+ if (err)
+ return err;
+
+ iommu->irq = platform_get_irq(pdev, 0);
+ if (iommu->irq < 0)
+ return iommu->irq;
+
+ err = devm_request_irq(iommu->dev, iommu->irq, vsi_iommu_irq,
+ IRQF_SHARED, dev_name(dev), iommu);
+ if (err)
+ goto err_unprepare_clocks;
+
+ dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ platform_set_drvdata(pdev, iommu);
+
+ pm_runtime_set_autosuspend_delay(dev, 100);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_enable(dev);
+
+ err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
+ if (err)
+ goto err_runtime_disable;
+
+ err = iommu_device_register(&iommu->iommu, &vsi_iommu_ops, dev);
+ if (err)
+ goto err_remove_sysfs;
+
+ return 0;
+
+err_remove_sysfs:
+ iommu_device_sysfs_remove(&iommu->iommu);
+err_runtime_disable:
+ pm_runtime_disable(dev);
+err_unprepare_clocks:
+ clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
+ return err;
+}
+
+static void vsi_iommu_shutdown(struct platform_device *pdev)
+{
+ struct vsi_iommu *iommu = platform_get_drvdata(pdev);
+
+ disable_irq(iommu->irq);
+ pm_runtime_force_suspend(&pdev->dev);
+}
+
+static int __maybe_unused vsi_iommu_suspend(struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_get_drvdata(dev);
+
+ vsi_iommu_disable(iommu);
+
+ clk_bulk_disable(iommu->num_clocks, iommu->clocks);
+
+ return 0;
+}
+
+static int __maybe_unused vsi_iommu_resume(struct device *dev)
+{
+ struct vsi_iommu *iommu = dev_get_drvdata(dev);
+ unsigned long flags, flags2;
+ int ret;
+
+ ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
+ if (ret)
+ return ret;
+
+ if (iommu->domain) {
+ struct vsi_iommu_domain *vsi_domain = to_vsi_domain(iommu->domain);
+
+ spin_lock_irqsave(&vsi_domain->lock, flags);
+ spin_lock_irqsave(&iommu->lock, flags2);
+ vsi_iommu_enable(iommu, iommu->domain);
+ spin_unlock_irqrestore(&iommu->lock, flags2);
+ spin_unlock_irqrestore(&vsi_domain->lock, flags);
+ }
+
+ return 0;
+}
+
+static DEFINE_RUNTIME_DEV_PM_OPS(vsi_iommu_pm_ops,
+ vsi_iommu_suspend, vsi_iommu_resume,
+ NULL);
+
+static struct platform_driver rockchip_vsi_iommu_driver = {
+ .probe = vsi_iommu_probe,
+ .shutdown = vsi_iommu_shutdown,
+ .driver = {
+ .name = "vsi_iommu",
+ .of_match_table = vsi_iommu_dt_ids,
+ .pm = pm_sleep_ptr(&vsi_iommu_pm_ops),
+ .suppress_bind_attrs = true,
+ },
+};
+module_platform_driver(rockchip_vsi_iommu_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@collabora.com>");
+MODULE_DESCRIPTION("Verisilicon IOMMU driver");
--
2.34.1

100
packages/linux/patches/rockchip/rockchip-0035-FROMLIST-v7-media-verisilicon-AV1-Restore-IOMMU-cont.patch Normal file
View File

@@ -0,0 +1,100 @@
From 8ba4af5d9c0c85163e6f6b076e22dfc16311d2be Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 25 Aug 2025 17:34:43 +0200
Subject: [PATCH 035/108] FROMLIST(v7): media: verisilicon: AV1: Restore IOMMU
context before decoding a frame
AV1 is a stateless decoder and multiple AV1 bitstreams could be decoded
at the same time. Each decoding context got it own iommu domain which
need to be restored before each frame. To be sure that iommu context is
correctly set AV1 driver detach and attach before decoding the frame.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/media/platform/verisilicon/hantro.h | 5 +++++
drivers/media/platform/verisilicon/hantro_drv.c | 11 +++++++++++
.../platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 10 ++++++++++
3 files changed, 26 insertions(+)
diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
index 81328c63b796..a28a181013b9 100644
--- a/drivers/media/platform/verisilicon/hantro.h
+++ b/drivers/media/platform/verisilicon/hantro.h
@@ -12,6 +12,9 @@
#ifndef HANTRO_H_
#define HANTRO_H_
+#include <linux/dma-map-ops.h>
+#include <linux/iommu.h>
+#include <linux/iommu-dma.h>
#include <linux/platform_device.h>
#include <linux/videodev2.h>
#include <linux/wait.h>
@@ -266,6 +269,8 @@ struct hantro_ctx {
struct hantro_postproc_ctx postproc;
bool need_postproc;
+ struct iommu_domain *iommu_domain;
+
/* Specific for particular codec modes. */
union {
struct hantro_h264_dec_hw_ctx h264_dec;
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index fa972effd4a2..c31fd75902d4 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -674,6 +674,13 @@ static int hantro_open(struct file *filp)
}
ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+ if (use_dma_iommu(ctx->dev->v4l2_dev.dev)) {
+ ctx->iommu_domain = iommu_paging_domain_alloc(ctx->dev->v4l2_dev.dev);
+
+ if (!ctx->iommu_domain)
+ vpu_err("cannot alloc new empty domain\n");
+ }
+
return 0;
err_fh_free:
@@ -697,6 +704,10 @@ static int hantro_release(struct file *filp)
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+
+ if (ctx->iommu_domain)
+ iommu_domain_free(ctx->iommu_domain);
+
kfree(ctx);
return 0;
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
index e4703bb6be7c..b3e52387234f 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
@@ -2095,12 +2095,22 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx)
hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);
}
+static void rockchip_vpu981_av1_restore_iommu(struct hantro_ctx *ctx)
+{
+ if (ctx->iommu_domain) {
+ iommu_attach_device(ctx->iommu_domain, ctx->dev->v4l2_dev.dev);
+ iommu_detach_device(ctx->iommu_domain, ctx->dev->v4l2_dev.dev);
+ }
+}
+
int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *vb2_src;
int ret;
+ rockchip_vpu981_av1_restore_iommu(ctx);
+
hantro_start_prepare_run(ctx);
ret = rockchip_vpu981_av1_dec_prepare_run(ctx);
--
2.34.1

40
packages/linux/patches/rockchip/rockchip-0036-FROMLIST-v7-arm64-dts-rockchip-Add-verisilicon-IOMMU.patch Normal file
View File

@@ -0,0 +1,40 @@
From 8937d64d478bd515e07147a5cfe6fbc54afb251a Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 25 Aug 2025 17:34:44 +0200
Subject: [PATCH 036/108] FROMLIST(v7): arm64: dts: rockchip: Add verisilicon
IOMMU node on RK3588
Add the device tree node for the Verisilicon IOMMU present
in the RK3588 SoC.
This IOMMU handles address translation for the VPU hardware blocks.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 56bf903eb04f..3bd1b5e3b101 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1418,6 +1418,17 @@ av1d: video-codec@fdc70000 {
clock-names = "aclk", "hclk";
power-domains = <&power RK3588_PD_AV1>;
resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
+ iommus = <&av1d_mmu>;
+ };
+
+ av1d_mmu: iommu@fdca0000 {
+ compatible = "rockchip,rk3588-av1-iommu", "verisilicon,iommu-1.2";
+ reg = <0x0 0xfdca0000 0x0 0x600>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "core", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_AV1>;
};
vop: vop@fdd90000 {
--
2.34.1

53
packages/linux/patches/rockchip/rockchip-0037-FROMLIST-v1-drm-bridge-dw-hdmi-qp-Return-0-in-audio-.patch Normal file
View File

@@ -0,0 +1,53 @@
From 48c7a17a11c519e59a7b3e2d53268ff0ace54c51 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Thu, 17 Jul 2025 17:56:18 -0400
Subject: [PATCH 037/108] FROMLIST(v1): drm/bridge: dw-hdmi-qp: Return 0 in
audio prepare when disconnected
To configure audio registers, the clock of the video port in use must be
enabled.
As those clocks are managed by the VOP driver, they can't be enabled here
to write the registers even when the HDMI cable is disconnected.
Furthermore, the registers values are computed from the TMDS char rate,
which is not available when disconnected.
Returning -ENODEV seemed reasonable at first, but ASoC will log an error
multiple times if dw_hdmi_qp_audio_prepare() return an error.
Userspace might also retry multiple times, filling the kernel log with:
hdmi-audio-codec hdmi-audio-codec.0.auto: ASoC error (-19): at snd_soc_dai_prepare() on i2s-hifi
This has become even worse with the support of the second HDMI TX port.
Activating the clocks to write fake data (fake because the TMDS char
rate is unavailable) would require API changes to communicate between
VOP and HDMI, which doesn't really make sense.
Using a cached regmap to be dumped when a cable is connected won't work
because writing order is important and some data needs to be retrieved
from registers to write others.
Returning 0 to silently fail sounds like the best and simplest solution.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 39332c57f2c5..3d290f7b015f 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -460,7 +460,7 @@ static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge,
bool ref2stream = false;
if (!hdmi->tmds_char_rate)
- return -ENODEV;
+ return 0;
if (fmt->bit_clk_provider | fmt->frame_clk_provider) {
dev_err(hdmi->dev, "unsupported clock settings\n");
--
2.34.1

31
packages/linux/patches/rockchip/rockchip-0038-FROMLIST-v1-drm-bridge-synopsys-Do-not-warn-about-au.patch Normal file
View File

@@ -0,0 +1,31 @@
From b78e78578111f26f5ae1fd83fbd0a41658449f46 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Thu, 26 Jun 2025 08:53:07 -0400
Subject: [PATCH 038/108] FROMLIST(v1): drm/bridge: synopsys: Do not warn about
audio params computation
There is no need to warn about non pre-computed values, just change it to
dbg.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 3d290f7b015f..8f5059edb582 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -277,8 +277,7 @@ static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pix
if (n > 0)
return n;
- dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
- pixel_clk);
+ dev_dbg(hdmi->dev, "Rate %lu missing; compute N dynamically\n", pixel_clk);
return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate);
}
--
2.34.1

60
packages/linux/patches/rockchip/rockchip-0039-FROMLIST-v1-arm64-dts-rockchip-use-MAC-TX-delay-for-.patch Normal file
View File

@@ -0,0 +1,60 @@
From c1674bdd8306651c0fd258fcc32473e562ec078a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 24 Jul 2025 16:31:25 +0200
Subject: [PATCH 039/108] FROMLIST(v1): arm64: dts: rockchip: use MAC TX delay
for ROCK 4D
According to the Ethernet controller device tree binding "rgmii-id"
means, that the PCB does not have extra long lines to add the required
delays. This is indeed the case for the ROCK 4D.
The problem is, that the Rockchip MAC Linux driver interprets the
interface type differently and abuses the information to configure
RX and TX delays in the MAC using (vendor) properties 'rx_delay' and
'tx_delay'.
When Detlev Casanova upstreamed the ROCK 4D device tree, he used the
correct description for the board ("rgmii-id"). This results in no delays
being configured in the MAC. At the same time the PHY will provide
some delays.
This works to some degree, but is not a stable configuration. All five
ROCK 4D production boards, which have recently been added to the Collabora
LAVA lab for CI purposes have trouble with data not getting through
after a connection has been established.
Using the same delay setup as the vendor device tree fixes the
functionality (at the cost of not properly following the DT binding).
As we cannot fix the driver behavior for RK3576 (some other boards
already depend on this), let's update the ROCK 4D DT instead.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
index 9bc33422ced5..b607afb09635 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
@@ -272,7 +272,7 @@ &cpu_l3 {
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-rxid";
pinctrl-names = "default";
pinctrl-0 = <&eth0m0_miim
&eth0m0_tx_bus2
@@ -281,6 +281,8 @@ &eth0m0_rgmii_clk
&eth0m0_rgmii_bus
&ethm0_clk0_25m_out>;
status = "okay";
+ tx_delay = <0x20>;
+ rx_delay = <0x00>;
};
&gpu {
--
2.34.1

30
packages/linux/patches/rockchip/rockchip-0040-FROMLIST-v2-arm64-dts-rockchip-Fix-sound-output-from.patch Normal file
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@@ -0,0 +1,30 @@
From 1522430dfc988a0f13ceb046c97436b751042e88 Mon Sep 17 00:00:00 2001
From: Hide Hako <opi5plus@bcc.bai.ne.jp>
Date: Tue, 26 Aug 2025 01:44:00 +0000
Subject: [PATCH 040/108] FROMLIST(v2): arm64: dts: rockchip: Fix sound output
from the audio jack on OrangePI5 Plus
Currently, analog sound is not output from the audio jack.
This patch allows you to select analog headphones in alsamixer.
Fixes: 236d225e1ee7 ("arm64: dts: rockchip: Add board device tree for rk3588-orangepi-5-plus")
Signed-off-by: Hide Hako <opi5plus@bcc.bai.ne.jp>
---
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
index 9950d1147e12..2acadcfe52e4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
@@ -78,6 +78,7 @@ &analog_sound {
pinctrl-0 = <&hp_detect>;
simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,pin-switches = "Speaker", "Headphones";
simple-audio-card,widgets =
"Microphone", "Onboard Microphone",
"Microphone", "Microphone Jack",
--
2.34.1

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