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334b6a6e6b
Patches for RK356X, RK3576 and RK3588 are placed in a 'rockchip' folder under the Linux package dir. Boards use a common aarch64 arch defconfig. Patches for RK3288, RK3328 and RK3399 are moved to a 'rockchip-old' folder under the Linux package dir. Boards continue to use device level 6.16.y defconfigs to ensure all drivers are present, except for RK3288 which has been moved to the project level folder to be the common arm arch defconfig. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
75 lines
3.0 KiB
Diff
75 lines
3.0 KiB
Diff
From bf04a56d11d5691a02576a23c555b3aed84fb03f Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 4 Aug 2018 14:51:14 +0200
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Subject: [PATCH 16/59] WIP/1000: HACK: clk: rockchip: rk3288: use npll table
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to to improve HDMI compatibility
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Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++-
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1 file changed, 38 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 89141dbfd483..1da21ac9aad9 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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{ /* sentinel */ },
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};
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+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
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+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
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+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
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+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
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+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
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+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
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+ RK3066_PLL_RATE(348500000, 8, 697, 6),
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+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
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+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
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+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
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+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
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+ RK3066_PLL_RATE(241500000, 2, 161, 8),
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+ RK3066_PLL_RATE(162000000, 1, 81, 12),
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+ RK3066_PLL_RATE(154000000, 6, 539, 14),
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+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
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+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
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+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
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+ RK3066_PLL_RATE(121750000, 6, 487, 16),
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+ RK3066_PLL_RATE(119000000, 3, 238, 16),
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+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
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+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
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+ RK3066_PLL_RATE(101000000, 3, 202, 16),
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+ RK3066_PLL_RATE(88750000, 6, 355, 16),
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+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
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+ RK3066_PLL_RATE(83500000, 3, 167, 16),
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+ RK3066_PLL_RATE(79500000, 1, 53, 16),
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+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
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+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
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+ RK3066_PLL_RATE(72000000, 1, 48, 16),
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+ RK3066_PLL_RATE(71000000, 3, 142, 16),
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+ RK3066_PLL_RATE(68250000, 2, 91, 16),
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+ RK3066_PLL_RATE(65000000, 3, 130, 16),
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+ RK3066_PLL_RATE(40000000, 3, 80, 16),
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+ RK3066_PLL_RATE(33750000, 2, 45, 16),
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+ { /* sentinel */ },
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+};
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+
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#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
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#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
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#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
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@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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--
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2.34.1
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