Files
build/patch/kernel/archive/sunxi-5.18/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
The-going 7b0c873f4d Sunxi 5.18: add megous patches: tag: orange-pi-5.18-20220627-1924 (#3946)
* sunxi-5.18: add megous patches: tag: orange-pi-5.18-20220627-1924

* tools: mk_format_patch: ignore-matching-lines git version

* sunxi-5.18: re-extracted armbian patches after being applied to 5.18.8

* sunxi-5.18: switch to version tag=v5.18.8
2022-07-01 01:02:59 +02:00

120 lines
3.2 KiB
Diff

From 7531d7b11cd38f1f84b55eb3cb55f74b00c1cac4 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Sun, 23 Jan 2022 20:49:27 +0300
Subject: [PATCH 088/169] arm64:dts: sun50i-h6 Add r_uart uart2-3 pins
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++++++++++----
1 file changed, 50 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 412e0ab2c..ad4241a1a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -316,6 +316,17 @@ msgbox: mailbox@3003000 {
#mbox-cells = <1>;
};
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
sid: efuse@3006000 {
compatible = "allwinner,sun50i-h6-sid";
reg = <0x03006000 0x400>;
@@ -379,6 +390,7 @@ pio: pinctrl@300b000 {
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
ext_rgmii_pins: rgmii-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10",
@@ -442,6 +454,7 @@ pwm1_pin: pwm1-pin {
function = "pwm1";
};
+ /omit-if-no-ref/
mmc2_pins: mmc2-pins {
pins = "PC1", "PC4", "PC5", "PC6",
"PC7", "PC8", "PC9", "PC10",
@@ -495,17 +508,26 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
- };
- gic: interrupt-controller@3021000 {
- compatible = "arm,gic-400";
- reg = <0x03021000 0x1000>,
- <0x03022000 0x2000>,
- <0x03024000 0x2000>,
- <0x03026000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-controller;
- #interrupt-cells = <3>;
+ uart2_pins: uart2-pins {
+ pins = "PD19", "PD20";
+ function = "uart2";
+ };
+
+ uart2_rts_cts_pins: uart2-rts-cts-pins {
+ pins = "PD21", "PD22";
+ function = "uart2";
+ };
+
+ uart3_pins: uart3-pins {
+ pins = "PD23", "PD24";
+ function = "uart3";
+ };
+
+ uart3_rts_cts_pins: uart3-rts-cts-pins {
+ pins = "PD25", "PD26";
+ function = "uart3";
+ };
};
iommu: iommu@30f0000 {
@@ -1023,6 +1045,19 @@ tcon_tv_out_tcon_top: endpoint@1 {
};
};
+ r_uart: serial@7080000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07080000 0x400>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&r_ccu CLK_R_APB2_UART>;
+ resets = <&r_ccu RST_R_APB2_UART>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h6-rtc";
reg = <0x07000000 0x400>;
@@ -1087,6 +1122,11 @@ r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
};
+
+ r_uart_pins: r-uart-pins {
+ pins = "PL2", "PL3";
+ function = "s_uart";
+ };
};
r_ir: ir@7040000 {
--
2.35.3