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137 lines
5.0 KiB
Diff
137 lines
5.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Date: Sun, 14 Mar 2021 04:58:32 +0300
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Subject: drm/msm/dpu1: use one active CTL if it is available
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Unlike previous generation, with newer ("active") CTLs it is possible to
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use just one CTL to handle both interfaces. And one has to use single
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CTL to support master/slave DSI config. So use one active CTL if it is
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available.
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Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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---
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drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 +
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drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
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drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 ++++--
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drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
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drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 14 +++++++---
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drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
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6 files changed, 20 insertions(+), 6 deletions(-)
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
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index 9392ad2b4..35b3856f9 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
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+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
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@@ -15,6 +15,7 @@ static const struct dpu_caps sm8150_dpu_caps = {
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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+ .has_active_ctls = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
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index 94278a3e3..be95a27c4 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
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+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
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@@ -15,6 +15,7 @@ static const struct dpu_caps sm8250_dpu_caps = {
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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+ .has_active_ctls = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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index 1cf7ff6ca..98f46cc98 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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@@ -1117,14 +1117,18 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
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return;
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}
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- if (!hw_ctl[i]) {
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+ /* Use first (and only) CTL if active CTLs are supported */
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+ if (dpu_kms->catalog->caps->has_active_ctls)
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+ phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
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+ else
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+ phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
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+ if (!phys->hw_ctl) {
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DPU_ERROR_ENC(dpu_enc,
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"no ctl block assigned at idx: %d\n", i);
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return;
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}
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phys->hw_pp = dpu_enc->hw_pp[i];
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- phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
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phys->cached_mode = crtc_state->adjusted_mode;
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if (phys->ops.atomic_mode_set)
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
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index df024e10d..4e9533c7e 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
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@@ -359,6 +359,7 @@ struct dpu_caps {
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bool has_dim_layer;
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bool has_idle_pc;
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bool has_3d_merge;
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+ bool has_active_ctls;
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/* SSPP limits */
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u32 max_linewidth;
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u32 pixel_ram_size;
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
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index 8759466e2..ba55b4381 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
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@@ -196,6 +196,7 @@ int dpu_rm_init(struct dpu_rm *rm,
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}
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rm->ctl_blks[ctl->id - CTL_0] = &hw->base;
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}
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+ rm->has_active_ctls = cat->caps->has_active_ctls;
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for (i = 0; i < cat->dspp_count; i++) {
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struct dpu_hw_dspp *hw;
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@@ -418,10 +419,15 @@ static int _dpu_rm_reserve_ctls(
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int i = 0, j, num_ctls;
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bool needs_split_display;
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- /* each hw_intf needs its own hw_ctrl to program its control path */
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- num_ctls = top->num_intf;
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+ if (rm->has_active_ctls) {
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+ num_ctls = 1;
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+ needs_split_display = false;
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+ } else {
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+ /* each hw_intf needs its own hw_ctrl to program its control path */
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+ num_ctls = top->num_intf;
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- needs_split_display = _dpu_rm_needs_split_display(top);
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+ needs_split_display = _dpu_rm_needs_split_display(top);
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+ }
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for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
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const struct dpu_hw_ctl *ctl;
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@@ -439,7 +445,7 @@ static int _dpu_rm_reserve_ctls(
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DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
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- if (needs_split_display != has_split_display)
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+ if (!rm->has_active_ctls && needs_split_display != has_split_display)
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continue;
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ctl_idx[i] = j;
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
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index 2b551566c..6e4777f57 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
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@@ -33,6 +33,7 @@ struct dpu_rm {
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struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
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struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
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struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
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+ bool has_active_ctls;
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};
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/**
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--
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Armbian
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