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* Add MXQ target. Copy HDMI fix from odroid-c1. * meson8, MXQ: add boot from usb support, configurable dtb * MXQ: remove boot logo Built-in U-BOOT is used, so the logo will not be displayed anyway. * meson: kernel update: legacy -> 6.6, current -> 6.12 * Change Odroid C1 and Onecloud to community supported as build now passes --------- Co-authored-by: Igor Pecovnik <igor@armbian.com>
85 lines
3.0 KiB
Diff
85 lines
3.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Sat, 25 Apr 2020 22:03:27 +0200
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Subject: drm/meson: Update meson_vpu_init to work with Meson8/Meson8b/Meson8m2
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Don't modify the VPU_RDARB_MODE_* registers because they only exist on
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GXBB and newer SoCs. Initialize the VPU_MEM_PD_REG0 and VPU_MEM_PD_REG1
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to 0x0 (meaning: enable everything), just like vendor u-boot does for
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Meson8/Meson8b/Meson8m2.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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drivers/gpu/drm/meson/meson_drv.c | 55 ++++++----
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1 file changed, 33 insertions(+), 22 deletions(-)
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diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
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index 111111111111..222222222222 100644
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--- a/drivers/gpu/drm/meson/meson_drv.c
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+++ b/drivers/gpu/drm/meson/meson_drv.c
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@@ -135,28 +135,39 @@ static struct regmap_config meson_regmap_config = {
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static void meson_vpu_init(struct meson_drm *priv)
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{
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- u32 value;
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-
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- /*
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- * Slave dc0 and dc5 connected to master port 1.
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- * By default other slaves are connected to master port 0.
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- */
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- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
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- VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
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- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
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-
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- /* Slave dc0 connected to master port 1 */
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- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
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- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
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-
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- /* Slave dc4 and dc7 connected to master port 1 */
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- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
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- VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
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- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
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-
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- /* Slave dc1 connected to master port 1 */
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- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
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- writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
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+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
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+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0));
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+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1));
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+ } else {
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+ u32 value;
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+
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+ /*
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+ * Slave dc0 and dc5 connected to master port 1.
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+ * By default other slaves are connected to master port 0.
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+ */
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+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
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+ VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
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+ writel_relaxed(value,
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+ priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
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+
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+ /* Slave dc0 connected to master port 1 */
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+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
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+ writel_relaxed(value,
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+ priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
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+
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+ /* Slave dc4 and dc7 connected to master port 1 */
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+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
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+ VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
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+ writel_relaxed(value,
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+ priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
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+
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+ /* Slave dc1 connected to master port 1 */
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+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
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+ writel_relaxed(value,
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+ priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
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+ }
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}
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static void meson_fbdev_setup(struct meson_drm *priv)
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--
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Armbian
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