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25e60a726b
* sunxi-5.18: rebase megous patces to v5.18.3 * sunxi-5.18: Add upstream patches - tag: orange-pi-5.18-20220609-1318 * Check applicability to version 5.18.3 * sunxi-5.18: switch to version 5.18.3
55 lines
2.0 KiB
Diff
55 lines
2.0 KiB
Diff
From 8ceed49e8da109562c399f9501ca9b96880312f8 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Thu, 9 Jun 2022 13:14:06 +0200
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Subject: [PATCH 533/533] Import pgwipeout's pcie regs/ranges
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This should fix nvme SSDs again. :)
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 +++++---------
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1 file changed, 5 insertions(+), 9 deletions(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 90f3803d427c..ba706aaae72d 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -695,9 +695,6 @@ pcie2x1: pcie@fe260000 {
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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- assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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- <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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- <&cru CLK_PCIE20_AUX_NDFT>;
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clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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<&cru CLK_PCIE20_AUX_NDFT>;
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@@ -725,11 +722,11 @@ pcie2x1: pcie@fe260000 {
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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- reg = <0x3 0xc0000000 0x0 0x00400000>,
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- <0x0 0xfe260000 0x0 0x00010000>,
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- <0x3 0x00000000 0x0 0x01000000>;
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- ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000
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- 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>;
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+ reg = <0x3 0xc0000000 0x0 0x00400000>,
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+ <0x0 0xfe260000 0x0 0x00010000>,
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+ <0x3 0x3f000000 0x0 0x01000000>;
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+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
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+ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE20_POWERUP>;
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reset-names = "pipe";
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@@ -742,7 +739,6 @@ pcie_intc: legacy-interrupt-controller {
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
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};
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-
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};
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sdmmc0: mmc@fe2b0000 {
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--
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2.35.3
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