From 8ceed49e8da109562c399f9501ca9b96880312f8 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 9 Jun 2022 13:14:06 +0200 Subject: [PATCH 533/533] Import pgwipeout's pcie regs/ranges This should fix nvme SSDs again. :) Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 90f3803d427c..ba706aaae72d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -695,9 +695,6 @@ pcie2x1: pcie@fe260000 { #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xf>; - assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, <&cru CLK_PCIE20_AUX_NDFT>; @@ -725,11 +722,11 @@ pcie2x1: pcie@fe260000 { phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3568_PD_PIPE>; - reg = <0x3 0xc0000000 0x0 0x00400000>, - <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x00000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 - 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x3f000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 + 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; @@ -742,7 +739,6 @@ pcie_intc: legacy-interrupt-controller { interrupt-parent = <&gic>; interrupts = ; }; - }; sdmmc0: mmc@fe2b0000 { -- 2.35.3