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rk322x: uboot: upgrade to v2021.04-rc5

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* adapted efuse and gmac patches to u-boot v2021.04
 * enlarge SPL stack size to 0x8000 (caused u-boot freeze after SPL loading)
 * fix signed/unsigned comparison (caused u-boot freeze before SPL loading)
 * enable back size optimization flag

commit 0363085a3bec3f76db8937f24ef81fc38f89549f
Author: Paolo Sabatino <paolo.sabatino@gmail.com>
Date:   Sat Apr 3 16:02:14 2021 +0000

    rk322x: bump u-boot to v2021.01 (fix dtb load address in .its, revert offending mainline patch)
This commit is contained in:
Paolo Sabatino
2021-04-04 15:52:22 +00:00
parent 42b4396545
commit e4d895607e
6 changed files with 378 additions and 387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
config/sources/families/rk322x.conf
View File

@@ -3,7 +3,7 @@ BOOTENV_FILE='rk322x.txt'
OVERLAY_PREFIX='rk322x'
UBOOT_TARGET_MAP="all u-boot.itb;;u-boot-rk322x-with-spl.bin"
BOOTDELAY=0
BOOTBRANCH='tag:v2020.10'
BOOTBRANCH='tag:v2021.04-rc5'
ARCH=armhf
SERIALCON=ttyS2

7
patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-defconfig.patch
View File

@@ -1,9 +1,9 @@
diff --git a/configs/rk322x-box_defconfig b/configs/rk322x-box_defconfig
new file mode 100644
index 00000000..7c119dd4
index 0000000000..961dabb0e2
--- /dev/null
+++ b/configs/rk322x-box_defconfig
@@ -0,0 +1,113 @@
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x61000000
@@ -23,7 +23,6 @@ index 00000000..7c119dd4
+CONFIG_DEBUG_UART=y
+CONFIG_LOCALVERSION="-armbian"
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
@@ -40,7 +39,7 @@ index 00000000..7c119dd4
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x8000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_OPTEE=y
+CONFIG_CMD_GPIO=y

3
patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-its.patch
View File

@@ -3,7 +3,7 @@ new file mode 100644
index 00000000..a5824c61
--- /dev/null
+++ b/board/rockchip/rk322x-box/rk322x-box.its
@@ -0,0 +1,50 @@
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2017-2019 Rockchip Electronic Co.,Ltd
+ *
@@ -39,6 +39,7 @@ index 00000000..a5824c61
+ fdt {
+ description = "rk322x-box";
+ data = /incbin/("arch/arm/dts/rk322x-box.dtb");
+ load = <0x60010000>;
+ type = "flat_dt";
+ compression = "none";
+ };

461
patch/u-boot/u-boot-rk322x/u-boot-1000-rockchip.patch → patch/u-boot/u-boot-rk322x/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch
View File

@@ -1,20 +1,162 @@
From e54b3dfd77c4f72064fd62dd69f8bcc010ed0ef0 Mon Sep 17 00:00:00 2001
From: Francis Fan <francis.fan@rock-chips.com>
Date: Tue, 7 Nov 2017 17:50:11 +0800
Subject: [PATCH 1/3] rockchip: efuse: Support rk322x non-secure efuse.
From 768ff9ab40cc54e03895a46a4818d36dec150cac Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 4 Apr 2021 10:29:29 +0000
Subject: [PATCH] Enable rockchip efuse for rk322x, rk3288 and rk3328
Change-Id: Ia25df975d21d7c97cf090f0d374074c2c5cd1a58
Signed-off-by: Francis Fan <francis.fan@rock-chips.com>
Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
---
drivers/misc/rockchip-efuse.c | 75 +++++++++++++++++++++++++++++++++--
1 file changed, 71 insertions(+), 4 deletions(-)
arch/arm/dts/rk322x.dtsi | 14 +++
arch/arm/dts/rk3288.dtsi | 3 +-
configs/evb-rk3229_defconfig | 3 +
configs/evb-rk3328_defconfig | 3 +
configs/miqi-rk3288_defconfig | 2 +
configs/rock64-rk3328_defconfig | 2 +
configs/tinker-rk3288_defconfig | 1 +
configs/tinker-s-rk3288_defconfig | 1 +
drivers/misc/rockchip-efuse.c | 142 ++++++++++++++++++++++++-
include/dt-bindings/clock/rk3228-cru.h | 4 +
10 files changed, 169 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 4a8be5dabb..255e3a7a28 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -212,6 +212,20 @@
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk3228-efuse", "rockchip,rk3288-efuse";
+ reg = <0x11040000 0x20>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ cpu_id: cpu_id@7 {
+ reg = <0x7 0x10>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 22bb06cec5..381391360c 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -919,8 +919,7 @@
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
- reg = <0xffb40000 0x10000>;
- status = "disabled";
+ reg = <0xffb40000 0x20>;
};
gic: interrupt-controller@ffc01000 {
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index e708ed4909..e3ba0651fd 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -49,6 +49,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
@@ -68,3 +70,4 @@ CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_MISC_INIT_R=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 9cbfeb0279..f0acfd8abd 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -20,6 +20,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
+CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@@ -56,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 234ced5ab0..3d42e93866 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -49,6 +49,8 @@ CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index cb79cea821..dacb57165e 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -57,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 8686a66d13..b7dc845451 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -52,6 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 22714833cc..19aa314164 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index 2520c6a38e..36edf8d53d 100644
index 083ee65e0a..0fcbcfc69a 100644
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -27,6 +27,17 @@
@@ -14,6 +14,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <misc.h>
+#include <stdlib.h>
#define RK3399_A_SHIFT 16
#define RK3399_A_MASK 0x3ff
@@ -27,6 +28,24 @@
#define RK3399_STROBE BIT(1)
#define RK3399_CSB BIT(0)
@@ -27,12 +169,30 @@ index 2520c6a38e..36edf8d53d 100644
+#define RK3288_STROBE BIT(1)
+#define RK3288_CSB BIT(0)
+
+#define RK3328_INT_STATUS 0x0018
+#define RK3328_DOUT 0x0020
+#define RK3328_AUTO_CTRL 0x0024
+#define RK3328_INT_FINISH BIT(0)
+#define RK3328_AUTO_ENB BIT(0)
+#define RK3328_AUTO_RD BIT(1)
+
+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
+
struct rockchip_efuse_regs {
u32 ctrl; /* 0x00 efuse control register */
u32 dout; /* 0x04 efuse data out register */
@@ -53,7 +64,7 @@ static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
@@ -35,6 +54,10 @@ struct rockchip_efuse_regs {
u32 jtag_pass; /* 0x10 JTAG password */
u32 strobe_finish_ctrl;
/* 0x14 efuse strobe finish control register */
+ u32 int_status;/* 0x18 */
+ u32 reserved; /* 0x1c */
+ u32 dout2; /* 0x20 */
+ u32 auto_ctrl; /* 0x24 */
};
struct rockchip_efuse_plat {
@@ -53,7 +76,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
*/
struct udevice *dev;
@@ -41,7 +201,7 @@ index 2520c6a38e..36edf8d53d 100644
int ret;
/* retrieve the device */
@@ -77,7 +88,7 @@ static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
@@ -77,7 +100,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
}
U_BOOT_CMD(
@@ -50,14 +210,14 @@ index 2520c6a38e..36edf8d53d 100644
"Dump the content of the efuses",
""
);
@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
@@ -127,10 +150,110 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
return 0;
}
+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+ struct rockchip_efuse_regs *efuse =
+ (struct rockchip_efuse_regs *)plat->base;
+ u8 *buffer = buf;
@@ -97,85 +257,10 @@ index 2520c6a38e..36edf8d53d 100644
+ return 0;
+}
+
static int rockchip_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
- return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+ EFUSE_READ efuse_read = NULL;
+
+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
+ if (!efuse_read)
+ return -ENOSYS;
+
+ return (*efuse_read)(dev, offset, buf, size);
}
static const struct misc_ops rockchip_efuse_ops = {
@@ -146,7 +206,14 @@ static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
}
static const struct udevice_id rockchip_efuse_ids[] = {
- { .compatible = "rockchip,rk3399-efuse" },
+ {
+ .compatible = "rockchip,rk3288-efuse",
+ .data = (ulong)&rockchip_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3399-efuse",
+ .data = (ulong)&rockchip_rk3399_efuse_read,
+ },
{}
};
From d2794118b9ddbe8e76da4249d2de393476337e5b Mon Sep 17 00:00:00 2001
From: Joseph Chen <chenjh@rock-chips.com>
Date: Thu, 2 Aug 2018 20:33:16 +0800
Subject: [PATCH 2/3] rockchip: efuse: support rk3328 non-secure efuse
Change-Id: Ie74764ef946b79c2e9f73e9082c1cb8bbc288abb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
---
drivers/misc/rockchip-efuse.c | 66 +++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index 36edf8d53d..f2d362cef8 100644
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -36,6 +36,13 @@
#define RK3288_STROBE BIT(1)
#define RK3288_CSB BIT(0)
+#define RK3328_INT_STATUS 0x0018
+#define RK3328_DOUT 0x0020
+#define RK3328_AUTO_CTRL 0x0024
+#define RK3328_INT_FINISH BIT(0)
+#define RK3328_AUTO_ENB BIT(0)
+#define RK3328_AUTO_RD BIT(1)
+
typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
struct rockchip_efuse_regs {
@@ -46,6 +53,10 @@ struct rockchip_efuse_regs {
u32 jtag_pass; /* 0x10 JTAG password */
u32 strobe_finish_ctrl;
/* 0x14 efuse strobe finish control register */
+ u32 int_status;/* 0x18 */
+ u32 reserved; /* 0x1c */
+ u32 dout2; /* 0x20 */
+ u32 auto_ctrl; /* 0x24 */
};
struct rockchip_efuse_platdata {
@@ -181,6 +192,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
return 0;
}
+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+ struct rockchip_efuse_regs *efuse =
+ (struct rockchip_efuse_regs *)plat->base;
+ unsigned int addr_start, addr_end, addr_offset, addr_len;
@@ -226,121 +311,39 @@ index 36edf8d53d..f2d362cef8 100644
static int rockchip_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
@@ -210,6 +272,10 @@ static const struct udevice_id rockchip_efuse_ids[] = {
.compatible = "rockchip,rk3288-efuse",
.data = (ulong)&rockchip_rk3288_efuse_read,
},
- return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+ EFUSE_READ efuse_read = NULL;
+
+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
+ if (!efuse_read)
+ return -ENOSYS;
+
+ return (*efuse_read)(dev, offset, buf, size);
}
static const struct misc_ops rockchip_efuse_ops = {
@@ -146,7 +269,18 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev)
}
static const struct udevice_id rockchip_efuse_ids[] = {
- { .compatible = "rockchip,rk3399-efuse" },
+ {
+ .compatible = "rockchip,rk3288-efuse",
+ .data = (ulong)&rockchip_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3328-efuse",
+ .data = (ulong)&rockchip_rk3328_efuse_read,
+ },
{
.compatible = "rockchip,rk3399-efuse",
.data = (ulong)&rockchip_rk3399_efuse_read,
From 81fd1a75139801213cd29af46df7b282648f4559 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 23 Jan 2020 21:09:38 +0000
Subject: [PATCH 3/3] WIP: rockchip: get serial and ethaddr from efuse
---
arch/arm/dts/rk3288.dtsi | 3 +--
arch/arm/dts/rk3328.dtsi | 14 ++++++++++++++
configs/evb-rk3328_defconfig | 3 +++
configs/evb-rk3399_defconfig | 2 ++
configs/miqi-rk3288_defconfig | 2 ++
configs/rock64-rk3328_defconfig | 2 ++
configs/tinker-rk3288_defconfig | 1 +
configs/tinker-s-rk3288_defconfig | 1 +
8 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 866fc08215..b0d1b2f90a 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -910,8 +910,7 @@
+ {
+ .compatible = "rockchip,rk3399-efuse",
+ .data = (ulong)&rockchip_rk3399_efuse_read,
+ },
{}
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
- reg = <0xffb40000 0x10000>;
- status = "disabled";
+ reg = <0xffb40000 0x20>;
};
gic: interrupt-controller@ffc01000 {
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 3db40a9a1a..edd1c41f09 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -19,6 +19,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
+CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@@ -55,6 +56,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index cec8e42c5e..ac05d35392 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -50,6 +50,8 @@ CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 720b5e0424..c849bc4939 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -54,6 +54,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 83c3450839..d586b509f6 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 4925b14821..91dcc76564 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 1217d5239f..2904303034 100644
index 1217d5239f..13b2f4e4a4 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -67,6 +67,10 @@
@@ -354,58 +357,6 @@ index 1217d5239f..2904303034 100644
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 4a8be5dabb..255e3a7a28 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -212,6 +212,20 @@
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk3228-efuse", "rockchip,rk3288-efuse";
+ reg = <0x11040000 0x20>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ cpu_id: cpu_id@7 {
+ reg = <0x7 0x10>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 6b302e987c..3c0b82df1c 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -49,6 +50,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
@@ -68,3 +68,4 @@ CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_MISC_INIT_R=y
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index f2d362ce..2aa9373f 100644
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -14,6 +14,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <misc.h>
+#include <stdlib.h>
#define RK3399_A_SHIFT 16
#define RK3399_A_MASK 0x3ff
--
2.25.1

266
patch/u-boot/u-boot-rk322x/u-boot-1001-rockchip-rmii-integrated-phy.patch → patch/u-boot/u-boot-rk322x/u-boot-1002-support-rockchip-gmac-rmii.patch
View File

@@ -1,3 +1,21 @@
From e0f2e3d0a36fdb00896b94a1819f120e843b735c Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 4 Apr 2021 10:34:00 +0000
Subject: [PATCH] Support rockchip gmac rmii
---
arch/arm/dts/rk3229-evb.dts | 32 +-
arch/arm/dts/rk322x.dtsi | 8 +-
arch/arm/dts/rk3328.dtsi | 35 ++
.../include/asm/arch-rockchip/cru_rk322x.h | 1 +
configs/evb-rk3229_defconfig | 2 +
configs/evb-rk3328_defconfig | 2 +
doc/device-tree-bindings/net/phy.txt | 13 +
drivers/clk/rockchip/clk_rk322x.c | 14 +-
drivers/clk/rockchip/clk_rk3328.c | 86 +++++
drivers/net/gmac_rockchip.c | 338 ++++++++++++++++--
10 files changed, 487 insertions(+), 44 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 632cdc9bc3..f868524ae1 100644
--- a/arch/arm/dts/rk3229-evb.dts
@@ -64,11 +82,11 @@ index 4a8be5dabb..3c2861f271 100644
status = "disabled";
};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 060c84e6c0..c9419db07f 100644
index 945387e579..68cf0a7eab 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -464,6 +464,41 @@
status = "disabled";
@@ -946,6 +946,41 @@
};
};
+ gmac2phy: ethernet@ff550000 {
@@ -110,10 +128,10 @@ index 060c84e6c0..c9419db07f 100644
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
index c87c830716..15039c87be 100644
index ee12fa831f..cfbc7e92f7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
@@ -12,6 +12,7 @@
@@ -10,6 +10,7 @@
#define APLL_HZ (600 * MHz)
#define GPLL_HZ (594 * MHz)
@@ -122,7 +140,7 @@ index c87c830716..15039c87be 100644
#define CORE_PERI_HZ 150000000
#define CORE_ACLK_HZ 300000000
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index f8e648bbb4..5fd2bd3ba2 100644
index e708ed4909..382cc9b263 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -58,6 +58,8 @@ CONFIG_GMAC_ROCKCHIP=y
@@ -135,7 +153,7 @@ index f8e648bbb4..5fd2bd3ba2 100644
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 5bbdc00214..19c09e4503 100644
index 9cbfeb0279..252f0ed839 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -71,6 +71,8 @@ CONFIG_DM_REGULATOR_FIXED=y
@@ -172,10 +190,10 @@ index 6599c667b5..ca1a4a8526 100644
ethernet-phy@0 {
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index ef33adbf29..c427e0438b 100644
index dbef606d88..925aacc6d6 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -38,6 +38,7 @@ enum {
@@ -43,6 +43,7 @@ enum {
/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
@@ -183,7 +201,7 @@ index ef33adbf29..c427e0438b 100644
static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
@@ -87,11 +88,13 @@ static void rkclk_init(struct rk322x_cru *cru)
@@ -92,11 +93,13 @@ static void rkclk_init(struct rk322x_cru *cru)
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK | APLL_MODE_MASK,
GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
@@ -198,7 +216,7 @@ index ef33adbf29..c427e0438b 100644
/*
* select apll as cpu/core clock pll source and
@@ -164,7 +167,8 @@ static void rkclk_init(struct rk322x_cru *cru)
@@ -169,7 +172,8 @@ static void rkclk_init(struct rk322x_cru *cru)
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK | APLL_MODE_MASK,
GPLL_MODE_NORM << GPLL_MODE_SHIFT |
@@ -208,7 +226,7 @@ index ef33adbf29..c427e0438b 100644
}
/* Get pll rate by id */
@@ -254,11 +258,10 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
@@ -259,11 +263,10 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
ulong pll_rate;
u8 div;
@@ -222,7 +240,7 @@ index ef33adbf29..c427e0438b 100644
div = DIV_ROUND_UP(pll_rate, freq) - 1;
if (div <= 0x1f)
@@ -387,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
@@ -392,6 +395,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
@@ -231,10 +249,10 @@ index ef33adbf29..c427e0438b 100644
new_rate = rk322x_mac_set_clk(priv->cru, rate);
break;
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 8e867c58df..ba2b34c626 100644
index b825ff4cf8..7add1df309 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -93,6 +93,14 @@ enum {
@@ -97,6 +97,14 @@ enum {
PCLK_DBG_DIV_SHIFT = 0,
PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
@@ -249,7 +267,7 @@ index 8e867c58df..ba2b34c626 100644
/* CLKSEL_CON27 */
GMAC2IO_PLL_SEL_SHIFT = 7,
GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
@@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
@@ -444,6 +452,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
return ret;
}
@@ -289,7 +307,7 @@ index 8e867c58df..ba2b34c626 100644
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
@@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
@@ -640,6 +681,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_MAC2IO:
ret = rk3328_gmac2io_set_clk(priv->cru, rate);
break;
@@ -302,7 +320,7 @@ index 8e867c58df..ba2b34c626 100644
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
@@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
@@ -763,6 +810,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
return -EINVAL;
}
@@ -346,7 +364,7 @@ index 8e867c58df..ba2b34c626 100644
static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
{
switch (clk->id) {
@@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
@@ -770,6 +854,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
return rk3328_gmac2io_set_parent(clk, parent);
case SCLK_MAC2IO_EXT:
return rk3328_gmac2io_ext_set_parent(clk, parent);
@@ -356,28 +374,28 @@ index 8e867c58df..ba2b34c626 100644
case SCLK_PDM:
case SCLK_RTC32K:
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..d3f6973043 100644
index f909660484..95456693dd 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <clk.h>
@@ -11,6 +11,7 @@
#include <log.h>
#include <net.h>
#include <phy.h>
+#include <reset.h>
#include <syscon.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
@@ -23,6 +24,8 @@
@@ -26,6 +27,8 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/grf_rv1108.h>
#include <dm/pinctrl.h>
+#include <dm/of_access.h>
+#include <linux/delay.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <linux/bitops.h>
#include "designware.h"
@@ -39,21 +41,29 @@ DECLARE_GLOBAL_DATA_PTR;
struct gmac_rockchip_platdata {
@@ -43,21 +46,30 @@ DECLARE_GLOBAL_DATA_PTR;
struct gmac_rockchip_plat {
struct dw_eth_pdata dw_eth_pdata;
bool clock_input;
+ bool integrated_phy;
@@ -387,27 +405,27 @@ index e152faf083..d3f6973043 100644
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_rmii_speed)(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv);
+ int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
+ int (*fix_rgmii_speed)(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
+ void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
+ void (*integrated_phy_powerup)(struct gmac_rockchip_plat *pdata);
};
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
static int gmac_rockchip_of_to_plat(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
+ struct ofnode_phandle_args args;
const char *string;
+ int ret;
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
@@ -61,6 +71,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
@@ -65,6 +77,25 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
else
pdata->clock_input = false;
@@ -433,22 +451,22 @@ index e152faf083..d3f6973043 100644
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
@@ -74,7 +103,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
return designware_eth_ofdata_to_platdata(dev);
@@ -78,7 +109,8 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
return designware_eth_of_to_plat(dev);
}
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct px30_grf *grf;
struct clk clk_speed;
@@ -115,7 +145,43 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -119,7 +151,43 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
@@ -483,37 +501,37 @@ index e152faf083..d3f6973043 100644
+ return 0;
+}
+
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk322x_grf *grf;
int clk;
@@ -148,7 +214,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -152,7 +220,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
int clk;
@@ -174,7 +241,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -178,7 +247,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3308_grf *grf;
struct clk clk_speed;
@@ -215,7 +283,43 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -219,7 +289,43 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
@@ -548,101 +566,94 @@ index e152faf083..d3f6973043 100644
+ return 0;
+}
+
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3328_grf_regs *grf;
int clk;
@@ -248,7 +352,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -252,7 +358,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
int clk;
@@ -280,7 +385,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -284,7 +391,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
int clk;
@@ -306,7 +412,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
@@ -310,7 +418,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
+ struct dw_eth_dev *priv)
{
struct rv1108_grf *grf;
int clk, speed;
@@ -357,6 +464,28 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
@@ -361,6 +470,47 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
PX30_GMAC_PHY_INTF_SEL_RMII);
}
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
+ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
+ RK3228_RMII_MODE_MASK = BIT(10),
+ RK3228_RMII_MODE_SEL = BIT(10),
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
+ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
+ RK3228_RMII_MODE_MASK = BIT(10),
+ RK3228_RMII_MODE_SEL = BIT(10),
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_GRF_CON_RMII_MODE_MASK |
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK,
+ RK3228_GRF_CON_RMII_MODE_SEL |
+ RK3228_RMII_MODE_SEL |
+ RK3228_GMAC_PHY_INTF_SEL_RMII);
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_GRF_CON_RMII_MODE_MASK |
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK,
+ RK3228_GRF_CON_RMII_MODE_SEL |
+ RK3228_RMII_MODE_SEL |
+ RK3228_GMAC_PHY_INTF_SEL_RMII);
+}
+
static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_MASK = BIT(9),
+ RK3328_RMII_MODE = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
+ RK3328_RMII_MODE_MASK |
+ RK3328_GMAC_PHY_INTF_SEL_MASK,
+ RK3328_GMAC_PHY_INTF_SEL_RMII |
+ RK3328_RMII_MODE);
+}
+
static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk322x_grf *grf;
@@ -435,6 +564,25 @@ static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
RK3308_GMAC_PHY_INTF_SEL_RMII);
}
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_MASK = BIT(9),
+ RK3328_RMII_MODE = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
+ RK3328_RMII_MODE_MASK |
+ RK3328_GMAC_PHY_INTF_SEL_MASK,
+ RK3328_GMAC_PHY_INTF_SEL_RMII |
+ RK3328_RMII_MODE);
+}
+
static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3328_grf_regs *grf;
@@ -550,6 +698,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
@@ -554,6 +704,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
RV1108_GMAC_PHY_INTF_SEL_RMII);
}
+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
@@ -702,7 +713,7 @@ index e152faf083..d3f6973043 100644
+ udelay(30 * 1000);
+}
+
+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
@@ -764,8 +775,8 @@ index e152faf083..d3f6973043 100644
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
@@ -569,6 +837,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
@@ -573,6 +843,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
if (ret)
return ret;
@@ -775,7 +786,7 @@ index e152faf083..d3f6973043 100644
switch (eth_pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
/* Set to RGMII mode */
@@ -652,7 +923,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
@@ -656,7 +929,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break;
default:
@@ -784,16 +795,16 @@ index e152faf083..d3f6973043 100644
return -ENXIO;
}
@@ -661,18 +932,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
@@ -665,18 +938,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = dev_get_platdata(dev);
- struct eth_pdata *pdata = dev_get_plat(dev);
+ struct eth_pdata *eth_pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
int ret;
- ret = designware_eth_init(priv, pdata->enetaddr);
@@ -805,25 +816,25 @@ index e152faf083..d3f6973043 100644
return ret;
+
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = ops->fix_rgmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = ops->fix_rmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ default:
+ debug("%s: no interface defined!\n", __func__);
+ return -ENXIO;
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = ops->fix_rgmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = ops->fix_rmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ default:
+ debug("%s: no interface defined!\n", __func__);
+ return -ENXIO;
+ }
+
ret = designware_eth_enable(priv);
if (ret)
return ret;
@@ -690,42 +976,48 @@ const struct eth_ops gmac_rockchip_eth_ops = {
@@ -694,42 +982,48 @@ const struct eth_ops gmac_rockchip_eth_ops = {
};
const struct rk_gmac_ops px30_gmac_ops = {
@@ -880,3 +891,6 @@ index e152faf083..d3f6973043 100644
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
--
2.25.1

26
patch/u-boot/u-boot-rk322x/u-boot-1004-fix-signed-unsigned-comparison-causing-massive-heada.patch Normal file
View File

@@ -0,0 +1,26 @@
From 3f12642b5947ee63e1e6fe08df558206d1b4daff Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 3 Apr 2021 19:38:20 +0000
Subject: [PATCH] Fix signed/unsigned comparison causing massive headache on
gcc-arm >= 8.0 due to valid images being unable to boot
---
drivers/core/lists.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index e06e4e853d..c355f0752f 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -58,7 +58,7 @@ static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only)
const int n_ents = ll_entry_count(struct driver_info, driver_info);
bool missing_parent = false;
int result = 0;
- uint idx;
+ int idx;
/*
* Do one iteration through the driver_info records. For of-platdata,
--
2.25.1