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Fix mvebu patches once more

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This commit is contained in:
Heisath
2021-11-25 09:03:40 +01:00
parent 38455f7f12
commit d861f37a9f
4 changed files with 341 additions and 175 deletions
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217
patch/kernel/archive/mvebu-5.15/10-mvebu-clearfog-pcie-updates.patch.disabled → patch/kernel/archive/mvebu-5.10/10-mvebu-clearfog-pcie-updates.patch
View File

@@ -1,18 +1,17 @@
From cf2cb15fb44ee05043232230cbaba444aa943b9c Mon Sep 17 00:00:00 2001
From 527312a74d9d85ba9520c8cb2979004f6d23c4da Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue, 29 Nov 2016 10:13:46 +0000
Subject: mvebu/clearfog pcie updates
Subject: [PATCH] mvebu/clearfog pcie updates
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++++++++++-
drivers/pci/pci-bridge-emul.c | 2 +
drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++-
drivers/pci/pci-bridge-emul.c | 83 ++++++++++++---------
drivers/pci/pci-bridge-emul.h | 15 ++++
drivers/pci/pcie/aspm.c | 6 ++
drivers/pci/pcie/portdrv_core.c | 2 +
4 files changed, 121 insertions(+), 1 deletion(-)
5 files changed, 184 insertions(+), 34 deletions(-)
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index ed13e81cd691..2dc9f457bc76 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -52,7 +52,14 @@
@@ -30,7 +29,7 @@ index ed13e81cd691..2dc9f457bc76 100644
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_STAT_OFF 0x1a04
@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_ch
&port->memwin);
}
@@ -85,7 +84,7 @@ index ed13e81cd691..2dc9f457bc76 100644
static pci_bridge_emul_read_status_t
mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
int reg, u32 *value)
@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
return PCI_BRIDGE_EMUL_HANDLED;
}
@@ -116,7 +115,7 @@ index ed13e81cd691..2dc9f457bc76 100644
static void
mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
int reg, u32 old, u32 new, u32 mask)
@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(st
mvebu_pcie_handle_iobase_change(port);
if ((old ^ new) & PCI_COMMAND_MEMORY)
mvebu_pcie_handle_membase_change(port);
@@ -126,7 +125,7 @@ index ed13e81cd691..2dc9f457bc76 100644
break;
}
@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(st
mvebu_pcie_handle_iobase_change(port);
break;
@@ -138,7 +137,7 @@ index ed13e81cd691..2dc9f457bc76 100644
case PCI_PRIMARY_BUS:
mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
break;
@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
switch (reg) {
case PCI_EXP_DEVCTL:
@@ -149,7 +148,7 @@ index ed13e81cd691..2dc9f457bc76 100644
/*
* Armada370 data says these bits must always
* be zero when in root complex mode.
@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
case PCI_EXP_RTSTA:
mvebu_writel(port, new, PCIE_RC_RTSTA);
break;
@@ -175,7 +174,7 @@ index ed13e81cd691..2dc9f457bc76 100644
}
}
@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_
.write_base = mvebu_pci_bridge_emul_base_conf_write,
.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
@@ -184,11 +183,9 @@ index ed13e81cd691..2dc9f457bc76 100644
};
/*
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index fbff7da94245..50b1b48f6e0d 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -153,6 +153,7 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
@@ -151,6 +151,7 @@ static const struct pci_bridge_reg_behav
.rw = (GENMASK(7, 0) |
((PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_SERR |
@@ -196,7 +193,7 @@ index fbff7da94245..50b1b48f6e0d 100644
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_MASTER_ABORT |
@@ -269,6 +270,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
@@ -264,6 +265,7 @@ int pci_bridge_emul_init(struct pci_brid
bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
bridge->conf.cache_line_size = 0x10;
bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
@@ -204,11 +201,180 @@ index fbff7da94245..50b1b48f6e0d 100644
bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
sizeof(pci_regs_behavior),
GFP_KERNEL);
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 013a47f587ce..26ee590caec0 100644
@@ -323,25 +325,26 @@ int pci_bridge_emul_conf_read(struct pci
__le32 *cfgspace;
const struct pci_bridge_reg_behavior *behavior;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
- *value = 0;
- return PCIBIOS_SUCCESSFUL;
- }
-
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
+ if (reg < PCI_CAP_PCIE_START) {
+ read_op = bridge->ops->read_base;
+ cfgspace = (__le32 *) &bridge->conf;
+ behavior = bridge->pci_regs_behavior;
+ } else if (!bridge->has_pcie) {
*value = 0;
return PCIBIOS_SUCCESSFUL;
- }
-
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
+ } else if (reg < PCI_CAP_PCIE_END) {
reg -= PCI_CAP_PCIE_START;
read_op = bridge->ops->read_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
+ } else if (reg < 0x100) {
+ *value = 0;
+ return PCIBIOS_SUCCESSFUL;
} else {
- read_op = bridge->ops->read_base;
- cfgspace = (__le32 *) &bridge->conf;
- behavior = bridge->pci_regs_behavior;
+ reg -= 0x100;
+ read_op = bridge->ops->read_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
if (read_op)
@@ -349,15 +352,20 @@ int pci_bridge_emul_conf_read(struct pci
else
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
- *value = le32_to_cpu(cfgspace[reg / 4]);
+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
+ if (cfgspace)
+ *value = le32_to_cpu(cfgspace[reg / 4]);
+ else
+ *value = 0;
+ }
/*
* Make sure we never return any reserved bit with a value
* different from 0.
*/
- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
- behavior[reg / 4].w1c;
+ if (behavior)
+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
+ behavior[reg / 4].w1c;
if (size == 1)
*value = (*value >> (8 * (where & 3))) & 0xff;
@@ -385,12 +393,6 @@ int pci_bridge_emul_conf_write(struct pc
__le32 *cfgspace;
const struct pci_bridge_reg_behavior *behavior;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
- return PCIBIOS_SUCCESSFUL;
-
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
- return PCIBIOS_SUCCESSFUL;
-
shift = (where & 0x3) * 8;
if (size == 4)
@@ -413,28 +413,44 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
- reg -= PCI_CAP_PCIE_START;
- write_op = bridge->ops->write_pcie;
- cfgspace = (__le32 *) &bridge->pcie_conf;
- behavior = bridge->pcie_cap_regs_behavior;
- } else {
+
+ if (reg < PCI_CAP_PCIE_START) {
write_op = bridge->ops->write_base;
cfgspace = (__le32 *) &bridge->conf;
behavior = bridge->pci_regs_behavior;
+ } else if (!bridge->has_pcie) {
+ return PCIBIOS_SUCCESSFUL;
+ } else if (reg < PCI_CAP_PCIE_END) {
+ reg -= PCI_CAP_PCIE_START;
+ write_op = bridge->ops->write_pcie;
+ cfgspace = (__le32 *) &bridge->pcie_conf;
+ behavior = bridge->pcie_cap_regs_behavior;
+ } else if (reg < 0x100) {
+ return PCIBIOS_SUCCESSFUL;
+ } else {
+ reg -= 0x100;
+ write_op = bridge->ops->write_ext;
+ cfgspace = NULL;
+ behavior = NULL;
+ }
+
+ if (behavior) {
+ /* Keep all bits, except the RW bits */
+ new = old & (~mask | ~behavior[reg / 4].rw);
+
+ /* Update the value of the RW bits */
+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
+
+ /* Clear the W1C bits */
+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ } else {
+ new = old & ~mask;
+ new |= (value << shift) & mask;
}
-
- /* Keep all bits, except the RW bits */
- new = old & (~mask | ~behavior[reg / 4].rw);
-
- /* Update the value of the RW bits */
- new |= (value << shift) & (behavior[reg / 4].rw & mask);
-
- /* Clear the W1C bits */
- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
-
- /* Save the new value with the cleared W1C bits into the cfgspace */
- cfgspace[reg / 4] = cpu_to_le32(new);
+
+ /* Save the new value with the cleared W1C bits into the cfgspace */
+ if (cfgspace)
+ cfgspace[reg / 4] = cpu_to_le32(new);
/*
* Clear the W1C bits not specified by the write mask, so that the
--- a/drivers/pci/pci-bridge-emul.h
+++ b/drivers/pci/pci-bridge-emul.h
@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
*/
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
int reg, u32 *value);
+
+ /*
+ * Same as ->read_base(), except it is for reading from the
+ * PCIe extended capability configuration space.
+ */
+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
+ int reg, u32 *value);
+
/*
* Called when writing to the regular PCI bridge configuration
* space. old is the current value, new is the new value being
@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
*/
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
u32 old, u32 new, u32 mask);
+
+ /*
+ * Same as ->write_base(), except it is for writing from the
+ * PCIe extended capability configuration space.
+ */
+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
+ u32 old, u32 new, u32 mask);
};
struct pci_bridge_reg_behavior;
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pc
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
@@ -221,11 +387,9 @@ index 013a47f587ce..26ee590caec0 100644
/*
* Setup L0s state
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 3ee63968deaa..52c61b14af50 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -327,6 +327,7 @@ int pcie_port_device_register(struct pci_dev *dev)
@@ -325,6 +325,7 @@ int pcie_port_device_register(struct pci
/* Get and check PCI Express port services */
capabilities = get_port_device_capability(dev);
@@ -233,7 +397,7 @@ index 3ee63968deaa..52c61b14af50 100644
if (!capabilities)
return 0;
@@ -339,6 +340,7 @@ int pcie_port_device_register(struct pci_dev *dev)
@@ -337,6 +338,7 @@ int pcie_port_device_register(struct pci
* if that is to be used.
*/
status = pcie_init_service_irqs(dev, irqs, capabilities);
@@ -241,6 +405,3 @@ index 3ee63968deaa..52c61b14af50 100644
if (status) {
capabilities &= PCIE_PORT_SERVICE_HP;
if (!capabilities)
--
cgit v1.2.3

2
patch/kernel/archive/mvebu-5.10/10-mvebu-clearfog-pcie-updates.patch.disabled → patch/kernel/archive/mvebu-5.15/10-mvebu-clearfog-pcie-updates.patch
View File

@@ -1,4 +1,4 @@
From cf2cb15fb44ee05043232230cbaba444aa943b9c Mon Sep 17 00:00:00 2001
From 7d1f8c149e244c4045cffc1950b78320e2e544be Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue, 29 Nov 2016 10:13:46 +0000
Subject: mvebu/clearfog pcie updates

152
patch/kernel/archive/mvebu-5.15/20-pcie-bridge-emul.patch
View File

@@ -1,4 +1,4 @@
From a99411d3be343e87de6e89df7b96913d723b8b17 Mon Sep 17 00:00:00 2001
From ca6a33ed3efd3a3d569744290860d0d827ca4196 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 2 Feb 2021 13:45:28 +0000
Subject: PCI: pci-bridge-emul: re-arrange register tests
@@ -101,4 +101,154 @@ index fdaf86a888b7..9988078e7b0e 100644
--
cgit v1.2.3
From 8bc25ed1e6eb38000f91e1eb71bc097012f5dcb1 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 2 Feb 2021 13:57:04 +0000
Subject: PCI: pci-bridge-emul: add support for PCIe extended capabilities
Add support for PCIe extended capabilities, which we just redirect to
the emulating driver.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/pci/pci-bridge-emul.c | 52 +++++++++++++++++++++++++++++++------------
drivers/pci/pci-bridge-emul.h | 15 +++++++++++++
2 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 9988078e7b0e..fbff7da94245 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -343,10 +343,16 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
read_op = bridge->ops->read_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
- } else {
- /* Beyond our PCIe space */
+ } else if (reg < PCI_CFG_SPACE_SIZE) {
+ /* Rest of PCI space not implemented */
*value = 0;
return PCIBIOS_SUCCESSFUL;
+ } else {
+ /* PCIe extended capability space */
+ reg -= PCI_CFG_SPACE_SIZE;
+ read_op = bridge->ops->read_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
if (read_op)
@@ -354,15 +360,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
else
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
- *value = le32_to_cpu(cfgspace[reg / 4]);
+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
+ if (cfgspace)
+ *value = le32_to_cpu(cfgspace[reg / 4]);
+ else
+ *value = 0;
+ }
/*
* Make sure we never return any reserved bit with a value
* different from 0.
*/
- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
- behavior[reg / 4].w1c;
+ if (behavior)
+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
+ behavior[reg / 4].w1c;
if (size == 1)
*value = (*value >> (8 * (where & 3))) & 0xff;
@@ -404,8 +415,15 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
write_op = bridge->ops->write_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
- } else {
+ } else if (reg < PCI_CFG_SPACE_SIZE) {
+ /* Rest of PCI space not implemented */
return PCIBIOS_SUCCESSFUL;
+ } else {
+ /* PCIe extended capability space */
+ reg -= PCI_CFG_SPACE_SIZE;
+ write_op = bridge->ops->write_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
shift = (where & 0x3) * 8;
@@ -443,17 +443,24 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
- /* Keep all bits, except the RW bits */
- new = old & (~mask | ~behavior[reg / 4].rw);
-
- /* Update the value of the RW bits */
- new |= (value << shift) & (behavior[reg / 4].rw & mask);
-
- /* Clear the W1C bits */
- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
-
- /* Save the new value with the cleared W1C bits into the cfgspace */
- cfgspace[reg / 4] = cpu_to_le32(new);
+
+ if (behavior) {
+ /* Keep all bits, except the RW bits */
+ new = old & (~mask | ~behavior[reg / 4].rw);
+
+ /* Update the value of the RW bits */
+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
+
+ /* Clear the W1C bits */
+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ } else {
+ new = old & ~mask;
+ new |= (value << shift) & mask;
+ }
+
+ /* Save the new value with the cleared W1C bits into the cfgspace */
+ if (cfgspace)
+ cfgspace[reg / 4] = cpu_to_le32(new);
/*
* Clear the W1C bits not specified by the write mask, so that the
diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h
index 49bbd37ee318..2552ab660b08 100644
--- a/drivers/pci/pci-bridge-emul.h
+++ b/drivers/pci/pci-bridge-emul.h
@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
*/
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
int reg, u32 *value);
+
+ /*
+ * Same as ->read_base(), except it is for reading from the
+ * PCIe extended capability configuration space.
+ */
+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
+ int reg, u32 *value);
+
/*
* Called when writing to the regular PCI bridge configuration
* space. old is the current value, new is the new value being
@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
*/
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
u32 old, u32 new, u32 mask);
+
+ /*
+ * Same as ->write_base(), except it is for writing from the
+ * PCIe extended capability configuration space.
+ */
+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
+ u32 old, u32 new, u32 mask);
};
struct pci_bridge_reg_behavior;
--
cgit v1.2.3

145
patch/kernel/archive/mvebu-5.15/21-pcie-bridge-emul.patch.disabled
View File

@@ -1,145 +0,0 @@
From bab91927c8694e5f3a7e834343d2ec7163da4988 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 2 Feb 2021 13:57:04 +0000
Subject: PCI: pci-bridge-emul: add support for PCIe extended capabilities
Add support for PCIe extended capabilities, which we just redirect to
the emulating driver.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/pci/pci-bridge-emul.c | 52 +++++++++++++++++++++++++++++++------------
drivers/pci/pci-bridge-emul.h | 15 +++++++++++++
2 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 9988078e7b0e..fbff7da94245 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -343,10 +343,16 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
read_op = bridge->ops->read_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
- } else {
- /* Beyond our PCIe space */
+ } else if (reg < PCI_CFG_SPACE_SIZE) {
+ /* Rest of PCI space not implemented */
*value = 0;
return PCIBIOS_SUCCESSFUL;
+ } else {
+ /* PCIe extended capability space */
+ reg -= PCI_CFG_SPACE_SIZE;
+ read_op = bridge->ops->read_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
if (read_op)
@@ -354,15 +360,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
else
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
- *value = le32_to_cpu(cfgspace[reg / 4]);
+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
+ if (cfgspace)
+ *value = le32_to_cpu(cfgspace[reg / 4]);
+ else
+ *value = 0;
+ }
/*
* Make sure we never return any reserved bit with a value
* different from 0.
*/
- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
- behavior[reg / 4].w1c;
+ if (behavior)
+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
+ behavior[reg / 4].w1c;
if (size == 1)
*value = (*value >> (8 * (where & 3))) & 0xff;
@@ -404,8 +415,15 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
write_op = bridge->ops->write_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
- } else {
+ } else if (reg < PCI_CFG_SPACE_SIZE) {
+ /* Rest of PCI space not implemented */
return PCIBIOS_SUCCESSFUL;
+ } else {
+ /* PCIe extended capability space */
+ reg -= PCI_CFG_SPACE_SIZE;
+ write_op = bridge->ops->write_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
shift = (where & 0x3) * 8;
@@ -423,16 +441,22 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
- /* Keep all bits, except the RW bits */
- new = old & (~mask | ~behavior[reg / 4].rw);
+ if (behavior) {
+ /* Keep all bits, except the RW bits */
+ new = old & (~mask | ~behavior[reg / 4].rw);
- /* Update the value of the RW bits */
- new |= (value << shift) & (behavior[reg / 4].rw & mask);
+ /* Update the value of the RW bits */
+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
- /* Clear the W1C bits */
- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ /* Clear the W1C bits */
+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ } else {
+ new = old & ~mask;
+ new |= (value << shift) & mask;
+ }
- cfgspace[reg / 4] = cpu_to_le32(new);
+ if (cfgspace)
+ cfgspace[reg / 4] = cpu_to_le32(new);
if (write_op)
write_op(bridge, reg, old, new, mask);
diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h
index b31883022a8e..5f64560aaa26 100644
--- a/drivers/pci/pci-bridge-emul.h
+++ b/drivers/pci/pci-bridge-emul.h
@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
*/
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
int reg, u32 *value);
+
+ /*
+ * Same as ->read_base(), except it is for reading from the
+ * PCIe extended capability configuration space.
+ */
+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
+ int reg, u32 *value);
+
/*
* Called when writing to the regular PCI bridge configuration
* space. old is the current value, new is the new value being
@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
*/
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
u32 old, u32 new, u32 mask);
+
+ /*
+ * Same as ->write_base(), except it is for writing from the
+ * PCIe extended capability configuration space.
+ */
+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
+ u32 old, u32 new, u32 mask);
};
struct pci_bridge_reg_behavior;
--
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