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u-boot: v2025.01: Add bananapi-m4-berry support
This commit is contained in:
The-going
@@ -0,0 +1,50 @@
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From 1fbb4fc8a902b1ceb73e5848000b340715886d4d Mon Sep 17 00:00:00 2001
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From: The-going <48602507+The-going@users.noreply.github.com>
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Date: Tue, 21 Jan 2025 23:04:54 +0300
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Subject: [PATCH 1/6] u-boot: configs: Add sun50i-h618-bananapi-m4berry
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defconfig
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---
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configs/bananapi_m4_berry_defconfig | 30 +++++++++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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create mode 100644 configs/bananapi_m4_berry_defconfig
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diff --git a/configs/bananapi_m4_berry_defconfig b/configs/bananapi_m4_berry_defconfig
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new file mode 100644
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index 00000000000..c5a97c739a0
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--- /dev/null
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+++ b/configs/bananapi_m4_berry_defconfig
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@@ -0,0 +1,30 @@
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+CONFIG_ARM=y
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+CONFIG_ARCH_SUNXI=y
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+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-bananapi-m4-berry"
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+CONFIG_OF_UPSTREAM=y
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+CONFIG_SPL=y
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+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
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+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
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+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
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+CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee
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+CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080
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+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
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+CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524
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+CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f
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+CONFIG_MACH_SUN50I_H616=y
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+CONFIG_SUNXI_DRAM_H616_LPDDR4=y
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+CONFIG_DRAM_CLK=792
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+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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+CONFIG_R_I2C_ENABLE=y
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+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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+CONFIG_SPL_I2C=y
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+CONFIG_SPL_SYS_I2C_LEGACY=y
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+CONFIG_SYS_I2C_MVTWSI=y
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+CONFIG_SYS_I2C_SLAVE=0x7f
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+CONFIG_SYS_I2C_SPEED=400000
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+CONFIG_SUN8I_EMAC=y
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+CONFIG_SUPPORT_EMMC_BOOT=y
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+CONFIG_AXP313_POWER=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_MUSB_GADGET=y
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--
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2.35.3
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@@ -0,0 +1,129 @@
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From 573dcff4016af4570a577d7e72c54538d911ab30 Mon Sep 17 00:00:00 2001
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From: The-going <48602507+The-going@users.noreply.github.com>
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Date: Sun, 16 Feb 2025 16:01:17 +0300
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Subject: [PATCH 2/6] dts: upstream: sun50i-h616: add emac1 node, pinctrl pins
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---
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.../src/arm64/allwinner/sun50i-h616.dtsi | 69 ++++++++++++++++++-
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1 file changed, 67 insertions(+), 2 deletions(-)
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diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
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index e88c1fbac6a..278ffdf2264 100644
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--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
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+++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
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@@ -100,12 +100,12 @@
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ranges;
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/*
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- * 256 KiB reserved for Trusted Firmware-A (BL31).
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+ * 512 KiB reserved for Trusted Firmware-A (BL31).
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* This is added by BL31 itself, but some bootloaders fail
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* to propagate this into the DTB handed to kernels.
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*/
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secmon@40000000 {
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- reg = <0x0 0x40000000 0x0 0x40000>;
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+ reg = <0x0 0x40000000 0x0 0x80000>;
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no-map;
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};
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};
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@@ -248,11 +248,23 @@
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drive-strength = <40>;
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};
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+ rmii_pins: rmii-pins {
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+ pins = "PA0", "PA1", "PA2", "PA3", "PA4",
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+ "PA5", "PA6", "PA7", "PA8", "PA9";
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+ function = "emac1";
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+ drive-strength = <40>;
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+ };
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+
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i2c0_pins: i2c0-pins {
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pins = "PI5", "PI6";
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function = "i2c0";
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};
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+ i2c3_pa_pins: i2c3-pa-pins {
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+ pins = "PA10", "PA11";
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+ function = "i2c3";
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+ };
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+
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i2c3_ph_pins: i2c3-ph-pins {
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pins = "PH4", "PH5";
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function = "i2c3";
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@@ -313,6 +325,12 @@
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function = "spi1";
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};
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+ /omit-if-no-ref/
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+ spi1_cs1_pin: spi1-cs1-pin {
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+ pins = "PH9";
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+ function = "spi1";
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+ };
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+
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spdif_tx_pin: spdif-tx-pin {
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pins = "PH4";
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function = "spdif";
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@@ -335,6 +353,24 @@
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function = "uart1";
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};
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+ /omit-if-no-ref/
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+ uart2_pins: uart2-pins {
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+ pins = "PH5", "PH6";
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+ function = "uart2";
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+ };
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+
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+ /omit-if-no-ref/
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+ uart2_rts_cts_pins: uart2-rts-cts-pins {
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+ pins = "PH7", "PH8";
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+ function = "uart2";
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+ };
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+
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+ /omit-if-no-ref/
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+ uart5_pins: uart5-pins {
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+ pins = "PH2", "PH3";
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+ function = "uart5";
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+ };
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+
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/omit-if-no-ref/
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x32clk_fanout_pin: x32clk-fanout-pin {
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pins = "PG10";
|
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@@ -630,6 +666,35 @@
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};
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};
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+ emac1: ethernet@5030000 {
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+ compatible = "allwinner,sunxi-gmac";
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+ reg = <0x05030000 0x10000>,
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+ <0x03000034 0x4>;
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+ reg-names = "gmac1_reg","ephy_reg";
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+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "gmacirq";
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+ resets = <&ccu RST_BUS_EMAC1>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>;
|
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+ clock-names = "bus-emac1","emac-25m";
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+ pinctrl-0 = <&rmii_pins>;
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+ pinctrl-names = "default";
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+ phy-mode = "rmii";
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+ tx-delay = <7>;
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+ rx-delay = <31>;
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+ phy-rst;
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+ gmac-power0;
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+ gmac-power1;
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+ gmac-power2;
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+ status = "disabled";
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+
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+ mdio1: mdio {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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spdif: spdif@5093000 {
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compatible = "allwinner,sun50i-h616-spdif";
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reg = <0x05093000 0x400>;
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--
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2.35.3
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@@ -0,0 +1,458 @@
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From 505d989ac115c9efe43742fe3fba557c271e944b Mon Sep 17 00:00:00 2001
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From: The-going <48602507+The-going@users.noreply.github.com>
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Date: Sat, 25 Jan 2025 19:30:16 +0300
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Subject: [PATCH 3/6] dts: upstream: arm64: Add
|
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sun50i-h618-bananapi-m4-berry.dts
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---
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.../sun50i-h618-bananapi-m4-berry.dts | 438 ++++++++++++++++++
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1 file changed, 438 insertions(+)
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create mode 100644 dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts
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diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts
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new file mode 100644
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index 00000000000..95280c81056
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--- /dev/null
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+++ b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts
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@@ -0,0 +1,438 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+/*
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+ * Copyright (C) 2020 Arm Ltd.
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+ */
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+
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+/dts-v1/;
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+
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+#include "sun50i-h616.dtsi"
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+#include "sun50i-h616-cpu-opp.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "BananaPi M4 Berry";
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+ compatible = "BiPai,bananapi-m4berry", "allwinner,sun50i-h616";
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+
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+ aliases {
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+ ethernet0 = &emac0;
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+ ethernet1 = &emac1;
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+ serial0 = &uart0;
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+ serial5 = &uart5;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds: leds {
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+ compatible = "gpio-leds";
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+
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+ led-greed {
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+ label = "red_led";
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+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
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+ linux,default-trigger = "heartbeat";
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+ };
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+ };
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+
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+ wifi_usb {
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+ compatible = "usb-wifi";
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+ status = "okay";
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+ power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */
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+ };
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+
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+ reg_vcc5v: reg-vcc5v {
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+ /* board wide 5V supply directly from the USB-C socket */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-5v";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_usb1_vbus: reg-usb1-vbus {
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+ /* separate discrete regulator for the USB ports */
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+ compatible = "regulator-fixed";
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+ regulator-min-microvolt = <5000000>;
|
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <®_vcc5v>;
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+ };
|
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+
|
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+ reg_gmac_3v3: reg-gmac-3v3 {
|
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+ compatible = "regulator-fixed";
|
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+ regulator-name = "gmac-3v3";
|
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+ regulator-min-microvolt = <3300000>;
|
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+ regulator-max-microvolt = <3300000>;
|
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+ regulator-always-on;
|
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+ vin-supply = <®_vcc5v>;
|
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+ };
|
||||
+
|
||||
+ ac200_pwm_clk: ac200_clk {
|
||||
+ compatible = "pwm-clock";
|
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+ #clock-cells = <0>;
|
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+ // pwm5 period_ns = 500 > 334 for select 24M clock.
|
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+ pwms = <&pwm 5 500 0>;
|
||||
+ clock-frequency = <2000000>;
|
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+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ soc {
|
||||
+ pwm: pwm@300a000 {
|
||||
+ compatible = "allwinner,sun50i-h616-pwm";
|
||||
+ reg = <0x0300a000 0x400>;
|
||||
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
|
||||
+ clock-names = "mod", "bus";
|
||||
+ resets = <&ccu RST_BUS_PWM>;
|
||||
+ pwm-number = <6>;
|
||||
+ pwm-base = <0x0>;
|
||||
+ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ pwm0: pwm0@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm0";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm0_pd_pin>;
|
||||
+ };
|
||||
+
|
||||
+ pwm1: pwm1@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm1";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm1_ph_pin>;
|
||||
+ };
|
||||
+
|
||||
+ pwm2: pwm2@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm2_ph_pin>;
|
||||
+ };
|
||||
+
|
||||
+ pwm3: pwm3@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm3";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm3_ph_pin>;
|
||||
+ };
|
||||
+
|
||||
+ pwm4: pwm4@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm4";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm4_ph_pin>;
|
||||
+ };
|
||||
+
|
||||
+ pwm5: pwm5@0300a000 {
|
||||
+ compatible = "allwinner,sunxi-pwm5";
|
||||
+ reg = <0x0 0x0300a015 0x0 0x4>;
|
||||
+ reg_base = <0x0300a000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm5_pin>;
|
||||
+ clk_bypass_output = <0x1>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pio {
|
||||
+ vcc-pc-supply = <®_aldo1>;
|
||||
+ vcc-pf-supply = <®_dldo1>;
|
||||
+ vcc-pg-supply = <®_dldo1>;
|
||||
+ vcc-ph-supply = <®_dldo1>;
|
||||
+ vcc-pi-supply = <®_dldo1>;
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm0_pd_pin: pwm0-pd-pin {
|
||||
+ pins = "PD28";
|
||||
+ function = "pwm0";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm1_pg_pin: pwm1-pg-pin {
|
||||
+ pins = "PG19";
|
||||
+ function = "pwm1";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm1_ph_pin: pwm1-ph-pin {
|
||||
+ pins = "PH3";
|
||||
+ function = "pwm1";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm2_ph_pin: pwm2-ph-pin {
|
||||
+ pins = "PH2";
|
||||
+ function = "pwm2";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm3_ph_pin: pwm3-ph-pin {
|
||||
+ pins = "PH0";
|
||||
+ function = "pwm3";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm4_ph_pin: pwm4-ph-pin {
|
||||
+ pins = "PH1";
|
||||
+ function = "pwm4";
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pwm5_pin: pwm5-pin {
|
||||
+ pins = "PA12";
|
||||
+ function = "pwm5";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&r_i2c {
|
||||
+ pinctrl-0 = <&r_i2c_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ axp313a: pmic@36 {
|
||||
+ compatible = "x-powers,axp313a";
|
||||
+ reg = <0x36>;
|
||||
+
|
||||
+ vin1-supply = <®_vcc5v>;
|
||||
+ vin2-supply = <®_vcc5v>;
|
||||
+ vin3-supply = <®_vcc5v>;
|
||||
+
|
||||
+ regulators{
|
||||
+ reg_dcdc1: dcdc1 {
|
||||
+ regulator-name = "dcdc1-gpu";
|
||||
+ regulator-min-microvolt = <810000>;
|
||||
+ regulator-max-microvolt = <990000>;
|
||||
+ regulator-step-delay-us = <25>;
|
||||
+ regulator-final-delay-us = <50>;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdc2: dcdc2 {
|
||||
+ regulator-name = "dcdc2-cpu";
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1200000>;
|
||||
+ regulator-step-delay-us = <25>;
|
||||
+ regulator-final-delay-us = <50>;
|
||||
+ regulator-ramp-delay = <200>;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ reg_dcdc3: dcdc3 {
|
||||
+ regulator-name = "dcdc3-dram";
|
||||
+ regulator-min-microvolt = <1100000>;
|
||||
+ regulator-max-microvolt = <1100000>;
|
||||
+ regulator-step-delay-us = <25>;
|
||||
+ regulator-final-delay-us = <50>;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ reg_aldo1: aldo1 {
|
||||
+ regulator-name = "aldo1-1v8";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-step-delay-us = <25>;
|
||||
+ regulator-final-delay-us = <50>;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ reg_dldo1: dldo1 {
|
||||
+ regulator-name = "dldo1-3v3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-step-delay-us = <25>;
|
||||
+ regulator-final-delay-us = <50>;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emac0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ext_rgmii_pins>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-handle = <&ext_rgmii_phy>;
|
||||
+ allwinner,rx-delay-ps = <3100>;
|
||||
+ allwinner,tx-delay-ps = <700>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ ext_rgmii_phy: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emac1 {
|
||||
+ phy-mode = "rmii";
|
||||
+ phy-handle = <&rmii_phy>;
|
||||
+ phy-supply = <®_dldo1>;
|
||||
+ allwinner,rx-delay-ps = <3100>;
|
||||
+ allwinner,tx-delay-ps = <700>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rmii_phy: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mmc0 {
|
||||
+ vmmc-supply = <®_dldo1>;
|
||||
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
|
||||
+ bus-width = <4>;
|
||||
+ max-frequency = <50000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mmc2 {
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ vmmc-supply = <®_dldo1>;
|
||||
+ bus-width = <8>;
|
||||
+ non-removable;
|
||||
+ cap-mmc-hw-reset;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_ph_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbotg {
|
||||
+ /*
|
||||
+ * PHY0 pins are connected to a USB-C socket, but a role switch
|
||||
+ * is not implemented: both CC pins are pulled to GND.
|
||||
+ * The VBUS pins power the device, so a fixed peripheral mode
|
||||
+ * is the best choice.
|
||||
+ * The board can be powered via GPIOs, in this case port0 *can*
|
||||
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
|
||||
+ * then provided by the GPIOs. Any user of this setup would
|
||||
+ * need to adjust the DT accordingly: dr_mode set to "host",
|
||||
+ * enabling OHCI0 and EHCI0.
|
||||
+ */
|
||||
+ dr_mode = "peripheral";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbphy {
|
||||
+ usb1_vbus-supply = <®_vcc5v>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ehci0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&ehci1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ehci2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ehci3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ohci0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&ohci1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ohci2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ohci3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&ir {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2c3_pa_pins>;
|
||||
+
|
||||
+ ac200_x: mfd@10 {
|
||||
+ compatible = "x-powers,ac200-sunxi";
|
||||
+ reg = <0x10>;
|
||||
+ clocks = <&ac200_pwm_clk>;
|
||||
+ // ephy id
|
||||
+ nvmem-cells = <&ephy_calibration>;
|
||||
+ nvmem-cell-names = "calibration";
|
||||
+
|
||||
+ ac200_ephy: phy {
|
||||
+ compatible = "x-powers,ac200-ephy-sunxi";
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart2_pins>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart5 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart5_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spi1 {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
|
||||
+
|
||||
+ spidev@1 {
|
||||
+ compatible = "rohm,dh2228fv";
|
||||
+ status = "okay";
|
||||
+ reg = <1>;
|
||||
+ spi-max-frequency = <1000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <®_dcdc2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sid {
|
||||
+ ephy_calibration: ephy-calibration@2c {
|
||||
+ reg = <0x2c 0x2>;
|
||||
+ };
|
||||
+};
|
||||
--
|
||||
2.35.3
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
From 783a11dad0e9c049e12efebbbd876703002ff992 Mon Sep 17 00:00:00 2001
|
||||
From: The-going <48602507+The-going@users.noreply.github.com>
|
||||
Date: Fri, 21 Feb 2025 14:21:13 +0300
|
||||
Subject: [PATCH 4/6] u-boot: v2025: DEBUG sunxi mmc fix logik
|
||||
|
||||
---
|
||||
drivers/mmc/sunxi_mmc.c | 18 +++++++++++++-----
|
||||
1 file changed, 13 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
|
||||
index 0b56d1405be..78814ecd50b 100644
|
||||
--- a/drivers/mmc/sunxi_mmc.c
|
||||
+++ b/drivers/mmc/sunxi_mmc.c
|
||||
@@ -36,6 +36,8 @@
|
||||
#define CCM_MMC_CTRL_MODE_SEL_NEW 0
|
||||
#endif
|
||||
|
||||
+#define DEBUG 1
|
||||
+
|
||||
struct sunxi_mmc_plat {
|
||||
struct mmc_config cfg;
|
||||
struct mmc mmc;
|
||||
@@ -61,6 +63,7 @@ static bool sunxi_mmc_can_calibrate(void)
|
||||
IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
|
||||
IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
|
||||
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
|
||||
+ IS_ENABLED(CONFIG_MACH_SUN8I_A83T) ||
|
||||
IS_ENABLED(CONFIG_MACH_SUN8I_R40);
|
||||
}
|
||||
|
||||
@@ -639,20 +642,25 @@ static int sunxi_mmc_probe(struct udevice *dev)
|
||||
struct mmc_config *cfg = &plat->cfg;
|
||||
struct ofnode_phandle_args args;
|
||||
u32 *ccu_reg;
|
||||
- int ret;
|
||||
+ int ret, bus_width;
|
||||
|
||||
cfg->name = dev->name;
|
||||
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
|
||||
|
||||
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
+ cfg->host_caps = 0;
|
||||
+ if (bus_width == 8)
|
||||
+ cfg->host_caps |= MMC_MODE_8BIT;
|
||||
+ if (bus_width >= 4)
|
||||
+ cfg->host_caps |= MMC_MODE_4BIT;
|
||||
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||||
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
||||
|
||||
cfg->f_min = 400000;
|
||||
cfg->f_max = 52000000;
|
||||
|
||||
- ret = mmc_of_parse(dev, cfg);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
+ if (bus_width == 8)
|
||||
+ cfg->f_max = 52000000;
|
||||
|
||||
priv->reg = dev_read_addr_ptr(dev);
|
||||
|
||||
@@ -686,7 +694,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
|
||||
|
||||
/* Reset controller */
|
||||
writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
|
||||
- udelay(1000);
|
||||
+ udelay(2000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
--
|
||||
2.35.3
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
From f6e223575f0f74e008e4688a58600eda615460e2 Mon Sep 17 00:00:00 2001
|
||||
From: The-going <48602507+The-going@users.noreply.github.com>
|
||||
Date: Thu, 6 Feb 2025 14:00:06 +0300
|
||||
Subject: [PATCH 5/6] h616: THS workaround
|
||||
|
||||
---
|
||||
board/sunxi/board.c | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
|
||||
index 824c322a0dc..981f406aeea 100644
|
||||
--- a/board/sunxi/board.c
|
||||
+++ b/board/sunxi/board.c
|
||||
@@ -227,6 +227,15 @@ int board_init(void)
|
||||
|
||||
eth_init_board();
|
||||
|
||||
+#if CONFIG_MACH_SUN50I_H616
|
||||
+ /*
|
||||
+ * The bit[16] of register reg[0x03000000] must be zero for the THS
|
||||
+ * driver to work properly in the kernel. The BSP u-boot is putting
|
||||
+ * the whole register to zero so we are doing the same.
|
||||
+ */
|
||||
+ writel(0x0, SUNXI_SRAMC_BASE);
|
||||
+#endif
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--
|
||||
2.35.3
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
From d2a852603b364b90903dc0a9040d4b11f79b8fea Mon Sep 17 00:00:00 2001
|
||||
From: The-going <48602507+The-going@users.noreply.github.com>
|
||||
Date: Thu, 6 Feb 2025 15:11:40 +0300
|
||||
Subject: [PATCH 6/6] h616: GPU enable. Magic register.
|
||||
|
||||
---
|
||||
arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
|
||||
index b424a7893ea..9ed5852d547 100644
|
||||
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
|
||||
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
|
||||
@@ -15,6 +15,8 @@ void clock_init_safe(void)
|
||||
/* this seems to enable PLLs on H616 */
|
||||
setbits_le32(&prcm->sys_pwroff_gating, 0x10);
|
||||
setbits_le32(&prcm->res_cal_ctrl, 2);
|
||||
+ /* enable GPU */
|
||||
+ writel(0, 0x7010254);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
|
||||
--
|
||||
2.35.3
|
||||
|
||||
Reference in New Issue
Block a user