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https://github.com/armbian/build
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Update mvebu patches
This commit is contained in:
Heisath
@@ -1,4 +1,4 @@
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From 49853eacbe2c75761c34e6198e5c3eec142a8d7c Mon Sep 17 00:00:00 2001
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From cf2cb15fb44ee05043232230cbaba444aa943b9c Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Tue, 29 Nov 2016 10:13:46 +0000
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Subject: mvebu/clearfog pcie updates
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@@ -222,10 +222,10 @@ index 013a47f587ce..26ee590caec0 100644
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/*
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* Setup L0s state
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diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
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index e1fed6649c41..a50dac9f8d39 100644
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index 3ee63968deaa..52c61b14af50 100644
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--- a/drivers/pci/pcie/portdrv_core.c
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+++ b/drivers/pci/pcie/portdrv_core.c
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@@ -322,6 +322,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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@@ -327,6 +327,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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/* Get and check PCI Express port services */
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capabilities = get_port_device_capability(dev);
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@@ -233,7 +233,7 @@ index e1fed6649c41..a50dac9f8d39 100644
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if (!capabilities)
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return 0;
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@@ -334,6 +335,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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@@ -339,6 +340,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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* if that is to be used.
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*/
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status = pcie_init_service_irqs(dev, irqs, capabilities);
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@@ -1,17 +1,18 @@
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From 527312a74d9d85ba9520c8cb2979004f6d23c4da Mon Sep 17 00:00:00 2001
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From cf2cb15fb44ee05043232230cbaba444aa943b9c Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Tue, 29 Nov 2016 10:13:46 +0000
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Subject: [PATCH] mvebu/clearfog pcie updates
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Subject: mvebu/clearfog pcie updates
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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---
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drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++-
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drivers/pci/pci-bridge-emul.c | 83 ++++++++++++---------
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drivers/pci/pci-bridge-emul.h | 15 ++++
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drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++++++++++-
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drivers/pci/pci-bridge-emul.c | 2 +
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drivers/pci/pcie/aspm.c | 6 ++
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drivers/pci/pcie/portdrv_core.c | 2 +
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5 files changed, 184 insertions(+), 34 deletions(-)
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4 files changed, 121 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
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index ed13e81cd691..2dc9f457bc76 100644
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -52,7 +52,14 @@
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@@ -29,7 +30,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_ch
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@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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&port->memwin);
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}
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@@ -84,7 +85,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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static pci_bridge_emul_read_status_t
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mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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int reg, u32 *value)
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@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
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@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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@@ -115,7 +116,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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static void
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mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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int reg, u32 old, u32 new, u32 mask)
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@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(st
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@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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mvebu_pcie_handle_iobase_change(port);
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if ((old ^ new) & PCI_COMMAND_MEMORY)
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mvebu_pcie_handle_membase_change(port);
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@@ -125,7 +126,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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break;
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}
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@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(st
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@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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mvebu_pcie_handle_iobase_change(port);
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break;
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@@ -137,7 +138,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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case PCI_PRIMARY_BUS:
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mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
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break;
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@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
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@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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switch (reg) {
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case PCI_EXP_DEVCTL:
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@@ -148,7 +149,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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/*
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* Armada370 data says these bits must always
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* be zero when in root complex mode.
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@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
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@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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case PCI_EXP_RTSTA:
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mvebu_writel(port, new, PCIE_RC_RTSTA);
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break;
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@@ -174,7 +175,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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}
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}
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@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_
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@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
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.write_base = mvebu_pci_bridge_emul_base_conf_write,
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.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
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.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
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@@ -183,9 +184,11 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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};
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/*
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diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
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index fbff7da94245..50b1b48f6e0d 100644
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -151,6 +151,7 @@ static const struct pci_bridge_reg_behav
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@@ -153,6 +153,7 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
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.rw = (GENMASK(7, 0) |
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((PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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@@ -193,7 +196,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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PCI_BRIDGE_CTL_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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@@ -264,6 +265,7 @@ int pci_bridge_emul_init(struct pci_brid
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@@ -269,6 +270,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
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@@ -201,171 +204,11 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
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sizeof(pci_regs_behavior),
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GFP_KERNEL);
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@@ -323,25 +325,26 @@ int pci_bridge_emul_conf_read(struct pci
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
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- *value = 0;
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- return PCIBIOS_SUCCESSFUL;
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- }
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-
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- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
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+ if (reg < PCI_CAP_PCIE_START) {
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+ read_op = bridge->ops->read_base;
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+ cfgspace = (__le32 *) &bridge->conf;
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+ behavior = bridge->pci_regs_behavior;
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+ } else if (!bridge->has_pcie) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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- }
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-
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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+ } else if (reg < PCI_CAP_PCIE_END) {
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reg -= PCI_CAP_PCIE_START;
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read_op = bridge->ops->read_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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+ } else if (reg < 0x100) {
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+ *value = 0;
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+ return PCIBIOS_SUCCESSFUL;
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} else {
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- read_op = bridge->ops->read_base;
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- cfgspace = (__le32 *) &bridge->conf;
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- behavior = bridge->pci_regs_behavior;
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+ reg -= 0x100;
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+ read_op = bridge->ops->read_ext;
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+ cfgspace = NULL;
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+ behavior = NULL;
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}
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if (read_op)
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@@ -349,15 +352,20 @@ int pci_bridge_emul_conf_read(struct pci
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else
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ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
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- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
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- *value = le32_to_cpu(cfgspace[reg / 4]);
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+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
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+ if (cfgspace)
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+ *value = le32_to_cpu(cfgspace[reg / 4]);
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+ else
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+ *value = 0;
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+ }
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/*
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* Make sure we never return any reserved bit with a value
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* different from 0.
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*/
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- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
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- behavior[reg / 4].w1c;
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+ if (behavior)
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+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
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+ behavior[reg / 4].w1c;
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if (size == 1)
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*value = (*value >> (8 * (where & 3))) & 0xff;
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@@ -385,12 +393,6 @@ int pci_bridge_emul_conf_write(struct pc
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
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- return PCIBIOS_SUCCESSFUL;
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-
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- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
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- return PCIBIOS_SUCCESSFUL;
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-
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shift = (where & 0x3) * 8;
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if (size == 4)
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@@ -406,27 +408,42 @@ int pci_bridge_emul_conf_write(struct pc
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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+ if (reg < PCI_CAP_PCIE_START) {
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+ write_op = bridge->ops->write_base;
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+ cfgspace = (__le32 *) &bridge->conf;
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+ behavior = bridge->pci_regs_behavior;
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+ } else if (!bridge->has_pcie) {
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+ return PCIBIOS_SUCCESSFUL;
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+ } else if (reg < PCI_CAP_PCIE_END) {
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reg -= PCI_CAP_PCIE_START;
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write_op = bridge->ops->write_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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+ } else if (reg < 0x100) {
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+ return PCIBIOS_SUCCESSFUL;
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} else {
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- write_op = bridge->ops->write_base;
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- cfgspace = (__le32 *) &bridge->conf;
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- behavior = bridge->pci_regs_behavior;
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+ reg -= 0x100;
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+ write_op = bridge->ops->write_ext;
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+ cfgspace = NULL;
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+ behavior = NULL;
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}
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- /* Keep all bits, except the RW bits */
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- new = old & (~mask | ~behavior[reg / 4].rw);
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+ if (behavior) {
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+ /* Keep all bits, except the RW bits */
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+ new = old & (~mask | ~behavior[reg / 4].rw);
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- /* Update the value of the RW bits */
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- new |= (value << shift) & (behavior[reg / 4].rw & mask);
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+ /* Update the value of the RW bits */
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+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
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- /* Clear the W1C bits */
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- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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+ /* Clear the W1C bits */
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+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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+ } else {
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+ new = old & ~mask;
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+ new |= (value << shift) & mask;
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+ }
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- cfgspace[reg / 4] = cpu_to_le32(new);
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+ if (cfgspace)
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+ cfgspace[reg / 4] = cpu_to_le32(new);
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if (write_op)
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write_op(bridge, reg, old, new, mask);
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--- a/drivers/pci/pci-bridge-emul.h
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+++ b/drivers/pci/pci-bridge-emul.h
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@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
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*/
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pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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+
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+ /*
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+ * Same as ->read_base(), except it is for reading from the
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+ * PCIe extended capability configuration space.
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+ */
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+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
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+ int reg, u32 *value);
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+
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/*
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* Called when writing to the regular PCI bridge configuration
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* space. old is the current value, new is the new value being
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@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
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*/
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void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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+
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+ /*
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+ * Same as ->write_base(), except it is for writing from the
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+ * PCIe extended capability configuration space.
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+ */
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+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
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+ u32 old, u32 new, u32 mask);
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};
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struct pci_bridge_reg_behavior;
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diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
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index 013a47f587ce..26ee590caec0 100644
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--- a/drivers/pci/pcie/aspm.c
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+++ b/drivers/pci/pcie/aspm.c
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@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pc
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@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
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@@ -378,9 +221,11 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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/*
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* Setup L0s state
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diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
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index 3ee63968deaa..52c61b14af50 100644
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--- a/drivers/pci/pcie/portdrv_core.c
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+++ b/drivers/pci/pcie/portdrv_core.c
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@@ -325,6 +325,7 @@ int pcie_port_device_register(struct pci
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@@ -327,6 +327,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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/* Get and check PCI Express port services */
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capabilities = get_port_device_capability(dev);
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@@ -388,7 +233,7 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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if (!capabilities)
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return 0;
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@@ -337,6 +338,7 @@ int pcie_port_device_register(struct pci
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@@ -339,6 +340,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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* if that is to be used.
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*/
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status = pcie_init_service_irqs(dev, irqs, capabilities);
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@@ -396,3 +241,6 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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if (status) {
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capabilities &= PCIE_PORT_SERVICE_HP;
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if (!capabilities)
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--
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cgit v1.2.3
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