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meson: Fix broken patches (#4795)

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This commit is contained in:
hzyitc
2023-02-02 21:08:22 +08:00
committed by GitHub
parent 50a1ecd2f6
commit c6b9135293
2 changed files with 18 additions and 181 deletions
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43
patch/kernel/archive/meson-6.1/0001-m8-m8b-m8m2-Support-HDMI.patch
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@@ -22,11 +22,11 @@ Special thank to Martin Blumenstingl.
drivers/gpu/drm/meson/meson_transwitch_hdmi.h | 536 ++++++
drivers/gpu/drm/meson/meson_vclk.c | 146 ++
drivers/gpu/drm/meson/meson_venc.c | 44 +-
drivers/gpu/drm/meson/meson_viu.c | 38 +-
drivers/gpu/drm/meson/meson_viu.c | 18 +-
drivers/phy/amlogic/Kconfig | 10 +
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-cvbs-dac.c | 375 ++++
21 files changed, 3593 insertions(+), 130 deletions(-)
21 files changed, 3577 insertions(+), 126 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml
create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.c
create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.h
@@ -1265,7 +1265,7 @@ index c62ee358456..fe0a8f8762f 100644
struct {
bool osd1_enabled;
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
index 5675bc2a92c..3e40bd45c90 100644
index 3f73b211fa8..833f701fe27 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
@@ -11,6 +11,7 @@
@@ -1318,7 +1318,7 @@ index 5675bc2a92c..3e40bd45c90 100644
static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge,
struct drm_connector *connector)
{
@@ -147,6 +159,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
@@ -148,6 +160,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
struct drm_connector_state *conn_state;
struct drm_crtc_state *crtc_state;
struct drm_connector *connector;
@@ -1326,7 +1326,7 @@ index 5675bc2a92c..3e40bd45c90 100644
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
if (WARN_ON(!connector))
@@ -176,16 +189,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
@@ -177,16 +190,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
priv->io_base + _REG(VENC_VDAC_DACSEL0));
@@ -1350,7 +1350,7 @@ index 5675bc2a92c..3e40bd45c90 100644
}
}
@@ -195,19 +205,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
@@ -196,19 +206,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
struct meson_encoder_cvbs *meson_encoder_cvbs =
bridge_to_meson_encoder_cvbs(bridge);
struct meson_drm *priv = meson_encoder_cvbs->priv;
@@ -3959,37 +3959,10 @@ index 3c55ed00335..009882bda7b 100644
/* Disable HDMI */
writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a2..836dac22c8e 100644
index cd399b0b718..bdfa342c4ca 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,10 +436,22 @@ void meson_viu_init(struct meson_drm *priv)
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
- VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
- VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
- VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
+ VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
+ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
+ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
+
+ /*
+ * When using AFBC on newer SoCs the AFBC encoder has to be reset. To
+ * leave time for that we need hold more lines to avoid glitches.
+ * On the 32-bit SoCs however we need to hold fewer lines because
+ * otherwise screen tearing can occur (for example in kmscube).
+ */
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
+ reg |= VIU_OSD_HOLD_FIFO_LINES(12);
+ else
+ reg |= VIU_OSD_HOLD_FIFO_LINES(31);
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
reg |= VIU_OSD_BURST_LENGTH_32;
@@ -449,13 +461,17 @@ void meson_viu_init(struct meson_drm *priv)
@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv)
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));