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synced 2025-09-24 19:47:06 +07:00
meson: Fix broken patches (#4795)
This commit is contained in:
hzyitc
@@ -14,7 +14,6 @@ Special thank.
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arch/arm/boot/dts/meson8m2.dtsi | 4 +
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drivers/clk/meson/meson8b.c | 163 +-
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drivers/clk/meson/meson8b.h | 26 +-
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drivers/gpu/drm/bridge/display-connector.c | 86 +
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drivers/gpu/drm/meson/Kconfig | 8 +
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drivers/gpu/drm/meson/Makefile | 3 +-
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drivers/gpu/drm/meson/meson_drv.c | 290 ++-
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@@ -28,13 +27,13 @@ Special thank.
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drivers/gpu/drm/meson/meson_vclk.c | 146 ++
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drivers/gpu/drm/meson/meson_venc.c | 45 +-
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drivers/gpu/drm/meson/meson_venc_cvbs.c | 293 ---
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drivers/gpu/drm/meson/meson_viu.c | 38 +-
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drivers/gpu/drm/meson/meson_viu.c | 18 +-
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drivers/phy/amlogic/Kconfig | 20 +
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drivers/phy/amlogic/Makefile | 2 +
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drivers/phy/amlogic/phy-meson-cvbs-dac.c | 310 ++++
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drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 160 ++
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include/dt-bindings/clock/meson8b-clkc.h | 10 +
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29 files changed, 4203 insertions(+), 476 deletions(-)
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28 files changed, 4101 insertions(+), 472 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml
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create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml
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create mode 100644 drivers/gpu/drm/meson/meson_encoder_cvbs.c
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@@ -751,7 +750,7 @@ index 6725dd9fd825..fcb2ad976098 100644
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compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
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};
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diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
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index a844d35b553a..cd0f5bae24d4 100644
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index 809a0bfb670d..12e9b6618dbb 100644
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--- a/drivers/clk/meson/meson8b.c
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+++ b/drivers/clk/meson/meson8b.c
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@@ -118,6 +118,56 @@ static struct clk_regmap meson8b_fixed_pll = {
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@@ -1308,114 +1307,6 @@ index b1a5074cf148..ce62ed47cbfc 100644
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/*
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* include the CLKID and RESETID that have
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diff --git a/drivers/gpu/drm/bridge/display-connector.c b/drivers/gpu/drm/bridge/display-connector.c
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index 847a0dce7f1d..d24f5b90feab 100644
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--- a/drivers/gpu/drm/bridge/display-connector.c
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+++ b/drivers/gpu/drm/bridge/display-connector.c
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@@ -13,6 +13,7 @@
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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+#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_edid.h>
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@@ -87,10 +88,95 @@ static struct edid *display_connector_get_edid(struct drm_bridge *bridge,
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return drm_get_edid(connector, conn->bridge.ddc);
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}
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+/*
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+ * Since this bridge is tied to the connector, it acts like a passthrough,
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+ * so concerning the output bus formats, either pass the bus formats from the
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+ * previous bridge or return fallback data like done in the bridge function:
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+ * drm_atomic_bridge_chain_select_bus_fmts().
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+ * This supports negotiation if the bridge chain has all bits in place.
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+ */
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+static u32 *display_connector_get_output_bus_fmts(struct drm_bridge *bridge,
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+ struct drm_bridge_state *bridge_state,
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+ struct drm_crtc_state *crtc_state,
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+ struct drm_connector_state *conn_state,
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+ unsigned int *num_output_fmts)
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+{
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+ struct drm_bridge *prev_bridge = drm_bridge_get_prev_bridge(bridge);
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+ struct drm_bridge_state *prev_bridge_state;
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+
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+ if (!prev_bridge || !prev_bridge->funcs->atomic_get_output_bus_fmts) {
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+ struct drm_connector *conn = conn_state->connector;
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+ u32 *out_bus_fmts;
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+
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+ *num_output_fmts = 1;
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+ out_bus_fmts = kmalloc(sizeof(*out_bus_fmts), GFP_KERNEL);
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+ if (!out_bus_fmts)
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+ return NULL;
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+
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+ if (conn->display_info.num_bus_formats &&
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+ conn->display_info.bus_formats)
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+ out_bus_fmts[0] = conn->display_info.bus_formats[0];
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+ else
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+ out_bus_fmts[0] = MEDIA_BUS_FMT_FIXED;
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+
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+ return out_bus_fmts;
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+ }
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+
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+ prev_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
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+ prev_bridge);
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+
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+ return prev_bridge->funcs->atomic_get_output_bus_fmts(prev_bridge, prev_bridge_state,
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+ crtc_state, conn_state,
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+ num_output_fmts);
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+}
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+
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+/*
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+ * Since this bridge is tied to the connector, it acts like a passthrough,
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+ * so concerning the input bus formats, either pass the bus formats from the
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+ * previous bridge or MEDIA_BUS_FMT_FIXED (like select_bus_fmt_recursive())
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+ * when atomic_get_input_bus_fmts is not supported.
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+ * This supports negotiation if the bridge chain has all bits in place.
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+ */
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+static u32 *display_connector_get_input_bus_fmts(struct drm_bridge *bridge,
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+ struct drm_bridge_state *bridge_state,
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+ struct drm_crtc_state *crtc_state,
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+ struct drm_connector_state *conn_state,
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+ u32 output_fmt,
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+ unsigned int *num_input_fmts)
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+{
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+ struct drm_bridge *prev_bridge = drm_bridge_get_prev_bridge(bridge);
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+ struct drm_bridge_state *prev_bridge_state;
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+
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+ if (!prev_bridge || !prev_bridge->funcs->atomic_get_input_bus_fmts) {
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+ u32 *in_bus_fmts;
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+
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+ *num_input_fmts = 1;
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+ in_bus_fmts = kmalloc(sizeof(*in_bus_fmts), GFP_KERNEL);
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+ if (!in_bus_fmts)
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+ return NULL;
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+
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+ in_bus_fmts[0] = MEDIA_BUS_FMT_FIXED;
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+
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+ return in_bus_fmts;
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+ }
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+
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+ prev_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
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+ prev_bridge);
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+
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+ return prev_bridge->funcs->atomic_get_input_bus_fmts(prev_bridge, prev_bridge_state,
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+ crtc_state, conn_state, output_fmt,
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+ num_input_fmts);
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+}
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+
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static const struct drm_bridge_funcs display_connector_bridge_funcs = {
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.attach = display_connector_attach,
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.detect = display_connector_detect,
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.get_edid = display_connector_get_edid,
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+ .atomic_get_output_bus_fmts = display_connector_get_output_bus_fmts,
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+ .atomic_get_input_bus_fmts = display_connector_get_input_bus_fmts,
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+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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+ .atomic_reset = drm_atomic_helper_bridge_reset,
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};
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static irqreturn_t display_connector_hpd_irq(int irq, void *arg)
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diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
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index a4e1ed96e5e8..2023bc2b4dec 100644
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--- a/drivers/gpu/drm/meson/Kconfig
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@@ -1448,7 +1339,7 @@ index 523fce45f16b..817a5270aee6 100644
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obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
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+obj-$(CONFIG_DRM_MESON_TRANSWITCH_HDMI) += meson_transwitch_hdmi.o
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diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
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index a56607501d36..0df139d8df8f 100644
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index 6e37de4fcb46..71d4cdc57d58 100644
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--- a/drivers/gpu/drm/meson/meson_drv.c
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+++ b/drivers/gpu/drm/meson/meson_drv.c
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@@ -12,6 +12,7 @@
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@@ -1827,9 +1718,9 @@ index a56607501d36..0df139d8df8f 100644
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}
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if (count && !match)
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@@ -520,6 +634,18 @@ static int meson_drv_probe(struct platform_device *pdev)
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@@ -527,6 +641,18 @@ static int meson_drv_remove(struct platform_device *pdev)
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return 0;
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};
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}
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+static struct meson_drm_match_data meson_drm_m8_data = {
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+ .compat = VPU_COMPATIBLE_M8,
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@@ -1846,7 +1737,7 @@ index a56607501d36..0df139d8df8f 100644
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static struct meson_drm_match_data meson_drm_gxbb_data = {
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.compat = VPU_COMPATIBLE_GXBB,
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};
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@@ -539,6 +665,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = {
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@@ -546,6 +672,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = {
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};
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static const struct of_device_id dt_match[] = {
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@@ -2342,7 +2233,7 @@ index a7692584487c..62c5cde59224 100644
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pdev = of_find_device_by_node(remote);
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of_node_put(remote);
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diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
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index 8640a8a8a469..456e2f421713 100644
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index 44aa52629443..c835e6d35568 100644
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--- a/drivers/gpu/drm/meson/meson_plane.c
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+++ b/drivers/gpu/drm/meson/meson_plane.c
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@@ -199,8 +199,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
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@@ -5091,37 +4982,10 @@ index f1747fde1fe0..000000000000
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- return 0;
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-}
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diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
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index bb7e109534de..406498ba2f79 100644
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index cd399b0b7181..bdfa342c4ca1 100644
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--- a/drivers/gpu/drm/meson/meson_viu.c
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+++ b/drivers/gpu/drm/meson/meson_viu.c
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@@ -436,10 +436,22 @@ void meson_viu_init(struct meson_drm *priv)
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/* Initialize OSD1 fifo control register */
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reg = VIU_OSD_DDR_PRIORITY_URGENT |
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- VIU_OSD_HOLD_FIFO_LINES(31) |
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- VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
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- VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
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- VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
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+ VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
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+ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
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+ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
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+
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+ /*
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+ * When using AFBC on newer SoCs the AFBC encoder has to be reset. To
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+ * leave time for that we need hold more lines to avoid glitches.
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+ * On the 32-bit SoCs however we need to hold fewer lines because
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+ * otherwise screen tearing can occur (for example in kmscube).
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+ */
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+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
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+ reg |= VIU_OSD_HOLD_FIFO_LINES(12);
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+ else
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+ reg |= VIU_OSD_HOLD_FIFO_LINES(31);
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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reg |= VIU_OSD_BURST_LENGTH_32;
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@@ -449,13 +461,17 @@ void meson_viu_init(struct meson_drm *priv)
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@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv)
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
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@@ -22,11 +22,11 @@ Special thank to Martin Blumenstingl.
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drivers/gpu/drm/meson/meson_transwitch_hdmi.h | 536 ++++++
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drivers/gpu/drm/meson/meson_vclk.c | 146 ++
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drivers/gpu/drm/meson/meson_venc.c | 44 +-
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drivers/gpu/drm/meson/meson_viu.c | 38 +-
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drivers/gpu/drm/meson/meson_viu.c | 18 +-
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drivers/phy/amlogic/Kconfig | 10 +
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drivers/phy/amlogic/Makefile | 1 +
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drivers/phy/amlogic/phy-meson-cvbs-dac.c | 375 ++++
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21 files changed, 3593 insertions(+), 130 deletions(-)
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21 files changed, 3577 insertions(+), 126 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml
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create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.c
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create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.h
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@@ -1265,7 +1265,7 @@ index c62ee358456..fe0a8f8762f 100644
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struct {
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bool osd1_enabled;
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diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
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index 5675bc2a92c..3e40bd45c90 100644
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index 3f73b211fa8..833f701fe27 100644
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--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
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+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
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@@ -11,6 +11,7 @@
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@@ -1318,7 +1318,7 @@ index 5675bc2a92c..3e40bd45c90 100644
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static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge,
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struct drm_connector *connector)
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{
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@@ -147,6 +159,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
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@@ -148,6 +160,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
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struct drm_connector_state *conn_state;
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struct drm_crtc_state *crtc_state;
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struct drm_connector *connector;
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@@ -1326,7 +1326,7 @@ index 5675bc2a92c..3e40bd45c90 100644
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connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
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if (WARN_ON(!connector))
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@@ -176,16 +189,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
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@@ -177,16 +190,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
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writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
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priv->io_base + _REG(VENC_VDAC_DACSEL0));
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@@ -1350,7 +1350,7 @@ index 5675bc2a92c..3e40bd45c90 100644
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}
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}
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@@ -195,19 +205,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
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@@ -196,19 +206,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
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struct meson_encoder_cvbs *meson_encoder_cvbs =
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bridge_to_meson_encoder_cvbs(bridge);
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struct meson_drm *priv = meson_encoder_cvbs->priv;
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@@ -3959,37 +3959,10 @@ index 3c55ed00335..009882bda7b 100644
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/* Disable HDMI */
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writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
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diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
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index d4b907889a2..836dac22c8e 100644
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index cd399b0b718..bdfa342c4ca 100644
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--- a/drivers/gpu/drm/meson/meson_viu.c
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+++ b/drivers/gpu/drm/meson/meson_viu.c
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@@ -436,10 +436,22 @@ void meson_viu_init(struct meson_drm *priv)
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/* Initialize OSD1 fifo control register */
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reg = VIU_OSD_DDR_PRIORITY_URGENT |
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- VIU_OSD_HOLD_FIFO_LINES(31) |
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- VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
|
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- VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
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- VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
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+ VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
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+ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
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+ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
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+
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+ /*
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+ * When using AFBC on newer SoCs the AFBC encoder has to be reset. To
|
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+ * leave time for that we need hold more lines to avoid glitches.
|
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+ * On the 32-bit SoCs however we need to hold fewer lines because
|
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+ * otherwise screen tearing can occur (for example in kmscube).
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+ */
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+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) ||
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+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2))
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+ reg |= VIU_OSD_HOLD_FIFO_LINES(12);
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+ else
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+ reg |= VIU_OSD_HOLD_FIFO_LINES(31);
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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reg |= VIU_OSD_BURST_LENGTH_32;
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@@ -449,13 +461,17 @@ void meson_viu_init(struct meson_drm *priv)
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@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv)
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
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