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rk322x: add DMC driver and runtime clock adjust, change rk322x-config emmc options

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* add DFI driver to provide hardware-based memory controller load
     * adapted DRAM Memory Controller driver from rk3328, add necessary headers
     * provide device tree overlays to enable DDR3 clock scaling
     * adapted rk322x-box to allow DDR speed bin selection to user
     * add ipb900 board gpio configuration
     * add rtl8723cs driver to linux-current kernel
     * use ddrbin v1.10 set to 330 Mhz at boot
     * provide overlays for ddr3 at 330, 528, 660 and 800 mhz
     * split emmc overlays to enable options by user choice
     * modified rk322x-config to support dmc, emmc overlays
     * remove optee trust os in favor of rockchip proprietary blob
       for dmc functionality
This commit is contained in:
Paolo Sabatino
2021-07-17 15:21:48 +00:00
parent b6dd6b5281
commit baf9815f8b
20 changed files with 712174 additions and 159 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
config/kernel/linux-rk322x-current.config
View File

@@ -2376,6 +2376,7 @@ CONFIG_RTLWIFI_USB=m
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8XXXU=y
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTL8723CS=m
CONFIG_RTW88=m
CONFIG_WLAN_VENDOR_RSI=y
# CONFIG_RSI_91X is not set
@@ -5650,8 +5651,11 @@ CONFIG_DEVFREQ_GOV_USERSPACE=y
#
# DEVFREQ Drivers
#
# CONFIG_ARM_RK3328_DMC_DEVFREQ is not set
CONFIG_ARM_RK3228_DMC_DEVFREQ=y
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y
#

2
config/sources/families/rk322x.conf
View File

@@ -56,7 +56,7 @@ uboot_custom_postprocess()
# tools/mkimage -n rk322x -T rksd -d tpl/u-boot-tpl.bin u-boot-rk322x-with-spl.bin
#
tools/mkimage -n rk322x -T rksd -d $SRC/packages/blobs/rockchip/rk322x_ddr3_660MHz_ddr2_330MHz_v1.10.bin u-boot-rk322x-with-spl.bin
tools/mkimage -n rk322x -T rksd -d $SRC/packages/blobs/rockchip/rk322x_ddr_330MHz_v1.10_no2t.bin u-boot-rk322x-with-spl.bin
cat spl/u-boot-spl.bin >> u-boot-rk322x-with-spl.bin
dd if=u-boot.itb of=u-boot-rk322x-with-spl.bin seek=$((0x200 - 0x40)) conv=notrunc

BIN
packages/blobs/rockchip/rk322x_ddr3_660MHz_ddr2_330MHz_v1.08.bin → packages/blobs/rockchip/rk322x_ddr_330MHz_v1.10_no2t.bin
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Binary file not shown.

BIN
packages/blobs/rockchip/rk322x_tee.bin
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Binary file not shown.

125
packages/bsp/rk322x/rk322x-config
View File

@@ -20,6 +20,20 @@ NOTE_LED_GPIO_SELECTION="${COLOR_RED}Important:${COLOR_BLACK} select the \
led/gpio configuration looking on the markings of the board.\nThe right \
configuration may solve problems with devices detection like leds,\nwifi and bluetooth\n\n"
EMMC_OPTIONS_WARNING="\nThese eMMC options are optimizations that can increase \
stability, reliability and performance, but may also cause errors and misdetections.\n\n\
${COLOR_RED}emmc-pins${COLOR_BLACK} sets the default pin configuration. It is suggested \
to use it, but may cause misdection on some boards\n\
${COLOR_RED}emmc-ddr-*${COLOR_BLACK} enables DDR mode, may work or not \
work on your board. Try one overlay at a time\n\
${COLOR_RED}emmc-hs200${COLOR_BLACK} enables HS200 mode, preferred over \
DDR mode, but old eMMC may not support it\n\n
Test througly the eMMC after setting any of these options, \n\
${COLOR_RED}Do not set any of these options you are unsure!${COLOR_BLACK}"
DDR_OPTIONS_WARNING="\n${COLOR_RED}The wrong choice will make the system unstable or even unable to boot\n
Use default option if you are unsure!${COLOR_BLACK}"
EFUSE_PATH="/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
SDIO_WIFI_PATH="/sys/bus/sdio/devices/mmc1:0001:1"
@@ -31,9 +45,14 @@ declare -A WIFI_NAMES
declare -A WIFI_CHIPS
declare -A DT_FLASH_OVERLAYS
declare -A DT_EMMC_OVERLAYS
declare -a DT_EMMC_OVERLAYS_ORDER
declare -A DT_LED_OVERLAYS
declare -a DT_LED_OVERLAYS_ORDER
declare -A DT_CPU_OVERLAYS
declare -A DT_WIFI_OVERLAYS
declare -A DT_DDR_OVERLAYS
declare -a DT_DDR_OVERLAYS_ORDER
# Declarations for the various SoCs IDs
CHIP_IDS+=(["524b2382"]="RK3228A/B")
@@ -57,19 +76,37 @@ WIFI_CHIPS+=(["024c:8179"]="8189es")
WIFI_CHIPS+=(["6666:1111"]="")
# Declarations for device tree overlays
DT_FLASH_OVERLAYS+=(["emmc"]="eMMC only flash memory")
DT_FLASH_OVERLAYS+=(["nand"]="NAND only flash memory")
DT_FLASH_OVERLAYS+=(["emmc-nand"]="eMMC or NAND flash memory")
DT_FLASH_OVERLAYS+=(["emmc"]="eMMC flash memory")
DT_FLASH_OVERLAYS+=(["nand"]="NAND flash memory")
DT_EMMC_OVERLAYS+=(["emmc-pins"]="set pin configuration")
DT_EMMC_OVERLAYS+=(["emmc-ddr-ph45"]="enable DDR mode, 45 degrees phase shift")
DT_EMMC_OVERLAYS+=(["emmc-ddr-ph180"]="enable DDR mode, 180 degrees phase shift")
DT_EMMC_OVERLAYS+=(["emmc-hs200"]="enable eMMC HS200 mode")
DT_EMMC_OVERLAYS_ORDER=("emmc-pins" "emmc-ddr-ph45" "emmc-ddr-ph180" "emmc-hs200")
DT_LED_OVERLAYS+=(["led-conf-default"]="Use default (single led)")
DT_LED_OVERLAYS+=(["led-conf1"]="Chiptrip brand (MX1VR, MX4VR)")
DT_LED_OVERLAYS+=(["led-conf2"]="R329q, MXQ-RK3229")
DT_LED_OVERLAYS+=(["led-conf3"]="R28-MXQ")
DT_LED_OVERLAYS+=(["led-conf4"]="T066/T066-V2")
DT_LED_OVERLAYS+=(["led-conf5"]="AEMS IPB900")
DT_LED_OVERLAYS_ORDER=("led-conf-default" "led-conf1" "led-conf2" "led-conf3" "led-conf4" "led-conf5")
DT_CPU_OVERLAYS+=(["cpu-hs"]="RK3228B or RK3229")
DT_WIFI_OVERLAYS+=(["6666:1111"]="wlan-esp8089")
DT_DDR_OVERLAYS+=(["default"]="Use DDR2/DDR3 default")
DT_DDR_OVERLAYS+=(["ddr3-330"]="DDR3 330 Mhz")
DT_DDR_OVERLAYS+=(["ddr3-528"]="DDR3 528 Mhz")
DT_DDR_OVERLAYS+=(["ddr3-660"]="DDR3 660 Mhz")
DT_DDR_OVERLAYS+=(["ddr3-800"]="DDR3 800 Mhz")
DT_DDR_OVERLAYS_ORDER=("default" "ddr3-330" "ddr3-528" "ddr3-660" "ddr3-800")
KERNEL_VERSION=$(uname -r | cut -d "-" -f 1)
if [[ "$KERNEL_VERSION" < "4.5.0" ]]; then
LEGACY_KERNEL=1
@@ -320,11 +357,83 @@ function select_flash() {
}
function select_emmc_options() {
declare -a DIALOG_ENTRIES
for KEY in "${DT_EMMC_OVERLAYS_ORDER[@]}"; do
DIALOG_ENTRIES+=($KEY "${DT_EMMC_OVERLAYS[$KEY]}" "off")
done
MENU_TITLE="${BOARD_INFO}Select the extra eMMC flash options\n${EMMC_OPTIONS_WARNING}"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --checklist "$MENU_TITLE" 28 0 56)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
RET=$?
if [ "$RET" -eq 1 ]; then
echo "Cancelled"
return 1
fi
if [ "$RET" -ne 0 ]; then
echo "dialog utility returned an unexpected error code: $RET"
return 1
fi
echo $SELECTION
return 0
}
function select_ddr() {
declare -a DIALOG_ENTRIES
# DDR section
SELECTION="default"
for KEY in "${DT_DDR_OVERLAYS_ORDER[@]}"; do
DIALOG_ENTRIES+=($KEY "${DT_DDR_OVERLAYS[$KEY]}")
done
MENU_TITLE="${BOARD_INFO}Select the DDR type and speed\n${DDR_OPTIONS_WARNING}"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "$SELECTION" --menu "$MENU_TITLE" 24 0 20)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
RET=$?
if [ "$RET" -eq 1 ]; then
echo "Cancelled"
return 1
fi
if [ "$RET" -ne 0 ]; then
echo "dialog utility returned an unexpected error code: $RET"
return 1
fi
[[ $SELECTION = "default" ]] && SELECTION=""
echo $SELECTION
return 0
}
function select_led_configuration() {
declare -a DIALOG_ENTRIES
for KEY in "${!DT_LED_OVERLAYS[@]}"; do
for KEY in "${DT_LED_OVERLAYS_ORDER[@]}"; do
DIALOG_ENTRIES+=($KEY "${DT_LED_OVERLAYS[$KEY]}")
done
@@ -398,6 +507,14 @@ DT_OVERLAYS_TO_APPLY+=($SELECTION)
SELECTION=$(select_flash) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
if [[ "$SELECTION" = "emmc" ]]; then
SELECTION=$(select_emmc_options) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
fi
SELECTION=$(select_ddr) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
SELECTION=$(select_led_configuration) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)

29
patch/kernel/archive/rk322x-4.4/02-006-dtsi-add-dmc-opps.patch Normal file
View File

@@ -0,0 +1,29 @@
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 7f586919..01988c8c 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -217,12 +217,24 @@
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
+ opp-330000000 {
+ opp-hz = /bits/ 64 <330000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1000000>;
+ };
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
+ opp-528000000 {
+ opp-hz = /bits/ 64 <528000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1000000>;
+ };
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000>;

368
patch/kernel/archive/rk322x-4.4/general-add-overlays.patch
View File

@@ -1,25 +1,34 @@
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
new file mode 100755
index 00000000..abd197ed
index 00000000..5e2b8cb4
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,28 @@
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk322x-emmc.dtbo \
+ rk322x-emmc-pins.dtbo \
+ rk322x-emmc-ddr-ph45.dtbo \
+ rk322x-emmc-ddr-ph180.dtbo \
+ rk322x-emmc-hs200.dtbo \
+ rk322x-nand.dtbo \
+ rk322x-emmc-nand.dtbo \
+ rk322x-led-conf-default.dtbo \
+ rk322x-led-conf1.dtbo \
+ rk322x-led-conf2.dtbo \
+ rk322x-led-conf3.dtbo \
+ rk322x-led-conf4.dtbo \
+ rk322x-led-conf5.dtbo \
+ rk322x-cpu-hs.dtbo \
+ rk322x-cpu-stability.dtbo \
+ rk322x-bluetooth.dtbo \
+ rk322x-wlan-ssv6051.dtbo \
+ rk322x-cpu-hs-lv.dtbo \
+ rk322x-wlan-esp8089.dtbo \
+ rk322x-wlan-alt-wiring.dtbo
+ rk322x-wlan-alt-wiring.dtbo \
+ rk322x-ddr3-330.dtbo \
+ rk322x-ddr3-528.dtbo \
+ rk322x-ddr3-660.dtbo \
+ rk322x-ddr3-800.dtbo
+
+scr-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk322x-fixup.scr
@@ -34,10 +43,10 @@ index 00000000..abd197ed
+
diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
new file mode 100755
index 00000000..8823a01d
index 00000000..cb893eb4
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
@@ -0,0 +1,80 @@
@@ -0,0 +1,92 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
@@ -50,13 +59,17 @@ index 00000000..8823a01d
+
+- rk322x-cpu-hs
+- rk322x-emmc
+- rk322x-emmc-pins
+- rk322x-emmc-ddr-ph45
+- rk322x-emmc-ddr-ph180
+- rk322x-emmc-hs200
+- rk322x-nand
+- rk322x-emmc-nand
+- rk322x-led-conf*
+- rk322x-bluetooth
+- rk322x-wlan-*
+- rk322x-cpu-hs-lv
+- rk322x-wlan-alt-wiring
+- rk322x-ddr3-*
+
+### Overlay details:
+
@@ -64,26 +77,26 @@ index 00000000..8823a01d
+
+Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
+
+### emmc
+### emmc*
+
+Activates onboard emmc device node and deactivates the nand controller.
+Also sets up the pin controller default pull up/down configuration
+rk322x-emmc activates onboard emmc device node and deactivates the
+nand controller.
+rk322x-emmc-pins sets the pin controller default pull up/down
+configuration, not all boards are happy with this overlay, so your
+mileage may vary and may want to not use it.
+rk322x-emmc-ddr-ph45/ph180 sets the emmc ddr mode. First overlay
+sets the default phase clock shifting to 45 degrees, the second
+overlay to 180 degrees. They are alternative, choose the one that
+makes your emmc perform better.
+rk322x-emmc-hs200 enables the hs200 mode. It is preferable to
+ddr mode because it is more stable, but old emmc parts don't
+support it.
+
+### nand
+
+Activates onboard nand device node and deactivates the emmc controller.
+Also sets up the pin controller default pull up/down configuration
+
+### emmc-nand
+
+Activates onboard nand and emmc devices. Usually they are alternative
+because manufacturers share the same pads so emmc and nand cannot be
+mixed together. Usually this works because the emmc and nand drivers
+can automatically guess what's in the pads, but may bring instabilities
+or misdetections. Also does not set up the pin controller default
+configuration, which in turn can be detrimental of stability and
+performance
+
+### rk322x-led-conf*
+
+Each device tree of this kind provides a different known wiring configuration
@@ -94,6 +107,7 @@ index 00000000..8823a01d
+led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
+led-conf3 is found in boards with R28-MXQ marking
+led-conf4 is found on boards with T066 marking
+led-conf5 is found on boards with IPB900 marking from AEMS PVT
+
+### rk322x-bluetooth
+
@@ -118,6 +132,13 @@ index 00000000..8823a01d
+
+Some boards have different SDIO wiring setup for wifi chips. This overlay
+enables the different pin controller wiring and power enable
+
+### rk322x-ddr3-*
+
+Enable DRAM memory controller and sets the speed to the given speed bin.
+The DRAM memory controller reclocking only works with DDR3/LPDDR3, if
+you enable one of these overlays on boards with DDR2 memory the system
+will not boot anymore
diff --git a/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
new file mode 100755
index 00000000..5698b14b
@@ -374,6 +395,195 @@ index 00000000..f434af92
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts
new file mode 100644
index 00000000..dc89436c
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts
@@ -0,0 +1,25 @@
+#include <dt-bindings/dram/rockchip,rk322x.h>
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 330000
+ >;
+
+ dram_freq = <330000000>;
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts
new file mode 100644
index 00000000..790586cb
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts
@@ -0,0 +1,27 @@
+#include <dt-bindings/dram/rockchip,rk322x.h>
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 528000
+ SYS_STATUS_VIDEO_4K 528000
+ SYS_STATUS_VIDEO_4K_10B 528000
+ >;
+
+ dram_freq = <528000000>;
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts
new file mode 100644
index 00000000..aea140cf
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts
@@ -0,0 +1,27 @@
+#include <dt-bindings/dram/rockchip,rk322x.h>
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 660000
+ SYS_STATUS_VIDEO_4K 660000
+ SYS_STATUS_VIDEO_4K_10B 660000
+ >;
+
+ dram_freq = <660000000>;
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts
new file mode 100644
index 00000000..6a5a6d36
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts
@@ -0,0 +1,27 @@
+#include <dt-bindings/dram/rockchip,rk322x.h>
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 800000
+ SYS_STATUS_VIDEO_4K 800000
+ SYS_STATUS_VIDEO_4K_10B 800000
+ >;
+
+ dram_freq = <800000000>;
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
new file mode 100644
index 00000000..4ba0afb8
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
new file mode 100644
index 00000000..73104525
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <45>;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
new file mode 100644
index 00000000..6ea81f5e
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ mmc-hs200-1_8v;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
new file mode 100755
index 00000000..b451da65
@@ -402,12 +612,12 @@ index 00000000..b451da65
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 00000000..f3b262ef
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
new file mode 100644
index 00000000..558cdd75
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,24 @@
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
@@ -419,8 +629,32 @@ index 00000000..f3b262ef
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+ fragment@1 {
+ target = <&nandc>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 00000000..91f06009
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
@@ -442,6 +676,34 @@ index 00000000..d4c39e20
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
new file mode 100644
index 00000000..73ef29de
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/rk-input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
new file mode 100755
index 00000000..f30f21a8
@@ -720,17 +982,24 @@ index 00000000..e9cda296
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
new file mode 100644
index 00000000..e9cda296
index 00000000..1450ee3c
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
@@ -0,0 +1,81 @@
@@ -0,0 +1,97 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/rk-input.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for AEMS IPB900 boards
+ *
+ * - enables working and auxiliary leds
+ * - fixes low strength on sdio pins for wifi
+ */
+
+/ {
+
+ fragment@0 {
@@ -738,12 +1007,12 @@ index 00000000..e9cda296
+ __overlay__ {
+
+ working {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ auxiliary {
+ gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
@@ -758,14 +1027,14 @@ index 00000000..e9cda296
+ target-path = "/pinctrl/gpio";
+ __overlay__ {
+
+ gpio_led_working: gpio-led-working {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ gpio_led_aux: gpio-led-aux {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ reset_key: reset-key {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ };
+ };
+
@@ -773,6 +1042,9 @@ index 00000000..e9cda296
+ target = <&gpio_keys>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_key>;
+
+ reset {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "reset";
@@ -785,25 +1057,31 @@ index 00000000..e9cda296
+ };
+
+ fragment@3 {
+ target = <&sdio_pwrseq>;
+ target = <&sdio_bus4>;
+ __overlay__ {
+
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; /* GPIO2_D3 */
+
+ rockchip,pins = <3 2 1 &pcfg_pull_up>,
+ <3 3 1 &pcfg_pull_up>,
+ <3 4 1 &pcfg_pull_up>,
+ <3 5 1 &pcfg_pull_up>;
+ };
+
+ };
+
+ fragment@4 {
+ target = <&wifi_enable_h>;
+ target = <&sdio_clk>;
+ __overlay__ {
+
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+
+ rockchip,pins = <3 0 1 &pcfg_pull_down>;
+ };
+
+ };
+
+ fragment@5 {
+ target = <&sdio_cmd>;
+ __overlay__ {
+ rockchip,pins = <3 1 1 &pcfg_pull_up>;
+ };
+ };
+
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
new file mode 100755

234
patch/kernel/archive/rk322x-5.10/03-0001-fix-ddr-clock-gate-add-SIP-v2-calls.patch Normal file
View File

@@ -0,0 +1,234 @@
From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 6 Jul 2021 14:21:52 +0000
Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls
---
drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++++
drivers/clk/rockchip/clk-rk3228.c | 14 ++--
drivers/clk/rockchip/clk-rk3328.c | 7 +-
drivers/clk/rockchip/clk.h | 3 +-
4 files changed, 143 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 86718c54e..b16b3795f 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
.get_parent = rockchip_ddrclk_get_parent,
};
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
+#define SCREEN_NULL 0
+#define SCREEN_HDMI 6
+
+static inline int rk_drm_get_lcdc_type(void)
+{
+ return SCREEN_NULL;
+}
+
+struct share_params {
+ u32 hz;
+ u32 lcdc_type;
+ u32 vop;
+ u32 vop_dclk_mode;
+ u32 sr_idle_en;
+ u32 addr_mcu_el3;
+ /*
+ * 1: need to wait flag1
+ * 0: never wait flag1
+ */
+ u32 wait_flag1;
+ /*
+ * 1: need to wait flag1
+ * 0: never wait flag1
+ */
+ u32 wait_flag0;
+ u32 complt_hwirq;
+ /* if need, add parameter after */
+};
+
+struct rockchip_ddrclk_data {
+ u32 inited_flag;
+ void __iomem *share_memory;
+};
+
+static struct rockchip_ddrclk_data ddr_data;
+
+static void rockchip_ddrclk_data_init(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
+ 1, SHARE_PAGE_TYPE_DDR, 0,
+ 0, 0, 0, 0, &res);
+
+ if (!res.a0) {
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
+ ddr_data.inited_flag = 1;
+ }
+}
+
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long prate)
+{
+ struct share_params *p;
+ struct arm_smccc_res res;
+
+ if (!ddr_data.inited_flag)
+ rockchip_ddrclk_data_init();
+
+ p = (struct share_params *)ddr_data.share_memory;
+
+ p->hz = drate;
+ p->lcdc_type = rk_drm_get_lcdc_type();
+ p->wait_flag1 = 1;
+ p->wait_flag0 = 1;
+
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
+ SHARE_PAGE_TYPE_DDR, 0,
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
+ 0, 0, 0, 0, &res);
+
+ if ((int)res.a1 == -6) {
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
+ }
+
+ return res.a0;
+}
+
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
+ (struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
+ SHARE_PAGE_TYPE_DDR, 0,
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
+ 0, 0, 0, 0, &res);
+ if (!res.a0)
+ return res.a1;
+ else
+ return 0;
+}
+
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
+{
+ struct share_params *p;
+ struct arm_smccc_res res;
+
+ if (!ddr_data.inited_flag)
+ rockchip_ddrclk_data_init();
+
+ p = (struct share_params *)ddr_data.share_memory;
+
+ p->hz = rate;
+
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
+ SHARE_PAGE_TYPE_DDR, 0,
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
+ 0, 0, 0, 0, &res);
+ if (!res.a0)
+ return res.a1;
+ else
+ return 0;
+}
+
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
+ .get_parent = rockchip_ddrclk_get_parent,
+};
+
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
const char *const *parent_names,
u8 num_parents, int mux_offset,
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
case ROCKCHIP_DDRCLK_SIP:
init.ops = &rockchip_ddrclk_sip_ops;
break;
+ case ROCKCHIP_DDRCLK_SIP_V2:
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
+ break;
default:
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
kfree(ddrclk);
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 1f9176a5c..96393aa16 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
/* PD_DDR */
- COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+ RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
+ ROCKCHIP_DDRCLK_SIP_V2),
GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(7), 1, GFLAGS),
FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
- GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+ GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = {
"sclk_initmem_mbist",
"aclk_initmem",
"hclk_rom",
- "pclk_ddrupctl",
- "pclk_ddrmon",
+ "pclk_ddr_upctl",
+ "pclk_ddr_mon",
"pclk_msch_noc",
"pclk_stimer",
"pclk_ddrphy",
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index cc18dbc18..5fdd611bb 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
RK3328_CLKGATE_CON(14), 1, GFLAGS),
/* PD_DDR */
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
+ ROCKCHIP_DDRCLK_SIP_V2),
+
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 6, GFLAGS),
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index ae059b774..fdaa81ebb 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
* DDRCLK flags, including method of setting the rate
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
*/
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
+#define ROCKCHIP_DDRCLK_SIP 0x01
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
const char *const *parent_names,
--
2.25.1

67
patch/kernel/archive/rk322x-5.10/03-0002-add-ddr-clock-and-SIP-related-constant.patch Normal file
View File

@@ -0,0 +1,67 @@
From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 6 Jul 2021 14:23:36 +0000
Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants
and defines
---
include/dt-bindings/clock/rk3228-cru.h | 1 +
include/soc/rockchip/rockchip_sip.h | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index de550ea56..911824731 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -15,6 +15,7 @@
#define ARMCLK 5
/* sclk gates (special clocks) */
+#define SCLK_DDRCLK 64
#define SCLK_SPI0 65
#define SCLK_NANDC 67
#define SCLK_SDMMC 68
diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
index c46a9ae2a..34e653751 100644
--- a/include/soc/rockchip/rockchip_sip.h
+++ b/include/soc/rockchip/rockchip_sip.h
@@ -6,6 +6,7 @@
#ifndef __SOC_ROCKCHIP_SIP_H
#define __SOC_ROCKCHIP_SIP_H
+#define ROCKCHIP_SIP_ATF_VERSION 0x82000001
#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008
#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
@@ -16,5 +17,28 @@
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
+#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09
+#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a
+#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b
+
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
+#define ROCKCHIP_SIP_SIP_VERSION 0x8200000a
+
+/* Rockchip Sip version */
+#define ROCKCHIP_SIP_IMPLEMENT_V1 (1)
+#define ROCKCHIP_SIP_IMPLEMENT_V2 (2)
+
+/* SIP_ACCESS_REG: read or write */
+#define SECURE_REG_RD 0x0
+#define SECURE_REG_WR 0x1
+
+/* Share mem page types */
+typedef enum {
+ SHARE_PAGE_TYPE_INVALID = 0,
+ SHARE_PAGE_TYPE_UARTDBG,
+ SHARE_PAGE_TYPE_DDR,
+ SHARE_PAGE_TYPE_MAX,
+} share_page_type_t;
#endif
--
2.25.1

744
patch/kernel/archive/rk322x-5.10/03-0003-extend-rockchip-dfi-driver.patch Normal file
View File

@@ -0,0 +1,744 @@
From 415ed43c9b64ca38bc433bd5dc0359292dd80380 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 6 Jul 2021 14:25:41 +0000
Subject: [PATCH 3/5] rk3228/rk3328: extend rockchip dfi driver
---
arch/arm/boot/dts/rk322x.dtsi | 7 +
drivers/devfreq/event/rockchip-dfi.c | 598 ++++++++++++++++++++++++---
2 files changed, 557 insertions(+), 48 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 885fe0af4..88e33eb11 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -97,6 +97,13 @@ opp-1200000000 {
};
};
+ dfi: dfi@11210000 {
+ reg = <0x11210000 0x400>;
+ compatible = "rockchip,rk3228-dfi";
+ rockchip,grf = <&grf>;
+ status = "okay";
+ };
+
amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 9a88faaf8..01fb84b99 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -18,25 +18,68 @@
#include <linux/list.h>
#include <linux/of.h>
-#include <soc/rockchip/rk3399_grf.h>
-
-#define RK3399_DMC_NUM_CH 2
-
+#define PX30_PMUGRF_OS_REG2 0x208
+
+#define RK3128_GRF_SOC_CON0 0x140
+#define RK3128_GRF_OS_REG1 0x1cc
+#define RK3128_GRF_DFI_WRNUM 0x220
+#define RK3128_GRF_DFI_RDNUM 0x224
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
+
+#define RK3228_GRF_OS_REG2 0x5d0
+
+#define RK3288_PMU_SYS_REG2 0x9c
+#define RK3288_GRF_SOC_CON4 0x254
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
+#define RK3288_DFI_EN (0x30003 << 14)
+#define RK3288_DFI_DIS (0x30000 << 14)
+#define RK3288_LPDDR_SEL (0x10001 << 13)
+#define RK3288_DDR3_SEL (0x10000 << 13)
+
+#define RK3328_GRF_OS_REG2 0x5d0
+
+#define RK3368_GRF_DDRC0_CON0 0x600
+#define RK3368_GRF_SOC_STATUS5 0x494
+#define RK3368_GRF_SOC_STATUS6 0x498
+#define RK3368_GRF_SOC_STATUS8 0x4a0
+#define RK3368_GRF_SOC_STATUS9 0x4a4
+#define RK3368_GRF_SOC_STATUS10 0x4a8
+#define RK3368_DFI_EN (0x30003 << 5)
+#define RK3368_DFI_DIS (0x30000 << 5)
+
+#define MAX_DMC_NUM_CH 2
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
/* DDRMON_CTRL */
-#define DDRMON_CTRL 0x04
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
-#define LPDDR4_EN (0x10001 << 4)
-#define HARDWARE_EN (0x10001 << 3)
-#define LPDDR3_EN (0x10001 << 2)
-#define SOFTWARE_EN (0x10001 << 1)
-#define SOFTWARE_DIS (0x10000 << 1)
-#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CTRL 0x04
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
+#define DDR4_EN (0x10001 << 5)
+#define LPDDR4_EN (0x10001 << 4)
+#define HARDWARE_EN (0x10001 << 3)
+#define LPDDR2_3_EN (0x10001 << 2)
+#define SOFTWARE_EN (0x10001 << 1)
+#define SOFTWARE_DIS (0x10000 << 1)
+#define TIME_CNT_EN (0x10001 << 0)
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/* pmu grf */
+#define PMUGRF_OS_REG2 0x308
+
+enum {
+ DDR4 = 0,
+ DDR3 = 3,
+ LPDDR2 = 5,
+ LPDDR3 = 6,
+ LPDDR4 = 7,
+ UNUSED = 0xFF
+};
+
struct dmc_usage {
u32 access;
u32 total;
@@ -50,33 +93,261 @@ struct dmc_usage {
struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc *desc;
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
+ struct regmap *regmap_grf;
+ struct regmap *regmap_pmugrf;
struct clk *clk;
+ u32 dram_type;
+ /*
+ * available mask, 1: available, 0: not available
+ * each bit represent a channel
+ */
+ u32 ch_msk;
+};
+
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf,
+ RK3128_GRF_SOC_CON0,
+ RK3128_DDR_MONITOR_EN);
+}
+
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf,
+ RK3128_GRF_SOC_CON0,
+ RK3128_DDR_MONITOR_DISB);
+}
+
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3128_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3128_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ unsigned long flags;
+ u32 dfi_wr, dfi_rd, dfi_timer;
+
+ local_irq_save(flags);
+
+ rk3128_dfi_stop_hardware_counter(edev);
+
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
+
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
+ edata->total_count = dfi_timer;
+
+ rk3128_dfi_start_hardware_counter(edev);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3128_dfi_ops = {
+ .disable = rk3128_dfi_disable,
+ .enable = rk3128_dfi_enable,
+ .get_event = rk3128_dfi_get_event,
+ .set_event = rk3128_dfi_set_event,
+};
+
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
+}
+
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
+}
+
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3288_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3288_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ u32 tmp, max = 0;
+ u32 i, busier_ch = 0;
+ u32 rd_count, wr_count, total_count;
+
+ rk3288_dfi_stop_hardware_counter(edev);
+
+ /* Find out which channel is busier */
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
+ if (!(info->ch_msk & BIT(i)))
+ continue;
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
+ info->ch_usage[i].total = total_count;
+ tmp = info->ch_usage[i].access;
+ if (tmp > max) {
+ busier_ch = i;
+ max = tmp;
+ }
+ }
+ rk3288_dfi_start_hardware_counter(edev);
+
+ return busier_ch;
+}
+
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ int busier_ch;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
+ local_irq_restore(flags);
+
+ edata->load_count = info->ch_usage[busier_ch].access;
+ edata->total_count = info->ch_usage[busier_ch].total;
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3288_dfi_ops = {
+ .disable = rk3288_dfi_disable,
+ .enable = rk3288_dfi_enable,
+ .get_event = rk3288_dfi_get_event,
+ .set_event = rk3288_dfi_set_event,
+};
+
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
+}
+
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
+}
+
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3368_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3368_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ unsigned long flags;
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
+
+ local_irq_save(flags);
+
+ rk3368_dfi_stop_hardware_counter(edev);
+
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
+
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
+ edata->total_count = dfi_timer;
+
+ rk3368_dfi_start_hardware_counter(edev);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3368_dfi_ops = {
+ .disable = rk3368_dfi_disable,
+ .enable = rk3368_dfi_enable,
+ .get_event = rk3368_dfi_get_event,
+ .set_event = rk3368_dfi_set_event,
};
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = info->regs;
- u32 val;
- u32 ddr_type;
-
- /* get ddr type */
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
- RK3399_PMUGRF_DDRTYPE_MASK;
/* clear DDRMON_CTRL setting */
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
+ else if (info->dram_type == LPDDR4)
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ else if (info->dram_type == DDR4)
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
@@ -100,12 +371,22 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
rockchip_dfi_stop_hardware_counter(edev);
/* Find out which channel is busier */
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
+ if (!(info->ch_msk & BIT(i)))
+ continue;
+
info->ch_usage[i].total = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
- tmp = info->ch_usage[i].access;
+
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
+ tmp = readl_relaxed(dfi_regs +
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ if (info->dram_type == LPDDR4)
+ tmp *= 8;
+ else
+ tmp *= 4;
+ info->ch_usage[i].access = tmp;
+
if (tmp > max) {
busier_ch = i;
max = tmp;
@@ -118,10 +399,14 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
{
+ struct device *dev = &edev->dev;
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
rockchip_dfi_stop_hardware_counter(edev);
- clk_disable_unprepare(info->clk);
+ if (info->clk)
+ clk_disable_unprepare(info->clk);
+
+ dev_notice(dev,"Rockchip DFI interface disabled\n");
return 0;
}
@@ -129,20 +414,28 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ struct device *dev = &edev->dev;
int ret;
- ret = clk_prepare_enable(info->clk);
- if (ret) {
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
- return ret;
+ if (info->clk) {
+ ret = clk_prepare_enable(info->clk);
+ if (ret) {
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
+ ret);
+ return ret;
+ }
}
rockchip_dfi_start_hardware_counter(edev);
+
+ dev_notice(dev,"Rockchip DFI interface enabled\n");
+
return 0;
}
static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
{
+
return 0;
}
@@ -151,8 +444,11 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
{
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
int busier_ch;
+ unsigned long flags;
+ local_irq_save(flags);
busier_ch = rockchip_dfi_get_busier_ch(edev);
+ local_irq_restore(flags);
edata->load_count = info->ch_usage[busier_ch].access;
edata->total_count = info->ch_usage[busier_ch].total;
@@ -167,22 +463,151 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
.set_event = rockchip_dfi_set_event,
};
-static const struct of_device_id rockchip_dfi_id_match[] = {
- { .compatible = "rockchip,rk3399-dfi" },
- { },
-};
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+static __init int px30_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct resource *res;
+ u32 val;
-static int rockchip_dfi_probe(struct platform_device *pdev)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
+ if (node) {
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_pmugrf))
+ return PTR_ERR(data->regmap_pmugrf);
+ }
+
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = 1;
+ data->clk = NULL;
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3128_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ desc->ops = &rk3128_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3228_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
{
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct resource *res;
struct device *dev = &pdev->dev;
- struct rockchip_dfi *data;
- struct devfreq_event_desc *desc;
+ u32 val;
+
+ dev_notice(dev,"rk3228_dfi_init enter\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ regmap_read(data->regmap_grf, RK3228_GRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = 1;
+ data->clk = NULL;
+
+ desc->ops = &rockchip_dfi_ops;
+
+ dev_notice(dev,"rk3228-dfi initialized, dram type: 0x%x, channels: %d\n", data->dram_type, data->ch_msk);
+
+ return 0;
+}
+
+static __init int rk3288_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
struct device_node *np = pdev->dev.of_node, *node;
+ u32 val;
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
+ if (node) {
+ data->regmap_pmu = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_pmu))
+ return PTR_ERR(data->regmap_pmu);
+ }
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = READ_CH_INFO(val);
+
+ if (data->dram_type == DDR3)
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
+ RK3288_DDR3_SEL);
+ else
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
+ RK3288_LPDDR_SEL);
+
+ desc->ops = &rk3288_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3368_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device *dev = &pdev->dev;
+
+ if (!dev->parent || !dev->parent->of_node)
+ return -EINVAL;
+
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+
+ desc->ops = &rk3368_dfi_ops;
+
+ return 0;
+}
+
+static __init int rockchip_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node, *node;
+ u32 val;
data->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->regs))
@@ -202,21 +627,98 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
if (IS_ERR(data->regmap_pmu))
return PTR_ERR(data->regmap_pmu);
}
- data->dev = dev;
+
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = READ_CH_INFO(val);
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3328_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct resource *res;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = 1;
+ data->clk = NULL;
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static const struct of_device_id rockchip_dfi_id_match[] = {
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
+ { .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
+ { },
+};
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+
+static int rockchip_dfi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rockchip_dfi *data;
+ struct devfreq_event_desc *desc;
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc);
+
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
if (!desc)
return -ENOMEM;
- desc->ops = &rockchip_dfi_ops;
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
+ if (match) {
+ init = match->data;
+ if (init) {
+ if (init(pdev, data, desc))
+ return -EINVAL;
+ } else {
+ return 0;
+ }
+ } else {
+ return 0;
+ }
+
desc->driver_data = data;
desc->name = np->name;
data->desc = desc;
+ data->dev = dev;
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
if (IS_ERR(data->edev)) {
- dev_err(&pdev->dev,
- "failed to add devfreq-event device\n");
+ dev_err(dev, "failed to add devfreq-event device\n");
return PTR_ERR(data->edev);
}
--
2.25.1

1936
patch/kernel/archive/rk322x-5.10/03-0004-add-dmc-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

44
patch/kernel/archive/rk322x-5.10/board-rk322x-box.patch
View File

@@ -1,9 +1,9 @@
diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
new file mode 100644
index 000000000..fc6f41c56
index 000000000..556539618
--- /dev/null
+++ b/arch/arm/boot/dts/rk322x-box.dts
@@ -0,0 +1,480 @@
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
@@ -82,6 +82,15 @@ index 000000000..fc6f41c56
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_host: vcc-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
@@ -137,15 +146,6 @@ index 000000000..fc6f41c56
+ vin-supply = <&vccio_1v8>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdd_arm: vdd-arm-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
@@ -252,6 +252,10 @@ index 000000000..fc6f41c56
+ cpu-supply = <&vdd_arm>;
+};
+
+&dmc {
+ logic-supply = <&vdd_log>;
+};
+
+&io_domains {
+ vccio1-supply = <&vccio_3v3>;
+ vccio2-supply = <&vccio_1v8>;
@@ -466,21 +470,3 @@ index 000000000..fc6f41c56
+ };
+
+};
+
+&gpu_opp_table {
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1075000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1075000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ };
+};

582
patch/kernel/archive/rk322x-5.10/general-add-overlays.patch
View File

@@ -1,21 +1,30 @@
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
new file mode 100755
index 000000000..e39fd5d37
index 000000000..092ff28da
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,24 @@
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk322x-emmc.dtbo \
+ rk322x-emmc-pins.dtbo \
+ rk322x-emmc-ddr-ph45.dtbo \
+ rk322x-emmc-ddr-ph180.dtbo \
+ rk322x-emmc-hs200.dtbo \
+ rk322x-nand.dtbo \
+ rk322x-emmc-nand.dtbo \
+ rk322x-led-conf-default.dtbo \
+ rk322x-led-conf1.dtbo \
+ rk322x-led-conf2.dtbo \
+ rk322x-led-conf3.dtbo \
+ rk322x-led-conf4.dtbo \
+ rk322x-led-conf5.dtbo \
+ rk322x-cpu-hs.dtbo \
+ rk322x-wlan-alt-wiring.dtbo \
+ rk322x-cpu-stability.dtbo
+ rk322x-cpu-stability.dtbo \
+ rk322x-ddr3-330.dtbo \
+ rk322x-ddr3-528.dtbo \
+ rk322x-ddr3-660.dtbo \
+ rk322x-ddr3-800.dtbo
+
+scr-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk322x-fixup.scr
@@ -30,10 +39,10 @@ index 000000000..e39fd5d37
+
diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
new file mode 100755
index 000000000..e4ea2f573
index 000000000..c3d25a204
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
@@ -0,0 +1,68 @@
@@ -0,0 +1,75 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
@@ -46,14 +55,12 @@ index 000000000..e4ea2f573
+
+- rk322x-cpu-hs
+- rk322x-cpu-stability
+- rk322x-emmc
+- rk322x-emmc*
+- rk322x-nand
+- rk322x-emmc-nand
+- rk322x-led1-low
+- rk322x-led1-high
+- rk322x-led2-low
+- rk322x-led2-high
+- rk322x-led-conf*
+- rk322x-wlan-alt-wiring
+- rk322x-ddr3-*
+
+### Overlay details:
+
@@ -67,26 +74,26 @@ index 000000000..e4ea2f573
+on some boards which have power regulation issues. Also adds a settling
+time to allow power regulator stabilize voltage.
+
+### emmc
+### emmc*
+
+Activates onboard emmc device node and deactivates the nand controller.
+Also sets up the pin controller default pull up/down configuration
+rk322x-emmc activates onboard emmc device node and deactivates the
+nand controller.
+rk322x-emmc-pins sets the pin controller default pull up/down
+configuration, not all boards are happy with this overlay, so your
+mileage may vary and may want to not use it.
+rk322x-emmc-ddr-ph45/ph180 sets the emmc ddr mode. First overlay
+sets the default phase clock shifting to 45 degrees, the second
+overlay to 180 degrees. They are alternative, choose the one that
+makes your emmc perform better.
+rk322x-emmc-hs200 enables the hs200 mode. It is preferable to
+ddr mode because it is more stable, but old emmc parts don't
+support it.
+
+### nand
+
+Activates onboard nand device node and deactivates the emmc controller.
+Also sets up the pin controller default pull up/down configuration
+
+### emmc-nand
+
+Activates onboard nand and emmc devices. Usually they are alternative
+because manufacturers share the same pads so emmc and nand cannot be
+mixed together. Usually this works because the emmc and nand drivers
+can automatically guess what's in the pads, but may bring instabilities
+or misdetections. Also does not set up the pin controller default
+configuration, which in turn can be detrimental of stability and
+performance
+
+### rk322x-led-conf*
+
+Each device tree of this kind provides a different known wiring configuration
@@ -97,11 +104,184 @@ index 000000000..e4ea2f573
+led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
+led-conf3 is found in boards with R28-MXQ marking
+led-conf4 is found on boards with T066 marking
+led-conf5 is found on boards with IPB900 marking from AEMS PVT
+
+### rk322x-alt-wiring
+
+Some boards have different SDIO wiring setup for wifi chips. This overlay
+enables the different pin controller wiring and power enable
+
+### rk322x-ddr3-*
+
+Enable DRAM memory controller and sets the speed to the given speed bin.
+The DRAM memory controller reclocking only works with DDR3/LPDDR3, if
+you enable one of these overlays on boards with DDR2 memory the system
+will not boot anymore
+
diff --git a/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
new file mode 100755
index 000000000..5698b14ba
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
@@ -0,0 +1,39 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/";
+ __overlay__ {
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ BT,power_gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
+ BT,wake_gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
+ BT,wake_host_irq = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart11_rts>;
+ pinctrl-1 = <&uart11_rts_gpio>;
+ status = "okay";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&uart1>;
+ __overlay__ {
+ dma-names = "!tx", "!rx";
+ dmas = <&pdma 0x04 &pdma 0x05>;
+ #dma-cells = <0x02>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart11_xfer &uart11_cts>;
+ status = "okay";
+ };
+
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
new file mode 100755
index 000000000..4cde11782
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
@@ -0,0 +1,113 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&cpu0_opp_table>;
+ __overlay__ {
+
+ opp-408000000 {
+ opp-microvolt = <850000 850000 1275000>;
+ opp-microvolt-L0 = <850000 850000 1275000>;
+ opp-microvolt-L1 = <850000 850000 1275000>;
+ };
+ opp-600000000 {
+ opp-microvolt = <875000 875000 1275000>;
+ opp-microvolt-L0 = <875000 875000 1275000>;
+ opp-microvolt-L1 = <875000 875000 1275000>;
+ };
+ opp-816000000 {
+ opp-microvolt = <900000 900000 1275000>;
+ opp-microvolt-L0 = <900000 900000 1275000>;
+ opp-microvolt-L1 = <900000 900000 1275000>;
+ };
+ opp-1008000000 {
+ opp-microvolt = <1075000 1075000 1275000>;
+ opp-microvolt-L0 = <1075000 1075000 1275000>;
+ opp-microvolt-L1 = <1025000 1025000 1275000>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <1175000 1175000 1275000>;
+ opp-microvolt-L0 = <1175000 1175000 1275000>;
+ opp-microvolt-L1 = <1125000 1125000 1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1225000 1225000 1400000>;
+ opp-microvolt-L0 = <1225000 1225000 1400000>;
+ opp-microvolt-L1 = <1225000 1225000 1400000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1250000 1250000 1400000>;
+ opp-microvolt-L0 = <1250000 1250000 1400000>;
+ opp-microvolt-L1 = <1250000 1250000 1400000>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&vdd_arm>;
+ __overlay__ {
+ regulator-min-microvolt = <850000>;
+ };
+ };
+
+ fragment@2 {
+ target = <&gpu_opp_table>;
+ __overlay__ {
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1000000>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&vdd_log>;
+ __overlay__ {
+ regulator-min-microvolt = <900000>;
+ };
+ };
+
+ fragment@4 {
+ target = <&rkvdec_opp_table>;
+ __overlay__ {
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
new file mode 100755
index 000000000..1c2fc79e1
@@ -194,12 +374,148 @@ index 000000000..f434af926
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
new file mode 100755
index 000000000..9b273bf75
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts
new file mode 100644
index 000000000..78145548e
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
@@ -0,0 +1,22 @@
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&dmc_opp_table>;
+ __overlay__ {
+ opp-534000000 {
+ status = "disabled";
+ };
+ opp-660000000 {
+ status = "disabled";
+ };
+ opp-786000000 {
+ status = "disabled";
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts
new file mode 100644
index 000000000..dbbd222dd
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&dmc_opp_table>;
+ __overlay__ {
+ opp-534000000 {
+ status = "okay";
+ };
+ opp-660000000 {
+ status = "disabled";
+ };
+ opp-786000000 {
+ status = "disabled";
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts
new file mode 100644
index 000000000..65b707515
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&dmc_opp_table>;
+ __overlay__ {
+ opp-534000000 {
+ status = "okay";
+ };
+ opp-660000000 {
+ status = "okay";
+ };
+ opp-786000000 {
+ status = "disabled";
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts
new file mode 100644
index 000000000..7d11453ad
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&dmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&dmc_opp_table>;
+ __overlay__ {
+ opp-534000000 {
+ status = "okay";
+ };
+ opp-660000000 {
+ status = "okay";
+ };
+ opp-786000000 {
+ status = "okay";
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
new file mode 100644
index 000000000..4ba0afb8a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
@@ -208,26 +524,57 @@ index 000000000..9b273bf75
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+ fragment@1 {
+ target = <&nfc>;
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
new file mode 100644
index 000000000..73104525d
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <45>;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 000000000..10b2f0f0d
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
new file mode 100644
index 000000000..6ea81f5e7
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,24 @@
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ mmc-hs200-1_8v;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
new file mode 100644
index 000000000..0074d029a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
@@ -239,8 +586,32 @@ index 000000000..10b2f0f0d
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+ fragment@1 {
+ target = <&nfc>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 000000000..0a59ee30e
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
@@ -262,6 +633,34 @@ index 000000000..d4c39e20a
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
new file mode 100644
index 000000000..7e4b35e33
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
new file mode 100755
index 000000000..6846109d3
@@ -559,6 +958,109 @@ index 000000000..0ebd846eb
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
new file mode 100755
index 000000000..1450ee3c3
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
@@ -0,0 +1,97 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for AEMS IPB900 boards
+ *
+ * - enables working and auxiliary leds
+ * - fixes low strength on sdio pins for wifi
+ */
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ auxiliary {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target-path = "/pinctrl/gpio";
+ __overlay__ {
+
+ gpio_led_aux: gpio-led-aux {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ reset_key: reset-key {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&gpio_keys>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_key>;
+
+ reset {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <200>;
+ wakeup-source;
+ };
+
+ };
+ };
+
+ fragment@3 {
+ target = <&sdio_bus4>;
+ __overlay__ {
+ rockchip,pins = <3 2 1 &pcfg_pull_up>,
+ <3 3 1 &pcfg_pull_up>,
+ <3 4 1 &pcfg_pull_up>,
+ <3 5 1 &pcfg_pull_up>;
+ };
+
+ };
+
+ fragment@4 {
+ target = <&sdio_clk>;
+ __overlay__ {
+ rockchip,pins = <3 0 1 &pcfg_pull_down>;
+ };
+ };
+
+ fragment@5 {
+ target = <&sdio_cmd>;
+ __overlay__ {
+ rockchip,pins = <3 1 1 &pcfg_pull_up>;
+ };
+ };
+
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
new file mode 100755
index 000000000..2a939ab49

26
patch/kernel/archive/rk322x-5.10/wifi-4001-add-realtek-8723cs-kconfig-makefile.patch Normal file
View File

@@ -0,0 +1,26 @@
diff --git a/drivers/net/wireless/realtek/Kconfig b/drivers/net/wireless/realtek/Kconfig
index 8ea2d8d..600c44d 100644
--- a/drivers/net/wireless/realtek/Kconfig
+++ b/drivers/net/wireless/realtek/Kconfig
@@ -13,8 +13,9 @@ config WLAN_VENDOR_REALTEK
if WLAN_VENDOR_REALTEK
source "drivers/net/wireless/realtek/rtl818x/Kconfig"
source "drivers/net/wireless/realtek/rtlwifi/Kconfig"
source "drivers/net/wireless/realtek/rtl8xxxu/Kconfig"
+source "drivers/net/wireless/realtek/rtl8723cs/Kconfig"
source "drivers/net/wireless/realtek/rtw88/Kconfig"
endif # WLAN_VENDOR_REALTEK
diff --git a/drivers/net/wireless/realtek/Makefile b/drivers/net/wireless/realtek/Makefile
index 9c78deb5..07b47850 100644
--- a/drivers/net/wireless/realtek/Makefile
+++ b/drivers/net/wireless/realtek/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_RTL8180) += rtl818x/
obj-$(CONFIG_RTL8187) += rtl818x/
+obj-$(CONFIG_RTL8723CS) += rtl8723cs/
obj-$(CONFIG_RTLWIFI) += rtlwifi/
obj-$(CONFIG_RTL8XXXU) += rtl8xxxu/

349055
patch/kernel/archive/rk322x-5.10/wifi-4002-add-realtek-8723cs.patch Normal file
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File diff suppressed because it is too large Load Diff

431
patch/kernel/archive/rk322x-5.12/general-add-overlays.patch
View File

@@ -1,18 +1,23 @@
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
new file mode 100755
index 000000000..e39fd5d37
index 000000000..894db3d1e
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,24 @@
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0
+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk322x-emmc.dtbo \
+ rk322x-emmc-pins.dtbo \
+ rk322x-emmc-ddr-ph45.dtbo \
+ rk322x-emmc-ddr-ph180.dtbo \
+ rk322x-emmc-hs200.dtbo \
+ rk322x-nand.dtbo \
+ rk322x-emmc-nand.dtbo \
+ rk322x-led-conf-default.dtbo \
+ rk322x-led-conf1.dtbo \
+ rk322x-led-conf2.dtbo \
+ rk322x-led-conf3.dtbo \
+ rk322x-led-conf4.dtbo \
+ rk322x-led-conf5.dtbo \
+ rk322x-cpu-hs.dtbo \
+ rk322x-wlan-alt-wiring.dtbo \
+ rk322x-cpu-stability.dtbo
@@ -30,10 +35,10 @@ index 000000000..e39fd5d37
+
diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
new file mode 100755
index 000000000..e4ea2f573
index 000000000..aeabdb0cc
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
@@ -0,0 +1,68 @@
@@ -0,0 +1,66 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
@@ -46,13 +51,10 @@ index 000000000..e4ea2f573
+
+- rk322x-cpu-hs
+- rk322x-cpu-stability
+- rk322x-emmc
+- rk322x-emmc*
+- rk322x-nand
+- rk322x-emmc-nand
+- rk322x-led1-low
+- rk322x-led1-high
+- rk322x-led2-low
+- rk322x-led2-high
+- rk322x-led-conf*
+- rk322x-wlan-alt-wiring
+
+### Overlay details:
@@ -67,26 +69,26 @@ index 000000000..e4ea2f573
+on some boards which have power regulation issues. Also adds a settling
+time to allow power regulator stabilize voltage.
+
+### emmc
+### emmc*
+
+Activates onboard emmc device node and deactivates the nand controller.
+Also sets up the pin controller default pull up/down configuration
+rk322x-emmc activates onboard emmc device node and deactivates the
+nand controller.
+rk322x-emmc-pins sets the pin controller default pull up/down
+configuration, not all boards are happy with this overlay, so your
+mileage may vary and may want to not use it.
+rk322x-emmc-ddr-ph45/ph180 sets the emmc ddr mode. First overlay
+sets the default phase clock shifting to 45 degrees, the second
+overlay to 180 degrees. They are alternative, choose the one that
+makes your emmc perform better.
+rk322x-emmc-hs200 enables the hs200 mode. It is preferable to
+ddr mode because it is more stable, but old emmc parts don't
+support it.
+
+### nand
+
+Activates onboard nand device node and deactivates the emmc controller.
+Also sets up the pin controller default pull up/down configuration
+
+### emmc-nand
+
+Activates onboard nand and emmc devices. Usually they are alternative
+because manufacturers share the same pads so emmc and nand cannot be
+mixed together. Usually this works because the emmc and nand drivers
+can automatically guess what's in the pads, but may bring instabilities
+or misdetections. Also does not set up the pin controller default
+configuration, which in turn can be detrimental of stability and
+performance
+
+### rk322x-led-conf*
+
+Each device tree of this kind provides a different known wiring configuration
@@ -97,11 +99,176 @@ index 000000000..e4ea2f573
+led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
+led-conf3 is found in boards with R28-MXQ marking
+led-conf4 is found on boards with T066 marking
+led-conf5 is found on boards with IPB900 marking from AEMS PVT
+
+### rk322x-alt-wiring
+
+Some boards have different SDIO wiring setup for wifi chips. This overlay
+enables the different pin controller wiring and power enable
diff --git a/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
new file mode 100755
index 000000000..5698b14ba
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts
@@ -0,0 +1,39 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/";
+ __overlay__ {
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ BT,power_gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
+ BT,wake_gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
+ BT,wake_host_irq = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart11_rts>;
+ pinctrl-1 = <&uart11_rts_gpio>;
+ status = "okay";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&uart1>;
+ __overlay__ {
+ dma-names = "!tx", "!rx";
+ dmas = <&pdma 0x04 &pdma 0x05>;
+ #dma-cells = <0x02>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart11_xfer &uart11_cts>;
+ status = "okay";
+ };
+
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
new file mode 100755
index 000000000..4cde11782
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs-lv.dts
@@ -0,0 +1,113 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&cpu0_opp_table>;
+ __overlay__ {
+
+ opp-408000000 {
+ opp-microvolt = <850000 850000 1275000>;
+ opp-microvolt-L0 = <850000 850000 1275000>;
+ opp-microvolt-L1 = <850000 850000 1275000>;
+ };
+ opp-600000000 {
+ opp-microvolt = <875000 875000 1275000>;
+ opp-microvolt-L0 = <875000 875000 1275000>;
+ opp-microvolt-L1 = <875000 875000 1275000>;
+ };
+ opp-816000000 {
+ opp-microvolt = <900000 900000 1275000>;
+ opp-microvolt-L0 = <900000 900000 1275000>;
+ opp-microvolt-L1 = <900000 900000 1275000>;
+ };
+ opp-1008000000 {
+ opp-microvolt = <1075000 1075000 1275000>;
+ opp-microvolt-L0 = <1075000 1075000 1275000>;
+ opp-microvolt-L1 = <1025000 1025000 1275000>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <1175000 1175000 1275000>;
+ opp-microvolt-L0 = <1175000 1175000 1275000>;
+ opp-microvolt-L1 = <1125000 1125000 1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1225000 1225000 1400000>;
+ opp-microvolt-L0 = <1225000 1225000 1400000>;
+ opp-microvolt-L1 = <1225000 1225000 1400000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1250000 1250000 1400000>;
+ opp-microvolt-L0 = <1250000 1250000 1400000>;
+ opp-microvolt-L1 = <1250000 1250000 1400000>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&vdd_arm>;
+ __overlay__ {
+ regulator-min-microvolt = <850000>;
+ };
+ };
+
+ fragment@2 {
+ target = <&gpu_opp_table>;
+ __overlay__ {
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1000000>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&vdd_log>;
+ __overlay__ {
+ regulator-min-microvolt = <900000>;
+ };
+ };
+
+ fragment@4 {
+ target = <&rkvdec_opp_table>;
+ __overlay__ {
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ opp-microvolt-L0 = <950000>;
+ opp-microvolt-L1 = <900000>;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
new file mode 100755
index 000000000..1c2fc79e1
@@ -194,12 +361,12 @@ index 000000000..f434af926
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
new file mode 100755
index 000000000..9b273bf75
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
new file mode 100644
index 000000000..4ba0afb8a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
@@ -0,0 +1,22 @@
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
@@ -208,26 +375,57 @@ index 000000000..9b273bf75
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+ fragment@1 {
+ target = <&nfc>;
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
new file mode 100644
index 000000000..73104525d
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph45.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <45>;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 000000000..10b2f0f0d
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
new file mode 100644
index 000000000..6ea81f5e7
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,24 @@
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-hs200.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ mmc-hs200-1_8v;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
new file mode 100644
index 000000000..0074d029a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc-pins.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
@@ -239,8 +437,32 @@ index 000000000..10b2f0f0d
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
+ mmc-ddr-1_8v;
+ rockchip,default-sample-phase = <180>;
+ };
+ };
+
+ fragment@1 {
+ target = <&nfc>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
new file mode 100755
index 000000000..0a59ee30e
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
@@ -262,6 +484,34 @@ index 000000000..d4c39e20a
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
new file mode 100644
index 000000000..7e4b35e33
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf-default.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
new file mode 100755
index 000000000..6846109d3
@@ -559,6 +809,109 @@ index 000000000..0ebd846eb
+ };
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
new file mode 100755
index 000000000..1450ee3c3
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/rk322x-led-conf5.dts
@@ -0,0 +1,97 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/*
+ * gpio configuration for AEMS IPB900 boards
+ *
+ * - enables working and auxiliary leds
+ * - fixes low strength on sdio pins for wifi
+ */
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ auxiliary {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target-path = "/pinctrl/gpio";
+ __overlay__ {
+
+ gpio_led_aux: gpio-led-aux {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ reset_key: reset-key {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&gpio_keys>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_key>;
+
+ reset {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <200>;
+ wakeup-source;
+ };
+
+ };
+ };
+
+ fragment@3 {
+ target = <&sdio_bus4>;
+ __overlay__ {
+ rockchip,pins = <3 2 1 &pcfg_pull_up>,
+ <3 3 1 &pcfg_pull_up>,
+ <3 4 1 &pcfg_pull_up>,
+ <3 5 1 &pcfg_pull_up>;
+ };
+
+ };
+
+ fragment@4 {
+ target = <&sdio_clk>;
+ __overlay__ {
+ rockchip,pins = <3 0 1 &pcfg_pull_down>;
+ };
+ };
+
+ fragment@5 {
+ target = <&sdio_cmd>;
+ __overlay__ {
+ rockchip,pins = <3 1 1 &pcfg_pull_up>;
+ };
+ };
+
+
+};
diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
new file mode 100755
index 000000000..2a939ab49

26
patch/kernel/archive/rk322x-5.12/wifi-4001-add-realtek-8723cs-kconfig-makefile.patch Normal file
View File

@@ -0,0 +1,26 @@
diff --git a/drivers/net/wireless/realtek/Kconfig b/drivers/net/wireless/realtek/Kconfig
index 8ea2d8d..600c44d 100644
--- a/drivers/net/wireless/realtek/Kconfig
+++ b/drivers/net/wireless/realtek/Kconfig
@@ -13,8 +13,9 @@ config WLAN_VENDOR_REALTEK
if WLAN_VENDOR_REALTEK
source "drivers/net/wireless/realtek/rtl818x/Kconfig"
source "drivers/net/wireless/realtek/rtlwifi/Kconfig"
source "drivers/net/wireless/realtek/rtl8xxxu/Kconfig"
+source "drivers/net/wireless/realtek/rtl8723cs/Kconfig"
source "drivers/net/wireless/realtek/rtw88/Kconfig"
endif # WLAN_VENDOR_REALTEK
diff --git a/drivers/net/wireless/realtek/Makefile b/drivers/net/wireless/realtek/Makefile
index 9c78deb5..07b47850 100644
--- a/drivers/net/wireless/realtek/Makefile
+++ b/drivers/net/wireless/realtek/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_RTL8180) += rtl818x/
obj-$(CONFIG_RTL8187) += rtl818x/
+obj-$(CONFIG_RTL8723CS) += rtl8723cs/
obj-$(CONFIG_RTLWIFI) += rtlwifi/
obj-$(CONFIG_RTL8XXXU) += rtl8xxxu/

349055
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