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remove a83t-OPP and H3-H5-THS patches since Megous 5.3.0-RC6 have them

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Martin Ayotte
2019-09-02 14:55:55 -04:00
parent 58406ce59b
commit b53556a5f1
2 changed files with 0 additions and 71 deletions
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39
patch/kernel/sunxi-dev/0019-arm-dts-sunxi-h3-h5-add-support-for-the-thermal-sens.patch
View File

@@ -1,39 +0,0 @@
From f1b96d20375eb192d017999740c0055f2efbf576 Mon Sep 17 00:00:00 2001
From: Philipp Rossak <embed3d@gmail.com>
Date: Fri, 26 Jan 2018 01:01:34 +0100
Subject: [PATCH 019/146] arm: dts: sunxi-h3-h5: add support for the thermal
sensor in H3 and H5
As we have gained the support for the thermal sensor in H3 and H5,
we can now add its device nodes to the device tree. The H3 and H5 share
most of its compatible. The compatible and the thermal sensor cells
will be added in an additional patch per device.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc6131315c47..8fde0f6c16e4 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -488,6 +488,15 @@
};
};
+ ths: thermal-sensor@1c25000 {
+ reg = <0x01c25000 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_THS>;
+ #io-channel-cells = <0>;
+ };
+
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
--
2.17.1

32
patch/kernel/sunxi-dev/board-a83t-add-one-more-freq-step-1.6ghz.patch
View File

@@ -1,32 +0,0 @@
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0233008a8..c707fed8c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -243,6 +243,13 @@
opp-microvolt = <840000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <920000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
};
cpu1_opp_table: opp_table1 {
@@ -296,6 +303,13 @@
opp-microvolt = <840000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <920000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
};
soc {