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rockchip: Remove old edge kernel patch folder 6.7

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ColorfulRhino
2024-04-17 13:09:33 +02:00
committed by Igor
parent 5b867a1cbd
commit a4aa9972d8
120 changed files with 0 additions and 83060 deletions
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35
patch/kernel/archive/rockchip-6.7/0000.patching_config.yaml
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@@ -1,35 +0,0 @@
config:
# Just some info stuff; not used by the patching scripts
name: rockchip-6.7
kind: kernel
type: mainline # or: vendor
branch: linux-6.7.y
last-known-good-tag: v6.7.0
maintainers:
- { github: paolo.sabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock }
# .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones.
# This is meant to provide a way to "add a board DTS" without having to null-patch them in.
dts-directories:
- { source: "dt", target: "arch/arm/boot/dts/rockchip" }
# every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones
# This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in.
# @TODO need a solution to auto-Makefile the overlays as well
overlay-directories:
- { source: "overlay", target: "arch/arm/boot/dts/rockchip/overlay" }
# the Makefile in each of these directories will be magically patched to include the dts files copied
# or patched-in; overlay subdir will be included "-y" if it exists.
# No more Makefile patching needed, yay!
auto-patch-dt-makefile:
- { directory: "arch/arm/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" }
# configuration for when applying patches to git / auto-rewriting patches (development cycle helpers)
patches-to-git:
do-not-commit-files:
- "MAINTAINERS" # constant churn, drop them. sorry.
- "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry.
do-not-commit-regexes: # Python-style regexes
- "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now

49
patch/kernel/archive/rockchip-6.7/armbian.series
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@@ -1,49 +0,0 @@
# Series from patches.armbian/
patches.armbian/bt-broadcom-serdev-workaround.patch
patches.armbian/clk-rk322x-composite-mmc-clk.patch
patches.armbian/clk-rockchip-max-frac-divider.patch
patches.armbian/driver-rk322x-audio-codec.patch
patches.armbian/driver-rk3288-gpiomem.patch
patches.armbian/driver-tinkerboard-alc4040-codec.patch
patches.armbian/drm-rk322x-plane-overlay.patch
patches.armbian/drm-rk322x-yuv-10bit-modes.patch
patches.armbian/drm-rockchip-hardware-cursor.patch
patches.armbian/dts-miqi-fan.patch
patches.armbian/dts-miqi-hevc-rga.patch
patches.armbian/dts-miqi-mali-gpu.patch
patches.armbian/dts-miqi-regulator-fix.patch
patches.armbian/dts-rk322x-iep-node.patch
patches.armbian/dts-rk322x-pinctrl-nand.patch
patches.armbian/dts-rk3288-disable-serial-dma.patch
patches.armbian/dts-rk3288-fix-mmc-aliases.patch
patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
patches.armbian/dts-rk3288-pinctrl-spi2.patch
patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
patches.armbian/dts-tinkerboard-bt-uart-pins.patch
patches.armbian/dts-tinkerboard-hevc-rga.patch
patches.armbian/dts-tinkerboard-sdio-wifi.patch
patches.armbian/dts-tinkerboard-sdmmc-properties.patch
patches.armbian/dts-tinkerboard-spi-interface.patch
patches.armbian/dts-veyron-flag-cache-flush.patch
patches.armbian/general-add-overlay-compilation-support.patch
patches.armbian/general-add-overlay-configfs.patch
patches.armbian/general-add-restart-handler-for-act8846.patch
patches.armbian/general-fix-reboot-from-kwiboo.patch
patches.armbian/general-linux-export-mm-trace-rss-stats.patch
patches.armbian/general-rk322x-gpio-ir-driver.patch
patches.armbian/general-rockchip-various-fixes.patch
patches.armbian/ir-keymap-rk322x-box.patch
patches.armbian/ir-keymap-xt-q8l-v10.patch
patches.armbian/misc-tinkerboard-spi-interface.patch
patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch
patches.armbian/rk322x-dwc2-no-clock-gating.patch
patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch
patches.armbian/rk322x-dmc-driver-02-sip-constants.patch
patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch
patches.armbian/rk322x-dmc-driver-04-driver.patch
patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch
patches.armbian/wifi-brcmfmac-add-bcm43342.patch
patches.armbian/wifi-brcmfmac-ap6330-firmware.patch
patches.armbian/wifi-driver-esp8089.patch
patches.armbian/wifi-driver-ssv6051.patch

782
patch/kernel/archive/rockchip-6.7/dt/rk322x-box.dts
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@@ -1,782 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk322x.dtsi"
/ {
model = "Generic RK322x Tv Box board";
compatible = "rockchip,rk3229";
/*
* No need to reserve memory manually as long as u-boot v2020.10 and
* OPTEE autoconfigure the reserved zones
*/
/delete-node/ reserved-memory;
/*
* We rebuild the cpu-opp-table by ourselves
*/
/delete-node/ opp-table-0;
/*
* Rebuild the thermal zones and cooling maps ourselved
*/
/delete-node/ thermal-zones;
/*
* Include the mmc devices into aliases table
*/
aliases {
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
};
analog-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "analog";
simple-audio-card,cpu {
sound-dai = <&i2s1>;
};
simple-audio-card,codec {
sound-dai = <&codec>;
};
};
chosen {
bootargs = "earlyprintk=uart8250,mmio32,0x11030000";
};
cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1175000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1275000>;
};
};
gpio_leds: gpio-leds {
compatible = "gpio-leds";
/*
* Working led, available on all boards
*/
working {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
label = "working";
default-state = "on";
linux,default-trigger = "timer";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_working>;
};
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
};
ir_receiver: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&ir_int>;
pinctrl-names = "default";
status = "okay";
linux,rc-map-name = "rc-rk322x-tvbox";
};
rockchip_ir_receiver: rockchip-ir-receiver {
compatible = "rockchip-ir-receiver";
reg = <0x110b0030 0x10>;
gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
clocks = <&cru PCLK_PWM>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
linux,rc-map-name = "rc-rk322x-tvbox";
pinctrl-names = "default", "suspend";
pinctrl-0 = <&ir_int>;
pinctrl-1 = <&pwm3_pin>;
pwm-id = <3>;
shutdown-is-virtual-poweroff;
wakeup-source;
status = "disabled";
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
};
spdif_out: spdif-out {
status = "okay";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vccio_1v8: vccio-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vccio_3v3: vccio-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_otg: vcc-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vccio_1v8>;
};
vdd_arm: vdd-arm-regulator {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log-regulator {
compatible = "pwm-regulator";
pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <95000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <105000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
cpu_throttle_low: map-cpu-throttle-low {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 1>,
<&cpu1 THERMAL_NO_LIMIT 1>,
<&cpu2 THERMAL_NO_LIMIT 1>,
<&cpu3 THERMAL_NO_LIMIT 1>;
};
cpu_throttle_high: map-cpu-throttle-high {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
gpu_throttle_low: map-gpu-throttle-low {
trip = <&cpu_alert0>;
cooling-device =
<&gpu THERMAL_NO_LIMIT 1>;
};
gpu_throttle_high: map-gpu-throttle-high {
trip = <&cpu_alert1>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
dmc_throttle_low: map-dmc-throttle-low {
trip = <&cpu_alert0>;
cooling-device = <&dmc THERMAL_NO_LIMIT 1>;
};
dmc_throttle_high: map-dmc-throttle-high {
trip = <&cpu_alert1>;
cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
&codec {
#sound-dai-cells = <0>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&cru {
assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>,
<&cru PLL_CPLL>, <&cru ACLK_PERI>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
<&cru PCLK_CPU>, <&cru ACLK_VOP>;
assigned-clock-rates = <1200000000>, <816000000>,
<500000000>, <150000000>,
<150000000>, <75000000>,
<150000000>, <150000000>,
<75000000>, <400000000>;
};
&dmc {
logic-supply = <&vdd_log>;
};
&emmc {
cap-mmc-highspeed;
keep-power-in-suspend;
non-removable;
status = "okay";
/delete-property/ mmc-ddr-1_8v;
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
/delete-property/ rockchip,default-sample-phase;
rockchip,default-sample-phase = <90>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-handle = <&phy>;
phy-mode = "rmii";
phy-supply = <&vcc_phy>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
clocks = <&cru SCLK_MAC_PHY>;
phy-is-integrated;
resets = <&cru SRST_MACPHY>;
};
};
};
&gpu {
assigned-clocks = <&cru ACLK_GPU>;
assigned-clock-rates = <300000000>;
mali-supply = <&vdd_log>;
};
&gpu_opp_table {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000 1000000 1200000>;
};
};
&io_domains {
vccio1-supply = <&vccio_3v3>;
vccio2-supply = <&vccio_1v8>;
vccio4-supply = <&vccio_3v3>;
status = "okay";
};
&nfc {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
nand@0 {
reg = <0>;
label = "rk-nand";
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <60>;
nand-is-boot-medium;
rockchip,boot-blks = <8>;
rockchip,boot-ecc-strength = <60>;
};
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&hdmi_phy {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s1 {
#sound-dai-cells = <0>;
status = "okay";
};
/** Integration to pin controller */
&pinctrl {
pcfg_pull_up_12ma: pcfg-pull-up-12ma {
drive-strength = <12>;
bias-pull-up;
};
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
drive-strength = <12>;
bias-pull-down;
};
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
drive-strength = <12>;
bias-disable;
};
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
drive-strength = <8>;
bias-pull-up;
};
pcfg_pull_down_8ma: pcfg-pull-down-8ma {
drive-strength = <8>;
bias-pull-down;
};
pcfg_pull_none_8ma: pcfg-pull-none-8ma {
drive-strength = <8>;
bias-disable;
};
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
drive-strength = <2>;
bias-pull-up;
};
pcfg_pull_down_2ma: pcfg-pull-down-2ma {
drive-strength = <2>;
bias-pull-down;
};
pcfg_pull_none_2ma: pcfg-pull-none-2ma {
drive-strength = <2>;
bias-disable;
};
/*
* Some rk322x electrical schemes report this kind of pull-up/down
* pin configurations. We set them here, but we don't use it in this
* device tree. These instead are useful for overlays, because they seem
* to increase stability on at least one board I got here
*/
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 16 1 &pcfg_pull_down>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 15 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 18 1 &pcfg_pull_up>,
<1 19 1 &pcfg_pull_up>,
<1 20 1 &pcfg_pull_up>,
<1 21 1 &pcfg_pull_up>;
};
};
/*
* Same as above, decreasing strength of SDIO pins seems to be benefical
* to stability
*/
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <3 0 1 &pcfg_pull_down_2ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 1 1 &pcfg_pull_up_2ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 2 1 &pcfg_pull_up_2ma>,
<3 3 1 &pcfg_pull_up_2ma>,
<3 4 1 &pcfg_pull_up_2ma>,
<3 5 1 &pcfg_pull_up_2ma>;
};
};
/*
* Same drill as above, electrical schemes also report this pull-up/down
* configurations.
*/
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 2 &pcfg_pull_up>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 22 2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 24 2 &pcfg_pull_up>,
<1 25 2 &pcfg_pull_up>,
<1 26 2 &pcfg_pull_up>,
<1 27 2 &pcfg_pull_up>,
<1 28 2 &pcfg_pull_up>,
<1 29 2 &pcfg_pull_up>,
<1 30 2 &pcfg_pull_up>,
<1 31 2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_down>;
};
emmc_rst: emmc-rst {
rockchip,pins = <1 RK_PC7 2 &pcfg_pull_up>;
};
};
gpio-items {
gpio_led_working: gpio-led-working {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ir {
ir_int: ir-int {
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin_pull_up: pwm2-pin-pull-up {
rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
};
&uart2 {
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_host: host-port {
phy-supply = <&vcc_host>;
};
u2phy0_otg: otg-port {
phy-supply = <&vcc_otg>;
};
};
&u2phy0_otg {
status = "okay";
};
&u2phy0_host {
status = "okay";
};
&u2phy1 {
status = "okay";
u2phy1_host: host-port {
phy-supply = <&vcc_host>;
};
u2phy1_otg: otg-port {
phy-supply = <&vcc_otg>;
};
};
&u2phy1_otg {
status = "okay";
};
&u2phy1_host {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_ehci {
status = "okay";
};
&usb_host2_ohci {
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&sdio {
mmc-pwrseq = <&sdio_pwrseq>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
no-sd;
status = "okay";
};
&sdmmc {
cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <500>;
cap-sd-highspeed;
keep-power-in-suspend;
no-sdio;
status = "okay";
};
&spdif {
status = "okay";
};
&tsadc {
rockchip,grf = <&grf>;
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <1>;
rockchip,hw-tshut-temp = <110000>;
/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
change the GPIO configuration of the associated PIN. On most boards that pin is not connected
so it does not do anything, but some other boards (X96-Mini) have that pin connected to
a reset pin of the soc or whatever, thus changing the configuration of the pin at boot
causes them to bootloop.
We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
unit of the SoC does the reboot*/
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-1;
/delete-property/ pinctrl-2;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP>;
assigned-clock-parents = <&cru SCLK_HDMI_PHY>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&wdt {
status = "okay";
};

1128
patch/kernel/archive/rockchip-6.7/dt/rk3288-xt-q8l-v10.dts
View File

File diff suppressed because it is too large Load Diff

9
patch/kernel/archive/rockchip-6.7/libreelec.series
View File

@@ -1,9 +0,0 @@
# Series from patches.libreelec/
patches.libreelec/linux-0002-rockchip-from-list.patch
patches.libreelec/linux-0011-v4l2-from-list.patch
patches.libreelec/linux-1000-drm-rockchip.patch
patches.libreelec/linux-1001-v4l2-rockchip.patch
patches.libreelec/linux-1002-for-libreelec.patch
patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch
patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch
patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch

55
patch/kernel/archive/rockchip-6.7/overlay/Makefile
View File

@@ -1,55 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-ds1307.dtbo \
rockchip-i2c1.dtbo \
rockchip-i2c4.dtbo \
rockchip-spi0.dtbo \
rockchip-spi2.dtbo \
rockchip-spidev0.dtbo \
rockchip-spidev2.dtbo \
rockchip-uart1.dtbo \
rockchip-uart2.dtbo \
rockchip-uart3.dtbo \
rockchip-uart4.dtbo \
rockchip-w1-gpio.dtbo \
rk322x-emmc.dtbo \
rk322x-emmc-pins.dtbo \
rk322x-emmc-ddr-ph45.dtbo \
rk322x-emmc-ddr-ph180.dtbo \
rk322x-emmc-hs200.dtbo \
rk322x-nand.dtbo \
rk322x-led-conf-default.dtbo \
rk322x-led-conf1.dtbo \
rk322x-led-conf2.dtbo \
rk322x-led-conf3.dtbo \
rk322x-led-conf4.dtbo \
rk322x-led-conf5.dtbo \
rk322x-led-conf6.dtbo \
rk322x-led-conf7.dtbo \
rk322x-led-conf8.dtbo \
rk322x-cpu-hs.dtbo \
rk322x-cpu-hs-lv.dtbo \
rk322x-wlan-alt-wiring.dtbo \
rk322x-cpu-stability.dtbo \
rk322x-ir-wakeup.dtbo \
rk322x-ddr3-330.dtbo \
rk322x-ddr3-528.dtbo \
rk322x-ddr3-660.dtbo \
rk322x-ddr3-800.dtbo \
rk322x-bt-8723cs.dtbo \
rk322x-usb-otg-peripheral.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rk322x-fixup.scr \
rockchip-fixup.scr
dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
README.rk322x-overlays \
README.rockchip-overlays
targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
always := $(dtbo-y) $(scr-y) $(dtbotxt-y)
clean-files := *.dtbo *.scr

98
patch/kernel/archive/rockchip-6.7/overlay/README.rk322x-overlays
View File

@@ -1,98 +0,0 @@
This document describes overlays provided in the kernel packages
For generic Armbian overlays documentation please see
https://docs.armbian.com/User-Guide_Allwinner_overlays/
### Platform:
rk322x (Rockchip)
### Provided overlays:
- rk322x-cpu-hs
- rk322x-cpu-stability
- rk322x-emmc*
- rk322x-nand
- rk322x-emmc-nand
- rk322x-led-conf*
- rk322x-wlan-alt-wiring
- rk322x-ddr3-*
- rk322x-bt-*
- rk322x-usb-otg-peripheral
- rk322x-ir-wakeup
### Overlay details:
### rk322x-cpu-hs
Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
### rk322x-cpu-stability
Increases the voltage of the lowest operating point to increase stability
on some boards which have power regulation issues. Also adds a settling
time to allow power regulator stabilize voltage.
### emmc*
rk322x-emmc activates onboard emmc device node and deactivates the
nand controller.
rk322x-emmc-pins sets the pin controller default pull up/down
configuration, not all boards are happy with this overlay, so your
mileage may vary and may want to not use it.
rk322x-emmc-ddr-ph45/ph180 sets the emmc ddr mode. First overlay
sets the default phase clock shifting to 45 degrees, the second
overlay to 180 degrees. They are alternative, choose the one that
makes your emmc perform better.
rk322x-emmc-hs200 enables the hs200 mode. It is preferable to
ddr mode because it is more stable, but old emmc parts don't
support it.
### nand
Activates onboard nand device node and deactivates the emmc controller.
Also sets up the pin controller default pull up/down configuration
### rk322x-led-conf*
Each device tree of this kind provides a different known wiring configuration
(ie: gpio and active low/high) of the onboard leds. Each board manufacturer
usually choose a different GPIO for the auxiliary led, but the main "working"
led is always wired to the same gpio (although it may be active high or low)
led-conf1 is commonly found in boards made by Chiptrip manufacturer
led-conf2 is found in other boards with R329Q and MXQ_RK3229 marking
led-conf3 is found in boards with R28-MXQ marking
led-conf4 is found on boards with T066 marking
led-conf5 is found on boards with IPB900 marking from AEMS PVT
led-conf6 is found on boards with MXQ_PRO_V72 and similar markings, possibly
with eMCP module.
led-conf7 is found on boards with R29_MXQ, R2B_MXQ and H20 markings
led-conf8 is specific for H20_221_V1.71 boards, but may work on other variants
### rk322x-alt-wiring
Some boards have different SDIO wiring setup for wifi chips. This overlay
enables the different pin controller wiring and power enable
### rk322x-ddr3-*
Enable DRAM memory controller and sets the speed to the given speed bin.
The DRAM memory controller reclocking only works with DDR3/LPDDR3, if
you enable one of these overlays on boards with DDR2 memory the system
will not boot anymore
### rk322x-bt-*
Overlays that enable bluetooth devices. Most common bluetooth chips are
realtek ones.
rk322x-bt-8723cs: enable this overlay for 8723cs and 8703bs wifi/bluetooth
### rk322x-usb-otg-peripheral
Set the OTG USB port to peripheral mode to be used as USB slave instead
of USB host
### rk322x-ir-wakeup
Enable the rockchip-ir-driver in place of the standard gpio-ir-receiver.
The rockchip-specific driver exploits the Trust OS and Virtual Poweroff mode
to allow power up via remote controller power button.

78
patch/kernel/archive/rockchip-6.7/overlay/README.rockchip-overlays
View File

@@ -1,78 +0,0 @@
This document describes overlays provided in the kernel packages
For generic Armbian overlays documentation please see
https://docs.armbian.com/User-Guide_Allwinner_overlays/
### Platform:
rockchip (Rockchip)
### Provided overlays:
- ds1307
- i2c1
- i2c4
- spi0
- spi2
- spidev0
- spidev2
- uart1
- uart2
- uart3
- uart4
- w1-gpio
### Overlay details:
### ds1307
Activates ds1307 rtc on i2c1
### i2c1
Activate i2c1
### i2c4
Activate i2c4
### spi0
Activate spi0
conflicts with uart4
### spi2
Activate spi2
### spidev0
Activate spidev on spi0
Depends on spi0
### spidev2
Activate spidev on spi2
depends on spi2
### uart1
Activate uart1
### uart2
Activate uart2
### uart3
Activate uart3
### uart4
Activate uart4
Conflicts with spi0
### w1-gpio
Activates 1-wire gpio master on GPIO0 17

19
patch/kernel/archive/rockchip-6.7/overlay/rk322x-bt-8723cs.dts
View File

@@ -1,19 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
&uart1 {
pinctrl-0 = <&uart11_xfer>, <&uart11_rts>, <&uart11_cts>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8723cs-bt";
enable-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
};
};

68
patch/kernel/archive/rockchip-6.7/overlay/rk322x-cpu-hs-lv.dts
View File

@@ -1,68 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&cpu0_opp_table>;
__overlay__ {
opp-600000000 {
opp-microvolt = <950000 950000 1275000>;
};
opp-816000000 {
opp-microvolt = <950000 950000 1275000>;
};
opp-1008000000 {
opp-microvolt = <1000000 1000000 1275000>;
};
opp-1200000000 {
opp-microvolt = <1100000 1100000 1275000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1150000 1150000 1275000>;
};
opp-1392000000 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <1225000 1225000 1275000>;
};
};
};
fragment@1 {
target = <&gpu_opp_table>;
__overlay__ {
opp-200000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-300000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-400000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-500000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
};
};
fragment@2 {
target = <&dmc_opp_table>;
__overlay__ {
opp-330000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-534000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-660000000 {
opp-microvolt = <1050000 1050000 1200000>;
};
opp-786000000 {
opp-microvolt = <1100000 1050000 1200000>;
};
};
};
};

28
patch/kernel/archive/rockchip-6.7/overlay/rk322x-cpu-hs.dts
View File

@@ -1,28 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&cpu0_opp_table>;
__overlay__ {
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1325000 1325000 1400000>;
};
opp-1392000000 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <1350000 1350000 1400000>;
};
/*
opp-1464000000 {
opp-hz = /bits/ 64 <1464000000>;
opp-microvolt = <1400000 1400000 1400000>;
};
*/
};
};
};

52
patch/kernel/archive/rockchip-6.7/overlay/rk322x-cpu-stability.dts
View File

@@ -1,52 +0,0 @@
/dts-v1/;
/plugin/;
/ {
/*
Device tree overlay that tries to overcome issues on power regulators (expecially ARM
power regulator) increasing lowest voltage and adding settling time to allow voltage
stabilization
*/
fragment@0 {
target = <&cpu0_opp_table>;
__overlay__ {
/*
Increase 600 and 800 Mhz operating points voltage to decrease the range
between minimum and maximum voltages
*/
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1100000>;
};
};
};
fragment@1 {
target = <&vdd_arm>;
__overlay__ {
regulator-ramp-delay = <300>; // 30 uV/us, so 0.3v transition settling time is 1ms
};
};
fragment@2 {
target = <&vdd_log>;
__overlay__ {
regulator-ramp-delay = <600>; // 600 uV/us, so 0,3v transition settling time is 0.5ms
};
};
};

28
patch/kernel/archive/rockchip-6.7/overlay/rk322x-ddr3-330.dts
View File

@@ -1,28 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&dmc>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&dmc_opp_table>;
__overlay__ {
opp-534000000 {
status = "disabled";
};
opp-660000000 {
status = "disabled";
};
opp-786000000 {
status = "disabled";
};
};
};
};

28
patch/kernel/archive/rockchip-6.7/overlay/rk322x-ddr3-528.dts
View File

@@ -1,28 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&dmc>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&dmc_opp_table>;
__overlay__ {
opp-534000000 {
status = "okay";
};
opp-660000000 {
status = "disabled";
};
opp-786000000 {
status = "disabled";
};
};
};
};

28
patch/kernel/archive/rockchip-6.7/overlay/rk322x-ddr3-660.dts
View File

@@ -1,28 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&dmc>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&dmc_opp_table>;
__overlay__ {
opp-534000000 {
status = "okay";
};
opp-660000000 {
status = "okay";
};
opp-786000000 {
status = "disabled";
};
};
};
};

28
patch/kernel/archive/rockchip-6.7/overlay/rk322x-ddr3-800.dts
View File

@@ -1,28 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&dmc>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&dmc_opp_table>;
__overlay__ {
opp-534000000 {
status = "okay";
};
opp-660000000 {
status = "okay";
};
opp-786000000 {
status = "okay";
};
};
};
};

14
patch/kernel/archive/rockchip-6.7/overlay/rk322x-emmc-ddr-ph180.dts
View File

@@ -1,14 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&emmc>;
__overlay__ {
mmc-ddr-1_8v;
rockchip,default-sample-phase = <180>;
};
};
};

14
patch/kernel/archive/rockchip-6.7/overlay/rk322x-emmc-ddr-ph45.dts
View File

@@ -1,14 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&emmc>;
__overlay__ {
mmc-ddr-1_8v;
rockchip,default-sample-phase = <45>;
};
};
};

13
patch/kernel/archive/rockchip-6.7/overlay/rk322x-emmc-hs200.dts
View File

@@ -1,13 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&emmc>;
__overlay__ {
mmc-hs200-1_8v;
};
};
};

34
patch/kernel/archive/rockchip-6.7/overlay/rk322x-emmc-pins.dts
View File

@@ -1,34 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&{/} {
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
};
sdmmc_pwrseq: sdmmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
};
};
&emmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
mmc-pwrseq = <&emmc_pwrseq>;
};
&sdmmc {
mmc-pwrseq = <&sdmmc_pwrseq>;
};
&nfc {
status = "disabled";
};

20
patch/kernel/archive/rockchip-6.7/overlay/rk322x-emmc.dts
View File

@@ -1,20 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&emmc>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&nfc>;
__overlay__ {
status = "disabled";
};
};
};

4
patch/kernel/archive/rockchip-6.7/overlay/rk322x-fixup.scr-cmd
View File

@@ -1,4 +0,0 @@
# overlays fixup script
# implements (or rather substitutes) overlay arguments functionality
# using u-boot scripting, environment variables and "fdt" command

16
patch/kernel/archive/rockchip-6.7/overlay/rk322x-ir-wakeup.dts
View File

@@ -1,16 +0,0 @@
/dts-v1/;
/plugin/;
/*
* Disable regular gpio-ir-receiver and enable
* rockchip-ir-receiver driver; also enables virtual
* poweroff on shutdown to allow restart with power key
* on remote controller
*/
&ir_receiver {
status = "disabled";
};
&rockchip_ir_receiver {
status = "okay";
};

22
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf-default.dts
View File

@@ -1,22 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
};
};

64
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf1.dts
View File

@@ -1,64 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
auxiliary {
gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_aux>;
};
};
};
fragment@1 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
gpio_led_aux: gpio-led-aux {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
fragment@2 {
target = <&gpio_keys>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
};

64
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf2.dts
View File

@@ -1,64 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
auxiliary {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_aux>;
};
};
};
fragment@1 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
gpio_led_aux: gpio-led-aux {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
fragment@2 {
target = <&gpio_keys>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
};

64
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf3.dts
View File

@@ -1,64 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
auxiliary {
gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_aux>;
};
};
};
fragment@1 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
gpio_led_aux: gpio-led-aux {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
fragment@2 {
target = <&gpio_keys>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
};

96
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf4.dts
View File

@@ -1,96 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
auxiliary {
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_aux>;
};
};
};
fragment@1 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
gpio_led_working: gpio-led-working {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_aux: gpio-led-aux {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
fragment@2 {
target = <&gpio_keys>;
__overlay__ {
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
fragment@3 {
target = <&sdio_pwrseq>;
__overlay__ {
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; /* GPIO2_D3 */
};
};
fragment@4 {
target = <&wifi_enable_h>;
__overlay__ {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fragment@5 {
target = <&sdio>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <0>;
};
};
};
};

97
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf5.dts
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@@ -1,97 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/*
* gpio configuration for AEMS IPB900 boards
*
* - enables working and auxiliary leds
* - fixes low strength on sdio pins for wifi
*/
/ {
fragment@0 {
target-path = "/gpio-leds";
__overlay__ {
working {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
auxiliary {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_aux>;
};
};
};
fragment@1 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
gpio_led_aux: gpio-led-aux {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
fragment@2 {
target = <&gpio_keys>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
fragment@3 {
target = <&sdio_bus4>;
__overlay__ {
rockchip,pins = <3 2 1 &pcfg_pull_none_8ma>,
<3 3 1 &pcfg_pull_none_8ma>,
<3 4 1 &pcfg_pull_none_8ma>,
<3 5 1 &pcfg_pull_none_8ma>;
};
};
fragment@4 {
target = <&sdio_clk>;
__overlay__ {
rockchip,pins = <3 0 1 &pcfg_pull_none_8ma>;
};
};
fragment@5 {
target = <&sdio_cmd>;
__overlay__ {
rockchip,pins = <3 1 1 &pcfg_pull_none_8ma>;
};
};
};

96
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf6.dts
View File

@@ -1,96 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/*
* gpio configuration for MXQ_PRO eMCP boards
*
* - fixes low strength on sdio pins for wifi
* - correct gpio pins for wifi
* - set emmc pins and default phase shift
*/
/ {
fragment@0 {
target-path = "/pinctrl/gpio-items";
__overlay__ {
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
fragment@1 {
target = <&gpio_keys>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
};
fragment@2 {
target = <&sdio_bus4>;
__overlay__ {
rockchip,pins = <3 2 1 &pcfg_pull_up>,
<3 3 1 &pcfg_pull_up>,
<3 4 1 &pcfg_pull_up>,
<3 5 1 &pcfg_pull_up>;
};
};
fragment@3 {
target = <&sdio_clk>;
__overlay__ {
rockchip,pins = <3 0 1 &pcfg_pull_none>;
};
};
fragment@4 {
target = <&sdio_cmd>;
__overlay__ {
rockchip,pins = <3 1 1 &pcfg_pull_up>;
};
};
fragment@5 {
target = <&sdio_pwrseq>;
__overlay__ {
post-power-on-delay-ms = <300>;
power-off-delay-us = <200000>;
reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
};
};
fragment@6 {
target = <&sdio>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <1>;
};
};
};
};

180
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf7.dts
View File

@@ -1,180 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/*
* gpio configuration for R29_MXQ boards
*
*/
&{/gpio-leds} {
working {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
pinctrl-0 = <&gpio_led_working>;
};
auxiliary {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_auxiliary>;
};
};
&{/pinctrl/gpio-items} {
gpio_led_working: gpio-led-working {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_auxiliary: gpio-led-auxiliary {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_ethlink: gpio-led-ethlink{
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_ethled: gpio-led-ethled{
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
&emmc {
rockchip,default-sample-phase = <112>;
bus-width = <8>;
clock-frequency = <125000000>;
max-frequency = <125000000>;
};
&vdd_arm {
compatible = "regulator-fixed";
regulator-name = "vdd_arm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
&vdd_log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
/*
* R29, R2B ad H20 boards require a GPIO to be turned low to enable HDMI output, we simulate it
* here as a regulator that must be always on.
* Also these boards don't have the necessary power regulators for CPU and Logic.
* R29 and R2B have a single power regulator fixed to 1.2v, hence the CPU can't go over 1.0 ghz
*/
&{/} {
vdd_hdmi_phy: vdd-hdmi-phy-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_phy_enable>;
regulator-name = "vdd-hdmi-phy";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
cpu_opp_table_r29: cpu-opp-table-r29 {
compatible = "operating-points-v2";
opp-shared;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1200000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1200000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000>;
};
};
};
&pinctrl {
hdmi-phy {
hdmi_phy_enable: hdmi-phy-enable {
rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "disabled";
};
&pwm2 {
status = "disabled";
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table_r29>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table_r29>;
};
&cpu2 {
operating-points-v2 = <&cpu_opp_table_r29>;
};
&cpu3 {
operating-points-v2 = <&cpu_opp_table_r29>;
};

109
patch/kernel/archive/rockchip-6.7/overlay/rk322x-led-conf8.dts
View File

@@ -1,109 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
/*
* gpio configuration for H20_221_V1.71 boards
*
*/
&{/gpio-leds} {
working {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
pinctrl-0 = <&gpio_led_working>;
};
auxiliary {
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
label = "auxiliary";
linux,default-trigger = "mmc2";
default-state = "off";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_auxiliary>;
};
};
&{/pinctrl/gpio-items} {
gpio_led_working: gpio-led-working {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_auxiliary: gpio-led-auxiliary {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_ethlink: gpio-led-ethlink{
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
gpio_led_ethled: gpio-led-ethled{
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
reset_key: reset-key {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&reset_key>;
reset {
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
debounce-interval = <200>;
wakeup-source;
};
};
&emmc {
rockchip,default-sample-phase = <112>;
bus-width = <8>;
clock-frequency = <125000000>;
max-frequency = <125000000>;
};
/*
* R29, R2B ad H20 boards require a GPIO to be turned low to enable HDMI output, we simulate it
* here as a regulator that must be always on.
* Also these boards don't have the necessary power regulators for CPU and Logic.
* R29 and R2B have a single power regulator fixed to 1.2v, hence the CPU can't go over 1.0 ghz
*/
&{/} {
vdd_hdmi_phy: vdd-hdmi-phy-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_phy_enable>;
regulator-name = "vdd-hdmi-phy";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
};
&pinctrl {
hdmi-phy {
hdmi_phy_enable: hdmi-phy-enable {
rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

22
patch/kernel/archive/rockchip-6.7/overlay/rk322x-nand.dts
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@@ -1,22 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&nfc>;
__overlay__ {
status = "okay";
pinctrl-0 = <&flash_cs0 &flash_cs1 &flash_cs2 &flash_cs3 &flash_rdy &flash_ale &flash_cle &flash_wrn &flash_bus8 &flash_dqs &flash_wp>;
pinctrl-names = "default";
};
};
fragment@1 {
target = <&emmc>;
__overlay__ {
status = "disabled";
};
};
};

11
patch/kernel/archive/rockchip-6.7/overlay/rk322x-usb-otg-peripheral.dts
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@@ -1,11 +0,0 @@
/dts-v1/;
/plugin/;
/*
* change OTG USB port mode to "peripheral"
*
*/
&usb_otg {
dr_mode = "peripheral";
};

67
patch/kernel/archive/rockchip-6.7/overlay/rk322x-wlan-alt-wiring.dts
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@@ -1,67 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target = <&pinctrl>;
__overlay__ {
pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
bias-disable;
drive-strength = <0x04>;
};
pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
bias-pull-up;
drive-strength = <0x04>;
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <1 0 1 &pcfg_pull_none_drv_4ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <0 3 2 &pcfg_pull_up_drv_4ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <1 1 1 &pcfg_pull_up_drv_4ma>,
<1 2 1 &pcfg_pull_up_drv_4ma>,
<1 4 1 &pcfg_pull_up_drv_4ma>,
<1 5 1 &pcfg_pull_up_drv_4ma>;
};
};
};
};
fragment@1 {
target = <&sdio_pwrseq>;
__overlay__ {
reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
};
};
fragment@2 {
target = <&wifi_enable_h>;
__overlay__ {
rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fragment@3 {
target = <&sdio>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
};
};
};

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23
patch/kernel/archive/rockchip-6.7/overlay/rockchip-ds1307.dts
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@@ -1,23 +0,0 @@
/* Definitions for ds1307
* From ASUS: https://github.com/TinkerBoard/debian_kernel/commits/develop/arch/arm/boot/dts/overlays/ds1307-overlay.dts
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
rtc: ds1307@68 {
compatible = "dallas,ds1307";
reg = <0x68>;
status = "okay";
};
};
};
};

4
patch/kernel/archive/rockchip-6.7/overlay/rockchip-fixup.scr-cmd
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@@ -1,4 +0,0 @@
# overlays fixup script
# implements (or rather substitutes) overlay arguments functionality
# using u-boot scripting, environment variables and "fdt" command

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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-i2c1.dts
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@@ -1,16 +0,0 @@
/* Definitions for i2c1
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&i2c1>;
__overlay__ {
status = "okay";
};
};
};

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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-i2c4.dts
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@@ -1,16 +0,0 @@
/* Definitions for i2c4
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&i2c4>;
__overlay__ {
status = "okay";
};
};
};

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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-spi0.dts
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@@ -1,16 +0,0 @@
/* Definitions for spi0
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&spi0>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-spi2.dtbo
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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-spi2.dts
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@@ -1,16 +0,0 @@
/* Definitions for spi2
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&spi2>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-spidev0.dtbo
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35
patch/kernel/archive/rockchip-6.7/overlay/rockchip-spidev0.dts
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@@ -1,35 +0,0 @@
/* Definition for SPI0 Spidev
* spi port for Tinker Board
*/
/dts-v1/;
/plugin/;
/{
compatible = "rockchip,rk3288";
fragment@0 {
target = <&spi0>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spi_tinker";
reg = <0>;
spi-max-frequency = <50000000>;
spi-cpha = <1>;
status = "okay";
};
spidev@1 {
compatible = "rockchip,spi_tinker";
reg = <1>;
spi-max-frequency = <50000000>;
spi-cpha = <1>;
status = "okay";
};
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-spidev2.dtbo
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35
patch/kernel/archive/rockchip-6.7/overlay/rockchip-spidev2.dts
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@@ -1,35 +0,0 @@
/* Definition for SPI2 Spidev
* spi port for Tinker Board
*/
/dts-v1/;
/plugin/;
/{
compatible = "rockchip,rk3288";
fragment@0 {
target = <&spi2>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spi_tinker";
reg = <0>;
spi-max-frequency = <50000000>;
spi-cpha = <1>;
status = "okay";
};
spidev@1 {
compatible = "rockchip,spi_tinker";
reg = <1>;
spi-max-frequency = <50000000>;
spi-cpha = <1>;
status = "okay";
};
};
};
};

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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart1.dts
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@@ -1,16 +0,0 @@
/* Definitions for uart1
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&uart1>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart2.dtbo
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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart2.dts
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@@ -1,16 +0,0 @@
/* Definitions for uart2
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&uart2>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart3.dtbo
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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart3.dts
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@@ -1,16 +0,0 @@
/* Definitions for uart3
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&uart3>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart4.dtbo
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16
patch/kernel/archive/rockchip-6.7/overlay/rockchip-uart4.dts
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@@ -1,16 +0,0 @@
/* Definitions for uart4
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target = <&uart4>;
__overlay__ {
status = "okay";
};
};
};

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patch/kernel/archive/rockchip-6.7/overlay/rockchip-w1-gpio.dtbo
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23
patch/kernel/archive/rockchip-6.7/overlay/rockchip-w1-gpio.dts
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@@ -1,23 +0,0 @@
/* 1-Wire GPIO
* From ASUS: https://github.com/TinkerBoard/debian_kernel/blob/develop/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts
*
*
*/
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3288";
fragment@0 {
target-path = "/";
__overlay__ {
w1: onewire@0 {
compatible = "w1-gpio";
pinctrl-names = "default";
gpios = <&gpio0 17 0>;
status = "okay";
};
};
};
};

27
patch/kernel/archive/rockchip-6.7/patches.armbian/bt-broadcom-serdev-workaround.patch
View File

@@ -1,27 +0,0 @@
From e5c9702bd2ffd09e48c118ab40c2764590af7929 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 1 May 2021 12:41:14 +0000
Subject: [PATCH] Workaround to make several broadcom bluetooth serdev devices
work even without proper MAC address
---
drivers/bluetooth/btbcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
index 1b9743b7f..b274f1cdd 100644
--- a/drivers/bluetooth/btbcm.c
+++ b/drivers/bluetooth/btbcm.c
@@ -129,7 +129,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev)
if (btbcm_set_bdaddr_from_efi(hdev) != 0) {
bt_dev_info(hdev, "BCM: Using default device address (%pMR)",
&bda->bdaddr);
- set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
+ //set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
}
}
--
2.25.1

38
patch/kernel/archive/rockchip-6.7/patches.armbian/clk-rk322x-composite-mmc-clk.patch
View File

@@ -1,38 +0,0 @@
From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 2 Apr 2023 10:53:07 +0000
Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks
---
drivers/clk/rockchip/clk-rk3228.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 996f8bfee..0f690dd84 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
- COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
+ COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
+ RK2928_CLKSEL_CON(12), 0, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
- DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
- RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
- COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
+ COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
+ RK2928_CLKSEL_CON(12), 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 14, GFLAGS),
- DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
- RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
/*
* Clock-Architecture Diagram 2
--
2.34.1

1536
patch/kernel/archive/rockchip-6.7/patches.armbian/clk-rockchip-max-frac-divider.patch
View File

File diff suppressed because it is too large Load Diff

914
patch/kernel/archive/rockchip-6.7/patches.armbian/driver-rk322x-audio-codec.patch
View File

@@ -1,914 +0,0 @@
From b4f40590a4f946d8ee704faf8579930e53ef4650 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 12 Sep 2021 10:15:56 +0000
Subject: [PATCH] rk322x: analog audio codec
---
.../bindings/sound/rockchip,rk3228-codec.txt | 22 +
arch/arm/boot/dts/rockchip/rk322x.dtsi | 9 +
drivers/clk/rockchip/clk-rk3228.c | 2 +-
include/dt-bindings/clock/rk3228-cru.h | 1 +
sound/soc/codecs/Kconfig | 5 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/rk3228_codec.c | 545 ++++++++++++++++++
sound/soc/codecs/rk3228_codec.h | 218 +++++++
8 files changed, 803 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
create mode 100644 sound/soc/codecs/rk3228_codec.c
create mode 100644 sound/soc/codecs/rk3228_codec.h
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
new file mode 100644
index 000000000..9191a8593
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
@@ -0,0 +1,22 @@
+* Rockchip Rk3228 internal codec
+
+Required properties:
+
+- compatible: "rockchip,rk3228-codec"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
+- clock-names: a list of clock names, one for each entry in clocks.
+- spk-en-gpio: speaker enable gpio.
+- spk-depop-time-ms: speaker depop time msec.
+
+Example for rk3228 internal codec:
+
+codec: codec@12010000 {
+ compatible = "rockchip,rk3228-codec";
+ reg = <0x12010000 0x1000>;
+ clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
+ clock-names = "mclk", "pclk", "sclk";
+ spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
index 75af99c76..c2670d498 100644
--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
@@ -145,6 +145,15 @@ i2s1: i2s1@100b0000 {
status = "disabled";
};
+ codec: codec@12010000 {
+ compatible = "rockchip,rk3228-codec";
+ reg = <0x12010000 0x1000>;
+ clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
+ clock-names = "mclk", "pclk", "sclk";
+ spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
i2s0: i2s0@100c0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index a24a35553..69f8c792f 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
- GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+ GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index de550ea56..30d44ce90 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -115,6 +115,7 @@
#define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365
#define PCLK_GMAC 367
+#define PCLK_ACODECPHY 368
/* hclk gates */
#define HCLK_I2S0_8CH 442
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 07747565c3b5..0a05315786bc 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -168,6 +168,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_PCM512x_I2C
imply SND_SOC_PCM512x_SPI
imply SND_SOC_PEB2466
+ imply SND_SOC_RK3228
imply SND_SOC_RK3328
imply SND_SOC_RK817
imply SND_SOC_RT274
@@ -1251,6 +1252,10 @@ config SND_SOC_PEB2466
To compile this driver as a module, choose M here: the module
will be called snd-soc-peb2466.
+config SND_SOC_RK3228
+ select REGMAP_MMIO
+ tristate "Rockchip RK3228 CODEC"
+
config SND_SOC_RK3328
tristate "Rockchip RK3328 audio CODEC"
select REGMAP_MMIO
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index f1ca18f7946c..73d3f6ffd7be 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -188,6 +188,7 @@ snd-soc-pcm512x-objs := pcm512x.o
snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
snd-soc-pcm512x-spi-objs := pcm512x-spi.o
snd-soc-peb2466-objs := peb2466.o
+snd-soc-rk3228-objs := rk3228_codec.o
snd-soc-rk3328-objs := rk3328_codec.o
snd-soc-rk817-objs := rk817_codec.o
snd-soc-rl6231-objs := rl6231.o
@@ -550,6 +551,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
obj-$(CONFIG_SND_SOC_PEB2466) += snd-soc-peb2466.o
+obj-$(CONFIG_SND_SOC_RK3228) += snd-soc-rk3228.o
obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o
obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o
obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
diff --git a/sound/soc/codecs/rk3228_codec.c b/sound/soc/codecs/rk3228_codec.c
new file mode 100644
index 000000000..b65307435
--- /dev/null
+++ b/sound/soc/codecs/rk3228_codec.c
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// rk3228_codec.c -- rk3228 ALSA Soc Audio driver
+//
+// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <sound/pcm_params.h>
+#include <sound/dmaengine_pcm.h>
+#include "rk3228_codec.h"
+
+/*
+ * volume setting
+ * 0: -39dB
+ * 26: 0dB
+ * 31: 6dB
+ * Step: 1.5dB
+ */
+#define OUT_VOLUME (0x18)
+#define INITIAL_FREQ (11289600)
+
+struct rk3228_codec_priv {
+ struct regmap *regmap;
+ struct clk *mclk;
+ struct clk *pclk;
+ struct clk *sclk;
+ struct gpio_desc *spk_en_gpio;
+ int spk_depop_time; /* msec */
+};
+
+static const struct reg_default rk3228_codec_reg_defaults[] = {
+ { CODEC_RESET, 0x03 },
+ { DAC_INIT_CTRL1, 0x00 },
+ { DAC_INIT_CTRL2, 0x50 },
+ { DAC_INIT_CTRL3, 0x0e },
+ { DAC_PRECHARGE_CTRL, 0x01 },
+ { DAC_PWR_CTRL, 0x00 },
+ { DAC_CLK_CTRL, 0x00 },
+ { HPMIX_CTRL, 0x00 },
+ { HPOUT_CTRL, 0x00 },
+ { HPOUTL_GAIN_CTRL, 0x00 },
+ { HPOUTR_GAIN_CTRL, 0x00 },
+ { HPOUT_POP_CTRL, 0x11 },
+};
+
+static int rk3228_codec_reset(struct snd_soc_component *component)
+{
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+
+ regmap_write(rk3228->regmap, CODEC_RESET, 0);
+ mdelay(10);
+ regmap_write(rk3228->regmap, CODEC_RESET, 0x03);
+
+ return 0;
+}
+
+static int rk3228_set_dai_fmt(struct snd_soc_dai *dai,
+ unsigned int fmt)
+{
+ struct snd_soc_component *component = dai->component;
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+ unsigned int val = 0;
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ val |= PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ val |= PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL1,
+ PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
+
+ val = 0;
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ val |= DAC_MODE_PCM;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ val |= DAC_MODE_I2S;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ val |= DAC_MODE_RJM;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ val |= DAC_MODE_LJM;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2,
+ DAC_MODE_MASK, val);
+ return 0;
+}
+
+static void rk3228_analog_output(struct rk3228_codec_priv *rk3228, int mute)
+{
+ if (rk3228->spk_en_gpio)
+ gpiod_set_value(rk3228->spk_en_gpio, mute);
+}
+
+static int rk3228_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
+{
+ struct snd_soc_component *component = dai->component;
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+ unsigned int val = 0;
+
+ if (direction != SNDRV_PCM_STREAM_PLAYBACK)
+ return 0;
+
+ if (mute)
+ val = HPOUTL_MUTE | HPOUTR_MUTE;
+ else
+ val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
+
+ regmap_update_bits(rk3228->regmap, HPOUT_CTRL,
+ HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
+ return 0;
+}
+
+static int rk3228_codec_power_on(struct snd_soc_component *component, int wait_ms)
+{
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
+ mdelay(10);
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_CURRENT_ALL_MASK,
+ DAC_CHARGE_CURRENT_ALL_ON);
+
+ mdelay(wait_ms);
+
+ return 0;
+}
+
+static int rk3228_codec_power_off(struct snd_soc_component *component, int wait_ms)
+{
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
+ mdelay(10);
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_CURRENT_ALL_MASK,
+ DAC_CHARGE_CURRENT_ALL_ON);
+
+ mdelay(wait_ms);
+
+ return 0;
+}
+
+static struct rk3228_reg_msk_val playback_open_list[] = {
+ { DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
+ { DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
+ DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
+ { DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON,
+ HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
+ { HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
+ HPOUTR_POP_WORK | HPOUTL_POP_WORK },
+ { HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
+ { HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
+ HPMIXL_INIT_EN | HPMIXR_INIT_EN },
+ { HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
+ { HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
+ HPOUTL_INIT_EN | HPOUTR_INIT_EN },
+ { DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
+ DACL_REFV_ON | DACR_REFV_ON },
+ { DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
+ DACL_CLK_ON | DACR_CLK_ON },
+ { DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
+ { DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
+ DACL_INIT_ON | DACR_INIT_ON },
+ { DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
+ DACL_SELECT | DACR_SELECT },
+ { HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
+ HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
+ { HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
+ HPOUTL_UNMUTE | HPOUTR_UNMUTE },
+};
+
+#define PLAYBACK_OPEN_LIST_LEN ARRAY_SIZE(playback_open_list)
+
+static int rk3228_codec_open_playback(struct snd_soc_component *component)
+{
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+ int i = 0;
+
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_CURRENT_ALL_MASK,
+ DAC_CHARGE_CURRENT_I);
+
+ for (i = 0; i < PLAYBACK_OPEN_LIST_LEN; i++) {
+ regmap_update_bits(rk3228->regmap,
+ playback_open_list[i].reg,
+ playback_open_list[i].msk,
+ playback_open_list[i].val);
+ mdelay(1);
+ }
+
+ msleep(rk3228->spk_depop_time);
+ rk3228_analog_output(rk3228, 1);
+
+ regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
+ HPOUTL_GAIN_MASK, OUT_VOLUME);
+ regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
+ HPOUTR_GAIN_MASK, OUT_VOLUME);
+ return 0;
+}
+
+static struct rk3228_reg_msk_val playback_close_list[] = {
+ { HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
+ HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
+ { DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
+ DACL_DESELECT | DACR_DESELECT },
+ { HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
+ HPOUTL_MUTE | HPOUTR_MUTE },
+ { HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
+ HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
+ { HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
+ { HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
+ { DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
+ { DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
+ DACL_CLK_OFF | DACR_CLK_OFF },
+ { DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
+ DACL_REFV_OFF | DACR_REFV_OFF },
+ { HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
+ HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
+ { DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
+ DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
+ { DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
+ { HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
+ HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
+ { DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
+ DACL_INIT_OFF | DACR_INIT_OFF },
+};
+
+#define PLAYBACK_CLOSE_LIST_LEN ARRAY_SIZE(playback_close_list)
+
+static int rk3228_codec_close_playback(struct snd_soc_component *component)
+{
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+ int i = 0;
+
+ rk3228_analog_output(rk3228, 0);
+
+ regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
+ HPOUTL_GAIN_MASK, 0);
+ regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
+ HPOUTR_GAIN_MASK, 0);
+
+ for (i = 0; i < PLAYBACK_CLOSE_LIST_LEN; i++) {
+ regmap_update_bits(rk3228->regmap,
+ playback_close_list[i].reg,
+ playback_close_list[i].msk,
+ playback_close_list[i].val);
+ mdelay(1);
+ }
+
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
+ DAC_CHARGE_CURRENT_ALL_MASK,
+ DAC_CHARGE_CURRENT_I);
+ return 0;
+}
+
+static int rk3228_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
+ unsigned int val = 0;
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ val |= DAC_VDL_16BITS;
+ break;
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ val |= DAC_VDL_20BITS;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ val |= DAC_VDL_24BITS;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ val |= DAC_VDL_32BITS;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
+ val = DAC_WL_32BITS | DAC_RST_DIS;
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL3,
+ DAC_WL_MASK | DAC_RST_MASK, val);
+
+ return 0;
+}
+
+static int rk3228_pcm_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+
+ return rk3228_codec_open_playback(component);
+}
+
+static void rk3228_pcm_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+
+ rk3228_codec_close_playback(component);
+}
+
+static struct snd_soc_dai_ops rk3228_dai_ops = {
+ .hw_params = rk3228_hw_params,
+ .set_fmt = rk3228_set_dai_fmt,
+ .mute_stream = rk3228_mute_stream,
+ .startup = rk3228_pcm_startup,
+ .shutdown = rk3228_pcm_shutdown,
+};
+
+static struct snd_soc_dai_driver rk3228_dai[] = {
+ {
+ .name = "rk3228-hifi",
+ .id = RK3228_HIFI,
+ .playback = {
+ .stream_name = "HIFI Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S20_3LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE),
+ },
+ /*.capture = {
+ .stream_name = "HIFI Capture",
+ .channels_min = 2,
+ .channels_max = 8,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S20_3LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE),
+ },*/
+ .ops = &rk3228_dai_ops,
+ },
+};
+
+static int rk3228_codec_probe(struct snd_soc_component *component)
+{
+ rk3228_codec_reset(component);
+ rk3228_codec_power_on(component, 0);
+
+ return 0;
+}
+
+static void rk3228_codec_remove(struct snd_soc_component *component)
+{
+ rk3228_codec_close_playback(component);
+ rk3228_codec_power_off(component, 0);
+}
+
+static struct snd_soc_component_driver soc_codec_dev_rk3228 = {
+ .probe = rk3228_codec_probe,
+ .remove = rk3228_codec_remove,
+};
+
+static bool rk3228_codec_write_read_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CODEC_RESET:
+ case DAC_INIT_CTRL1:
+ case DAC_INIT_CTRL2:
+ case DAC_INIT_CTRL3:
+ case DAC_PRECHARGE_CTRL:
+ case DAC_PWR_CTRL:
+ case DAC_CLK_CTRL:
+ case HPMIX_CTRL:
+ case DAC_SELECT:
+ case HPOUT_CTRL:
+ case HPOUTL_GAIN_CTRL:
+ case HPOUTR_GAIN_CTRL:
+ case HPOUT_POP_CTRL:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool rk3228_codec_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CODEC_RESET:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct regmap_config rk3228_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = HPOUT_POP_CTRL,
+ .writeable_reg = rk3228_codec_write_read_reg,
+ .readable_reg = rk3228_codec_write_read_reg,
+ .volatile_reg = rk3228_codec_volatile_reg,
+ .reg_defaults = rk3228_codec_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(rk3228_codec_reg_defaults),
+ .cache_type = REGCACHE_FLAT,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id rk3228codec_of_match[] = {
+ { .compatible = "rockchip,rk3228-codec", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rk3228codec_of_match);
+#endif
+
+static int rk3228_platform_probe(struct platform_device *pdev)
+{
+ struct device_node *rk3228_np = pdev->dev.of_node;
+ struct rk3228_codec_priv *rk3228;
+ struct resource *res;
+ void __iomem *base;
+ int ret = 0;
+
+ rk3228 = devm_kzalloc(&pdev->dev, sizeof(*rk3228), GFP_KERNEL);
+ if (!rk3228)
+ return -ENOMEM;
+
+ rk3228->mclk = devm_clk_get(&pdev->dev, "mclk");
+ if (PTR_ERR(rk3228->mclk) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ rk3228->pclk = devm_clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(rk3228->pclk))
+ return PTR_ERR(rk3228->pclk);
+
+ rk3228->sclk = devm_clk_get(&pdev->dev, "sclk");
+ if (IS_ERR(rk3228->sclk))
+ return PTR_ERR(rk3228->sclk);
+
+ rk3228->spk_en_gpio = devm_gpiod_get_optional(&pdev->dev,
+ "spk-en",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(rk3228->spk_en_gpio))
+ return PTR_ERR(rk3228->spk_en_gpio);
+
+ ret = of_property_read_u32(rk3228_np, "spk-depop-time-ms",
+ &rk3228->spk_depop_time);
+ if (ret < 0) {
+ dev_info(&pdev->dev, "spk_depop_time use default value.\n");
+ rk3228->spk_depop_time = 100;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ ret = clk_prepare_enable(rk3228->mclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(rk3228->pclk);
+ if (ret < 0)
+ goto err_pclk;
+
+ ret = clk_prepare_enable(rk3228->sclk);
+ if (ret)
+ goto err_sclk;
+
+ clk_set_rate(rk3228->sclk, INITIAL_FREQ);
+
+ rk3228->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &rk3228_codec_regmap_config);
+ if (IS_ERR(rk3228->regmap)) {
+ ret = PTR_ERR(rk3228->regmap);
+ goto err_clk;
+ }
+
+ platform_set_drvdata(pdev, rk3228);
+
+ ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3228,
+ rk3228_dai, ARRAY_SIZE(rk3228_dai));
+ if (!ret)
+ return 0;
+
+err_clk:
+ clk_disable_unprepare(rk3228->sclk);
+err_sclk:
+ clk_disable_unprepare(rk3228->pclk);
+err_pclk:
+ clk_disable_unprepare(rk3228->mclk);
+
+ return ret;
+}
+
+static int rk3228_platform_remove(struct platform_device *pdev)
+{
+ struct rk3228_codec_priv *rk3228 = platform_get_drvdata(pdev);
+
+ if (!IS_ERR(rk3228->mclk))
+ clk_disable_unprepare(rk3228->mclk);
+
+ if (!IS_ERR(rk3228->pclk))
+ clk_disable_unprepare(rk3228->pclk);
+
+ if (!IS_ERR(rk3228->sclk))
+ clk_disable_unprepare(rk3228->sclk);
+
+ return 0;
+}
+
+static struct platform_driver rk3228_codec_driver = {
+ .driver = {
+ .name = "rk3228-codec",
+ .of_match_table = of_match_ptr(rk3228codec_of_match),
+ },
+ .probe = rk3228_platform_probe,
+ .remove = rk3228_platform_remove,
+};
+module_platform_driver(rk3228_codec_driver);
+
+MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
+MODULE_DESCRIPTION("ASoC rk3228 codec driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rk3228_codec.h b/sound/soc/codecs/rk3228_codec.h
new file mode 100644
index 000000000..7283d0ba8
--- /dev/null
+++ b/sound/soc/codecs/rk3228_codec.h
@@ -0,0 +1,218 @@
+/*
+ * rk3228_codec.h -- rk3228 ALSA Soc Audio driver
+ *
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _RK3228_CODEC_H
+#define _RK3228_CODEC_H
+
+/* codec register */
+#define CODEC_RESET (0x00 << 2)
+#define DAC_INIT_CTRL1 (0x03 << 2)
+#define DAC_INIT_CTRL2 (0x04 << 2)
+#define DAC_INIT_CTRL3 (0x05 << 2)
+#define DAC_PRECHARGE_CTRL (0x22 << 2)
+#define DAC_PWR_CTRL (0x23 << 2)
+#define DAC_CLK_CTRL (0x24 << 2)
+#define HPMIX_CTRL (0x25 << 2)
+#define DAC_SELECT (0x26 << 2)
+#define HPOUT_CTRL (0x27 << 2)
+#define HPOUTL_GAIN_CTRL (0x28 << 2)
+#define HPOUTR_GAIN_CTRL (0x29 << 2)
+#define HPOUT_POP_CTRL (0x2a << 2)
+
+/* REG00: CODEC_RESET */
+#define PWR_RST_BYPASS_DIS BIT(6)
+#define PWR_RST_BYPASS_EN BIT(6)
+#define DIG_CORE_RST (0 << 1)
+#define DIG_CORE_WORK BIT(1)
+#define SYS_RST (0)
+#define SYS_WORK BIT(0)
+
+/* REG03: DAC_INIT_CTRL1 */
+#define PIN_DIRECTION_MASK BIT(5)
+#define PIN_DIRECTION_IN (0 << 5)
+#define PIN_DIRECTION_OUT BIT(5)
+#define DAC_I2S_MODE_MASK BIT(4)
+#define DAC_I2S_MODE_SLAVE (0 << 4)
+#define DAC_I2S_MODE_MASTER BIT(4)
+
+/* REG04: DAC_INIT_CTRL2 */
+#define DAC_I2S_LRP_MASK BIT(7)
+#define DAC_I2S_LRP_NORMAL (0 << 7)
+#define DAC_I2S_LRP_REVERSAL BIT(7)
+#define DAC_VDL_MASK (3 << 5)
+#define DAC_VDL_16BITS (0 << 5)
+#define DAC_VDL_20BITS BIT(5)
+#define DAC_VDL_24BITS (2 << 5)
+#define DAC_VDL_32BITS (3 << 5)
+#define DAC_MODE_MASK (3 << 3)
+#define DAC_MODE_RJM (0 << 3)
+#define DAC_MODE_LJM BIT(3)
+#define DAC_MODE_I2S (2 << 3)
+#define DAC_MODE_PCM (3 << 3)
+#define DAC_LR_SWAP_MASK BIT(2)
+#define DAC_LR_SWAP_DIS (0 << 2)
+#define DAC_LR_SWAP_EN BIT(2)
+
+/* REG05: DAC_INIT_CTRL3 */
+#define DAC_WL_MASK (3 << 2)
+#define DAC_WL_16BITS (0 << 2)
+#define DAC_WL_20BITS BIT(2)
+#define DAC_WL_24BITS (2 << 2)
+#define DAC_WL_32BITS (3 << 2)
+#define DAC_RST_MASK BIT(1)
+#define DAC_RST_EN (0 << 1)
+#define DAC_RST_DIS BIT(1)
+#define DAC_BCP_MASK BIT(0)
+#define DAC_BCP_NORMAL (0 << 0)
+#define DAC_BCP_REVERSAL BIT(0)
+
+/* REG22: DAC_PRECHARGE_CTRL */
+#define DAC_CHARGE_PRECHARGE BIT(7)
+#define DAC_CHARGE_DISCHARGE (0 << 7)
+#define DAC_CHARGE_XCHARGE_MASK BIT(7)
+#define DAC_CHARGE_CURRENT_64I BIT(6)
+#define DAC_CHARGE_CURRENT_64I_MASK BIT(6)
+#define DAC_CHARGE_CURRENT_32I BIT(5)
+#define DAC_CHARGE_CURRENT_32I_MASK BIT(5)
+#define DAC_CHARGE_CURRENT_16I BIT(4)
+#define DAC_CHARGE_CURRENT_16I_MASK BIT(4)
+#define DAC_CHARGE_CURRENT_08I BIT(3)
+#define DAC_CHARGE_CURRENT_08I_MASK BIT(3)
+#define DAC_CHARGE_CURRENT_04I BIT(2)
+#define DAC_CHARGE_CURRENT_04I_MASK BIT(2)
+#define DAC_CHARGE_CURRENT_02I BIT(1)
+#define DAC_CHARGE_CURRENT_02I_MASK BIT(1)
+#define DAC_CHARGE_CURRENT_I BIT(0)
+#define DAC_CHARGE_CURRENT_I_MASK BIT(0)
+#define DAC_CHARGE_CURRENT_ALL_MASK (0x7f)
+#define DAC_CHARGE_CURRENT_ALL_OFF (0x0)
+#define DAC_CHARGE_CURRENT_ALL_ON (0x7f)
+
+/* REG23: DAC_PWR_CTRL */
+#define DAC_PWR_OFF (0 << 6)
+#define DAC_PWR_ON BIT(6)
+#define DAC_PWR_MASK BIT(6)
+#define DACL_PATH_REFV_OFF (0 << 5)
+#define DACL_PATH_REFV_ON BIT(5)
+#define DACL_PATH_REFV_MASK BIT(5)
+#define HPOUTL_ZERO_CROSSING_OFF (0 << 4)
+#define HPOUTL_ZERO_CROSSING_ON BIT(4)
+#define DACR_PATH_REFV_OFF (0 << 1)
+#define DACR_PATH_REFV_ON BIT(1)
+#define DACR_PATH_REFV_MASK BIT(1)
+#define HPOUTR_ZERO_CROSSING_OFF (0 << 0)
+#define HPOUTR_ZERO_CROSSING_ON BIT(0)
+
+/* REG24: DAC_CLK_CTRL */
+#define DACL_REFV_OFF (0 << 7)
+#define DACL_REFV_ON BIT(7)
+#define DACL_REFV_MASK BIT(7)
+#define DACL_CLK_OFF (0 << 6)
+#define DACL_CLK_ON BIT(6)
+#define DACL_CLK_MASK BIT(6)
+#define DACL_OFF (0 << 5)
+#define DACL_ON BIT(5)
+#define DACL_MASK BIT(5)
+#define DACL_INIT_OFF (0 << 4)
+#define DACL_INIT_ON BIT(4)
+#define DACL_INIT_MASK BIT(4)
+#define DACR_REFV_OFF (0 << 3)
+#define DACR_REFV_ON BIT(3)
+#define DACR_REFV_MASK BIT(3)
+#define DACR_CLK_OFF (0 << 2)
+#define DACR_CLK_ON BIT(2)
+#define DACR_CLK_MASK BIT(2)
+#define DACR_OFF (0 << 1)
+#define DACR_ON BIT(1)
+#define DACR_MASK BIT(1)
+#define DACR_INIT_OFF (0 << 0)
+#define DACR_INIT_ON BIT(0)
+#define DACR_INIT_MASK BIT(0)
+
+/* REG25: HPMIX_CTRL*/
+#define HPMIXL_DIS (0 << 6)
+#define HPMIXL_EN BIT(6)
+#define HPMIXL_MASK BIT(6)
+#define HPMIXL_INIT_DIS (0 << 5)
+#define HPMIXL_INIT_EN BIT(5)
+#define HPMIXL_INIT_MASK BIT(5)
+#define HPMIXL_INIT2_DIS (0 << 4)
+#define HPMIXL_INIT2_EN BIT(4)
+#define HPMIXL_INIT2_MASK BIT(4)
+#define HPMIXR_DIS (0 << 2)
+#define HPMIXR_EN BIT(2)
+#define HPMIXR_MASK BIT(2)
+#define HPMIXR_INIT_DIS (0 << 1)
+#define HPMIXR_INIT_EN BIT(1)
+#define HPMIXR_INIT_MASK BIT(1)
+#define HPMIXR_INIT2_DIS (0 << 0)
+#define HPMIXR_INIT2_EN BIT(0)
+#define HPMIXR_INIT2_MASK BIT(0)
+
+/* REG26: DAC_SELECT */
+#define DACL_SELECT BIT(4)
+#define DACL_SELECT_MASK BIT(4)
+#define DACL_DESELECT (0 << 4)
+#define DACR_SELECT BIT(0)
+#define DACR_SELECT_MASK BIT(0)
+#define DACR_DESELECT (0 << 0)
+
+/* REG27: HPOUT_CTRL */
+#define HPOUTL_DIS (0 << 7)
+#define HPOUTL_EN BIT(7)
+#define HPOUTL_MASK BIT(7)
+#define HPOUTL_INIT_DIS (0 << 6)
+#define HPOUTL_INIT_EN BIT(6)
+#define HPOUTL_INIT_MASK BIT(6)
+#define HPOUTL_MUTE (0 << 5)
+#define HPOUTL_UNMUTE BIT(5)
+#define HPOUTL_MUTE_MASK BIT(5)
+#define HPOUTR_DIS (0 << 4)
+#define HPOUTR_EN BIT(4)
+#define HPOUTR_MASK BIT(4)
+#define HPOUTR_INIT_DIS (0 << 3)
+#define HPOUTR_INIT_EN BIT(3)
+#define HPOUTR_INIT_MASK BIT(3)
+#define HPOUTR_MUTE (0 << 2)
+#define HPOUTR_UNMUTE BIT(2)
+#define HPOUTR_MUTE_MASK BIT(2)
+
+/* REG28: HPOUTL_GAIN_CTRL */
+#define HPOUTL_GAIN_MASK (0X1f << 0)
+
+/* REG29: HPOUTR_GAIN_CTRL */
+#define HPOUTR_GAIN_MASK (0X1f << 0)
+
+/* REG2a: HPOUT_POP_CTRL */
+#define HPOUTR_POP_XCHARGE BIT(4)
+#define HPOUTR_POP_WORK (2 << 4)
+#define HPOUTR_POP_MASK (3 << 4)
+#define HPOUTL_POP_XCHARGE BIT(0)
+#define HPOUTL_POP_WORK (2 << 0)
+#define HPOUTL_POP_MASK (3 << 0)
+
+#define RK3228_HIFI (0)
+
+struct rk3228_reg_msk_val {
+ unsigned int reg;
+ unsigned int msk;
+ unsigned int val;
+};
+
+#endif
--
2.25.1

395
patch/kernel/archive/rockchip-6.7/patches.armbian/driver-rk3288-gpiomem.patch
View File

@@ -1,395 +0,0 @@
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
index e5b7ef1a5..f88c913ff 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
@@ -544,3 +544,6 @@
&wdt {
status = "okay";
};
+&gpiomem {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index f3ca55496..14bbcb192 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1418,6 +1418,12 @@
interrupts = <GIC_PPI 9 0xf04>;
};
+ gpiomem: rk3288-gpiomem@ff750000 {
+ compatible = "rockchip,rk3288-gpiomem";
+ reg = <0x0 0xff750000 0x0 0x1000>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 3143db5..9c18b74 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -5,6 +5,7 @@
menu "Character devices"
source "drivers/tty/Kconfig"
+source "drivers/char/rockchip/Kconfig"
config DEVMEM
bool "/dev/mem virtual device support"
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 264eb398f..9fd5f240b 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -43,6 +43,8 @@ obj-$(CONFIG_TCG_TPM) += tpm/
obj-$(CONFIG_PS3_FLASH) += ps3flash.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+
obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/
obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o
obj-$(CONFIG_ADI) += adi.o
diff --git a/drivers/char/rockchip/Kconfig b/drivers/char/rockchip/Kconfig
new file mode 100644
index 0000000..6e97486
--- /dev/null
+++ b/drivers/char/rockchip/Kconfig
@@ -0,0 +1,16 @@
+#
+# Broadcom char driver config
+#
+
+menuconfig RK_CHAR_DRIVERS
+ bool "Rockchip Char Drivers"
+ help
+ Rockchip's char drivers
+
+config RK3288_DEVGPIOMEM
+ tristate "/dev/gpiomem rootless GPIO access via mmap() on the RK3288"
+ default y
+ help
+ Provides users with root-free access to the GPIO registers
+ on the 3288. Calling mmap(/dev/gpiomem) will map the GPIO
+ register page to the user's pointer.
\ No newline at end of file
diff --git a/drivers/char/rockchip/Makefile b/drivers/char/rockchip/Makefile
new file mode 100644
index 0000000..2287ec2
--- /dev/null
+++ b/drivers/char/rockchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_RK3288_DEVGPIOMEM)+= rk3288-gpiomem.o
\ No newline at end of file
diff --git a/drivers/char/rockchip/rk3288-gpiomem.c b/drivers/char/rockchip/rk3288-gpiomem.c
new file mode 100644
index 0000000..984471c
--- /dev/null
+++ b/drivers/char/rockchip/rk3288-gpiomem.c
@@ -0,0 +1,303 @@
+/**
+ * GPIO memory device driver
+ *
+ * Creates a chardev /dev/gpiomem which will provide user access to
+ * the rk3288's GPIO registers when it is mmap()'d.
+ * No longer need root for user GPIO access, but without relaxing permissions
+ * on /dev/mem.
+ *
+ * Written by Luke Wren <luke@raspberrypi.org>
+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2, as published by the Free
+ * Software Foundation.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/cdev.h>
+#include <linux/pagemap.h>
+#include <linux/io.h>
+
+#define DEVICE_NAME "rk3288-gpiomem"
+#define DRIVER_NAME "gpiomem-rk3288"
+#define DEVICE_MINOR 0
+
+struct rk3288_gpiomem_instance {
+ unsigned long gpio_regs_phys;
+ struct device *dev;
+};
+
+static struct cdev rk3288_gpiomem_cdev;
+static dev_t rk3288_gpiomem_devid;
+static struct class *rk3288_gpiomem_class;
+static struct device *rk3288_gpiomem_dev;
+static struct rk3288_gpiomem_instance *inst;
+
+
+/****************************************************************************
+*
+* GPIO mem chardev file ops
+*
+***************************************************************************/
+
+static int rk3288_gpiomem_open(struct inode *inode, struct file *file)
+{
+ int dev = iminor(inode);
+ int ret = 0;
+
+ if (dev != DEVICE_MINOR) {
+ dev_err(inst->dev, "Unknown minor device: %d", dev);
+ ret = -ENXIO;
+ }
+ return ret;
+}
+
+static int rk3288_gpiomem_release(struct inode *inode, struct file *file)
+{
+ int dev = iminor(inode);
+ int ret = 0;
+
+ if (dev != DEVICE_MINOR) {
+ dev_err(inst->dev, "Unknown minor device %d", dev);
+ ret = -ENXIO;
+ }
+ return ret;
+}
+
+static const struct vm_operations_struct rk3288_gpiomem_vm_ops = {
+#ifdef CONFIG_HAVE_IOREMAP_PROT
+ .access = generic_access_phys
+#endif
+};
+static int address_is_allowed(unsigned long pfn, unsigned long size)
+{
+ unsigned long address = pfn << PAGE_SHIFT;
+
+ dev_info(inst->dev, "address_is_allowed.pfn: 0x%08lx", address);
+
+ switch(address) {
+
+ case 0xff750000:
+ case 0xff760000:
+ case 0xff780000:
+ case 0xff790000:
+ case 0xff7a0000:
+ case 0xff7b0000:
+ case 0xff7c0000:
+ case 0xff7d0000:
+ case 0xff7e0000:
+ case 0xff7f0000:
+ case 0xff7f2000:
+ case 0xff770000:
+ case 0xff730000:
+ case 0xff680000:
+ dev_info(inst->dev, "address_is_allowed.return 1");
+ return 1;
+ break;
+ default :
+ dev_info(inst->dev, "address_is_allowed.return 0");
+ return 0;
+ }
+}
+
+static int rk3288_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)
+{
+
+ size_t size;
+
+ size = vma->vm_end - vma->vm_start;
+
+
+ if (!address_is_allowed(vma->vm_pgoff, size))
+ return -EPERM;
+
+ vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
+ size,
+ vma->vm_page_prot);
+
+ vma->vm_ops = &rk3288_gpiomem_vm_ops;
+
+ /* Remap-pfn-range will mark the range VM_IO */
+ if (remap_pfn_range(vma,
+ vma->vm_start,
+ vma->vm_pgoff,
+ size,
+ vma->vm_page_prot)) {
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static const struct file_operations
+rk3288_gpiomem_fops = {
+ .owner = THIS_MODULE,
+ .open = rk3288_gpiomem_open,
+ .release = rk3288_gpiomem_release,
+ .mmap = rk3288_gpiomem_mmap,
+};
+
+static int rk3288_gpiomem_dev_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+ add_uevent_var(env, "DEVMODE=%#o", 0666);
+ return 0;
+}
+
+ /****************************************************************************
+*
+* Probe and remove functions
+*
+***************************************************************************/
+
+
+static int rk3288_gpiomem_probe(struct platform_device *pdev)
+{
+ int err;
+ void *ptr_err;
+ struct device *dev = &pdev->dev;
+ struct resource *ioresource;
+
+ /* Allocate buffers and instance data */
+
+ inst = kzalloc(sizeof(struct rk3288_gpiomem_instance), GFP_KERNEL);
+
+ if (!inst) {
+ err = -ENOMEM;
+ goto failed_inst_alloc;
+ }
+
+ inst->dev = dev;
+
+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (ioresource) {
+ inst->gpio_regs_phys = ioresource->start;
+ } else {
+ dev_err(inst->dev, "failed to get IO resource");
+ err = -ENOENT;
+ goto failed_get_resource;
+ }
+
+ /* Create character device entries */
+
+ err = alloc_chrdev_region(&rk3288_gpiomem_devid,
+ DEVICE_MINOR, 1, DEVICE_NAME);
+ if (err != 0) {
+ dev_err(inst->dev, "unable to allocate device number");
+ goto failed_alloc_chrdev;
+ }
+ cdev_init(&rk3288_gpiomem_cdev, &rk3288_gpiomem_fops);
+ rk3288_gpiomem_cdev.owner = THIS_MODULE;
+ err = cdev_add(&rk3288_gpiomem_cdev, rk3288_gpiomem_devid, 1);
+ if (err != 0) {
+ dev_err(inst->dev, "unable to register device");
+ goto failed_cdev_add;
+ }
+
+ /* Create sysfs entries */
+
+ rk3288_gpiomem_class = class_create(DEVICE_NAME);
+ ptr_err = rk3288_gpiomem_class;
+ if (IS_ERR(ptr_err))
+ goto failed_class_create;
+ rk3288_gpiomem_class->dev_uevent = rk3288_gpiomem_dev_uevent;
+ rk3288_gpiomem_dev = device_create(rk3288_gpiomem_class, NULL,
+ rk3288_gpiomem_devid, NULL,
+ "gpiomem");
+ ptr_err = rk3288_gpiomem_dev;
+ if (IS_ERR(ptr_err))
+ goto failed_device_create;
+
+ dev_info(inst->dev, "Initialised: Registers at 0x%08lx",
+ inst->gpio_regs_phys);
+
+ return 0;
+
+failed_device_create:
+ class_destroy(rk3288_gpiomem_class);
+failed_class_create:
+ cdev_del(&rk3288_gpiomem_cdev);
+ err = PTR_ERR(ptr_err);
+failed_cdev_add:
+ unregister_chrdev_region(rk3288_gpiomem_devid, 1);
+failed_alloc_chrdev:
+failed_get_resource:
+ kfree(inst);
+failed_inst_alloc:
+ dev_err(inst->dev, "could not load rk3288_gpiomem");
+ return err;
+}
+
+static int rk3288_gpiomem_remove(struct platform_device *pdev)
+{
+ struct device *dev = inst->dev;
+
+ kfree(inst);
+ device_destroy(rk3288_gpiomem_class, rk3288_gpiomem_devid);
+ class_destroy(rk3288_gpiomem_class);
+ cdev_del(&rk3288_gpiomem_cdev);
+ unregister_chrdev_region(rk3288_gpiomem_devid, 1);
+
+ dev_info(dev, "GPIO mem driver removed - OK");
+ return 0;
+}
+
+ /****************************************************************************
+*
+* Register the driver with device tree
+*
+***************************************************************************/
+
+static const struct of_device_id rk3288_gpiomem_of_match[] = {
+ {.compatible = "rockchip,rk3288-gpiomem",},
+ { /* sentinel */ },
+};
+
+MODULE_DEVICE_TABLE(of, rk3288_gpiomem_of_match);
+
+static struct platform_driver rk3288_gpiomem_driver = {
+ .probe = rk3288_gpiomem_probe,
+ .remove = rk3288_gpiomem_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = rk3288_gpiomem_of_match,
+ },
+};
+
+module_platform_driver(rk3288_gpiomem_driver);
+
+MODULE_ALIAS("platform:gpiomem-rk3288");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace");
+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
\ No newline at end of file

19
patch/kernel/archive/rockchip-6.7/patches.armbian/driver-tinkerboard-alc4040-codec.patch
View File

@@ -1,19 +0,0 @@
diff --git a/sound/usb/card.c b/sound/usb/card.c
index 2bfe4e80a..cea93aaf5 100644
--- a/sound/usb/card.c
+++ b/sound/usb/card.c
@@ -382,6 +382,14 @@ static void usb_audio_make_shortname(struct usb_device *dev,
}
strim(card->shortname);
+
+ /* Tinker Board ALC4040 CODEC */
+
+ if(USB_ID_VENDOR(chip->usb_id) == 0x0bda &&
+ USB_ID_PRODUCT(chip->usb_id) == 0x481a) {
+ strlcat(card->shortname, " OnBoard", sizeof(card->shortname));
+ }
+
}
static void usb_audio_make_longname(struct usb_device *dev,

66
patch/kernel/archive/rockchip-6.7/patches.armbian/drm-rk322x-plane-overlay.patch
View File

@@ -1,66 +0,0 @@
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 73d24c6bbf05..d4ac6e161ef2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
};
+static const struct vop_win_phy rk3228_win0_data = {
+ .scl = &rk3288_win_full_scl,
+ .data_formats = formats_win_full,
+ .nformats = ARRAY_SIZE(formats_win_full),
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
+};
+
+static const struct vop_win_phy rk3228_win1_data = {
+ .scl = &rk3288_win_full_scl,
+ .data_formats = formats_win_lite,
+ .nformats = ARRAY_SIZE(formats_win_lite),
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
+};
+
/*
* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
* special support to get alpha blending working. For now, just use overlay
@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
};
static const struct vop_win_data rk3228_vop_win_data[] = {
- { .base = 0x00, .phy = &rk3288_win01_data,
+ { .base = 0x00, .phy = &rk3228_win0_data,
.type = DRM_PLANE_TYPE_PRIMARY },
- { .base = 0x40, .phy = &rk3288_win01_data,
- .type = DRM_PLANE_TYPE_CURSOR },
+ { .base = 0x40, .phy = &rk3228_win1_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
};
static const struct vop_data rk3228_vop = {
--
2.17.1

44
patch/kernel/archive/rockchip-6.7/patches.armbian/drm-rk322x-yuv-10bit-modes.patch
View File

@@ -1,44 +0,0 @@
From 2d42546642fa4299d88fa4ae414fa1ab205dad70 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 11 Sep 2021 17:38:48 +0000
Subject: [PATCH] rk322x: enable YUV modes for win1, 10-bit for win0/win1
---
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 70930b410..3fd00b323 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -719,10 +719,11 @@ static const struct vop_common rk3288_common = {
static const struct vop_win_phy rk3228_win0_data = {
.scl = &rk3288_win_full_scl,
- .data_formats = formats_win_full,
- .nformats = ARRAY_SIZE(formats_win_full),
+ .data_formats = formats_win_full_10,
+ .nformats = ARRAY_SIZE(formats_win_full_10),
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
@@ -738,10 +739,11 @@ static const struct vop_win_phy rk3228_win0_data = {
static const struct vop_win_phy rk3228_win1_data = {
.scl = &rk3288_win_full_scl,
- .data_formats = formats_win_lite,
- .nformats = ARRAY_SIZE(formats_win_lite),
+ .data_formats = formats_win_full_10,
+ .nformats = ARRAY_SIZE(formats_win_full_10),
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
--
2.25.1

358
patch/kernel/archive/rockchip-6.7/patches.armbian/drm-rockchip-hardware-cursor.patch
View File

@@ -1,358 +0,0 @@
From ff9a0ab9d920d4a855b4be9912a57ac65e8906e2 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Fri, 10 Sep 2021 14:10:18 +0000
Subject: [PATCH] drm rockchip hardware cursor
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 218 +++++++++++++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 +-
3 files changed, 238 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 83a926c0a..b0832320e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1160,6 +1160,207 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane,
}
}
+static void vop_cursor_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_state->crtc;
+ struct vop_win *vop_win = to_vop_win(plane);
+ const struct vop_win_data *win = vop_win->data;
+ struct vop *vop = to_vop(new_state->crtc);
+ struct drm_framebuffer *fb = new_state->fb;
+ unsigned int actual_w, actual_h;
+ unsigned int dsp_stx, dsp_sty;
+ uint32_t dsp_st;
+ struct drm_rect *src = &new_state->src;
+ struct drm_rect *dest = &new_state->dst;
+ struct drm_gem_object *obj;
+ struct rockchip_gem_object *rk_obj;
+ dma_addr_t dma_addr;
+ uint32_t val;
+ bool rb_swap;
+ int win_index = VOP_WIN_TO_INDEX(vop_win);
+ int format;
+
+ /*
+ * can't update plane when vop is disabled.
+ */
+ if (WARN_ON(!crtc))
+ return;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ if (!new_state->visible) {
+ vop_plane_atomic_disable(plane, state);
+ return;
+ }
+
+ obj = fb->obj[0];
+ rk_obj = to_rockchip_obj(obj);
+
+// actual_w = drm_rect_width(src) >> 16;
+// actual_h = drm_rect_height(src) >> 16;
+
+ dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+ dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
+ dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
+
+ dma_addr = rk_obj->dma_addr;
+
+ /*
+ * For y-mirroring we need to move address
+ * to the beginning of the last line.
+ */
+// if (new_state->rotation & DRM_MODE_REFLECT_Y)
+// dma_addr += (actual_h - 1) * fb->pitches[0];
+
+ spin_lock(&vop->reg_lock);
+
+ if (!(vop->win_enabled & BIT(win_index))) {
+
+ format = vop_convert_format(fb->format->format);
+
+ VOP_WIN_SET(vop, win, format, format);
+
+// if (win->phy->scl)
+// scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+// drm_rect_width(dest), drm_rect_height(dest),
+// fb->format);
+
+ rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
+ VOP_WIN_SET(vop, win, rb_swap, rb_swap);
+
+ /*
+ * Blending win0 with the background color doesn't seem to work
+ * correctly. We only get the background color, no matter the contents
+ * of the win0 framebuffer. However, blending pre-multiplied color
+ * with the default opaque black default background color is a no-op,
+ * so we can just disable blending to get the correct result.
+ */
+ if (fb->format->has_alpha && win_index > 0) {
+ VOP_WIN_SET(vop, win, dst_alpha_ctl,
+ DST_FACTOR_M0(ALPHA_SRC_INVERSE));
+ val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
+ SRC_ALPHA_M0(ALPHA_STRAIGHT) |
+ SRC_BLEND_M0(ALPHA_PER_PIX) |
+ SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
+ SRC_FACTOR_M0(ALPHA_ONE);
+ VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+
+ VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
+ VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
+ VOP_WIN_SET(vop, win, alpha_en, 1);
+ } else {
+ VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
+ VOP_WIN_SET(vop, win, alpha_en, 0);
+ }
+
+ // 32x32 = 0, 64x64 = 1, 96x96 = 2, 128x128 = 3
+ VOP_WIN_SET(vop, win, hwc_size, (new_state->crtc_w >> 5) - 1);
+
+ VOP_WIN_SET(vop, win, enable, 1);
+ vop->win_enabled |= BIT(win_index);
+
+ }
+
+ VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
+ VOP_WIN_SET(vop, win, dsp_st, dsp_st);
+
+ spin_unlock(&vop->reg_lock);
+
+}
+
+static void vop_cursor_atomic_async_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct vop *vop = to_vop(plane->state->crtc);
+ struct drm_framebuffer *old_fb = plane->state->fb;
+
+ plane->state->crtc_x = new_state->crtc_x;
+ plane->state->crtc_y = new_state->crtc_y;
+ plane->state->crtc_h = new_state->crtc_h;
+ plane->state->crtc_w = new_state->crtc_w;
+ plane->state->src_x = new_state->src_x;
+ plane->state->src_y = new_state->src_y;
+ plane->state->src_h = new_state->src_h;
+ plane->state->src_w = new_state->src_w;
+ swap(plane->state->fb, new_state->fb);
+
+ if (vop->is_enabled) {
+ vop_cursor_atomic_update(plane, state);
+ spin_lock(&vop->reg_lock);
+ vop_cfg_done(vop);
+ spin_unlock(&vop->reg_lock);
+
+ /*
+ * A scanout can still be occurring, so we can't drop the
+ * reference to the old framebuffer. To solve this we get a
+ * reference to old_fb and set a worker to release it later.
+ * FIXME: if we perform 500 async_update calls before the
+ * vblank, then we can have 500 different framebuffers waiting
+ * to be released.
+ */
+ if (old_fb && plane->state->fb != old_fb) {
+ drm_framebuffer_get(old_fb);
+ WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
+ drm_flip_work_queue(&vop->fb_unref_work, old_fb);
+ set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
+ }
+ }
+
+}
+
+static int vop_cursor_atomic_check(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_plane_state->crtc;
+ struct drm_crtc_state *crtc_state;
+ struct drm_framebuffer *fb = new_plane_state->fb;
+ int ret;
+
+ if (!crtc || WARN_ON(!fb))
+ return 0;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ DRM_PLANE_NO_SCALING, DRM_PLANE_NO_SCALING,
+ true, true);
+
+ if (ret)
+ return ret;
+
+ if (!new_plane_state->visible)
+ return 0;
+
+ ret = vop_convert_format(fb->format->format);
+ if (ret < 0)
+ return ret;
+
+ if (new_plane_state->crtc_w != new_plane_state->crtc_h)
+ return -EINVAL;
+
+ if (new_plane_state->crtc_w != 0 &&
+ new_plane_state->crtc_w != 32 &&
+ new_plane_state->crtc_w != 64 &&
+ new_plane_state->crtc_w != 96 &&
+ new_plane_state->crtc_w != 128)
+ return -EINVAL;
+
+ return 0;
+
+}
+
static const struct drm_plane_helper_funcs plane_helper_funcs = {
.atomic_check = vop_plane_atomic_check,
.atomic_update = vop_plane_atomic_update,
@@ -1169,6 +1370,15 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
.prepare_fb = drm_gem_plane_helper_prepare_fb,
};
+static const struct drm_plane_helper_funcs cursor_plane_helper_funcs = {
+ .atomic_check = vop_cursor_atomic_check,
+ .atomic_update = vop_cursor_atomic_update,
+ .atomic_disable = vop_plane_atomic_disable,
+ .atomic_async_check = vop_plane_atomic_async_check,
+ .atomic_async_update = vop_cursor_atomic_async_update,
+ .prepare_fb = drm_gem_plane_helper_prepare_fb,
+};
+
static const struct drm_plane_funcs vop_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -1956,6 +2166,7 @@ static int vop_create_crtc(struct vop *vop)
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
struct device_node *port;
+ const struct drm_plane_helper_funcs *helper_funcs;
int ret;
int i;
@@ -1976,7 +2187,12 @@ static int vop_create_crtc(struct vop *vop)
}
plane = &vop_win->base;
- drm_plane_helper_add(plane, &plane_helper_funcs);
+ helper_funcs = &plane_helper_funcs;
+
+ if ((plane->type == DRM_PLANE_TYPE_CURSOR) && (vop_data->feature & VOP_FEATURE_SPECIAL_CURSOR_PLANE))
+ helper_funcs = &cursor_plane_helper_funcs;
+
+ drm_plane_helper_add(plane, helper_funcs);
vop_plane_add_properties(plane, i, win_data, vop_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index a997578e1..42dc299d9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -190,6 +190,8 @@ struct vop_win_phy {
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg channel;
+
+ struct vop_reg hwc_size;
};
struct vop_win_yuv2yuv_data {
@@ -225,6 +227,7 @@ struct vop_data {
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
+#define VOP_FEATURE_SPECIAL_CURSOR_PLANE BIT(2)
u64 feature;
};
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index ab0a78097..70930b410 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -665,6 +665,19 @@ static const struct vop_win_phy rk3288_win23_data = {
.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
};
+static const struct vop_win_phy rk3288_cursor_data = {
+ .data_formats = formats_win_lite,
+ .nformats = ARRAY_SIZE(formats_win_lite),
+ .enable = VOP_REG(RK3288_HWC_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3288_HWC_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3288_HWC_CTRL0, 0x1, 12),
+ .dsp_st = VOP_REG(RK3288_HWC_DSP_ST, 0x1fff1fff, 0),
+ .yrgb_mst = VOP_REG(RK3288_HWC_MST, 0xffffffff, 0),
+ .src_alpha_ctl = VOP_REG(RK3288_HWC_SRC_ALPHA_CTRL, 0xff, 0),
+ .dst_alpha_ctl = VOP_REG(RK3288_HWC_DST_ALPHA_CTRL, 0xff, 0),
+ .hwc_size = VOP_REG(RK3288_HWC_CTRL0, 0x3, 5),
+};
+
static const struct vop_modeset rk3288_modeset = {
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
@@ -756,6 +769,8 @@ static const struct vop_win_data rk3288_vop_win_data[] = {
{ .base = 0x00, .phy = &rk3288_win23_data,
.type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x50, .phy = &rk3288_win23_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+ { .base = 0x00, .phy = &rk3288_cursor_data,
.type = DRM_PLANE_TYPE_CURSOR },
};
@@ -1132,11 +1132,13 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x40, .phy = &rk3228_win1_data,
.type = DRM_PLANE_TYPE_OVERLAY },
+ { .base = 0x00, .phy = &rk3288_cursor_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
};
static const struct vop_data rk3228_vop = {
.version = VOP_VERSION(3, 7),
- .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
.intr = &rk3366_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 04e30bdc8a0e..26a246a0fe1d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -809,7 +809,7 @@ static const struct vop_intr rk3288_vop_intr = {
static const struct vop_data rk3288_vop_big = {
.version = VOP_VERSION(3, 1),
- .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
.intr = &rk3288_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -827,7 +827,7 @@ static const struct vop_data rk3288_vop_big = {
static const struct vop_data rk3288_vop_lit = {
.version = VOP_VERSION(3, 1),
- .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
.max_output = { 2560, 1600 },
.intr = &rk3288_vop_intr,
.common = &rk3288_common,
--
2.25.1

45
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-miqi-fan.patch
View File

@@ -1,45 +0,0 @@
From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 12 Mar 2017 19:43:15 +0000
Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
The MiQi board is sold with an enclosure in which a fan is connected
to the second LED output, and configured by default in "heartbeat"
mode so that it rotates slowly and increases when the CPU load
increases, ensuring appropriate cooling by default. This LED output
is called "Fan" in the original kernel and connected to GPIO18
(gpiochip 0, pin 18). Here we called it "miqi:green:fan" to stay
consistent with the kernel's naming conventions.
It's worth noting that without this patch the fan doesn't work at
all, risking to make the board overheat.
Fixes: 162718c (v4.7)
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Myy <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index a1c3cdaa..0e383595 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -67,6 +67,13 @@
leds {
compatible = "gpio-leds";
+ fan {
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "miqi:green:fan";
+ linux,default-trigger = "heartbeat";
+ };
+
+
work_led: led-0 {
gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "miqi:green:user";
--
2.11.0

42
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-miqi-hevc-rga.patch
View File

@@ -1,42 +0,0 @@
From 2fdd826a704ef70df42d92b38ad88ef869c3729b Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 18 Sep 2021 12:32:05 +0000
Subject: [PATCH 2/2] rockchip: enable hevc, hevc_mmu and rga nodes for miqi
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index 94bc76099..68eb766f0 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -162,6 +162,14 @@ &hdmi {
status = "okay";
};
+&hevc {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@@ -405,6 +413,10 @@ host_vbus_drv: host-vbus-drv {
};
};
+&rga {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_18>;
status = "okay";
--
2.30.2

35
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-miqi-mali-gpu.patch
View File

@@ -1,35 +0,0 @@
From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:09:50 +0200
Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
Why is the MiQi the only one left without a working mali GPU node ?
Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
they enable it once in the DTSI, instead of defining it as "disabled"
and enabling it in every DTS file ?
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index 4d923aa6..3cd60674 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -149,6 +149,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
--
2.11.0

45
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-miqi-regulator-fix.patch
View File

@@ -1,45 +0,0 @@
From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
From: Willy Tarreau <w@1wt.eu>
Date: Tue, 2 Aug 2016 08:31:00 +0200
Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
on MiQi board
The board declared too narrow a voltage range for the CPU and GPU
regulators, preventing it from using the full CPU frequency range.
The regulators support 712500 to 1500000 microvolts.
Signed-off-by: Willy Tarreau <w@1wt.eu>
(cherry picked from commit 95330e63a9295a2632cee8cce5db80677f01857a)
---
arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
index 3cd60674..a1c3cdaa 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts
@@ -168,8 +168,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x40>;
regulator-name = "vdd_cpu";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
@@ -182,8 +182,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x41>;
regulator-name = "vdd_gpu";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
--
2.11.0

34
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk322x-iep-node.patch
View File

@@ -1,34 +0,0 @@
From adecdd57a0155e0d96af2c84cc4fa52309fbb535 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 9 Sep 2021 19:14:08 +0000
Subject: [PATCH] add iep node for rk322x
---
arch/arm/boot/dts/rockchip/rk322x.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
index 0ae753c1d..271e7835f 100644
--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
@@ -834,6 +834,17 @@ rga: rga@20060000 {
reset-names = "core", "axi", "ahb";
};
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ iommus = <&iep_mmu>;
+ power-domains = <&power RK3228_PD_VIO>;
+ status = "disabled";
+ };
+
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
--
2.25.1

93
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk322x-pinctrl-nand.patch
View File

@@ -1,93 +0,0 @@
diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
index 48e6e8d44..1dfd27f9f 100644
--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
@@ -712,6 +712,22 @@ emmc: mmc@30020000 {
status = "disabled";
};
+ nfc: nand-controller@30030000 {
+ compatible = "rockchip,rk3228-nfc", "rockchip,rk2928-nfc";
+ reg = <0x30030000 0x4000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
+ clock-names = "nfc", "ahb";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_cs0 &flash_rdy &flash_ale &flash_cle
+ &flash_wrn &flash_rdn &flash_bus8>;
+ status = "disabled";
+
+ };
+
usb_otg: usb@30040000 {
compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
"snps,dwc2";
@@ -950,6 +966,65 @@ emmc_bus8: emmc-bus8 {
};
};
+ flash {
+
+ flash_cs0: flash-cs0 {
+ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ flash_cs1: flash-cs1 {
+ rockchip,pins = <0 RK_PC7 1 &pcfg_pull_up>;
+ };
+
+ flash_cs2: flash-cs2 {
+ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_up>;
+ };
+
+ flash_cs3: flash-cs3 {
+ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_up>;
+ };
+
+ flash_rdy: flash-rdy {
+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ flash_ale: flash-ale {
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_down>;
+ };
+
+ flash_cle: flash-cle {
+ rockchip,pins = <2 RK_PA1 1 &pcfg_pull_down>;
+ };
+
+ flash_wrn: flash-wrn {
+ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_up>;
+ };
+
+ flash_rdn: flash-rdn {
+ rockchip,pins = <2 RK_PA3 1 &pcfg_pull_up>;
+ };
+
+ flash_bus8: flash-bus8 {
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_up>,
+ <1 RK_PD1 1 &pcfg_pull_up>,
+ <1 RK_PD2 1 &pcfg_pull_up>,
+ <1 RK_PD3 1 &pcfg_pull_up>,
+ <1 RK_PD4 1 &pcfg_pull_up>,
+ <1 RK_PD5 1 &pcfg_pull_up>,
+ <1 RK_PD6 1 &pcfg_pull_up>,
+ <1 RK_PD7 1 &pcfg_pull_up>;
+ };
+
+ flash_dqs: flash-dqs {
+ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up>;
+ };
+
+ flash_wp: flash-wp {
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_down>;
+ };
+
+ };
+
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,

40
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk3288-disable-serial-dma.patch
View File

@@ -1,40 +0,0 @@
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 0cd88774d..07681f1f0 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -420,8 +420,6 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac_peri 1>, <&dmac_peri 2>;
- dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
@@ -435,8 +433,6 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac_peri 3>, <&dmac_peri 4>;
- dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -463,8 +459,6 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac_peri 7>, <&dmac_peri 8>;
- dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
status = "disabled";
@@ -478,8 +472,6 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac_peri 9>, <&dmac_peri 10>;
- dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";

20
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk3288-fix-mmc-aliases.patch
View File

@@ -1,20 +0,0 @@
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 511ca864c1b2..d7ecb6b4de40 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -25,10 +25,10 @@ aliases {
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
- mshc0 = &emmc;
- mshc1 = &sdmmc;
- mshc2 = &sdio0;
- mshc3 = &sdio1;
+ mmc0 = &sdmmc;
+ mmc1 = &sdio0;
+ mmc2 = &emmc;
+ mmc3 = &sdio1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;

42
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch
View File

@@ -1,42 +0,0 @@
From 73258d32daf3a661281bb5c77c5e2e06c7ff714e Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Fri, 3 Jul 2020 02:02:18 +0200
Subject: [PATCH] arm: dtsi: rk3288: add GPU 500 Mhz OPP again
Undoing the very bizarre mainline kernel patch,
75481833c6dbab4c29d15452f6b4337c16f5407b
which main purpose is to sync some 3.14 kernels hacks to
mainline kernels, for reasons that only matter for a few Chromebooks,
and shove it down the throat of every RK3288 user.
If you need to avoid the GPU going to 500 Mhz on Chromebooks,
remove the OPP entry inside the DTS that actually matters to RK3288
Chromebooks.
Meanwhile, the 600 Mhz operating point can prove to be unstable on
some RK3288 boards, while 500 Mhz works fine.
https://forum.armbian.com/topic/13515-panfrost-on-rk3288-and-gpu-on-600mhz-problems/
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index a66412547..ef7457f79 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1312,6 +1312,10 @@ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000>;
+ };
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1250000>;
--
2.27.0

31
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk3288-pinctrl-spi2.patch
View File

@@ -1,31 +0,0 @@
From 062488e4b8fd552c01e1104b3bc91a6f7ffe6c41 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:24:47 +0200
Subject: [PATCH 10/28] RK3288: DTSI: rk3288.dtsi: Add missing SPI2 pinctrl
The spi2_cs1 pin reference is missing in the spi2 first pin control
definition.
This patch is taken from the patches provided by the ARMbian team.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 5b789528..9ed532cc 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -334,7 +334,7 @@
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
reg = <0x0 0xff130000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0

32
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch
View File

@@ -1,32 +0,0 @@
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index bc3601a..37ae378 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -467,13 +467,6 @@
};
thermal-zones {
- reserve_thermal: reserve-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&tsadc 0>;
- };
-
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
@@ -539,6 +532,13 @@
};
};
};
+
+ reserve_thermal: reserve-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ };
};
tsadc: tsadc@ff280000 {

34
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch
View File

@@ -1,34 +0,0 @@
From 87313f95f809fc34f499c1ceff1b95cd4efa0f3f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 22 Mar 2022 22:02:46 +0000
Subject: [PATCH] rockchip: add tinkerboard bluetooth
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
index ff2c6de3216..23acfdecee7 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
@@ -510,6 +510,17 @@ &tsadc {
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ enable-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ };
+
};
&uart1 {
--
2.30.2

62
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-bt-uart-pins.patch
View File

@@ -1,62 +0,0 @@
From 2c2e60256f2cbb2fce50a6317f85b1500efd1a6c Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 22:03:26 +0100
Subject: [PATCH] ARM: DTS: rk3288-tinker: Setup the Bluetooth UART pins
The most essential being the RTS pin, which is clearly needed to
upload the initial configuration into the Realtek Bluetooth
chip, and make the Bluetooth chip work.
Now, the Bluetooth chip also needs 3 other GPIOS to be enabled.
I'll see how I do that through the DTS file in a near future.
The 3 GPIOS being :
Bluetooth Reset : <&gpio4 29 GPIO_ACTIVE_HIGH>
Bluetooth Wake : <&gpio4 26 GPIO_ACTIVE_HIGH>
Bluetooth Wake_Host_IRQ : <&gpio4 31 GPIO_ACTIVE_HIGH>
These are currently setup manually, through scripts. But it seems that
GPIO handling through /sys entries might not be possible in the long
term, the replacement being libgpio.
Anyway, if you're interesting in enabling the Bluetooth GPIO by hand,
here are the commands :
cd /sys/class/gpio &&
echo 146 > export &&
echo 149 > export &&
echo 151 > export &&
echo high > gpio146/direction &&
echo high > gpio149/direction &&
echo high > gpio151/direction
Resetting the chip is done like this :
echo "Resetting the Bluetooth chip"
cd /sys/class/gpio/gpio149 &&
echo 0 > value &&
sleep 1 &&
echo 1 > value &&
sleep 1
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
index d4df13bed..b92e59c1e 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
@@ -73,3 +73,9 @@
status = "okay";
supports-sdio;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+};
+
--
2.16.4

43
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-hevc-rga.patch
View File

@@ -1,43 +0,0 @@
From 0bcc81848ec1fb34fee9d3c7eb1550495cc8efc9 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 18 Sep 2021 12:31:19 +0000
Subject: [PATCH 1/2] rockchip: enable hevc, hevc_mmu and rga nodes for
tinkerboard (both)
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
index aa36aedf9..ff2c6de32 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
@@ -150,6 +150,14 @@ &hdmi {
status = "okay";
};
+&hevc {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@@ -449,6 +457,10 @@ &pwm0 {
status = "okay";
};
+&rga {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc18_ldo1>;
status = "okay";
--
2.30.2

98
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-sdio-wifi.patch
View File

@@ -1,98 +0,0 @@
From d5d5c53173c484a13cda62a537cbf75a5df4b0e4 Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 21:58:56 +0100
Subject: [PATCH] ARM: DTS: rk3288-tinker: Enabling SDIO and Wifi
Adding the appropriate nodes in order to exploit the WiFi capabilities
of the board.
Since these capabilities are provided through SDIO, and the SDIO
nodes were not defined, these were added too.
These seems to depend on each other so they are added in one big
patch.
Split if necessary.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 62 +++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
index 1e43527aa..d4df13bed 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
@@ -6,8 +6,70 @@
/dts-v1/;
#include "rk3288-tinker.dtsi"
+#include <dt-bindings/clock/rockchip,rk808.h>
/ {
model = "Rockchip RK3288 Asus Tinker Board";
compatible = "asus,rk3288-tinker", "rockchip,rk3288";
+
+ /* This is essential to get SDIO devices working.
+ The Wifi depends on SDIO ! */
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>;
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ sdio_vref = <1800>;
+ status = "okay";
+ wifi_chip_type = "8723bs";
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&io_domains {
+ wifi-supply = <&vcc_18>;
+};
+
+&pinctrl {
+ sdio-pwrseq {
+ wifi_enable_h: wifienable-h {
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ chip_enable_h: chip-enable-h {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <200000 50000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+ supports-sdio;
};
--
2.16.4

33
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-sdmmc-properties.patch
View File

@@ -1,33 +0,0 @@
From 487db7cefc9861fdaf30579c378a98f0360690ae Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 20:27:14 +0100
Subject: [PATCH] ARM: DTSI: rk3288-tinker: Defining SDMMC properties
I never knew if these properties were required to fix the dreaded
reboot issue...
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
index dd1090728..8edd6f681 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi
@@ -436,7 +436,12 @@
disable-wp; /* wp not hooked up */
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
+ supports-sd;
vmmc-supply = <&vcc33_sd>;
vqmmc-supply = <&vccio_sd>;
};
--
2.16.4

50
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-tinkerboard-spi-interface.patch
View File

@@ -1,50 +0,0 @@
From b24b8f83e150811ad54ee2a4843e44cd1421fafa Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 22:15:14 +0100
Subject: [PATCH] ARM: DTS: rk3288-tinker: Defining the SPI interface
Taken from, and tested by @TonyMac32 .
Well, the original one was tested by him but I had to adapt the
registers definitions to the new 64-bits LPAE-compliant syntax.
Therefore that *might* break, along with a few other patches.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
index 96d05fc6b..17bfea298 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts
@@ -99,6 +99,25 @@
supports-sdio;
};
+&spi2 {
+ max-freq = <50000000>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
--
2.16.4

32
patch/kernel/archive/rockchip-6.7/patches.armbian/dts-veyron-flag-cache-flush.patch
View File

@@ -1,32 +0,0 @@
From 9177b30ab083dbda2bede3b3d61ef71ad4b1ffe0 Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Thu, 1 Nov 2018 21:31:26 +0100
Subject: [PATCH 2/2] arm: dts: veyron: Added a flag to disable cache flush
during reset
Flushing the MMC cache of ASUS Chromebooks during initialization or
"recovery" generates 10 minutes hangup, according to @SolidHal.
This is an adaptation of @SolidHal, in order to pinpoint the fix to
Veyron Chromebooks, and avoiding issues other RK3288 boards.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
index 2075120cf..fa4951fd7 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
@@ -123,6 +123,7 @@
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
+ no-recovery-cache-flush;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
--
2.16.4

99
patch/kernel/archive/rockchip-6.7/patches.armbian/general-add-overlay-compilation-support.patch
View File

@@ -1,99 +0,0 @@
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
index 3c79f859..4e5c1d59 100644
--- a/arch/arm/boot/.gitignore
+++ b/arch/arm/boot/.gitignore
@@ -3,3 +3,5 @@ zImage
xipImage
bootpImage
uImage
+*.dtb*
+*.scr
diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
index 50d580d77..94bd15617 100644
--- a/scripts/Makefile.dtbinst
+++ b/scripts/Makefile.dtbinst
@@ -18,9 +18,12 @@ include scripts/Kbuild.include
include $(src)/Makefile
dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))
+dtbos := $(addprefix $(dst)/overlay/, $(dtbo-y))
+scrs := $(addprefix $(dst)/overlay/, $(scr-y))
+readmes := $(addprefix $(dst)/overlay/, $(dtbotxt-y))
subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m))
-__dtbs_install: $(dtbs) $(subdirs)
+__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs)
@:
quiet_cmd_dtb_install = INSTALL $@
@@ -29,6 +32,18 @@ quiet_cmd_dtb_install = INSTALL $@
$(dst)/%.dtb: $(obj)/%.dtb
$(call cmd,dtb_install)
+$(dst)/overlay/%.dtbo: $(obj)/%.dtbo
+ $(call cmd,dtb_install)
+
+$(dst)/overlay/%.scr: $(obj)/%.scr
+ $(call cmd,dtb_install)
+
+$(dst)/overlay/README.rockchip-overlays: $(src)/README.rockchip-overlays
+ $(call cmd,dtb_install)
+
+$(dst)/overlay/README.rk322x-overlays: $(src)/README.rk322x-overlays
+ $(call cmd,dtb_install)
+
PHONY += $(subdirs)
$(subdirs):
$(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 58c05e5d..2b95dda9 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
# ---------------------------------------------------------------------------
DTC ?= $(objtree)/scripts/dtc/dtc
+# Overlay support
+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
+
# Disable noisy checks by default
ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),)
DTC_FLAGS += -Wno-unit_address_vs_reg \
@@ -324,6 +327,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
$(obj)/%.dtb: $(src)/%.dts FORCE
$(call if_changed_dep,dtc)
+quiet_cmd_dtco = DTCO $@
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ $(DTC) -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtbo: $(src)/%.dts FORCE
+ $(call if_changed_dep,dtco)
+
+quiet_cmd_scr = MKIMAGE $@
+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
+
+$(obj)/%.scr: $(src)/%.scr-cmd FORCE
+ $(call if_changed,scr)
+
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
# Bzip2
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 41c50f9461e5..387659d5b252 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -79,6 +79,9 @@ header-test-y += $(filter-out $(header-test-), \
extra-$(CONFIG_HEADER_TEST) += $(addsuffix .s, $(header-test-y) $(header-test-m))
+# Overlay targets
+extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
# Add subdir path
extra-y := $(addprefix $(obj)/,$(extra-y))

358
patch/kernel/archive/rockchip-6.7/patches.armbian/general-add-overlay-configfs.patch
View File

@@ -1,358 +0,0 @@
--- /dev/null
+++ b/Documentation/devicetree/configfs-overlays.txt
@@ -0,0 +1,31 @@
+Howto use the configfs overlay interface.
+
+A device-tree configfs entry is created in /config/device-tree/overlays
+and and it is manipulated using standard file system I/O.
+Note that this is a debug level interface, for use by developers and
+not necessarily something accessed by normal users due to the
+security implications of having direct access to the kernel's device tree.
+
+* To create an overlay you mkdir the directory:
+
+ # mkdir /config/device-tree/overlays/foo
+
+* Either you echo the overlay firmware file to the path property file.
+
+ # echo foo.dtbo >/config/device-tree/overlays/foo/path
+
+* Or you cat the contents of the overlay to the dtbo file
+
+ # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
+
+The overlay file will be applied, and devices will be created/destroyed
+as required.
+
+To remove it simply rmdir the directory.
+
+ # rmdir /config/device-tree/overlays/foo
+
+The rationalle of the dual interface (firmware & direct copy) is that each is
+better suited to different use patterns. The firmware interface is what's
+intended to be used by hardware managers in the kernel, while the copy interface
+make sense for developers (since it avoids problems with namespaces).
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 37c2ccbefecdc..d3fc81a40c0e7 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -103,4 +103,11 @@ config OF_OVERLAY
config OF_NUMA
bool
+config OF_CONFIGFS
+ bool "Device Tree Overlay ConfigFS interface"
+ select CONFIGFS_FS
+ select OF_OVERLAY
+ help
+ Enable a simple user-space driven DT overlay interface.
+
endif # OF
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index 663a4af0cccd5..b00a95adf5199 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-y = base.o device.o platform.o property.o
obj-$(CONFIG_OF_KOBJ) += kobj.o
+obj-$(CONFIG_OF_CONFIGFS) += configfs.o
obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
obj-$(CONFIG_OF_FLATTREE) += fdt.o
obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
new file mode 100644
index 000000000..5dd509e8f
--- /dev/null
+++ b/drivers/of/configfs.c
@@ -0,0 +1,290 @@
+/*
+ * Configfs entries for device-tree
+ *
+ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/ctype.h>
+#include <linux/cpu.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <linux/configfs.h>
+#include <linux/types.h>
+#include <linux/stat.h>
+#include <linux/limits.h>
+#include <linux/file.h>
+#include <linux/vmalloc.h>
+#include <linux/firmware.h>
+#include <linux/sizes.h>
+
+#include "of_private.h"
+
+struct cfs_overlay_item {
+ struct config_item item;
+
+ char path[PATH_MAX];
+
+ const struct firmware *fw;
+ struct device_node *overlay;
+ int ov_id;
+
+ void *dtbo;
+ int dtbo_size;
+};
+
+static int create_overlay(struct cfs_overlay_item *overlay, void *blob, u32 blob_size)
+{
+ int err;
+
+ err = of_overlay_fdt_apply(blob, blob_size, &overlay->ov_id, NULL);
+ if (err < 0) {
+ pr_err("%s: Failed to create overlay (err=%d)\n",
+ __func__, err);
+ goto out_err;
+ }
+
+out_err:
+ return err;
+}
+
+static inline struct cfs_overlay_item *to_cfs_overlay_item(
+ struct config_item *item)
+{
+ return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
+}
+
+static ssize_t cfs_overlay_item_path_show(struct config_item *item,
+ char *page)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+ return sprintf(page, "%s\n", overlay->path);
+}
+
+static ssize_t cfs_overlay_item_path_store(struct config_item *item,
+ const char *page, size_t count)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+ const char *p = page;
+ char *s;
+ int err;
+
+ /* if it's set do not allow changes */
+ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
+ return -EPERM;
+
+ /* copy to path buffer (and make sure it's always zero terminated */
+ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
+ overlay->path[sizeof(overlay->path) - 1] = '\0';
+
+ /* strip trailing newlines */
+ s = overlay->path + strlen(overlay->path);
+ while (s > overlay->path && *--s == '\n')
+ *s = '\0';
+
+ pr_debug("%s: path is '%s'\n", __func__, overlay->path);
+
+ err = request_firmware(&overlay->fw, overlay->path, NULL);
+ if (err != 0)
+ goto out_err;
+
+ err = create_overlay(overlay, (void *)overlay->fw->data, overlay->fw->size);
+ if (err != 0)
+ goto out_err;
+
+ return count;
+
+out_err:
+
+ release_firmware(overlay->fw);
+ overlay->fw = NULL;
+
+ overlay->path[0] = '\0';
+ return err;
+}
+
+static ssize_t cfs_overlay_item_status_show(struct config_item *item,
+ char *page)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+
+ return sprintf(page, "%s\n",
+ overlay->ov_id >= 0 ? "applied" : "unapplied");
+}
+
+CONFIGFS_ATTR(cfs_overlay_item_, path);
+CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
+
+static struct configfs_attribute *cfs_overlay_attrs[] = {
+ &cfs_overlay_item_attr_path,
+ &cfs_overlay_item_attr_status,
+ NULL,
+};
+
+ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
+ void *buf, size_t max_count)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+
+ pr_debug("%s: buf=%p max_count=%zu\n", __func__,
+ buf, max_count);
+
+ if (overlay->dtbo == NULL)
+ return 0;
+
+ /* copy if buffer provided */
+ if (buf != NULL) {
+ /* the buffer must be large enough */
+ if (overlay->dtbo_size > max_count)
+ return -ENOSPC;
+
+ memcpy(buf, overlay->dtbo, overlay->dtbo_size);
+ }
+
+ return overlay->dtbo_size;
+}
+
+ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
+ const void *buf, size_t count)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+ int err;
+
+ /* if it's set do not allow changes */
+ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
+ return -EPERM;
+
+ /* copy the contents */
+ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
+ if (overlay->dtbo == NULL)
+ return -ENOMEM;
+
+ overlay->dtbo_size = count;
+
+ err = create_overlay(overlay, overlay->dtbo, overlay->dtbo_size);
+ if (err != 0)
+ goto out_err;
+
+ return count;
+
+out_err:
+ kfree(overlay->dtbo);
+ overlay->dtbo = NULL;
+ overlay->dtbo_size = 0;
+
+ return err;
+}
+
+CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
+
+static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
+ &cfs_overlay_item_attr_dtbo,
+ NULL,
+};
+
+static void cfs_overlay_release(struct config_item *item)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+
+ if (overlay->ov_id >= 0)
+ of_overlay_remove(&overlay->ov_id);
+ if (overlay->fw)
+ release_firmware(overlay->fw);
+ /* kfree with NULL is safe */
+ kfree(overlay->dtbo);
+ kfree(overlay);
+}
+
+static struct configfs_item_operations cfs_overlay_item_ops = {
+ .release = cfs_overlay_release,
+};
+
+static struct config_item_type cfs_overlay_type = {
+ .ct_item_ops = &cfs_overlay_item_ops,
+ .ct_attrs = cfs_overlay_attrs,
+ .ct_bin_attrs = cfs_overlay_bin_attrs,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct config_item *cfs_overlay_group_make_item(
+ struct config_group *group, const char *name)
+{
+ struct cfs_overlay_item *overlay;
+
+ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
+ if (!overlay)
+ return ERR_PTR(-ENOMEM);
+ overlay->ov_id = -1;
+
+ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
+ return &overlay->item;
+}
+
+static void cfs_overlay_group_drop_item(struct config_group *group,
+ struct config_item *item)
+{
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
+
+ config_item_put(&overlay->item);
+}
+
+static struct configfs_group_operations overlays_ops = {
+ .make_item = cfs_overlay_group_make_item,
+ .drop_item = cfs_overlay_group_drop_item,
+};
+
+static struct config_item_type overlays_type = {
+ .ct_group_ops = &overlays_ops,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct configfs_group_operations of_cfs_ops = {
+ /* empty - we don't allow anything to be created */
+};
+
+static struct config_item_type of_cfs_type = {
+ .ct_group_ops = &of_cfs_ops,
+ .ct_owner = THIS_MODULE,
+};
+
+struct config_group of_cfs_overlay_group;
+
+static struct configfs_subsystem of_cfs_subsys = {
+ .su_group = {
+ .cg_item = {
+ .ci_namebuf = "device-tree",
+ .ci_type = &of_cfs_type,
+ },
+ },
+ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
+};
+
+static int __init of_cfs_init(void)
+{
+ int ret;
+
+ pr_info("%s\n", __func__);
+
+ config_group_init(&of_cfs_subsys.su_group);
+ config_group_init_type_name(&of_cfs_overlay_group, "overlays",
+ &overlays_type);
+ configfs_add_default_group(&of_cfs_overlay_group,
+ &of_cfs_subsys.su_group);
+
+ ret = configfs_register_subsystem(&of_cfs_subsys);
+ if (ret != 0) {
+ pr_err("%s: failed to register subsys\n", __func__);
+ goto out;
+ }
+ pr_info("%s: OK\n", __func__);
+out:
+ return ret;
+}
+late_initcall(of_cfs_init);

71
patch/kernel/archive/rockchip-6.7/patches.armbian/general-add-restart-handler-for-act8846.patch
View File

@@ -1,71 +0,0 @@
From 7f2d6a02498ce3fa7771893072e81b31f9bd64b2 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Fri, 24 Mar 2023 17:15:16 +0000
Subject: [PATCH] register act8846 restart handler for SIPC function
---
drivers/regulator/act8865-regulator.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
index 53f2c75cd..e45ad8430 100644
--- a/drivers/regulator/act8865-regulator.c
+++ b/drivers/regulator/act8865-regulator.c
@@ -20,6 +20,7 @@
#include <linux/regulator/of_regulator.h>
#include <linux/regmap.h>
#include <dt-bindings/regulator/active-semi,8865-regulator.h>
+#include <linux/reboot.h>
/*
* ACT8600 Global Register Map.
@@ -141,6 +142,8 @@
#define ACT8865_VOLTAGE_NUM 64
#define ACT8600_SUDCDC_VOLTAGE_NUM 256
+#define ACT8846_SIPC_MASK 0x01
+
struct act8865 {
struct regmap *regmap;
int off_reg;
@@ -582,6 +585,22 @@ static void act8865_power_off(void)
while (1);
}
+static int act8846_power_cycle(struct notifier_block *this,
+ unsigned long code, void *unused)
+{
+ struct act8865 *act8846;
+
+ act8846 = i2c_get_clientdata(act8865_i2c_client);
+ regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block act8846_restart_handler = {
+ .notifier_call = act8846_power_cycle,
+ .priority = 129,
+};
+
static int act8600_charger_get_status(struct regmap *map)
{
unsigned int val;
@@ -733,6 +752,14 @@ static int act8865_pmic_probe(struct i2c_client *client)
} else {
dev_err(dev, "Failed to set poweroff capability, already defined\n");
}
+
+ if (type == ACT8846) {
+ act8865_i2c_client = client;
+ ret = register_restart_handler(&act8846_restart_handler);
+ if (ret)
+ pr_err("%s: cannot register restart handler, %d\n",
+ __func__, ret);
+ }
}
/* Finally register devices */
--
2.34.1

26
patch/kernel/archive/rockchip-6.7/patches.armbian/general-dwc2-fix-wait-peripheral.patch
View File

@@ -1,26 +0,0 @@
From e477f1546f2739e9ea053d677f421e01a9babff4 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 2 Mar 2024 21:56:44 +0100
Subject: [PATCH] dwc2: add fixes for rk322x peripheral mode
---
drivers/usb/dwc2/core.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 5635e4d7ec88..0a3d387a497a 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -532,6 +532,9 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
gusbcfg |= set;
dwc2_writel(hsotg, gusbcfg, GUSBCFG);
+ /* On some rockchip platforms, this fixes hang on reset in peripheral mode */
+ msleep(10);
+
dwc2_wait_for_mode(hsotg, host);
return;
}
--
2.34.1

56
patch/kernel/archive/rockchip-6.7/patches.armbian/general-dwc2-fix-wait-time.patch
View File

@@ -1,56 +0,0 @@
From ee7c3ab6b5a4d284a04f110792508a7f8decd7f7 Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Tue, 6 Dec 2022 14:45:54 +0800
Subject: [PATCH] usb: dwc2: fix waiting time for host only mode
The current code uses 50ms sleep to wait for host only
mode, the delay time is not enough for some Rockchip
platforms (e.g RK3036G EVB1).
Test on RK3036G EVB1, the dwc2 host only controller reg
GOTGCTL.ConIDSts = 1'b1 (device mode) if only wait for
50ms. And the host fails to detect usb2 device with the
following error log:
usb usb2-port1: connect-debounce failed
This patch checks the GOTGCTL.ConIDSts for host only
mode and increases the maximum waiting time to 200ms.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ie28299934aba09907ea08f5fd3b34bf2fb35822e
---
drivers/usb/dwc2/core.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 15911ac7582b4..cbd5f1142f35e 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -656,14 +656,24 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
*/
void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
{
+ u32 count = 0;
+
switch (hsotg->dr_mode) {
case USB_DR_MODE_HOST:
/*
* NOTE: This is required for some rockchip soc based
* platforms on their host-only dwc2.
*/
- if (!dwc2_hw_is_otg(hsotg))
- msleep(50);
+ if (!dwc2_hw_is_otg(hsotg)) {
+ while (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_CONID_B) {
+ msleep(20);
+ if (++count > 10)
+ break;
+ }
+ if (count > 10)
+ dev_err(hsotg->dev,
+ "Waiting for Host Mode timed out");
+ }
break;
case USB_DR_MODE_PERIPHERAL:

88
patch/kernel/archive/rockchip-6.7/patches.armbian/general-dwc2-nak-gadget.patch
View File

@@ -1,88 +0,0 @@
From 15b317ff84dc09faa47995b1d973d96a6172fa4c Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Thu, 15 Dec 2022 14:19:28 +0800
Subject: [PATCH] usb: dwc2: gadget: Disable nak interrupt when get first isoc
in token
The dwc2 driver use the nak interrupt for the starting point
of isoc-in transfer. The first nak interrupt for isoc-in means
that in token has arrived and the dwc2 driver can obtain the
(micro) frame of the token to set the even/odd (micro) frame
field of DIEPCTL.
However, on some platforms (e.g Rockchip rk3308) which don't
support the "OTG_MULTI_PROC_INTRPT", it means that all device
endpoints share the same nak mask and interrupt. If the nak
interrupt is always enabled, it may trigger nak interrupt storm
by other endpoints except the isoc-in endpoint. So we disable
the nak interrupt when get first isoc in token if the feature
"OTG_MULTI_PROC_INTRPT" isn't enabled.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I99c71a5e0d7903346fd8f71619b6736c3181c0ec
---
drivers/usb/dwc2/gadget.c | 37 +++++++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index e1dc4735a99c..0e185ef474ac 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -1402,6 +1402,8 @@ static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
return 0;
}
+static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep);
+
static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
gfp_t gfp_flags)
{
@@ -1518,6 +1520,20 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
+ } else if (hs_ep->isochronous && hs_ep->dir_in && !hs_ep->req &&
+ !(dwc2_readl(hs, GHWCFG2) & GHWCFG2_MULTI_PROC_INT)) {
+ /* Update current frame number value. */
+ hs->frame_number = dwc2_hsotg_read_frameno(hs);
+ while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
+ dwc2_gadget_incr_frame_num(hs_ep);
+ /* Update current frame number value once more as it
+ * changes here.
+ */
+ hs->frame_number = dwc2_hsotg_read_frameno(hs);
+ }
+
+ if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
+ dwc2_gadget_start_next_request(hs_ep);
}
return 0;
}
@@ -2989,8 +3005,25 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
hs_ep->target_frame = hsotg->frame_number;
if (hs_ep->interval > 1) {
- u32 ctrl = dwc2_readl(hsotg,
- DIEPCTL(hs_ep->index));
+ u32 mask;
+ u32 ctrl;
+
+ /*
+ * Disable nak interrupt when we have got the first
+ * isoc in token. This can avoid nak interrupt storm
+ * on the Rockchip platforms which don't support the
+ * "OTG_MULTI_PROC_INTRPT", and all device endpoints
+ * share the same nak mask and interrupt.
+ */
+ if (!(dwc2_readl(hsotg, GHWCFG2) &
+ GHWCFG2_MULTI_PROC_INT)) {
+ mask = dwc2_readl(hsotg, DIEPMSK);
+ mask &= ~DIEPMSK_NAKMSK;
+ dwc2_writel(hsotg, mask, DIEPMSK);
+ }
+
+ ctrl = dwc2_readl(hsotg,
+ DIEPCTL(hs_ep->index));
if (hs_ep->target_frame & 0x1)
ctrl |= DXEPCTL_SETODDFR;
else

19
patch/kernel/archive/rockchip-6.7/patches.armbian/general-fix-reboot-from-kwiboo.patch
View File

@@ -1,19 +0,0 @@
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 5bd58b95d..48ebe081f 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1684,6 +1684,14 @@ void mmc_power_off(struct mmc_host *host)
if (host->ios.power_mode == MMC_POWER_OFF)
return;
+ mmc_set_initial_signal_voltage(host);
+
+ /*
+ * This delay should be sufficient to allow the power supply
+ * to reach the minimum voltage.
+ */
+ mmc_delay(host->ios.power_delay_ms);
+
mmc_pwrseq_power_off(host);
host->ios.clock = 0;

24
patch/kernel/archive/rockchip-6.7/patches.armbian/general-linux-export-mm-trace-rss-stats.patch
View File

@@ -1,24 +0,0 @@
From 6408e6688b18e5c712c711110d196a4e95f3f870 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 9 Sep 2021 16:37:28 +0000
Subject: [PATCH 2/4] 01-linux-1000-export-mm_trace_rss_stat
---
mm/memory.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/mm/memory.c b/mm/memory.c
index 25fc46e87..7ef0adaa5 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -171,6 +171,7 @@ void mm_trace_rss_stat(struct mm_struct *mm, int member, long count)
{
trace_rss_stat(mm, member, count);
}
+EXPORT_SYMBOL(mm_trace_rss_stat);
#if defined(SPLIT_RSS_COUNTING)
--
2.25.1

786
patch/kernel/archive/rockchip-6.7/patches.armbian/general-rk322x-gpio-ir-driver.patch
View File

@@ -1,786 +0,0 @@
From 13498feb91614d59ebece61d0c278e31529bb8c8 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 10 Oct 2023 21:54:51 +0200
Subject: [PATCH] rockchip gpio IR driver
---
drivers/media/rc/Kconfig | 11 +
drivers/media/rc/Makefile | 1 +
drivers/media/rc/rockchip-ir.c | 723 +++++++++++++++++++++++++++++++++
3 files changed, 735 insertions(+)
create mode 100644 drivers/media/rc/rockchip-ir.c
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 2afe67ffa285..0fd671f5873c 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -338,6 +338,16 @@ config IR_REDRAT3
To compile this driver as a module, choose M here: the
module will be called redrat3.
+config IR_ROCKCHIP_CIR
+ tristate "Rockchip GPIO IR receiver"
+ depends on (OF && GPIOLIB) || COMPILE_TEST
+ help
+ Say Y here if you want to use the Rockchip IR receiver with
+ virtual poweroff features provided by rockchip Trust OS
+
+ To compile this driver as a module, choose M here: the
+ module will be called rockchip-ir
+
config IR_SERIAL
tristate "Homebrew Serial Port Receiver"
depends on HAS_IOPORT
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 2bca6f7f07bc..2ec037f8b939 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_IR_MTK) += mtk-cir.o
obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
obj-$(CONFIG_IR_PWM_TX) += pwm-ir-tx.o
obj-$(CONFIG_IR_REDRAT3) += redrat3.o
+obj-$(CONFIG_IR_ROCKCHIP_CIR) += rockchip-ir.o
obj-$(CONFIG_IR_SERIAL) += serial_ir.o
obj-$(CONFIG_IR_SPI) += ir-spi.o
obj-$(CONFIG_IR_STREAMZAP) += streamzap.o
diff --git a/drivers/media/rc/rockchip-ir.c b/drivers/media/rc/rockchip-ir.c
new file mode 100644
index 000000000000..43ade8c4adce
--- /dev/null
+++ b/drivers/media/rc/rockchip-ir.c
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio/consumer.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_qos.h>
+#include <linux/irq.h>
+#include <linux/arm-smccc.h>
+#include <linux/clk.h>
+#include <linux/reboot.h>
+#include <uapi/linux/psci.h>
+#include <media/rc-core.h>
+#include <soc/rockchip/rockchip_sip.h>
+
+#define ROCKCHIP_IR_DEVICE_NAME "rockchip_ir_recv"
+
+#ifdef CONFIG_64BIT
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+#else
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
+#endif
+
+/*
+* SIP/TEE constants for remote calls
+*/
+#define SIP_REMOTECTL_CFG 0x8200000b
+#define SIP_SUSPEND_MODE 0x82000003
+#define SIP_REMOTECTL_CFG 0x8200000b
+#define SUSPEND_MODE_CONFIG 0x01
+#define WKUP_SOURCE_CONFIG 0x02
+#define PWM_REGULATOR_CONFIG 0x03
+#define GPIO_POWER_CONFIG 0x04
+#define SUSPEND_DEBUG_ENABLE 0x05
+#define APIOS_SUSPEND_CONFIG 0x06
+#define VIRTUAL_POWEROFF 0x07
+
+#define REMOTECTL_SET_IRQ 0xf0
+#define REMOTECTL_SET_PWM_CH 0xf1
+#define REMOTECTL_SET_PWRKEY 0xf2
+#define REMOTECTL_GET_WAKEUP_STATE 0xf3
+#define REMOTECTL_ENABLE 0xf4
+#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf /* wakeup state */
+
+/*
+* PWM Registers
+* Each PWM has its own control registers
+*/
+#define PWM_REG_CNTR 0x00 /* Counter Register */
+#define PWM_REG_HPR 0x04 /* Period Register */
+#define PWM_REG_LPR 0x08 /* Duty Cycle Register */
+#define PWM_REG_CTRL 0x0c /* Control Register */
+
+/*
+* PWM General registers
+* Registers shared among PWMs
+*/
+#define PWM_REG_INT_EN 0x44
+
+/*REG_CTRL bits definitions*/
+#define PWM_ENABLE (1 << 0)
+#define PWM_DISABLE (0 << 0)
+
+/*operation mode*/
+#define PWM_MODE_ONESHOT (0x00 << 1)
+#define PWM_MODE_CONTINUMOUS (0x01 << 1)
+#define PWM_MODE_CAPTURE (0x02 << 1)
+
+/* Channel interrupt enable bit */
+#define PWM_CH_INT_ENABLE(n) BIT(n)
+
+enum pwm_div {
+ PWM_DIV1 = (0x0 << 12),
+ PWM_DIV2 = (0x1 << 12),
+ PWM_DIV4 = (0x2 << 12),
+ PWM_DIV8 = (0x3 << 12),
+ PWM_DIV16 = (0x4 << 12),
+ PWM_DIV32 = (0x5 << 12),
+ PWM_DIV64 = (0x6 << 12),
+ PWM_DIV128 = (0x7 << 12),
+};
+
+#define PWM_INT_ENABLE 1
+#define PWM_INT_DISABLE 0
+
+struct rockchip_rc_dev {
+ struct rc_dev *rcdev;
+ struct gpio_desc *gpiod;
+ int irq;
+ struct device *pmdev;
+ struct pm_qos_request qos;
+ void __iomem *pwm_base;
+ int pwm_wake_irq;
+ int pwm_id;
+ bool use_shutdown_handler; // if true, installs a shutdown handler and triggers virtual poweroff
+ bool use_suspend_handler; // if true, virtual poweroff is used as suspend mode otherwise use as regular suspend
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pinctrl_state_default;
+ struct pinctrl_state *pinctrl_state_suspend;
+};
+
+static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
+ unsigned long arg0,
+ unsigned long arg1,
+ unsigned long arg2)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
+
+ return res;
+}
+
+int sip_smc_remotectl_config(u32 func, u32 data)
+{
+ struct arm_smccc_res res;
+
+ res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
+
+ return res.a0;
+}
+
+int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
+{
+ struct arm_smccc_res res;
+
+ res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
+ return res.a0;
+}
+
+int sip_smc_virtual_poweroff(void)
+{
+ struct arm_smccc_res res;
+
+ res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
+ return res.a0;
+}
+
+static irqreturn_t rockchip_ir_recv_irq(int irq, void *dev_id)
+{
+ int val;
+ struct rockchip_rc_dev *gpio_dev = dev_id;
+ struct device *pmdev = gpio_dev->pmdev;
+
+ /*
+ * For some cpuidle systems, not all:
+ * Respond to interrupt taking more latency when cpu in idle.
+ * Invoke asynchronous pm runtime get from interrupt context,
+ * this may introduce a millisecond delay to call resume callback,
+ * where to disable cpuilde.
+ *
+ * Two issues lead to fail to decode first frame, one is latency to
+ * respond to interrupt, another is delay introduced by async api.
+ */
+ if (pmdev)
+ pm_runtime_get(pmdev);
+
+ val = gpiod_get_value(gpio_dev->gpiod);
+ if (val >= 0)
+ ir_raw_event_store_edge(gpio_dev->rcdev, val == 1);
+
+ if (pmdev) {
+ pm_runtime_mark_last_busy(pmdev);
+ pm_runtime_put_autosuspend(pmdev);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void rockchip_pwm_int_ctrl(struct rockchip_rc_dev *gpio_dev, bool enable)
+{
+
+ void __iomem *pwm_base = gpio_dev->pwm_base;
+ struct device *dev = &gpio_dev->rcdev->dev;
+ int pwm_id = gpio_dev->pwm_id;
+
+ void __iomem *reg_int_ctrl;
+ int val;
+
+ reg_int_ctrl= pwm_base - (0x10 * pwm_id) + PWM_REG_INT_EN;
+
+ val = readl_relaxed(reg_int_ctrl);
+
+ if (enable) {
+ val |= PWM_CH_INT_ENABLE(pwm_id);
+ dev_info(dev, "PWM interrupt enabled, register value %x\n", val);
+ } else {
+ val &= ~PWM_CH_INT_ENABLE(pwm_id);
+ dev_info(dev, "PWM interrupt disabled, register value %x\n", val);
+ }
+
+ writel_relaxed(val, reg_int_ctrl);
+
+}
+
+static int rockchip_pwm_hw_init(struct rockchip_rc_dev *gpio_dev)
+{
+
+ void __iomem *pwm_base = gpio_dev->pwm_base;
+ int val;
+
+ //1. disabled pwm
+ val = readl_relaxed(pwm_base + PWM_REG_CTRL);
+ val = (val & 0xFFFFFFFE) | PWM_DISABLE;
+ writel_relaxed(val, pwm_base + PWM_REG_CTRL);
+
+ //2. capture mode
+ val = readl_relaxed(pwm_base + PWM_REG_CTRL);
+ val = (val & 0xFFFFFFF9) | PWM_MODE_CAPTURE;
+ writel_relaxed(val, pwm_base + PWM_REG_CTRL);
+
+ //set clk div, clk div to 64
+ val = readl_relaxed(pwm_base + PWM_REG_CTRL);
+ val = (val & 0xFF0001FF) | PWM_DIV64;
+ writel_relaxed(val, pwm_base + PWM_REG_CTRL);
+
+ //4. enabled pwm int
+ rockchip_pwm_int_ctrl(gpio_dev, true);
+
+ //5. enabled pwm
+ val = readl_relaxed(pwm_base + PWM_REG_CTRL);
+ val = (val & 0xFFFFFFFE) | PWM_ENABLE;
+ writel_relaxed(val, pwm_base + PWM_REG_CTRL);
+
+ return 0;
+
+}
+
+static int rockchip_pwm_hw_stop(struct rockchip_rc_dev *gpio_dev)
+{
+
+ void __iomem *pwm_base = gpio_dev->pwm_base;
+ int val;
+
+ //disable pwm interrupt
+ rockchip_pwm_int_ctrl(gpio_dev, false);
+
+ //disable pwm
+ val = readl_relaxed(pwm_base + PWM_REG_CTRL);
+ val = (val & 0xFFFFFFFE) | PWM_DISABLE;
+ writel_relaxed(val, pwm_base + PWM_REG_CTRL);
+
+ return 0;
+
+}
+
+static int rockchip_pwm_sip_wakeup_init(struct rockchip_rc_dev *gpio_dev)
+{
+
+ struct device *dev = &gpio_dev->rcdev->dev;
+
+ struct irq_data *irq_data;
+ long hwirq;
+ int ret;
+
+ irq_data = irq_get_irq_data(gpio_dev->pwm_wake_irq);
+ if (!irq_data) {
+ dev_err(dev, "could not get irq data\n");
+ return -1;
+ }
+
+ hwirq = irq_data->hwirq;
+ dev_info(dev, "use hwirq %ld, pwm chip id %d for PWM SIP wakeup\n", hwirq, gpio_dev->pwm_id);
+
+ ret = 0;
+
+ ret |= sip_smc_remotectl_config(REMOTECTL_SET_IRQ, (int)hwirq);
+ ret |= sip_smc_remotectl_config(REMOTECTL_SET_PWM_CH, gpio_dev->pwm_id);
+ ret |= sip_smc_remotectl_config(REMOTECTL_ENABLE, 1);
+
+ if (ret) {
+ dev_err(dev, "SIP remote controller mode, TEE does not support feature\n");
+ return ret;
+ }
+
+ sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, 0x10042, 0);
+ sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, 0x0, 0);
+ sip_smc_set_suspend_mode(PWM_REGULATOR_CONFIG, 0x0, 0);
+ //sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, i, gpio_temp[i]);
+ sip_smc_set_suspend_mode(SUSPEND_DEBUG_ENABLE, 0x1, 0);
+ sip_smc_set_suspend_mode(APIOS_SUSPEND_CONFIG, 0x0, 0);
+ sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 1);
+
+ dev_info(dev, "TEE remote controller wakeup installed\n");
+
+ return 0;
+
+}
+
+static int rockchip_ir_recv_remove(struct platform_device *pdev)
+{
+ struct rockchip_rc_dev *gpio_dev = platform_get_drvdata(pdev);
+ struct device *pmdev = gpio_dev->pmdev;
+
+ if (pmdev) {
+ pm_runtime_get_sync(pmdev);
+ cpu_latency_qos_remove_request(&gpio_dev->qos);
+
+ pm_runtime_disable(pmdev);
+ pm_runtime_put_noidle(pmdev);
+ pm_runtime_set_suspended(pmdev);
+ }
+
+ // Disable the remote controller handling of the Trust OS
+ sip_smc_remotectl_config(REMOTECTL_ENABLE, 0);
+
+ // Disable the virtual poweroff of the Trust OS
+ sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 0);
+
+ return 0;
+}
+
+static int rockchip_ir_register_power_key(struct device *dev)
+{
+
+ struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
+
+ struct rc_map *key_map;
+ struct rc_map_table *key;
+ int idx, key_scancode, rev_scancode;
+ int tee_scancode;
+
+ key_map = &gpio_dev->rcdev->rc_map;
+
+ dev_info(dev, "remote key table %s, key map of %d items\n", key_map->name, key_map->len);
+
+ for (idx = 0; idx < key_map->len; idx++) {
+
+ key = &key_map->scan[idx];
+
+ if (key->keycode != KEY_POWER)
+ continue;
+
+ key_scancode = key->scancode;
+ rev_scancode = ~key_scancode;
+
+ // If key_scancode has higher 16 bits set to 0, then the scancode is NEC protocol, otherwise it is NECX/NEC32
+ if ((key_scancode & 0xffff) == key_scancode)
+ tee_scancode = (key_scancode & 0xff00) | ((rev_scancode & 0xff00) << 8); // NEC protocol
+ else
+ tee_scancode = ((key_scancode & 0xff0000) >> 8) | ((key_scancode & 0xff00) << 8); // NECX/NEC32 protocol
+
+ tee_scancode |= rev_scancode & 0xff;
+ tee_scancode <<= 8;
+
+ sip_smc_remotectl_config(REMOTECTL_SET_PWRKEY, tee_scancode);
+
+ dev_info(dev, "registered scancode %08x (SIP: %8x)\n", key_scancode, tee_scancode);
+
+ }
+
+ return 0;
+
+}
+
+static int rockchip_ir_recv_suspend_prepare(struct device *dev)
+{
+ struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
+ int ret;
+
+ dev_info(dev, "initialize rockchip SIP virtual poweroff\n");
+ ret = rockchip_pwm_sip_wakeup_init(gpio_dev);
+
+ if (ret)
+ return ret;
+
+ rockchip_ir_register_power_key(dev);
+
+ disable_irq(gpio_dev->irq);
+ dev_info(dev, "GPIO IRQ disabled\n");
+
+ ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_suspend);
+ if (ret) {
+ dev_err(dev, "unable to set pin in PWM mode\n");
+ return ret;
+ }
+
+ dev_info(dev, "set pin configuration to PWM mode\n");
+
+ rockchip_pwm_hw_init(gpio_dev);
+ dev_info(dev, "started pin PWM mode\n");
+
+ return 0;
+
+}
+
+#ifdef CONFIG_PM
+static int rockchip_ir_recv_suspend(struct device *dev)
+{
+ struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
+
+ /*
+ * if property suspend-is-virtual-poweroff is set, we can disable
+ * the regular gpio wakeup and enable the PWM mode for the Trust OS
+ * to take control and react to remote control.
+ * If the property is not set, we instead enable the wake up for the
+ * regular gpio.
+ */
+ if (gpio_dev->use_suspend_handler) {
+
+ rockchip_ir_recv_suspend_prepare(dev);
+
+ } else {
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(gpio_dev->irq);
+ else
+ disable_irq(gpio_dev->irq);
+
+ }
+
+ return 0;
+}
+
+static int rockchip_ir_recv_resume(struct device *dev)
+{
+ struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
+ int ret;
+
+ /*
+ * In case suspend-is-virtual-poweroff property is set,
+ * restore the pin from PWM mode to regular GPIO configuration
+ * and stop the PWM function.
+ * Otherwise, just enable the regular GPIO irq
+ */
+ if (gpio_dev->use_suspend_handler) {
+
+ rockchip_pwm_hw_stop(gpio_dev);
+ dev_info(dev, "stopped pin PWM mode\n");
+
+ ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_default);
+ if (ret) {
+ dev_err(dev, "unable to restore pin in GPIO mode\n");
+ return ret;
+ }
+ dev_info(dev, "restored pin configuration di GPIO\n");
+
+ enable_irq(gpio_dev->irq);
+ dev_info(dev, "restored GPIO IRQ\n");
+
+ } else {
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(gpio_dev->irq);
+ else
+ enable_irq(gpio_dev->irq);
+
+ }
+
+ return 0;
+}
+
+static void rockchip_ir_recv_shutdown(struct platform_device *pdev)
+{
+
+ struct device *dev = &pdev->dev;
+ struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
+
+ if (gpio_dev->use_shutdown_handler)
+ rockchip_ir_recv_suspend_prepare(dev);
+
+ return;
+
+}
+
+static int rockchip_ir_recv_sys_off(struct sys_off_data *data)
+{
+
+ sip_smc_virtual_poweroff();
+
+ return 0;
+
+}
+
+static int rockchip_ir_recv_init_sip(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res);
+
+ if (res.a0)
+ return 0;
+
+ return res.a1;
+
+}
+
+static int rockchip_ir_recv_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct rockchip_rc_dev *gpio_dev;
+ struct rc_dev *rcdev;
+ struct clk *clk;
+ struct clk *p_clk;
+ struct resource *res;
+ u32 period = 0;
+ int rc;
+ int ret;
+ int pwm_wake_irq;
+ int clocks;
+
+ if (!np)
+ return -ENODEV;
+
+ gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL);
+ if (!gpio_dev)
+ return -ENOMEM;
+
+ gpio_dev->gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN);
+ if (IS_ERR(gpio_dev->gpiod)) {
+ rc = PTR_ERR(gpio_dev->gpiod);
+ /* Just try again if this happens */
+ if (rc != -EPROBE_DEFER)
+ dev_err(dev, "error getting gpio (%d)\n", rc);
+ return rc;
+ }
+ gpio_dev->irq = gpiod_to_irq(gpio_dev->gpiod);
+ if (gpio_dev->irq < 0)
+ return gpio_dev->irq;
+
+ rcdev = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
+ if (!rcdev)
+ return -ENOMEM;
+
+ rcdev->priv = gpio_dev;
+ rcdev->device_name = ROCKCHIP_IR_DEVICE_NAME;
+ rcdev->input_phys = ROCKCHIP_IR_DEVICE_NAME "/input0";
+ rcdev->input_id.bustype = BUS_HOST;
+ rcdev->input_id.vendor = 0x0001;
+ rcdev->input_id.product = 0x0001;
+ rcdev->input_id.version = 0x0100;
+ rcdev->dev.parent = dev;
+ rcdev->driver_name = KBUILD_MODNAME;
+ rcdev->min_timeout = 1;
+ rcdev->timeout = IR_DEFAULT_TIMEOUT;
+ rcdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
+ rcdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
+ rcdev->map_name = of_get_property(np, "linux,rc-map-name", NULL);
+ if (!rcdev->map_name)
+ rcdev->map_name = RC_MAP_EMPTY;
+
+ gpio_dev->rcdev = rcdev;
+ if (of_property_read_bool(np, "wakeup-source")) {
+
+ ret = device_init_wakeup(dev, true);
+
+ if (ret)
+ dev_err(dev, "could not init wakeup device\n");
+
+ }
+
+ rc = devm_rc_register_device(dev, rcdev);
+ if (rc < 0) {
+ dev_err(dev, "failed to register rc device (%d)\n", rc);
+ return rc;
+ }
+
+ of_property_read_u32(np, "linux,autosuspend-period", &period);
+ if (period) {
+ gpio_dev->pmdev = dev;
+ pm_runtime_set_autosuspend_delay(dev, period);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_enable(dev);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "no memory resources defined\n");
+ return -ENODEV;
+ }
+
+ gpio_dev->pwm_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(gpio_dev->pwm_base))
+ return PTR_ERR(gpio_dev->pwm_base);
+
+ clocks = of_property_count_strings(np, "clock-names");
+ if (clocks == 2) {
+ clk = devm_clk_get(dev, "pwm");
+ p_clk = devm_clk_get(dev, "pclk");
+ } else {
+ clk = devm_clk_get(dev, NULL);
+ p_clk = clk;
+ }
+
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Can't get bus clock: %d\n", ret);
+ return ret;
+ }
+
+ if (IS_ERR(p_clk)) {
+ ret = PTR_ERR(p_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Can't get peripheral clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(dev, "Can't enable bus clk: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(p_clk);
+ if (ret) {
+ dev_err(dev, "Can't enable peripheral clk: %d\n", ret);
+ goto error_clk;
+ }
+
+ pwm_wake_irq = platform_get_irq(pdev, 0);
+ if (pwm_wake_irq < 0) {
+ dev_err(&pdev->dev, "cannot find PWM wake interrupt\n");
+ goto error_pclk;
+ }
+
+ gpio_dev->pwm_wake_irq = pwm_wake_irq;
+ ret = enable_irq_wake(pwm_wake_irq);
+ if (ret) {
+ dev_err(dev, "could not enable IRQ wakeup\n");
+ }
+
+ ret = of_property_read_u32(np, "pwm-id", &gpio_dev->pwm_id);
+ if (ret) {
+ dev_err(dev, "missing pwm-id property\n");
+ goto error_pclk;
+ }
+
+ if (gpio_dev->pwm_id > 3) {
+ dev_err(dev, "invalid pwm-id property\n");
+ goto error_pclk;
+ }
+
+ gpio_dev->use_shutdown_handler = of_property_read_bool(np, "shutdown-is-virtual-poweroff");
+ gpio_dev->use_suspend_handler = of_property_read_bool(np, "suspend-is-virtual-poweroff");
+
+ gpio_dev->pinctrl = devm_pinctrl_get(dev);
+ if (IS_ERR(gpio_dev->pinctrl)) {
+ dev_err(dev, "Unable to get pinctrl\n");
+ goto error_pclk;
+ }
+
+ gpio_dev->pinctrl_state_default = pinctrl_lookup_state(gpio_dev->pinctrl, "default");
+ if (IS_ERR(gpio_dev->pinctrl_state_default)) {
+ dev_err(dev, "Unable to get default pinctrl state\n");
+ goto error_pclk;
+ }
+
+ gpio_dev->pinctrl_state_suspend = pinctrl_lookup_state(gpio_dev->pinctrl, "suspend");
+ if (IS_ERR(gpio_dev->pinctrl_state_suspend)) {
+ dev_err(dev, "Unable to get suspend pinctrl state\n");
+ goto error_pclk;
+ }
+
+ platform_set_drvdata(pdev, gpio_dev);
+
+ ret = devm_request_irq(dev, gpio_dev->irq, rockchip_ir_recv_irq,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "gpio-ir-recv-irq", gpio_dev);
+ if (ret) {
+ dev_err(dev, "Can't request GPIO interrupt\n");
+ goto error_pclk;
+ }
+
+ if (gpio_dev->use_shutdown_handler) {
+
+ ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_POWER_OFF,
+ SYS_OFF_PRIO_FIRMWARE, rockchip_ir_recv_sys_off, NULL);
+
+ if (ret)
+ dev_err(dev, "could not register sys_off handler\n");
+
+ }
+
+ ret = rockchip_ir_recv_init_sip();
+ if (!ret) {
+ dev_err(dev, "Unable to initialize Rockchip SIP v2, virtual poweroff unavailable\n");
+ gpio_dev->use_shutdown_handler = false;
+ gpio_dev->use_suspend_handler = false;
+ } else {
+ dev_info(dev, "rockchip SIP initialized, version 0x%x\n", ret);
+ }
+
+ return 0;
+
+error_pclk:
+ clk_unprepare(p_clk);
+error_clk:
+ clk_unprepare(clk);
+
+ return -ENODEV;
+
+}
+
+static const struct dev_pm_ops rockchip_ir_recv_pm_ops = {
+ .suspend = rockchip_ir_recv_suspend,
+ .resume = rockchip_ir_recv_resume,
+};
+#endif
+
+static const struct of_device_id rockchip_ir_recv_of_match[] = {
+ { .compatible = "rockchip-ir-receiver", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, rockchip_ir_recv_of_match);
+
+static struct platform_driver rockchip_ir_recv_driver = {
+ .probe = rockchip_ir_recv_probe,
+ .remove = rockchip_ir_recv_remove,
+ .shutdown = rockchip_ir_recv_shutdown,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = of_match_ptr(rockchip_ir_recv_of_match),
+#ifdef CONFIG_PM
+ .pm = &rockchip_ir_recv_pm_ops,
+#endif
+ },
+};
+module_platform_driver(rockchip_ir_recv_driver);
+
+MODULE_DESCRIPTION("Rockchip IR Receiver driver");
+MODULE_LICENSE("GPL v2");

782
patch/kernel/archive/rockchip-6.7/patches.armbian/general-rockchip-various-fixes.patch
View File

@@ -1,782 +0,0 @@
From 92a42b2df843c0f6c2937dc6bdbfe72332c9e557 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 9 Sep 2021 16:46:33 +0000
Subject: [PATCH 3/4] 01-linux-1000-rockchip-wip
---
arch/arm/boot/dts/rockchip/rk322x.dtsi | 101 +++++++++++++++++-
arch/arm/boot/dts/rockchip/rk3xxx.dtsi | 2 +
drivers/clk/rockchip/clk-rk3228.c | 61 ++++-------
drivers/net/ethernet/arc/emac.h | 14 +++
drivers/net/ethernet/arc/emac_main.c | 81 ++++++++++++--
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 38 ++++++-
drivers/pmdomain/rockchip/pm-domains.c | 23 ++++
drivers/usb/dwc2/core.c | 2 +-
8 files changed, 266 insertions(+), 56 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
index 75af99c76..c50b2ccd7 100644
--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
@@ -15,6 +15,7 @@ / {
interrupt-parent = <&gic>;
aliases {
+ ethernet0 = &gmac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -105,6 +106,22 @@ arm-pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "hdmi-sound";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -132,6 +149,17 @@ display_subsystem: display-subsystem {
ports = <&vop_out>;
};
+ crypto: cypto-controller@100a0000 {
+ compatible = "rockchip,rk3288-crypto";
+ reg = <0x100a0000 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_M_CRYPTO>, <&cru HCLK_S_CRYPTO>,
+ <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC>;
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ };
+
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
@@ -142,6 +170,7 @@ i2s1: i2s1@100b0000 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -153,6 +182,7 @@ i2s0: i2s0@100c0000 {
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -166,6 +196,7 @@ spdif: spdif@100d0000 {
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -337,7 +368,7 @@ uart2: serial@11030000 {
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
+ pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -358,6 +389,10 @@ efuse_id: id@7 {
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
+ hdmi_phy_flag: hdmi-phy-flag@1d {
+ reg = <0x1d 0x1>;
+ bits = <1 1>;
+ };
};
i2c0: i2c@11050000 {
@@ -554,6 +589,11 @@ map1 {
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ map2 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
};
};
};
@@ -584,6 +624,8 @@ hdmi_phy: hdmi-phy@12030000 {
clock-names = "sysclk", "refoclk", "refpclk";
#clock-cells = <0>;
clock-output-names = "hdmiphy_phy";
+ nvmem-cells = <&hdmi_phy_flag>;
+ nvmem-cell-names = "hdmi-phy-flag";
#phy-cells = <0>;
status = "disabled";
};
@@ -607,7 +649,27 @@ gpu: gpu@20000000 {
clock-names = "bus", "core";
power-domains = <&power RK3228_PD_GPU>;
resets = <&cru SRST_GPU_A>;
- status = "disabled";
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ };
};
vpu: video-codec@20020000 {
@@ -727,6 +789,7 @@ hdmi: hdmi@200a0000 {
phys = <&hdmi_phy>;
phy-names = "hdmi";
rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
@@ -748,9 +811,13 @@ sdmmc: mmc@30000000 {
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_pwr>;
+ resets = <&cru SRST_SDMMC>;
+ reset-names = "reset";
status = "disabled";
};
@@ -760,10 +827,14 @@ sdio: mmc@30010000 {
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ bus-width = <4>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -771,14 +842,13 @@ emmc: mmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
rockchip,default-sample-phase = <158>;
fifo-depth = <0x100>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
@@ -1029,6 +1099,10 @@ sdmmc_bus4: sdmmc-bus4 {
<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
};
+
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
sdio {
@@ -1261,13 +1335,30 @@ uart1_xfer: uart1-xfer {
<1 RK_PB2 1 &pcfg_pull_none>;
};
+ uart11_xfer: uart11-xfer {
+ rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
};
+ uart11_cts: uart11-cts {
+ rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
+ };
+
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
};
+
+ uart11_rts: uart11-rts {
+ rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ uart11_rts_gpio: uart11-rts-gpio {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
uart2 {
diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
index 616a828e0..f233b7a77 100644
--- a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
@@ -64,6 +64,8 @@ L2: cache-controller@10138000 {
reg = <0x10138000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
};
scu@1013c000 {
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index aca1a483a..7250adc64 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -135,24 +135,22 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
-PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
+PNAME(mux_ddrphy_p) = { "dpll", "gpll", "apll" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
-PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
-PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
-PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
+PNAME(mux_sclk_vop_src_p) = { "gpll", "cpll" };
PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
@@ -221,27 +219,23 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
/* PD_DDR */
- GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
+ COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+ RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
- GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
- GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
- COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+ GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(7), 1, GFLAGS),
- GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
+ FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
RK2928_CLKGATE_CON(8), 5, GFLAGS),
- FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
+ FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
RK2928_CLKGATE_CON(7), 0, GFLAGS),
/* PD_CORE */
- GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
+ RK2928_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(4), 1, GFLAGS),
@@ -258,14 +252,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_MISC_CON, 15, 1, MFLAGS),
/* PD_BUS */
- GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
+ COMPOSITE(0, "aclk_cpu_src", mux_pll_src_3plls_p, 0,
+ RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(0), 1, GFLAGS),
- GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(0), 1, GFLAGS),
- GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(0), 1, GFLAGS),
- COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
- RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
@@ -338,14 +327,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(3), 8, GFLAGS),
/* PD_PERI */
- GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(2), 0, GFLAGS),
- GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
+ COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
+ RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
- GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
- RK2928_CLKGATE_CON(2), 0, GFLAGS),
- COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
- RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
RK2928_CLKGATE_CON(5), 2, GFLAGS),
@@ -380,7 +364,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
- RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
+ RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
@@ -403,12 +387,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
* Clock-Architecture Diagram 2
*/
- GATE(0, "gpll_vop", "gpll", 0,
- RK2928_CLKGATE_CON(3), 1, GFLAGS),
- GATE(0, "cpll_vop", "cpll", 0,
+ COMPOSITE_NODIV(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
+ RK2928_CLKSEL_CON(27), 0, 1, MFLAGS,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
- MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
- RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
@@ -640,13 +621,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
/* PD_MMC */
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
- MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
- MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
- MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
};
static const char *const rk3228_critical_clocks[] __initconst = {
@@ -661,6 +642,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
"aclk_vop_noc",
"aclk_hdcp_noc",
"hclk_vio_ahb_arbi",
+ "hclk_vio_h2p",
"hclk_vio_noc",
"hclk_vop_noc",
"hclk_host0_arb",
@@ -678,10 +660,13 @@ static const char *const rk3228_critical_clocks[] __initconst = {
"pclk_ddrphy",
"pclk_acodecphy",
"pclk_phy_noc",
+ "pclk_vio_h2p",
"aclk_vpu_noc",
"aclk_rkvdec_noc",
+ "aclk_rkvdec",
"hclk_vpu_noc",
"hclk_rkvdec_noc",
+ "hclk_rkvdec",
};
static void __init rk3228_clk_init(struct device_node *np)
diff --git a/drivers/net/ethernet/arc/emac.h b/drivers/net/ethernet/arc/emac.h
index d820ae03a..0ac87288b 100644
--- a/drivers/net/ethernet/arc/emac.h
+++ b/drivers/net/ethernet/arc/emac.h
@@ -91,6 +91,20 @@ struct arc_emac_bd {
#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
+/* PHY fixups */
+#define RTL_8201F_PHY_ID 0x001cc816
+
+#define RTL_8201F_PG_SELECT_REG 0x1f
+#define RTL_8201F_PG4_EEE_REG 0x10
+#define RTL_8201F_PG4_EEE_RX_QUIET_EN BIT(8)
+#define RTL_8201F_PG4_EEE_TX_QUIET_EN BIT(9)
+#define RTL_8201F_PG4_EEE_NWAY_EN BIT(12)
+#define RTL_8201F_PG4_EEE_10M_CAP BIT(13)
+#define RTL_8201F_PG7_RMSR_REG 0x10
+#define RTL_8201F_PG7_RMSR_CLK_DIR_IN BIT(12)
+#define RTL_8201F_PG0_PSMR_REG 0x18
+#define RTL_8201F_PG0_PSMR_PWRSVE_EN BIT(15)
+
/**
* struct buffer_state - Stores Rx/Tx buffer state.
* @sk_buff: Pointer to socket buffer.
diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c
index 67b8113a2..40332a976 100644
--- a/drivers/net/ethernet/arc/emac_main.c
+++ b/drivers/net/ethernet/arc/emac_main.c
@@ -140,7 +140,7 @@ static void arc_emac_tx_clean(struct net_device *ndev)
stats->tx_bytes += skb->len;
}
- dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
+ dma_unmap_single(ndev->dev.parent, dma_unmap_addr(tx_buff, addr),
dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
/* return the sk_buff to system */
@@ -223,9 +223,9 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
continue;
}
- addr = dma_map_single(&ndev->dev, (void *)skb->data,
+ addr = dma_map_single(ndev->dev.parent, (void *)skb->data,
EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
- if (dma_mapping_error(&ndev->dev, addr)) {
+ if (dma_mapping_error(ndev->dev.parent, addr)) {
if (net_ratelimit())
netdev_err(ndev, "cannot map dma buffer\n");
dev_kfree_skb(skb);
@@ -237,7 +237,7 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
}
/* unmap previosly mapped skb */
- dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
+ dma_unmap_single(ndev->dev.parent, dma_unmap_addr(rx_buff, addr),
dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
pktlen = info & LEN_MASK;
@@ -445,9 +445,9 @@ static int arc_emac_open(struct net_device *ndev)
if (unlikely(!rx_buff->skb))
return -ENOMEM;
- addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
+ addr = dma_map_single(ndev->dev.parent, (void *)rx_buff->skb->data,
EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
- if (dma_mapping_error(&ndev->dev, addr)) {
+ if (dma_mapping_error(ndev->dev.parent, addr)) {
netdev_err(ndev, "cannot dma map\n");
dev_kfree_skb(rx_buff->skb);
return -ENOMEM;
@@ -555,7 +555,7 @@ static void arc_free_tx_queue(struct net_device *ndev)
struct buffer_state *tx_buff = &priv->tx_buff[i];
if (tx_buff->skb) {
- dma_unmap_single(&ndev->dev,
+ dma_unmap_single(ndev->dev.parent,
dma_unmap_addr(tx_buff, addr),
dma_unmap_len(tx_buff, len),
DMA_TO_DEVICE);
@@ -586,7 +586,7 @@ static void arc_free_rx_queue(struct net_device *ndev)
struct buffer_state *rx_buff = &priv->rx_buff[i];
if (rx_buff->skb) {
- dma_unmap_single(&ndev->dev,
+ dma_unmap_single(ndev->dev.parent,
dma_unmap_addr(rx_buff, addr),
dma_unmap_len(rx_buff, len),
DMA_FROM_DEVICE);
@@ -692,10 +692,10 @@ static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
return NETDEV_TX_BUSY;
}
- addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
+ addr = dma_map_single(ndev->dev.parent, (void *)skb->data, len,
DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
+ if (unlikely(dma_mapping_error(ndev->dev.parent, addr))) {
stats->tx_dropped++;
stats->tx_errors++;
dev_kfree_skb_any(skb);
@@ -850,6 +850,62 @@ static const struct net_device_ops arc_emac_netdev_ops = {
#endif
};
+/**
+ * arc_emac_rtl8201f_phy_fixup
+ * @phydev: Pointer to phy_device structure.
+ *
+ * This function registers a fixup in case RTL8201F's phy
+ * clockout is used as reference for the mac interface
+ * and disable EEE, since emac can't handle it
+ */
+static int arc_emac_rtl8201f_phy_fixup(struct phy_device *phydev)
+{
+ unsigned int reg, curr_pg;
+ int err = 0;
+
+ curr_pg = phy_read(phydev, RTL_8201F_PG_SELECT_REG);
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 4);
+ if (err)
+ goto out_err;
+ mdelay(10);
+
+ /* disable EEE */
+ reg = phy_read(phydev, RTL_8201F_PG4_EEE_REG);
+ reg &= ~RTL_8201F_PG4_EEE_RX_QUIET_EN &
+ ~RTL_8201F_PG4_EEE_TX_QUIET_EN &
+ ~RTL_8201F_PG4_EEE_NWAY_EN &
+ ~RTL_8201F_PG4_EEE_10M_CAP;
+ err = phy_write(phydev, RTL_8201F_PG4_EEE_REG, reg);
+ if (err)
+ goto out_err;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 7);
+ if (err)
+ goto out_err;
+ mdelay(10);
+
+ reg = phy_read(phydev, RTL_8201F_PG7_RMSR_REG);
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 0);
+ if (err)
+ goto out_err;
+ mdelay(10);
+
+ if (!(reg & RTL_8201F_PG7_RMSR_CLK_DIR_IN)) {
+ /* disable powersave if phy's clock output is used */
+ reg = phy_read(phydev, RTL_8201F_PG0_PSMR_REG);
+ reg &= ~RTL_8201F_PG0_PSMR_PWRSVE_EN & 0xffff;
+ err = phy_write(phydev, RTL_8201F_PG0_PSMR_REG, reg);
+ }
+ }
+
+out_err:
+ phy_write(phydev, RTL_8201F_PG_SELECT_REG, curr_pg);
+ mdelay(10);
+
+ return err;
+};
+
int arc_emac_probe(struct net_device *ndev, int interface)
{
struct device *dev = ndev->dev.parent;
@@ -970,6 +1026,11 @@ int arc_emac_probe(struct net_device *ndev, int interface)
goto out_clken;
}
+ err = phy_register_fixup_for_uid(RTL_8201F_PHY_ID, 0xfffff0,
+ arc_emac_rtl8201f_phy_fixup);
+ if (err)
+ dev_warn(dev, "Cannot register PHY board fixup.\n");
+
phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
interface);
if (!phydev) {
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 1889e78e1..6209f51b3 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
struct clk *refoclk;
struct clk *refpclk;
+ /* phy_flag flag */
+ bool phy_flag;
+
/* platform data */
const struct inno_hdmi_phy_drv_data *plat_data;
int chip_version;
@@ -471,6 +474,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
static const struct post_pll_config post_pll_cfg_table[] = {
{33750000, 1, 40, 8, 1},
{33750000, 1, 80, 8, 2},
+ {33750000, 1, 10, 2, 4},
{74250000, 1, 40, 8, 1},
{74250000, 18, 80, 8, 2},
{148500000, 2, 40, 4, 3},
@@ -621,8 +625,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
return -EINVAL;
for (; cfg->tmdsclock != 0; cfg++)
- if (tmdsclock <= cfg->tmdsclock &&
- cfg->version & inno->chip_version)
+ if (((!inno->phy_flag || tmdsclock > 33750000)
+ && tmdsclock <= cfg->tmdsclock
+ && cfg->version & inno->chip_version) ||
+ (inno->phy_flag && tmdsclock <= 33750000
+ && cfg->version & 4))
break;
for (; phy_cfg->tmdsclock != 0; phy_cfg++)
@@ -1033,6 +1040,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
{
+ struct nvmem_cell *cell;
+ unsigned char *efuse_buf;
+ size_t len;
+
/*
* Use phy internal register control
* rxsense/poweron/pllpd/pdataen signal.
@@ -1047,7 +1058,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
RK3228_POST_PLL_CTRL_MANUAL);
+
inno->chip_version = 1;
+ inno->phy_flag = false;
+
+ cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
+ if (IS_ERR(cell)) {
+ if (PTR_ERR(cell) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ return 0;
+ }
+
+ efuse_buf = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(efuse_buf))
+ return 0;
+ if (len == 1)
+ inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
+ kfree(efuse_buf);
+
+ dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
return 0;
}
@@ -1147,6 +1179,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
/* try to read the chip-version */
inno->chip_version = 1;
+ inno->phy_flag = false;
+
cell = nvmem_cell_get(inno->dev, "cpu-version");
if (IS_ERR(cell)) {
if (PTR_ERR(cell) == -EPROBE_DEFER)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index fddb4022c..9583c76b4 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -73,6 +73,7 @@ struct rockchip_pm_domain {
struct regmap **qos_regmap;
u32 *qos_save_regs[MAX_QOS_REGS_NUM];
int num_clks;
+ bool is_ignore_pwr;
struct clk_bulk_data *clks;
};
@@ -361,6 +362,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
{
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ if (pd->is_ignore_pwr)
+ return 0;
+
return rockchip_pd_power(pd, true);
}
@@ -368,6 +372,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
{
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ if (pd->is_ignore_pwr)
+ return 0;
+
return rockchip_pd_power(pd, false);
}
@@ -447,6 +454,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->info = pd_info;
pd->pmu = pmu;
+ if (!pd_info->pwr_mask)
+ pd->is_ignore_pwr = true;
+
pd->num_clks = of_clk_get_parent_count(node);
if (pd->num_clks > 0) {
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
@@ -600,6 +610,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
{
struct device_node *np;
struct generic_pm_domain *child_domain, *parent_domain;
+ struct rockchip_pm_domain *child_pd, *parent_pd;
int error;
for_each_child_of_node(parent, np) {
@@ -640,6 +651,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
parent_domain->name, child_domain->name);
}
+ /*
+ * If child_pd doesn't do idle request or power on/off,
+ * parent_pd may fail to do power on/off, so if parent_pd
+ * need to power on/off, child_pd can't ignore to do idle
+ * request and power on/off.
+ */
+ child_pd = to_rockchip_pd(child_domain);
+ parent_pd = to_rockchip_pd(parent_domain);
+ if (!parent_pd->is_ignore_pwr)
+ child_pd->is_ignore_pwr = false;
+
+
rockchip_pm_add_subdomain(pmu, np);
}
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 272ae5722..cec178404 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -607,7 +607,7 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
* platforms on their host-only dwc2.
*/
if (!dwc2_hw_is_otg(hsotg))
- msleep(50);
+ msleep(200);
break;
case USB_DR_MODE_PERIPHERAL:
--
2.25.1

119
patch/kernel/archive/rockchip-6.7/patches.armbian/ir-keymap-rk322x-box.patch
View File

@@ -1,119 +0,0 @@
From f14539f8d08328ae5aad165a4deea25c7d6b09bf Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Mon, 25 Apr 2022 13:25:09 +0000
Subject: [PATCH] add generic rk322x tv box remote controller keymap
---
drivers/media/rc/keymaps/Makefile | 1 +
drivers/media/rc/keymaps/rc-rk322x-tvbox.c | 74 ++++++++++++++++++++++
include/media/rc-map.h | 1 +
3 files changed, 77 insertions(+)
create mode 100644 drivers/media/rc/keymaps/rc-rk322x-tvbox.c
diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
index 5fe5c9e1a46..1aa49b78a65 100644
--- a/drivers/media/rc/keymaps/Makefile
+++ b/drivers/media/rc/keymaps/Makefile
@@ -99,6 +99,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
rc-rc6-mce.o \
rc-real-audio-220-32-keys.o \
rc-reddo.o \
+ rc-rk322x-tvbox.o \
rc-snapstream-firefly.o \
rc-streamzap.o \
rc-tanix-tx3mini.o \
diff --git a/drivers/media/rc/keymaps/rc-rk322x-tvbox.c b/drivers/media/rc/keymaps/rc-rk322x-tvbox.c
new file mode 100644
index 00000000000..91e24ee52ee
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-rk322x-tvbox.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+// rc-rk322x-tvbox.c - Keytable for rk322x generic tv box remote controller
+//
+// keymap imported from ir-keymaps.c
+//
+// Copyright (c) 2022 Paolo Sabatino
+
+#include <media/rc-map.h>
+#include <linux/module.h>
+
+/*
+
+*/
+
+static struct rc_map_table rk322x_tvbox[] = {
+
+ { 0x40400d, KEY_ENTER },
+ { 0x40404d, KEY_POWER },
+ { 0x40401e, KEY_PREVIOUSSONG },
+ { 0x40401f, KEY_NEXTSONG },
+ { 0x404001, KEY_1 },
+ { 0x404002, KEY_2 },
+ { 0x404003, KEY_3 },
+ { 0x404004, KEY_4 },
+ { 0x404005, KEY_5 },
+ { 0x404006, KEY_6 },
+ { 0x404007, KEY_7 },
+ { 0x404008, KEY_8 },
+ { 0x404009, KEY_9 },
+ { 0x404000, KEY_0 },
+ { 0x40400c, KEY_BACKSPACE },
+ { 0x404044, KEY_F6 },
+ { 0x40401a, KEY_HOME },
+ { 0x404042, KEY_BACK },
+ { 0x404045, KEY_MENU },
+ { 0x40400f, KEY_TEXT },
+ { 0x404010, KEY_LEFT },
+ { 0x404011, KEY_RIGHT },
+ { 0x40400e, KEY_DOWN },
+ { 0x40400b, KEY_UP },
+ { 0x40401c, KEY_VOLUMEDOWN },
+ { 0x404043, KEY_MUTE },
+ { 0x404015, KEY_VOLUMEUP },
+ { 0x404053, KEY_F1 },
+ { 0x40405b, KEY_F2 },
+ { 0x404057, KEY_F3 },
+ { 0x404054, KEY_F4 },
+
+};
+
+static struct rc_map_list rk322x_tvbox_map = {
+ .map = {
+ .scan = rk322x_tvbox,
+ .size = ARRAY_SIZE(rk322x_tvbox),
+ .rc_proto = RC_PROTO_NEC, /* Legacy IR type */
+ .name = RC_MAP_RK322X_TVBOX,
+ }
+};
+
+static int __init init_rc_map_rk322x_tvbox(void)
+{
+ return rc_map_register(&rk322x_tvbox_map);
+}
+
+static void __exit exit_rc_map_rk322x_tvbox(void)
+{
+ rc_map_unregister(&rk322x_tvbox_map);
+}
+
+module_init(init_rc_map_rk322x_tvbox)
+module_exit(exit_rc_map_rk322x_tvbox)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Paolo Sabatino");
diff --git a/include/media/rc-map.h b/include/media/rc-map.h
index 793b54342df..35aba84be9f 100644
--- a/include/media/rc-map.h
+++ b/include/media/rc-map.h
@@ -310,6 +310,7 @@ struct rc_map *rc_map_get(const char *name);
#define RC_MAP_RC6_MCE "rc-rc6-mce"
#define RC_MAP_REAL_AUDIO_220_32_KEYS "rc-real-audio-220-32-keys"
#define RC_MAP_REDDO "rc-reddo"
+#define RC_MAP_RK322X_TVBOX "rc-rk322x-tvbox"
#define RC_MAP_SNAPSTREAM_FIREFLY "rc-snapstream-firefly"
#define RC_MAP_STREAMZAP "rc-streamzap"
#define RC_MAP_SU3000 "rc-su3000"
--
2.30.2

118
patch/kernel/archive/rockchip-6.7/patches.armbian/ir-keymap-xt-q8l-v10.patch
View File

@@ -1,118 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Fri, 10 Jun 2022 15:59:15 +0000
Subject: add xt-q8l-v10 keymap and makefile
---
drivers/media/rc/keymaps/Makefile | 1 +
drivers/media/rc/keymaps/rc-xt-q8l-v10.c | 76 ++++++++++
include/media/rc-map.h | 1 +
3 files changed, 78 insertions(+)
diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
index f513ff5caf4e..198ef8bc2614 100644
--- a/drivers/media/rc/keymaps/Makefile
+++ b/drivers/media/rc/keymaps/Makefile
@@ -136,4 +136,5 @@ obj-$(CONFIG_RC_MAP) += \
rc-x96max.o \
rc-xbox-360.o \
rc-xbox-dvd.o \
+ rc-xt-q8l-v10.o \
rc-zx-irdec.o
diff --git a/drivers/media/rc/keymaps/rc-xt-q8l-v10.c b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
new file mode 100644
index 000000000000..19c7d9ec8325
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+// rc-xt-q8l-v10.c - Keytable for xt-q8l-v10 tv box remote controller
+//
+// keymap imported from ir-keymaps.c
+//
+// Copyright (c) 2018 Paolo Sabatino
+
+#include <media/rc-map.h>
+#include <linux/module.h>
+
+/*
+
+*/
+
+static struct rc_map_table xt_q8l_v10[] = {
+
+ { 0xcc1d11, KEY_ENTER },
+ { 0xcc1d00, KEY_POWER },
+ { 0xcc1d15, KEY_PLAYPAUSE },
+ { 0xcc1d16, KEY_STOP },
+ { 0xcc1d06, KEY_PREVIOUSSONG },
+ { 0xcc1d0a, KEY_NEXTSONG },
+ { 0xcc1d41, KEY_1 },
+ { 0xcc1d45, KEY_2 },
+ { 0xcc1d4d, KEY_3 },
+ { 0xcc1d42, KEY_4 },
+ { 0xcc1d46, KEY_5 },
+ { 0xcc1d4e, KEY_6 },
+ { 0xcc1d43, KEY_7 },
+ { 0xcc1d47, KEY_8 },
+ { 0xcc1d4f, KEY_9 },
+ { 0xcc1d49, KEY_0 },
+ { 0xcc1d4a, KEY_BACKSPACE },
+ { 0xcc1d48, KEY_F6 },
+ { 0xcc1d03, KEY_HOME },
+ { 0xcc1d0f, KEY_BACK },
+ { 0xcc1d40, KEY_MENU },
+ { 0xcc1d4c, KEY_TEXT },
+ { 0xcc1d10, KEY_LEFT },
+ { 0xcc1d12, KEY_RIGHT },
+ { 0xcc1d44, KEY_DOWN },
+ { 0xcc1d07, KEY_UP },
+ { 0xcc1d02, KEY_VOLUMEDOWN },
+ { 0xcc1d0c, KEY_MUTE },
+ { 0xcc1d0e, KEY_VOLUMEUP },
+ { 0xcc1d01, KEY_F1 },
+ { 0xcc1d05, KEY_F2 },
+ { 0xcc1d09, KEY_F3 },
+ { 0xcc1d0d, KEY_F4 },
+
+};
+
+static struct rc_map_list xt_q8l_v10_map = {
+ .map = {
+ .scan = xt_q8l_v10,
+ .size = ARRAY_SIZE(xt_q8l_v10),
+ .rc_proto = RC_PROTO_NEC, /* Legacy IR type */
+ .name = RC_MAP_XT_Q8L_V10,
+ }
+};
+
+static int __init init_rc_map_xt_q8l_v10(void)
+{
+ return rc_map_register(&xt_q8l_v10_map);
+}
+
+static void __exit exit_rc_map_xt_q8l_v10(void)
+{
+ rc_map_unregister(&xt_q8l_v10_map);
+}
+
+module_init(init_rc_map_xt_q8l_v10)
+module_exit(exit_rc_map_xt_q8l_v10)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Paolo Sabatino");
diff --git a/include/media/rc-map.h b/include/media/rc-map.h
index 793b54342dff..ef7f3710eafe 100644
--- a/include/media/rc-map.h
+++ b/include/media/rc-map.h
@@ -343,6 +343,7 @@ struct rc_map *rc_map_get(const char *name);
#define RC_MAP_X96MAX "rc-x96max"
#define RC_MAP_XBOX_360 "rc-xbox-360"
#define RC_MAP_XBOX_DVD "rc-xbox-dvd"
+#define RC_MAP_XT_Q8L_V10 "rc-xt-q8l-v10"
#define RC_MAP_ZX_IRDEC "rc-zx-irdec"
/*
--
Armbian

20
patch/kernel/archive/rockchip-6.7/patches.armbian/misc-tinkerboard-spi-interface.patch
View File

@@ -1,20 +0,0 @@
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 5a038c667401..5dd1acf7f12a 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -713,6 +713,7 @@ static const struct spi_device_id spidev_spi_ids[] = {
{ .name = "spi-authenta" },
{ .name = "em3581" },
{ .name = "si3210" },
+ { .name = "spi_tinker" },
{},
};
MODULE_DEVICE_TABLE(spi, spidev_spi_ids);
@@ -741,6 +742,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "semtech,sx1301", .data = &spidev_of_check },
{ .compatible = "silabs,em3581", .data = &spidev_of_check },
{ .compatible = "silabs,si3210", .data = &spidev_of_check },
+ { .compatible = "rockchip,spi_tinker", .data = &spidev_of_check },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);

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