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update rk3588-edge to v6.5-rc1

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This commit is contained in:
Muhammed Efe Cetin
2023-07-11 19:15:39 +03:00
committed by Igor
parent 8ffdf8c55c
commit 9a0908f9ba
16 changed files with 207 additions and 7918 deletions
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91
config/kernel/linux-rockchip-rk3588-edge.config
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@@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.4.1 Kernel Configuration
# Linux/arm64 6.5.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0"
CONFIG_CC_IS_GCC=y
@@ -254,6 +254,7 @@ CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_CACHESTAT_SYSCALL=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
@@ -320,6 +321,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
@@ -327,6 +329,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
@@ -346,6 +349,7 @@ CONFIG_ARCH_ROCKCHIP=y
#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
@@ -502,7 +506,6 @@ CONFIG_ARM64_EPAN=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_SME=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
@@ -599,6 +602,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
# CONFIG_ARM_SCMI_CPUFREQ is not set
# end of CPU Frequency scaling
@@ -623,7 +627,6 @@ CONFIG_ACPI_FAN=m
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=m
CONFIG_ACPI_HOTPLUG_CPU=y
@@ -690,6 +693,8 @@ CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_HAVE_IMA_KEXEC=y
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
@@ -719,6 +724,8 @@ CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
@@ -927,6 +934,7 @@ CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
@@ -947,7 +955,7 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8
#
# SLAB allocator options
#
# CONFIG_SLAB is not set
# CONFIG_SLAB_DEPRECATED is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
@@ -2122,6 +2130,7 @@ CONFIG_CXL_PORT=m
CONFIG_CXL_SUSPEND=y
CONFIG_CXL_REGION=y
# CONFIG_CXL_REGION_INVALIDATION_TEST is not set
CONFIG_CXL_PMU=m
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set
@@ -3413,6 +3422,7 @@ CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB=m
CONFIG_CAN_ETAS_ES58X=m
# CONFIG_CAN_F81604 is not set
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
@@ -3438,6 +3448,7 @@ CONFIG_MDIO_MSCC_MIIM=m
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
CONFIG_MDIO_IPQ8064=m
CONFIG_MDIO_REGMAP=m
CONFIG_MDIO_THUNDER=y
#
@@ -3452,8 +3463,8 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_LYNX=m
CONFIG_PCS_MTK_LYNXI=m
CONFIG_PCS_ALTERA_TSE=m
# end of PCS device drivers
CONFIG_PPP=m
@@ -3464,6 +3475,11 @@ CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
@@ -3811,6 +3827,7 @@ CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852C=m
# CONFIG_RTW89_8851BE is not set
CONFIG_RTW89_8852AE=m
# CONFIG_RTW89_8852BE is not set
CONFIG_RTW89_8852CE=m
@@ -3839,8 +3856,6 @@ CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_RTL8723DU=m
CONFIG_RTL8723DS=m
CONFIG_RTL8822BU=m
CONFIG_RTL8821CU=m
CONFIG_88XXAU=m
CONFIG_RTL8192EU=m
CONFIG_RTL8189FS=m
@@ -3921,6 +3936,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_KUNIT_TEST is not set
#
# Input Device Drivers
@@ -4076,7 +4092,6 @@ CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
@@ -4847,6 +4862,7 @@ CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX31760=m
# CONFIG_MAX31827 is not set
CONFIG_SENSORS_MAX6620=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
@@ -5013,6 +5029,7 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
@@ -5046,6 +5063,7 @@ CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
CONFIG_WDAT_WDT=m
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_ARM_SBSA_WATCHDOG=y
@@ -5110,7 +5128,7 @@ CONFIG_MFD_CORE=y
# CONFIG_MFD_AXP20X_I2C is not set
CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX597X is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
@@ -5134,6 +5152,7 @@ CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
@@ -5191,6 +5210,8 @@ CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
@@ -5272,6 +5293,7 @@ CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
@@ -5292,6 +5314,7 @@ CONFIG_REGULATOR_SY8824X=m
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
@@ -5497,7 +5520,6 @@ CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m
#
@@ -5861,6 +5883,7 @@ CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
# CONFIG_VIDEO_OG01A1B is not set
# CONFIG_VIDEO_OV01A10 is not set
CONFIG_VIDEO_OV02A10=m
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
@@ -6384,6 +6407,7 @@ CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
@@ -6518,6 +6542,8 @@ CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SYS_HELPERS=y
CONFIG_FB_SYS_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
@@ -6656,6 +6682,7 @@ CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_MIDI_EMUL=m
CONFIG_SND_SEQ_VIRMIDI=m
# CONFIG_SND_SEQ_UMP is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_OPL3_LIB=m
CONFIG_SND_OPL3_LIB_SEQ=m
@@ -6664,6 +6691,7 @@ CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
@@ -6787,6 +6815,7 @@ CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
@@ -6841,6 +6870,7 @@ CONFIG_SND_SOC_FSL_RPMSG=m
CONFIG_SND_SOC_IMX_AUDMUX=m
# end of SoC Audio for Freescale CPUs
# CONFIG_SND_SOC_CHV3_I2S is not set
CONFIG_SND_I2S_HI6210_I2S=m
CONFIG_SND_SOC_IMG=y
CONFIG_SND_SOC_IMG_I2S_IN=m
@@ -6909,6 +6939,7 @@ CONFIG_SND_SOC_AW8738=m
# CONFIG_SND_SOC_AW88395 is not set
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
# CONFIG_SND_SOC_CHV3_CODEC is not set
CONFIG_SND_SOC_CROS_EC_CODEC=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
@@ -6974,6 +7005,7 @@ CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98373_SDW=m
# CONFIG_SND_SOC_MAX98388 is not set
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9860=m
@@ -7022,6 +7054,7 @@ CONFIG_SND_SOC_RT711_SDW=m
CONFIG_SND_SOC_RT711_SDCA_SDW=m
# CONFIG_SND_SOC_RT712_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set
# CONFIG_SND_SOC_RT722_SDCA_SDW is not set
CONFIG_SND_SOC_RT715=m
CONFIG_SND_SOC_RT715_SDW=m
CONFIG_SND_SOC_RT715_SDCA_SDW=m
@@ -7042,6 +7075,7 @@ CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
# CONFIG_SND_SOC_SSM3515 is not set
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
@@ -7051,6 +7085,7 @@ CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
# CONFIG_SND_SOC_TAS2781_I2C is not set
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
@@ -7109,6 +7144,7 @@ CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_WSA883X=m
# CONFIG_SND_SOC_WSA884X is not set
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MT6351=m
@@ -7223,6 +7259,7 @@ CONFIG_HID_NINTENDO=m
# CONFIG_NINTENDO_FF is not set
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
# CONFIG_HID_NVIDIA_SHIELD is not set
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
@@ -7274,6 +7311,7 @@ CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# CONFIG_HID_KUNIT_TEST is not set
# end of Special HID drivers
#
@@ -7591,6 +7629,7 @@ CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_MAX3420_UDC=m
# CONFIG_USB_CDNS2_UDC is not set
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller
@@ -7698,6 +7737,7 @@ CONFIG_TYPEC_WUSB3801=m
CONFIG_TYPEC_MUX_FSA4480=m
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
CONFIG_TYPEC_MUX_PI3USB30532=m
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support
#
@@ -7781,6 +7821,7 @@ CONFIG_LEDS_CLASS_FLASH=m
# LED drivers
#
CONFIG_LEDS_AN30259A=m
# CONFIG_LEDS_AW200XX is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
@@ -8066,13 +8107,25 @@ CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=y
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_VIRQFD=y
#
# VFIO support for PCI devices
#
CONFIG_VFIO_PCI_CORE=y
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=y
CONFIG_MLX5_VFIO_PCI=m
# CONFIG_HISI_ACC_VFIO_PCI is not set
# end of VFIO support for PCI devices
#
# VFIO support for platform devices
#
# CONFIG_VFIO_PLATFORM is not set
# CONFIG_VFIO_AMBA is not set
# end of VFIO support for platform devices
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
CONFIG_NITRO_ENCLAVES=m
@@ -8946,6 +8999,7 @@ CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27008 is not set
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
CONFIG_LTR501=m
@@ -8955,6 +9009,7 @@ CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
@@ -9047,6 +9102,7 @@ CONFIG_MCP4018=m
# CONFIG_MCP4531 is not set
CONFIG_MCP41010=m
# CONFIG_TPL0102 is not set
# CONFIG_X9250 is not set
# end of Digital potentiometers
#
@@ -9071,6 +9127,7 @@ CONFIG_ICP10100=m
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
@@ -9747,7 +9804,6 @@ CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=0
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
# CONFIG_STATIC_USERMODEHELPER is not set
@@ -9862,6 +9918,7 @@ CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
@@ -9954,6 +10011,7 @@ CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
@@ -9974,7 +10032,7 @@ CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=m
CONFIG_CRYPTO_SM3_GENERIC=m
CONFIG_CRYPTO_STREEBOG=m
@@ -10014,6 +10072,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
CONFIG_CRYPTO_KDF800108_CTR=y
# end of Random number generation
@@ -10228,6 +10287,7 @@ CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
@@ -10238,6 +10298,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
@@ -10427,8 +10488,11 @@ CONFIG_HAVE_ARCH_KFENCE=y
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
CONFIG_TEST_LOCKUP=m
# end of Debug Oops, Lockups and Hangs
@@ -10502,6 +10566,7 @@ CONFIG_RCU_TRACE=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
@@ -10612,6 +10677,7 @@ CONFIG_TEST_BLACKHOLE_DEV=m
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_BITFIELD_KUNIT is not set
# CONFIG_CHECKSUM_KUNIT is not set
# CONFIG_HASH_KUNIT_TEST is not set
CONFIG_RESOURCE_KUNIT_TEST=m
# CONFIG_SYSCTL_KUNIT_TEST is not set
@@ -10628,6 +10694,7 @@ CONFIG_MEMCPY_SLOW_KUNIT_TEST=y
# CONFIG_OVERFLOW_KUNIT_TEST is not set
# CONFIG_STACKINIT_KUNIT_TEST is not set
# CONFIG_FORTIFY_KUNIT_TEST is not set
# CONFIG_STRCAT_KUNIT_TEST is not set
# CONFIG_STRSCPY_KUNIT_TEST is not set
# CONFIG_SIPHASH_KUNIT_TEST is not set
# CONFIG_TEST_UDELAY is not set

4
config/sources/families/rockchip-rk3588.conf
View File

@@ -33,8 +33,8 @@ case $BRANCH in
SKIP_BOOTSPLASH="yes"
LINUXFAMILY=rockchip-rk3588
LINUXCONFIG='linux-rockchip-rk3588-'$BRANCH
KERNEL_MAJOR_MINOR="6.4" # Major and minor versions of this kernel.
KERNELBRANCH='branch:linux-6.4.y'
KERNEL_MAJOR_MINOR="6.5" # Major and minor versions of this kernel.
KERNELBRANCH='tag:v6.5-rc1'
KERNELPATCHDIR='rockchip-rk3588-edge'
;;

4362
patch/kernel/rockchip-rk3588-edge/0010-Introduce-RK806-Support.patch
View File

File diff suppressed because it is too large Load Diff

48
patch/kernel/rockchip-rk3588-edge/0011-arm64-dts-rockchip-rk3588-add-GIC-ITS-support.patch
View File

@@ -1,48 +0,0 @@
From 9572f9567627c5e80bf77248242ef2e5c90da600 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 18 Apr 2023 16:21:09 +0200
Subject: [PATCH 1/1] arm64: dts: rockchip: rk3588: add GIC ITS support
Add the two Interrupt Translation Service (ITS) IPs that are part of the
GIC-600. They are mainly required for PCIe Message Signalled Interrupts
(MSI).
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index b46574358dd1..05af9a0fddf4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1688,7 +1688,24 @@ gic: interrupt-controller@fe600000 {
mbi-alias = <0x0 0xfe610000>;
mbi-ranges = <424 56>;
msi-controller;
+ ranges;
+ #address-cells = <2>;
#interrupt-cells = <4>;
+ #size-cells = <2>;
+
+ its0: msi-controller@fe640000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfe640000 0x0 0x20000>;
+ };
+
+ its1: msi-controller@fe660000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfe660000 0x0 0x20000>;
+ };
ppi-partitions {
ppi_partition0: interrupt-partition-0 {
--
2.41.0

114
patch/kernel/rockchip-rk3588-edge/0029-RK3588-Add-Cpufreq-Support.patch → patch/kernel/rockchip-rk3588-edge/0014-RK3588-Add-Cpufreq-Support.patch
View File

@@ -1,4 +1,4 @@
From cd27d0c81ffbcbff5a06c50ebf7cddf36bc02157 Mon Sep 17 00:00:00 2001
From 292ab6078d7cbb8526e063f48ea6c2d7f1a72c8c Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 18 Aug 2022 14:21:30 +0200
Subject: [PATCH 1/2] cpufreq: rockchip: Introduce driver for rk3588
@@ -14,7 +14,6 @@ for the big CPU cores to avoid a system hang when firmware tries
to bring them up at reboot time.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
---
drivers/cpufreq/Kconfig.arm | 10 +
drivers/cpufreq/Makefile | 1 +
@@ -57,10 +56,10 @@ index ef8510774913..c3f8c9cd563f 100644
obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 338cf6cc6596..64cdc6496360 100644
index e2b20080de3a..7bc19a59be26 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -156,6 +156,8 @@ static const struct of_device_id blocklist[] __initconst = {
@@ -159,6 +159,8 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "qcom,sm8250", },
{ .compatible = "qcom,sm8350", },
@@ -719,29 +718,36 @@ index 000000000000..6a60ec05d652
2.41.0
From 5bcd240ccd436a8538d2e4c0f57773d59f632aeb Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Wed, 5 Jul 2023 00:42:45 +0300
From 61d65d90be91c8ffe8b50145ba48a330258a7067 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 4 Apr 2023 17:30:46 +0200
Subject: [PATCH 2/2] arm64: dts: rockchip: rk3588: add cpu frequency scaling
support
Add required bits for CPU frequency scaling to the Rockchip 3588
devicetree. This is missing the 2.4 GHz operating point for the
big cpu clusters, since that does not work well on all SoCs.
Downstream has a driver for PVTM, which reduces the requested
frequencies based on (among other things) silicon quality.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 500 ++++++++++++++++++++++
1 file changed, 500 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 452 ++++++++++++++++++++++
1 file changed, 452 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index d6dda0e6a5d0..3a9ac4b5cd04 100644
index 1576f9bfd6de..1eb5a4add04b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -10,6 +10,7 @@
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3588s", "rockchip,rk3588";
@@ -18,6 +19,263 @@ / {
compatible = "rockchip,rk3588";
@@ -16,6 +17,215 @@ / {
#address-cells = <2>;
#size-cells = <2>;
@@ -875,30 +881,6 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
+ <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2256000000 {
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
@@ -976,36 +958,12 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
+ <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2256000000 {
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -64,6 +322,7 @@ cpu_l0: cpu@0 {
@@ -62,6 +272,7 @@ cpu_l0: cpu@0 {
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
@@ -1013,7 +971,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -83,6 +342,7 @@ cpu_l1: cpu@100 {
@@ -81,6 +292,7 @@ cpu_l1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -1021,7 +979,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -102,6 +362,7 @@ cpu_l2: cpu@200 {
@@ -100,6 +312,7 @@ cpu_l2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -1029,7 +987,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -121,6 +382,7 @@ cpu_l3: cpu@300 {
@@ -119,6 +332,7 @@ cpu_l3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
@@ -1037,7 +995,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -142,6 +404,7 @@ cpu_b0: cpu@400 {
@@ -140,6 +354,7 @@ cpu_b0: cpu@400 {
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
@@ -1045,7 +1003,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -161,6 +424,7 @@ cpu_b1: cpu@500 {
@@ -159,6 +374,7 @@ cpu_b1: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
@@ -1053,7 +1011,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -182,6 +446,7 @@ cpu_b2: cpu@600 {
@@ -180,6 +396,7 @@ cpu_b2: cpu@600 {
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
@@ -1061,7 +1019,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -201,6 +466,7 @@ cpu_b3: cpu@700 {
@@ -199,6 +416,7 @@ cpu_b3: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
@@ -1069,7 +1027,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -362,6 +628,230 @@ spll: clock-0 {
@@ -360,6 +578,230 @@ spll: clock-0 {
#clock-cells = <0>;
};
@@ -1300,11 +1258,10 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -506,6 +996,16 @@ sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
@@ -402,6 +844,16 @@ sys_grf: syscon@fd58c000 {
reg = <0x0 0xfd58c000 0x0 0x1000>;
};
+
+ bigcore0_grf: syscon@fd590000 {
+ compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
+ reg = <0x0 0xfd590000 0x0 0x100>;
@@ -1314,9 +1271,10 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644
+ compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
+ reg = <0x0 0xfd592000 0x0 0x100>;
+ };
usb2phy0_grf: syscon@fd5d0000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
--
2.41.0

266
patch/kernel/rockchip-rk3588-edge/0014-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch
View File

@@ -1,266 +0,0 @@
From 9d842dbd76192184bd91f4a7abf57edc17ed5181 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Mon, 3 Apr 2023 21:32:50 +0200
Subject: [PATCH 1/1] soc: rockchip: power-domain: add rk3588 mem module
support
On RK3588 it's also possible to power down the memory used by the
particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
support for this feature.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
1 file changed, 125 insertions(+), 35 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 84bc022f9e5b..e3de49e671dc 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -43,8 +43,10 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
+ int mem_status_mask;
int repair_status_mask;
u32 pwr_offset;
+ u32 mem_offset;
u32 req_offset;
};
@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
+ u32 mem_pwr_offset;
+ u32 chain_status_offset;
+ u32 mem_status_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
@@ -119,13 +124,15 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
+ .mem_offset = m_offset, \
+ .mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
}
EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
return !(val & pd->info->status_mask);
}
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b0: power on, 1'b1: power off */
+ return !(val & pd->info->mem_status_mask);
+}
+
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b1: power on, 1'b0: power off */
+ return val & pd->info->mem_status_mask;
+}
+
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ struct generic_pm_domain *genpd = &pd->genpd;
+ bool is_on;
+ int ret = 0;
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get chain status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ udelay(20);
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ (pd->info->pwr_mask | pd->info->pwr_w_mask));
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == false, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=0, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ pd->info->pwr_w_mask);
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ }
+
+error:
+ return ret;
+}
+
static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
bool on)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = pd->info->pwr_offset;
- bool is_on;
+ bool is_on, is_mem_on = false;
if (pd->info->pwr_mask == 0)
return;
- else if (pd->info->pwr_w_mask)
+
+ if (on && pd->info->mem_status_mask)
+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
+
+ if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
wmb();
+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
+ return;
+
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000)) {
dev_err(pmu->dev,
@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
+ pm_genpd_init(&pd->genpd, NULL,
+ !rockchip_pmu_domain_is_on(pd) ||
+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
+ .mem_pwr_offset = 0x1a0,
+ .chain_status_offset = 0x1f0,
+ .mem_status_offset = 0x1f8,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
--
2.41.0

34
patch/kernel/rockchip-rk3588-edge/0015-arm64-dts-rockchip-Add-rk3588-timer.patch
View File

@@ -1,34 +0,0 @@
From 63cae5a6a417199ccc1965ceb1e1915a0b3c3e10 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 19 Apr 2023 21:13:09 +0300
Subject: [PATCH 1/1] arm64: dts: rockchip: Add rk3588 timer
Add DT node for Rockchip RK3588/RK3588S SoC timer.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 05af9a0fddf4..96fb3a6e0c68 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1805,6 +1805,14 @@ i2c5: i2c@fead0000 {
status = "disabled";
};
+ timer0: timer@feae0000 {
+ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xfeae0000 0x0 0x20>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
wdt: watchdog@feaf0000 {
compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
reg = <0x0 0xfeaf0000 0x0 0x100>;
--
2.41.0

172
patch/kernel/rockchip-rk3588-edge/0025-Add-RK3588-USB2-Support.patch → patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-USB2-Support.patch
View File

@@ -1,129 +1,7 @@
From 0900696b9f56a0ec692d22eff3ad84bce7988f1a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 30 Mar 2023 16:31:18 +0200
Subject: [PATCH 01/11] dt-bindings: usb: Add RK3588 OHCI
Add compatible for RK3588 OHCI. As far as I know it's fully
compatible with generic-ohci.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../devicetree/bindings/usb/generic-ohci.yaml | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index d06d1e7d8876..be268e23ca79 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -44,6 +44,7 @@ properties:
- hpe,gxp-ohci
- ibm,476gtr-ohci
- ingenic,jz4740-ohci
+ - rockchip,rk3588-ohci
- snps,hsdk-v1.0-ohci
- const: generic-ohci
- enum:
@@ -69,7 +70,7 @@ properties:
clocks:
minItems: 1
- maxItems: 3
+ maxItems: 4
description: |
In case the Renesas R-Car Gen3 SoCs:
- if a host only channel: first clock should be host.
@@ -147,6 +148,20 @@ allOf:
then:
properties:
transceiver: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3588-ohci
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 3
unevaluatedProperties: false
--
2.41.0
From 924974cf321fc4efadd8da84603b97bf80cbbeb2 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 4 Apr 2023 15:32:54 +0200
Subject: [PATCH 02/11] dt-bindings: usb: Add RK3588 EHCI
Add compatible for RK3588 EHCI. As far as I know it's fully
compatible with generic-ehci.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 9445764bd8de..b956bb5fada7 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -61,6 +61,7 @@ properties:
- ibm,476gtr-ehci
- nxp,lpc1850-ehci
- qca,ar7100-ehci
+ - rockchip,rk3588-ehci
- snps,hsdk-v1.0-ehci
- socionext,uniphier-ehci
- const: generic-ehci
--
2.41.0
From 1c5f2868b5fa9d48586f3e606baae4200516fd59 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 29 Mar 2023 18:54:49 +0200
Subject: [PATCH 03/11] usb: host: ohci-platform: increase max clock number to
4
Rockchip RK3588 OHCI requires 4 clocks to be enabled.
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/usb/host/ohci-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
index a84305091c43..dec38a845cff 100644
--- a/drivers/usb/host/ohci-platform.c
+++ b/drivers/usb/host/ohci-platform.c
@@ -33,7 +33,7 @@
#include "ohci.h"
#define DRIVER_DESC "OHCI generic platform driver"
-#define OHCI_MAX_CLKS 3
+#define OHCI_MAX_CLKS 4
#define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
struct ohci_platform_priv {
--
2.41.0
From bf550631e2c027488074d56b63dca6d2837418e1 Mon Sep 17 00:00:00 2001
From a4a5f99f91beeeeb641ab3d8e49bd4d318e8d473 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 30 Mar 2023 16:25:20 +0200
Subject: [PATCH 04/11] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588
Subject: [PATCH 1/8] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588
Add compatible for the USB2 phy in the Rockchip RK3588 SoC.
@@ -189,10 +67,10 @@ index 0d6b8c28be07..5254413137c6 100644
2.41.0
From 8c33eb76698b4d6648e9ae51eb3160baa108c761 Mon Sep 17 00:00:00 2001
From e93bbbd346ba4f70ff394c56b1d9f58fddb60b9a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 12 Jan 2023 19:15:52 +0100
Subject: [PATCH 05/11] phy: phy-rockchip-inno-usb2: add rk3588 support
Subject: [PATCH 2/8] phy: phy-rockchip-inno-usb2: add rk3588 support
Add basic support for the USB2 PHY found in the Rockchip RK3588.
@@ -544,10 +422,10 @@ index a0bc10aa7961..2c4683c67a8e 100644
2.41.0
From 06a9d6baed9ca58eb8b79e58887bebb81deac567 Mon Sep 17 00:00:00 2001
From 2eaf6c8660ded5426501e0da35d4746a25e142cc Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 3 Apr 2023 20:23:14 +0200
Subject: [PATCH 06/11] phy: phy-rockchip-inno-usb2: add reset support
Subject: [PATCH 3/8] phy: phy-rockchip-inno-usb2: add reset support
Add reset handling support, which is needed for proper
operation with RK3588.
@@ -645,10 +523,10 @@ index 2c4683c67a8e..101b46939f0b 100644
2.41.0
From f00308d812c063b4104214ff3d4b589f89ff96b4 Mon Sep 17 00:00:00 2001
From 8ba13deb082a06286010db007fdf308219617898 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 3 Apr 2023 20:24:06 +0200
Subject: [PATCH 07/11] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning
Subject: [PATCH 4/8] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning
support
On RK3588 some registers need to be tweaked to support waking up from
@@ -798,11 +676,10 @@ index 101b46939f0b..aa8c55609c0d 100644
2.41.0
From 656516de7b6bdce000fad36006d392bc03c4811a Mon Sep 17 00:00:00 2001
From 7b290174691a44964e2f735a13514c5771231d68 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 3 Apr 2023 21:49:58 +0200
Subject: [PATCH 08/11] phy: phy-rockchip-inno-usb2: simplify phy clock
handling
Subject: [PATCH 5/8] phy: phy-rockchip-inno-usb2: simplify phy clock handling
Simplify phyclk handling by using devm_clk_get_optional_enabled to
acquire and enable the optional clock. This also fixes a resource
@@ -864,11 +741,10 @@ index aa8c55609c0d..1cf84869e78b 100644
2.41.0
From 4c7c30ae33f9c7b899672d43abba0cfe4e387d14 Mon Sep 17 00:00:00 2001
From 1f09d9722948775d9ddbb55c566b1dd96cba6be1 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 3 Apr 2023 22:01:14 +0200
Subject: [PATCH 09/11] phy: phy-rockchip-inno-usb2: simplify getting match
data
Subject: [PATCH 6/8] phy: phy-rockchip-inno-usb2: simplify getting match data
Simplify the code by directly getting the match data via
device_get_match_data() instead of open coding its functionality.
@@ -924,10 +800,10 @@ index 1cf84869e78b..f5c30f117cba 100644
2.41.0
From b4885b6a9f0183c270fc54326b1a3aa7b916129f Mon Sep 17 00:00:00 2001
From 27587f10b0763bba73af92cb1d00af2de2638b40 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 15 May 2023 18:40:42 +0200
Subject: [PATCH 10/11] phy: phy-rockchip-inno-usb2: improve error message
Subject: [PATCH 7/8] phy: phy-rockchip-inno-usb2: improve error message
Printing the OF node is not useful, since we get the same information
from the device context. Instead print the reg address, that could
@@ -956,22 +832,24 @@ index f5c30f117cba..b982c3f0d4b5 100644
2.41.0
From 719bf79884297d5278f735bb08ed6a9fbaf37efa Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Tue, 4 Jul 2023 13:36:35 +0300
Subject: [PATCH 11/11] arm64: dts: rockchip: rk3588: add USB2 support
From c10b7b902f6d8d1b550c6b4ccd8615f407ca85a3 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 12 Jan 2023 19:20:37 +0100
Subject: [PATCH 8/8] arm64: dts: rockchip: rk3588: add USB2 support
This adds USB2 (EHCI & OHCI) ports including the related PHYs
and GRF modules to the rk3588(s) device tree.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 94 +++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 973fd6e8aa36..37e323ec9d74 100644
index 1eb5a4add04b..2ee12ca98824 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -399,11 +399,105 @@ scmi_shmem: sram@0 {
@@ -839,11 +839,105 @@ scmi_shmem: sram@0 {
};
};
@@ -1074,9 +952,9 @@ index 973fd6e8aa36..37e323ec9d74 100644
+ };
+ };
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
bigcore0_grf: syscon@fd590000 {
compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
reg = <0x0 0xfd590000 0x0 0x100>;
--
2.41.0

684
patch/kernel/rockchip-rk3588-edge/0020-RK3588-ADC-support.patch
View File

@@ -1,684 +0,0 @@
From cd425173fe5788b5bc17cc4a3de7c68fd571d151 Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Sun, 4 Jun 2023 00:23:33 +0530
Subject: [PATCH 1/9] iio: adc: rockchip_saradc: Add callback functions
Add start, read and power_down callback functions,
which will help in adding new rockchip device support
cleanly.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++------
1 file changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 79448c5ffc2a..21f9d92a6af4 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -38,10 +38,15 @@
#define SARADC_TIMEOUT msecs_to_jiffies(100)
#define SARADC_MAX_CHANNELS 8
+struct rockchip_saradc;
+
struct rockchip_saradc_data {
const struct iio_chan_spec *channels;
int num_channels;
unsigned long clk_rate;
+ void (*start)(struct rockchip_saradc *info, int chn);
+ int (*read)(struct rockchip_saradc *info);
+ void (*power_down)(struct rockchip_saradc *info);
};
struct rockchip_saradc {
@@ -60,27 +65,50 @@ struct rockchip_saradc {
struct notifier_block nb;
};
-static void rockchip_saradc_power_down(struct rockchip_saradc *info)
+static void rockchip_saradc_reset_controller(struct reset_control *reset);
+
+static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
+{
+ /* 8 clock periods as delay between power up and start cmd */
+ writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
+ /* Select the channel to be used and trigger conversion */
+ writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
+ SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
+}
+
+static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
+{
+ info->data->start(info, chn);
+}
+
+static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
+{
+ return readl_relaxed(info->regs + SARADC_DATA);
+}
+
+static int rockchip_saradc_read(struct rockchip_saradc *info)
+{
+ return info->data->read(info);
+}
+
+static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
{
- /* Clear irq & power down adc */
writel_relaxed(0, info->regs + SARADC_CTRL);
}
+static void rockchip_saradc_power_down(struct rockchip_saradc *info)
+{
+ if (info->data->power_down)
+ info->data->power_down(info);
+}
+
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
struct iio_chan_spec const *chan)
{
reinit_completion(&info->completion);
- /* 8 clock periods as delay between power up and start cmd */
- writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
-
info->last_chan = chan;
-
- /* Select the channel to be used and trigger conversion */
- writel(SARADC_CTRL_POWER_CTRL
- | (chan->channel & SARADC_CTRL_CHN_MASK)
- | SARADC_CTRL_IRQ_ENABLE,
- info->regs + SARADC_CTRL);
+ rockchip_saradc_start(info, chan->channel);
if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
return -ETIMEDOUT;
@@ -123,7 +151,7 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
struct rockchip_saradc *info = dev_id;
/* Read value */
- info->last_val = readl_relaxed(info->regs + SARADC_DATA);
+ info->last_val = rockchip_saradc_read(info);
info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
rockchip_saradc_power_down(info);
@@ -163,6 +191,9 @@ static const struct rockchip_saradc_data saradc_data = {
.channels = rockchip_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
@@ -174,6 +205,9 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = {
.channels = rockchip_rk3066_tsadc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
.clk_rate = 50000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
@@ -189,6 +223,9 @@ static const struct rockchip_saradc_data rk3399_saradc_data = {
.channels = rockchip_rk3399_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
@@ -206,6 +243,9 @@ static const struct rockchip_saradc_data rk3568_saradc_data = {
.channels = rockchip_rk3568_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct of_device_id rockchip_saradc_match[] = {
--
2.41.0
From b5d9db8b105387c66c2c44096a622c6d9adfd5e6 Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Sun, 4 Jun 2023 00:23:34 +0530
Subject: [PATCH 2/9] iio: adc: rockchip_saradc: Add support for RK3588
Add new start and read functions to support rk3588 device.
Also, add a device compatible string for the same.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 21f9d92a6af4..312286ec91dc 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -4,6 +4,7 @@
* Copyright (C) 2014 ROCKCHIP, Inc.
*/
+#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
@@ -38,6 +39,22 @@
#define SARADC_TIMEOUT msecs_to_jiffies(100)
#define SARADC_MAX_CHANNELS 8
+/* v2 registers */
+#define SARADC2_CONV_CON 0x0
+#define SARADC_T_PD_SOC 0x4
+#define SARADC_T_DAS_SOC 0xc
+#define SARADC2_END_INT_EN 0x104
+#define SARADC2_ST_CON 0x108
+#define SARADC2_STATUS 0x10c
+#define SARADC2_END_INT_ST 0x110
+#define SARADC2_DATA_BASE 0x120
+
+#define SARADC2_EN_END_INT BIT(0)
+#define SARADC2_START BIT(4)
+#define SARADC2_SINGLE_MODE BIT(5)
+
+#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
+
struct rockchip_saradc;
struct rockchip_saradc_data {
@@ -76,6 +93,25 @@ static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
}
+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
+{
+ int val;
+
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
+ val = FIELD_PREP(SARADC2_EN_END_INT, 1);
+ val |= val << 16;
+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
+ val = FIELD_PREP(SARADC2_START, 1) |
+ FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
+ FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
+ val |= val << 16;
+ writel(val, info->regs + SARADC2_CONV_CON);
+}
+
static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
{
info->data->start(info, chn);
@@ -86,6 +122,18 @@ static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
return readl_relaxed(info->regs + SARADC_DATA);
}
+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
+{
+ int offset;
+
+ /* Clear irq */
+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
+
+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
+
+ return readl_relaxed(info->regs + offset);
+}
+
static int rockchip_saradc_read(struct rockchip_saradc *info)
{
return info->data->read(info);
@@ -248,6 +296,25 @@ static const struct rockchip_saradc_data rk3568_saradc_data = {
.power_down = rockchip_saradc_power_down_v1,
};
+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
+ SARADC_CHANNEL(0, "adc0", 12),
+ SARADC_CHANNEL(1, "adc1", 12),
+ SARADC_CHANNEL(2, "adc2", 12),
+ SARADC_CHANNEL(3, "adc3", 12),
+ SARADC_CHANNEL(4, "adc4", 12),
+ SARADC_CHANNEL(5, "adc5", 12),
+ SARADC_CHANNEL(6, "adc6", 12),
+ SARADC_CHANNEL(7, "adc7", 12),
+};
+
+static const struct rockchip_saradc_data rk3588_saradc_data = {
+ .channels = rockchip_rk3588_saradc_iio_channels,
+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
+ .clk_rate = 1000000,
+ .start = rockchip_saradc_start_v2,
+ .read = rockchip_saradc_read_v2,
+};
+
static const struct of_device_id rockchip_saradc_match[] = {
{
.compatible = "rockchip,saradc",
@@ -261,6 +328,9 @@ static const struct of_device_id rockchip_saradc_match[] = {
}, {
.compatible = "rockchip,rk3568-saradc",
.data = &rk3568_saradc_data,
+ }, {
+ .compatible = "rockchip,rk3588-saradc",
+ .data = &rk3588_saradc_data,
},
{},
};
--
2.41.0
From a0ba1f7d0b8ce5cfeff1253d99556704a4b70139 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:35 +0530
Subject: [PATCH 3/9] iio: adc: rockchip_saradc: Make use of
devm_clk_get_enabled
Use devm_clk_get_enabled() to avoid manually disabling the
clock.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 56 +++++--------------------------
1 file changed, 8 insertions(+), 48 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 312286ec91dc..ac424ea50787 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -346,20 +346,6 @@ static void rockchip_saradc_reset_controller(struct reset_control *reset)
reset_control_deassert(reset);
}
-static void rockchip_saradc_clk_disable(void *data)
-{
- struct rockchip_saradc *info = data;
-
- clk_disable_unprepare(info->clk);
-}
-
-static void rockchip_saradc_pclk_disable(void *data)
-{
- struct rockchip_saradc *info = data;
-
- clk_disable_unprepare(info->pclk);
-}
-
static void rockchip_saradc_regulator_disable(void *data)
{
struct rockchip_saradc *info = data;
@@ -493,16 +479,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
return ret;
}
- info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
- if (IS_ERR(info->pclk))
- return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
- "failed to get pclk\n");
-
- info->clk = devm_clk_get(&pdev->dev, "saradc");
- if (IS_ERR(info->clk))
- return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
- "failed to get adc clock\n");
-
info->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(info->vref))
return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
@@ -540,31 +516,15 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
info->uv_vref = ret;
- ret = clk_prepare_enable(info->pclk);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to enable pclk\n");
- return ret;
- }
- ret = devm_add_action_or_reset(&pdev->dev,
- rockchip_saradc_pclk_disable, info);
- if (ret) {
- dev_err(&pdev->dev, "failed to register devm action, %d\n",
- ret);
- return ret;
- }
+ info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ if (IS_ERR(info->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
+ "failed to get pclk\n");
- ret = clk_prepare_enable(info->clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to enable converter clock\n");
- return ret;
- }
- ret = devm_add_action_or_reset(&pdev->dev,
- rockchip_saradc_clk_disable, info);
- if (ret) {
- dev_err(&pdev->dev, "failed to register devm action, %d\n",
- ret);
- return ret;
- }
+ info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
+ if (IS_ERR(info->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
+ "failed to get adc clock\n");
platform_set_drvdata(pdev, indio_dev);
--
2.41.0
From 412fdfbbfc17c588c1f9ae3ee838c29860549f8e Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:36 +0530
Subject: [PATCH 4/9] iio: adc: rockchip_saradc: Use of_device_get_match_data
Use of_device_get_match_data() to simplify the code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index ac424ea50787..cbe347fe8df7 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -415,10 +415,10 @@ static void rockchip_saradc_regulator_unreg_notifier(void *data)
static int rockchip_saradc_probe(struct platform_device *pdev)
{
+ const struct rockchip_saradc_data *match_data;
struct rockchip_saradc *info = NULL;
struct device_node *np = pdev->dev.of_node;
struct iio_dev *indio_dev = NULL;
- const struct of_device_id *match;
int ret;
int irq;
@@ -432,13 +432,13 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
}
info = iio_priv(indio_dev);
- match = of_match_device(rockchip_saradc_match, &pdev->dev);
- if (!match) {
+ match_data = of_device_get_match_data(&pdev->dev);
+ if (!match_data) {
dev_err(&pdev->dev, "failed to match device\n");
return -ENODEV;
}
- info->data = match->data;
+ info->data = match_data;
/* Sanity check for possible later IP variants with more channels */
if (info->data->num_channels > SARADC_MAX_CHANNELS) {
--
2.41.0
From 7706b5ab350facf848f44aa846a2d26a8fa64a65 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:37 +0530
Subject: [PATCH 5/9] iio: adc: rockchip_saradc: Match alignment with open
parenthesis
Match alignment with open parenthesis for improving the code
readability.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index cbe347fe8df7..436e219984fd 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -151,7 +151,7 @@ static void rockchip_saradc_power_down(struct rockchip_saradc *info)
}
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
- struct iio_chan_spec const *chan)
+ struct iio_chan_spec const *chan)
{
reinit_completion(&info->completion);
@@ -394,8 +394,7 @@ static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
}
static int rockchip_saradc_volt_notify(struct notifier_block *nb,
- unsigned long event,
- void *data)
+ unsigned long event, void *data)
{
struct rockchip_saradc *info =
container_of(nb, struct rockchip_saradc, nb);
--
2.41.0
From 6511ca5e340de5a0d146d86a705f839ffdeb35ec Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:38 +0530
Subject: [PATCH 6/9] iio: adc: rockchip_saradc: Use dev_err_probe
Use dev_err_probe instead of dev_err in probe function,
which simplifies code a little bit and prints the error
code.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
drivers/iio/adc/rockchip_saradc.c | 45 ++++++++++++++-----------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 436e219984fd..921844d9232d 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -425,25 +425,23 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
return -ENODEV;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
- if (!indio_dev) {
- dev_err(&pdev->dev, "failed allocating iio device\n");
- return -ENOMEM;
- }
+ if (!indio_dev)
+ return dev_err_probe(&pdev->dev, -ENOMEM,
+ "failed allocating iio device\n");
+
info = iio_priv(indio_dev);
match_data = of_device_get_match_data(&pdev->dev);
- if (!match_data) {
- dev_err(&pdev->dev, "failed to match device\n");
- return -ENODEV;
- }
+ if (!match_data)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "failed to match device\n");
info->data = match_data;
/* Sanity check for possible later IP variants with more channels */
- if (info->data->num_channels > SARADC_MAX_CHANNELS) {
- dev_err(&pdev->dev, "max channels exceeded");
- return -EINVAL;
- }
+ if (info->data->num_channels > SARADC_MAX_CHANNELS)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "max channels exceeded");
info->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->regs))
@@ -491,23 +489,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
* This may become user-configurable in the future.
*/
ret = clk_set_rate(info->clk, info->data->clk_rate);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
- return ret;
- }
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to set adc clk rate\n");
ret = regulator_enable(info->vref);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to enable vref regulator\n");
- return ret;
- }
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to enable vref regulator\n");
+
ret = devm_add_action_or_reset(&pdev->dev,
rockchip_saradc_regulator_disable, info);
- if (ret) {
- dev_err(&pdev->dev, "failed to register devm action, %d\n",
- ret);
- return ret;
- }
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to register devm action\n");
ret = regulator_get_voltage(info->vref);
if (ret < 0)
--
2.41.0
From 97f4513badc89771a4823235dab215078534419a Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:39 +0530
Subject: [PATCH 7/9] arm64: dts: rockchip: Add DT node for ADC support in
RK3588
Add DT node for ADC support in RK3588.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 977ed617f59e..e7622a44c9ea 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1906,6 +1906,18 @@ dmac2: dma-controller@fed10000 {
#dma-cells = <1>;
};
+ saradc: saradc@fec10000 {
+ compatible = "rockchip,rk3588-saradc";
+ reg = <0x0 0xfec10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
system_sram2: sram@ff001000 {
compatible = "mmio-sram";
reg = <0x0 0xff001000 0x0 0xef000>;
--
2.41.0
From a4bde5a0ce8037f213cb1ede73181c55d108df6a Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 4 Jun 2023 00:23:40 +0530
Subject: [PATCH 8/9] dt-bindings: iio: adc: Add rockchip,rk3588-saradc string
Add rockchip,rk3588-saradc compatible string.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
index da50b529c157..11c27ea451c8 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
@@ -21,6 +21,7 @@ properties:
- rockchip,rk3308-saradc
- rockchip,rk3328-saradc
- rockchip,rk3568-saradc
+ - rockchip,rk3588-saradc
- rockchip,rv1108-saradc
- rockchip,rv1126-saradc
- const: rockchip,rk3399-saradc
--
2.41.0
From 0bea534abbafa0f8d43fb27c65d9c9d84f3269f3 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Sun, 11 Jun 2023 00:56:47 +0530
Subject: [PATCH 9/9] dt-bindings: iio: rockchip: Fix 'oneOf' condition failed
warning
rk3588-saradc isn't compatible with the rk3399-saradc variant,
hence, fix the following dtbs_check warning for 'oneOf' condition
failure.
DTC_CHK arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb
/home/shreeya/linux/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb:
saradc@fec10000: compatible: 'oneOf' conditional failed,
one must be fixed:
['rockchip,rk3588-saradc'] is too short
'rockchip,saradc' was expected
'rockchip,rk3066-tsadc' was expected
'rockchip,rk3399-saradc' was expected
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
index 11c27ea451c8..aa24b841393c 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
@@ -15,13 +15,13 @@ properties:
- const: rockchip,saradc
- const: rockchip,rk3066-tsadc
- const: rockchip,rk3399-saradc
+ - const: rockchip,rk3588-saradc
- items:
- enum:
- rockchip,px30-saradc
- rockchip,rk3308-saradc
- rockchip,rk3328-saradc
- rockchip,rk3568-saradc
- - rockchip,rk3588-saradc
- rockchip,rv1108-saradc
- rockchip,rv1126-saradc
- const: rockchip,rk3399-saradc
--
2.41.0

341
patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-SATA-support.patch
View File

@@ -1,313 +1,12 @@
From 03b582ba80822d93be46e13ca7121f99c7132da8 Mon Sep 17 00:00:00 2001
From a62faa8b31b2e19cffe0e299f9e1c4cbd439722f Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 12 Jun 2023 19:13:33 +0200
Subject: [PATCH 1/5] dt-bindings: ata: dwc-ahci: add PHY clocks
Add PHY transmit and receive clocks as described by the
DW SATA AHCI HW manual.
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../devicetree/bindings/ata/snps,dwc-ahci-common.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
index c1457910520b..34c5bf65b02d 100644
--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
@@ -31,11 +31,11 @@ properties:
PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
clock, etc.
minItems: 1
- maxItems: 4
+ maxItems: 6
clock-names:
minItems: 1
- maxItems: 4
+ maxItems: 6
items:
oneOf:
- description: Application APB/AHB/AXI BIU clock
@@ -48,6 +48,10 @@ properties:
const: pmalive
- description: RxOOB detection clock
const: rxoob
+ - description: PHY Transmit Clock
+ const: asic
+ - description: PHY Receive Clock
+ const: rbc
- description: SATA Ports reference clock
const: ref
--
2.41.0
From 81b1ff2b1b72caa5ed7776df1547bbddc83395e8 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 12 Jun 2023 19:13:34 +0200
Subject: [PATCH 2/5] dt-bindings: ata: dwc-ahci: add Rockchip RK3588
This adds Rockchip RK3588 AHCI binding. In order to narrow down the
allowed clocks without bloating the generic binding, the description
of Rockchip's AHCI controllers has been moved to its own file.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/ata/rockchip,dwc-ahci.yaml | 124 ++++++++++++++++++
.../bindings/ata/snps,dwc-ahci.yaml | 13 +-
2 files changed, 133 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
diff --git a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
new file mode 100644
index 000000000000..b5e5767d8698
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DWC AHCI SATA controller for Rockchip devices
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description:
+ This document defines device tree bindings for the Synopsys DWC
+ implementation of the AHCI SATA controller found in Rockchip
+ devices.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3568-dwc-ahci
+ - rockchip,rk3588-dwc-ahci
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - rockchip,rk3568-dwc-ahci
+ - rockchip,rk3588-dwc-ahci
+ - const: snps,dwc-ahci
+
+ ports-implemented:
+ const: 1
+
+ sata-port@0:
+ $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
+
+ properties:
+ reg:
+ const: 0
+
+ unevaluatedProperties: false
+
+patternProperties:
+ "^sata-port@[1-9a-e]$": false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports-implemented
+
+allOf:
+ - $ref: snps,dwc-ahci-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3588-dwc-ahci
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: sata
+ - const: pmalive
+ - const: rxoob
+ - const: ref
+ - const: asic
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3568-dwc-ahci
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: sata
+ - const: pmalive
+ - const: rxoob
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/ata/ahci.h>
+ #include <dt-bindings/phy/phy.h>
+
+ sata@fe210000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0xfe210000 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
index 5afa4b57ce20..4c848fcb5a5d 100644
--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
@@ -13,6 +13,15 @@ description:
This document defines device tree bindings for the generic Synopsys DWC
implementation of the AHCI SATA controller.
+select:
+ properties:
+ compatible:
+ enum:
+ - snps,dwc-ahci
+ - snps,spear-ahci
+ required:
+ - compatible
+
allOf:
- $ref: snps,dwc-ahci-common.yaml#
@@ -23,10 +32,6 @@ properties:
const: snps,dwc-ahci
- description: SPEAr1340 AHCI SATA device
const: snps,spear-ahci
- - description: Rockhip RK3568 AHCI controller
- items:
- - const: rockchip,rk3568-dwc-ahci
- - const: snps,dwc-ahci
patternProperties:
"^sata-port@[0-9a-e]$":
--
2.41.0
From 15f3049fcf0e6657c7f4c594b83f4df437a6c03c Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 12 Jun 2023 19:13:35 +0200
Subject: [PATCH 3/5] dt-bindings: phy: rockchip: rk3588 has two reset lines
The RK3588 has two reset lines for the combphy. One for the
APB interface and one for the actual PHY.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../phy/phy-rockchip-naneng-combphy.yaml | 34 ++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
index 9ae514fa7533..d3cd7997879f 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -31,8 +31,14 @@ properties:
- const: pipe
resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
items:
- - description: exclusive PHY reset line
+ - const: phy
+ - const: apb
rockchip,enable-ssc:
type: boolean
@@ -78,6 +84,32 @@ required:
- rockchip,pipe-phy-grf
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3568-naneng-combphy
+ then:
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3588-naneng-combphy
+ then:
+ properties:
+ resets:
+ minItems: 2
+ reset-names:
+ minItems: 2
+ required:
+ - reset-names
+
additionalProperties: false
examples:
--
2.41.0
From 571fb8a07c593ddafa101138ef89d346677cc518 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Tue, 4 Jul 2023 13:11:19 +0300
Subject: [PATCH 4/5] arm64: dts: rockchip: rk3588: add combo PHYs
Date: Thu, 6 Apr 2023 16:54:11 +0200
Subject: [PATCH 1/2] arm64: dts: rockchip: rk3588: add combo PHYs
Add all 3 combo PHYs that can be found in RK3588.
They are used for SATA, PCIe or USB3.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++
@@ -351,10 +50,10 @@ index 8be75556af8f..9d8539b5309b 100644
+ };
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index e7622a44c9ea..4aa15ce78365 100644
index 2ee12ca98824..e51cd3250ad0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -407,6 +407,16 @@ php_grf: syscon@fd5b0000 {
@@ -953,6 +953,16 @@ php_grf: syscon@fd5b0000 {
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
@@ -371,7 +70,7 @@ index e7622a44c9ea..4aa15ce78365 100644
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -1906,6 +1916,38 @@ dmac2: dma-controller@fed10000 {
@@ -2489,6 +2499,38 @@ dmac2: dma-controller@fed10000 {
#dma-cells = <1>;
};
@@ -407,19 +106,21 @@ index e7622a44c9ea..4aa15ce78365 100644
+ status = "disabled";
+ };
+
saradc: saradc@fec10000 {
compatible = "rockchip,rk3588-saradc";
reg = <0x0 0xfec10000 0x0 0x10000>;
system_sram2: sram@ff001000 {
compatible = "mmio-sram";
reg = <0x0 0xff001000 0x0 0xef000>;
--
2.41.0
From 95ad8212851df865bb4146278a7bc782bca45880 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Tue, 4 Jul 2023 13:16:57 +0300
Subject: [PATCH 5/5] arm64: dts: rockchip: rk3588: add SATA support
From b4d4e5cf5bdd5ce79f7b2cecaece5aafc0c432e2 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 6 Apr 2023 17:14:19 +0200
Subject: [PATCH 2/2] arm64: dts: rockchip: rk3588: add SATA support
Add all three SATA IP blocks to the RK3588 DT.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++
@@ -460,19 +161,19 @@ index 9d8539b5309b..b9508cea34f1 100644
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 4aa15ce78365..ee091f0a3ca3 100644
index e51cd3250ad0..7e6c08817284 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
@@ -9,6 +9,8 @@
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/ata/ahci.h>
/ {
compatible = "rockchip,rk3588";
@@ -1180,6 +1182,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
@@ -1726,6 +1728,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};

119
patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe2-support.patch
View File

@@ -1,7 +1,7 @@
From 55f62897ce675d323b81dc92e9ce9060543e61f3 Mon Sep 17 00:00:00 2001
From ce732448e140a388f74734edf2e2ec02a0478c55 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 16 Jun 2023 19:00:19 +0200
Subject: [PATCH 1/4] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names
Date: Wed, 19 Apr 2023 14:57:14 +0200
Subject: [PATCH 1/3] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names
issue
The RK356x (and RK3588) have 5 ganged interrupts. For example the
@@ -15,19 +15,18 @@ Fix this by specifying the interrupts and add them to the example
to prevent regressions.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/rockchip-dw-pcie.yaml | 18 ++++++++++++++++++
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++++++++++++++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index 24c88942e59e..98e45d2d8dfe 100644
index a4f61ced5e88..aad53c7d8485 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -56,6 +56,17 @@ properties:
- const: pclk
@@ -60,6 +60,17 @@ properties:
- const: aux
- const: pipe
+ interrupts:
+ maxItems: 5
@@ -43,7 +42,7 @@ index 24c88942e59e..98e45d2d8dfe 100644
msi-map: true
num-lanes: true
@@ -98,6 +109,7 @@ unevaluatedProperties: false
@@ -108,6 +119,7 @@ unevaluatedProperties: false
examples:
- |
@@ -51,7 +50,7 @@ index 24c88942e59e..98e45d2d8dfe 100644
bus {
#address-cells = <2>;
@@ -117,6 +129,12 @@ examples:
@@ -127,6 +139,12 @@ examples:
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
@@ -96,10 +95,10 @@ index 1a83f0f65f19..9f605eb297f5 100644
2.41.0
From ed28eed118bb1815347fbb4ea3e4ebb2a917e2b4 Mon Sep 17 00:00:00 2001
From 24502533a9950837c50469c1cbb37324a6c83b0e Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 16 Jun 2023 19:00:20 +0200
Subject: [PATCH 2/4] dt-bindings: PCI: dwc: rockchip: Add missing
Date: Wed, 19 Apr 2023 18:27:12 +0200
Subject: [PATCH 2/3] dt-bindings: PCI: dwc: rockchip: Add missing
legacy-interrupt-controller
Rockchip RK356x and RK3588 handle legacy interrupts via a ganged
@@ -109,16 +108,15 @@ implementations. This adds proper documentation for this and updates
the example to avoid regressions.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/rockchip-dw-pcie.yaml | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index 98e45d2d8dfe..bf81d306cc80 100644
index aad53c7d8485..7897af0ec297 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -67,6 +67,22 @@ properties:
@@ -71,6 +71,22 @@ properties:
- const: legacy
- const: err
@@ -141,7 +139,7 @@ index 98e45d2d8dfe..bf81d306cc80 100644
msi-map: true
num-lanes: true
@@ -148,6 +164,14 @@ examples:
@@ -158,6 +174,14 @@ examples:
reset-names = "pipe";
#address-cells = <3>;
#size-cells = <2>;
@@ -160,81 +158,10 @@ index 98e45d2d8dfe..bf81d306cc80 100644
2.41.0
From 4298296463a25b9a7830001da790e8240654337a Mon Sep 17 00:00:00 2001
From 9afd072bbcb97efccf1be82515cbe4ba682cce38 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 16 Jun 2023 19:00:21 +0200
Subject: [PATCH 3/4] dt-bindings: PCI: dwc: rockchip: Update for RK3588
The PCIe 2.0 controllers on RK3588 need one additional clock,
one additional reset line and one for ranges entry.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
.../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index bf81d306cc80..7897af0ec297 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -41,20 +41,24 @@ properties:
- const: config
clocks:
+ minItems: 5
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
+ - description: PIPE clock
clock-names:
+ minItems: 5
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
+ - const: pipe
interrupts:
maxItems: 5
@@ -97,13 +101,19 @@ properties:
maxItems: 1
ranges:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- const: pipe
+ oneOf:
+ - const: pipe
+ - items:
+ - const: pwr
+ - const: pipe
vpcie3v3-supply: true
--
2.41.0
From 83fbcafeea18de93601461ffd14311ea1ef8a433 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 16 Jun 2023 19:00:22 +0200
Subject: [PATCH 4/4] arm64: dts: rockchip: rk3588: add PCIe2 support
Date: Mon, 17 Apr 2023 20:03:08 +0200
Subject: [PATCH 3/3] arm64: dts: rockchip: rk3588: add PCIe2 support
Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588
also has two PCIe3 IP blocks, that will be handled separately.
@@ -248,7 +175,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2 files changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index b9508cea34f1..40fee1367b34 100644
index b9508cea34f1..5c61cce52a21 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -80,6 +80,60 @@ i2s10_8ch: i2s@fde00000 {
@@ -291,7 +218,7 @@ index b9508cea34f1..40fee1367b34 100644
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
+ <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ reg = <0xa 0x40800000 0x0 0x00400000>,
+ <0x0 0xfe170000 0x0 0x00010000>,
+ <0x0 0xf2000000 0x0 0x00100000>;
@@ -313,10 +240,10 @@ index b9508cea34f1..40fee1367b34 100644
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index ee091f0a3ca3..973fd6e8aa36 100644
index 7e6c08817284..a009c4414256 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1133,6 +1133,114 @@ qos_vop_m1: qos@fdf82200 {
@@ -1679,6 +1679,114 @@ qos_vop_m1: qos@fdf82200 {
reg = <0x0 0xfdf82200 0x0 0x20>;
};
@@ -356,7 +283,7 @@ index ee091f0a3ca3..973fd6e8aa36 100644
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
+ <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ reg = <0xa 0x40c00000 0x0 0x00400000>,
+ <0x0 0xfe180000 0x0 0x00010000>,
+ <0x0 0xf3000000 0x0 0x00100000>;
@@ -410,7 +337,7 @@ index ee091f0a3ca3..973fd6e8aa36 100644
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+ <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ reg = <0xa 0x41000000 0x0 0x00400000>,
+ <0x0 0xfe190000 0x0 0x00010000>,
+ <0x0 0xf4000000 0x0 0x00100000>;

847
patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-OTP-memory-support.patch
View File

@@ -1,847 +0,0 @@
From a71fb1ef5b28f73ef42f4becc2c3fcb944797348 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:41 +0300
Subject: [PATCH 1/9] dt-bindings: nvmem: Convert rockchip-otp.txt to dt-schema
Convert the Rockchip OTP memory bindings to dt-schema.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/nvmem/rockchip,otp.yaml | 82 +++++++++++++++++++
.../bindings/nvmem/rockchip-otp.txt | 25 ------
2 files changed, 82 insertions(+), 25 deletions(-)
create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
delete mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
new file mode 100644
index 000000000000..4cd425ae2823
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip internal OTP (One Time Programmable) memory
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-otp
+ - rockchip,rk3308-otp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: otp
+ - const: apb_pclk
+ - const: phy
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: phy
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/px30-cru.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ otp: efuse@ff290000 {
+ compatible = "rockchip,px30-otp";
+ reg = <0x0 0xff290000 0x0 0x4000>;
+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
+ <&cru PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTP_PHY>;
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+
+ performance: performance@1e {
+ reg = <0x1e 0x1>;
+ bits = <4 3>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
deleted file mode 100644
index 40f649f7c2e5..000000000000
--- a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Rockchip internal OTP (One Time Programmable) memory device tree bindings
-
-Required properties:
-- compatible: Should be one of the following.
- - "rockchip,px30-otp" - for PX30 SoCs.
- - "rockchip,rk3308-otp" - for RK3308 SoCs.
-- reg: Should contain the registers location and size
-- clocks: Must contain an entry for each entry in clock-names.
-- clock-names: Should be "otp", "apb_pclk" and "phy".
-- resets: Must contain an entry for each entry in reset-names.
- See ../../reset/reset.txt for details.
-- reset-names: Should be "phy".
-
-See nvmem.txt for more information.
-
-Example:
- otp: otp@ff290000 {
- compatible = "rockchip,px30-otp";
- reg = <0x0 0xff290000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
- <&cru PCLK_OTP_PHY>;
- clock-names = "otp", "apb_pclk", "phy";
- };
--
2.41.0
From 3282bc8fec63200ed6a3c485bb39b3c094117209 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:42 +0300
Subject: [PATCH 2/9] dt-bindings: nvmem: rockchip,otp: Add compatible for
RK3588
Document the OTP memory found on Rockchip RK3588 SoC.
Since RK3588 uses different clocks & resets configurations than PX30 /
RK3308, provide the required changes in the binding to be able to handle
both variants.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/nvmem/rockchip,otp.yaml | 54 ++++++++++++++++---
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
index 4cd425ae2823..9c6eff788928 100644
--- a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
@@ -9,33 +9,35 @@ title: Rockchip internal OTP (One Time Programmable) memory
maintainers:
- Heiko Stuebner <heiko@sntech.de>
-allOf:
- - $ref: nvmem.yaml#
-
properties:
compatible:
enum:
- rockchip,px30-otp
- rockchip,rk3308-otp
+ - rockchip,rk3588-otp
reg:
maxItems: 1
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
clock-names:
+ minItems: 3
items:
- const: otp
- const: apb_pclk
- const: phy
+ - const: arb
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
reset-names:
- items:
- - const: phy
+ minItems: 1
+ maxItems: 3
required:
- compatible
@@ -45,6 +47,44 @@ required:
- resets
- reset-names
+allOf:
+ - $ref: nvmem.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-otp
+ - rockchip,rk3308-otp
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3588-otp
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ resets:
+ minItems: 3
+ reset-names:
+ items:
+ - const: otp
+ - const: apb
+ - const: arb
+
unevaluatedProperties: false
examples:
--
2.41.0
From e4131e9dc168176bf647116e998f34e53cf7233f Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:43 +0300
Subject: [PATCH 3/9] nvmem: rockchip-otp: Add clks and reg_read to
rockchip_data
In preparation to support new Rockchip OTP memory devices with different
clock configurations and register layout, extend rockchip_data struct
with the related members: clks, num_clks, reg_read.
Additionally, to avoid managing redundant driver data, drop num_clks
member from rockchip_otp struct and update all references to point to
the equivalent member in rockchip_data.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++--------------
1 file changed, 49 insertions(+), 30 deletions(-)
diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
index 9f53bcce2f87..b5a84b379da4 100644
--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -54,21 +54,19 @@
#define OTPC_TIMEOUT 10000
+struct rockchip_data {
+ int size;
+ const char * const *clks;
+ int num_clks;
+ nvmem_reg_read_t reg_read;
+};
+
struct rockchip_otp {
struct device *dev;
void __iomem *base;
- struct clk_bulk_data *clks;
- int num_clks;
+ struct clk_bulk_data *clks;
struct reset_control *rst;
-};
-
-/* list of required clocks */
-static const char * const rockchip_otp_clocks[] = {
- "otp", "apb_pclk", "phy",
-};
-
-struct rockchip_data {
- int size;
+ const struct rockchip_data *data;
};
static int rockchip_otp_reset(struct rockchip_otp *otp)
@@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
return ret;
}
-static int rockchip_otp_read(void *context, unsigned int offset,
- void *val, size_t bytes)
+static int px30_otp_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
{
struct rockchip_otp *otp = context;
u8 *buf = val;
- int ret = 0;
-
- ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
- if (ret < 0) {
- dev_err(otp->dev, "failed to prepare/enable clks\n");
- return ret;
- }
+ int ret;
ret = rockchip_otp_reset(otp);
if (ret) {
dev_err(otp->dev, "failed to reset otp phy\n");
- goto disable_clks;
+ return ret;
}
ret = rockchip_otp_ecc_enable(otp, false);
if (ret < 0) {
dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
- goto disable_clks;
+ return ret;
}
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
@@ -174,8 +166,28 @@ static int rockchip_otp_read(void *context, unsigned int offset,
read_end:
writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
-disable_clks:
- clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
+
+ return ret;
+}
+
+static int rockchip_otp_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct rockchip_otp *otp = context;
+ int ret;
+
+ if (!otp->data || !otp->data->reg_read)
+ return -EINVAL;
+
+ ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks);
+ if (ret < 0) {
+ dev_err(otp->dev, "failed to prepare/enable clks\n");
+ return ret;
+ }
+
+ ret = otp->data->reg_read(context, offset, val, bytes);
+
+ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks);
return ret;
}
@@ -189,8 +201,15 @@ static struct nvmem_config otp_config = {
.reg_read = rockchip_otp_read,
};
+static const char * const px30_otp_clocks[] = {
+ "otp", "apb_pclk", "phy",
+};
+
static const struct rockchip_data px30_data = {
.size = 0x40,
+ .clks = px30_otp_clocks,
+ .num_clks = ARRAY_SIZE(px30_otp_clocks),
+ .reg_read = px30_otp_read,
};
static const struct of_device_id rockchip_otp_match[] = {
@@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct platform_device *pdev)
if (!otp)
return -ENOMEM;
+ otp->data = data;
otp->dev = dev;
otp->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(otp->base))
return PTR_ERR(otp->base);
- otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks);
- otp->clks = devm_kcalloc(dev, otp->num_clks,
- sizeof(*otp->clks), GFP_KERNEL);
+ otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
+ GFP_KERNEL);
if (!otp->clks)
return -ENOMEM;
- for (i = 0; i < otp->num_clks; ++i)
- otp->clks[i].id = rockchip_otp_clocks[i];
+ for (i = 0; i < data->num_clks; ++i)
+ otp->clks[i].id = data->clks[i];
- ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
+ ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
if (ret)
return ret;
--
2.41.0
From a0cad270a253d54eaea3643f9d8426dbb436ec2c Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:44 +0300
Subject: [PATCH 4/9] nvmem: rockchip-otp: Generalize
rockchip_otp_wait_status()
In preparation to support additional Rockchip OTP memory devices with
different register layout, generalize rockchip_otp_wait_status() to
accept a new parameter for specifying the offset of the status register.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/nvmem/rockchip-otp.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
index b5a84b379da4..b62e001f9116 100644
--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct rockchip_otp *otp)
return 0;
}
-static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
+static int rockchip_otp_wait_status(struct rockchip_otp *otp,
+ unsigned int reg, u32 flag)
{
u32 status = 0;
int ret;
- ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
+ ret = readl_poll_timeout_atomic(otp->base + reg, status,
(status & flag), 1, OTPC_TIMEOUT);
if (ret)
return ret;
/* clean int status */
- writel(flag, otp->base + OTPC_INT_STATUS);
+ writel(flag, otp->base + reg);
return 0;
}
@@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
- ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE);
if (ret < 0)
dev_err(otp->dev, "timeout during ecc_enable\n");
@@ -156,7 +157,7 @@ static int px30_otp_read(void *context, unsigned int offset,
otp->base + OTPC_USER_ADDR);
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
otp->base + OTPC_USER_ENABLE);
- ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
if (ret < 0) {
dev_err(otp->dev, "timeout during read setup\n");
goto read_end;
--
2.41.0
From f993ae18db25b7033c4453225d4063775048d9e0 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:45 +0300
Subject: [PATCH 5/9] nvmem: rockchip-otp: Use
devm_reset_control_array_get_exclusive()
In preparation to support new Rockchip OTP memory devices having
specific reset configurations, switch devm_reset_control_get() to
devm_reset_control_array_get_exclusive().
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/nvmem/rockchip-otp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
index b62e001f9116..439aea1f8874 100644
--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct platform_device *pdev)
if (ret)
return ret;
- otp->rst = devm_reset_control_get(dev, "phy");
+ otp->rst = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(otp->rst))
return PTR_ERR(otp->rst);
--
2.41.0
From 1db5714fc59aa0b0b829155493389429cc497ddb Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:46 +0300
Subject: [PATCH 6/9] nvmem: rockchip-otp: Improve probe error handling
Enhance error handling in the probe function by making use of
dev_err_probe(), which ensures the error code is always printed, in
addition to the specified error message.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/nvmem/rockchip-otp.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
index 439aea1f8874..84bf956cc4e1 100644
--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct platform_device *pdev)
int ret, i;
data = of_device_get_match_data(dev);
- if (!data) {
- dev_err(dev, "failed to get match data\n");
- return -EINVAL;
- }
+ if (!data)
+ return dev_err_probe(dev, -EINVAL, "failed to get match data\n");
otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
GFP_KERNEL);
@@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct platform_device *pdev)
otp->dev = dev;
otp->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(otp->base))
- return PTR_ERR(otp->base);
+ return dev_err_probe(dev, PTR_ERR(otp->base),
+ "failed to ioremap resource\n");
otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
GFP_KERNEL);
@@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct platform_device *pdev)
ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
if (ret)
- return ret;
+ return dev_err_probe(dev, ret, "failed to get clocks\n");
otp->rst = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(otp->rst))
- return PTR_ERR(otp->rst);
+ return dev_err_probe(dev, PTR_ERR(otp->rst),
+ "failed to get resets\n");
otp_config.size = data->size;
otp_config.priv = otp;
otp_config.dev = dev;
- nvmem = devm_nvmem_register(dev, &otp_config);
- return PTR_ERR_OR_ZERO(nvmem);
+ nvmem = devm_nvmem_register(dev, &otp_config);
+ if (IS_ERR(nvmem))
+ return dev_err_probe(dev, PTR_ERR(nvmem),
+ "failed to register nvmem device\n");
+ return 0;
}
static struct platform_driver rockchip_otp_driver = {
--
2.41.0
From a3266c7a0d896cd793a070b18fd456c9dfcf48f6 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:47 +0300
Subject: [PATCH 7/9] nvmem: rockchip-otp: Add support for RK3588
Add support for the OTP memory device found on the Rockchip RK3588 SoC.
While here, remove the unnecessary 'void *' casts in the OF device ID
table.
Co-developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/nvmem/rockchip-otp.c | 78 +++++++++++++++++++++++++++++++++++-
1 file changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
index 84bf956cc4e1..cb9aa5428350 100644
--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -54,6 +54,19 @@
#define OTPC_TIMEOUT 10000
+/* RK3588 Register */
+#define RK3588_OTPC_AUTO_CTRL 0x04
+#define RK3588_OTPC_AUTO_EN 0x08
+#define RK3588_OTPC_INT_ST 0x84
+#define RK3588_OTPC_DOUT0 0x20
+#define RK3588_NO_SECURE_OFFSET 0x300
+#define RK3588_NBYTES 4
+#define RK3588_BURST_NUM 1
+#define RK3588_BURST_SHIFT 8
+#define RK3588_ADDR_SHIFT 16
+#define RK3588_AUTO_EN BIT(0)
+#define RK3588_RD_DONE BIT(1)
+
struct rockchip_data {
int size;
const char * const *clks;
@@ -171,6 +184,52 @@ static int px30_otp_read(void *context, unsigned int offset,
return ret;
}
+static int rk3588_otp_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct rockchip_otp *otp = context;
+ unsigned int addr_start, addr_end, addr_len;
+ int ret, i = 0;
+ u32 data;
+ u8 *buf;
+
+ addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES;
+ addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
+ addr_len = addr_end - addr_start;
+ addr_start += RK3588_NO_SECURE_OFFSET;
+
+ buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ while (addr_len--) {
+ writel((addr_start << RK3588_ADDR_SHIFT) |
+ (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
+ otp->base + RK3588_OTPC_AUTO_CTRL);
+ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
+
+ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST,
+ RK3588_RD_DONE);
+ if (ret < 0) {
+ dev_err(otp->dev, "timeout during read setup\n");
+ goto read_end;
+ }
+
+ data = readl(otp->base + RK3588_OTPC_DOUT0);
+ memcpy(&buf[i], &data, RK3588_NBYTES);
+
+ i += RK3588_NBYTES;
+ addr_start++;
+ }
+
+ memcpy(val, buf + offset % RK3588_NBYTES, bytes);
+
+read_end:
+ kfree(buf);
+
+ return ret;
+}
+
static int rockchip_otp_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
@@ -213,14 +272,29 @@ static const struct rockchip_data px30_data = {
.reg_read = px30_otp_read,
};
+static const char * const rk3588_otp_clocks[] = {
+ "otp", "apb_pclk", "phy", "arb",
+};
+
+static const struct rockchip_data rk3588_data = {
+ .size = 0x400,
+ .clks = rk3588_otp_clocks,
+ .num_clks = ARRAY_SIZE(rk3588_otp_clocks),
+ .reg_read = rk3588_otp_read,
+};
+
static const struct of_device_id rockchip_otp_match[] = {
{
.compatible = "rockchip,px30-otp",
- .data = (void *)&px30_data,
+ .data = &px30_data,
},
{
.compatible = "rockchip,rk3308-otp",
- .data = (void *)&px30_data,
+ .data = &px30_data,
+ },
+ {
+ .compatible = "rockchip,rk3588-otp",
+ .data = &rk3588_data,
},
{ /* sentinel */ },
};
--
2.41.0
From 4e3178487898d3e21deb144dfa967b4f8c71c8f3 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 4 May 2023 23:06:48 +0300
Subject: [PATCH 8/9] arm64: dts: rockchip: Add rk3588 OTP node
Add DT node for Rockchip RK3588/RK3588S OTP memory.
Co-developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 7b93abd8f65c..977ed617f59e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1841,6 +1841,60 @@ spi4: spi@fecb0000 {
status = "disabled";
};
+ otp: efuse@fecc0000 {
+ compatible = "rockchip,rk3588-otp";
+ reg = <0x0 0xfecc0000 0x0 0x400>;
+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
+ clock-names = "otp", "apb_pclk", "phy", "arb";
+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+ <&cru SRST_OTPC_ARB>;
+ reset-names = "otp", "apb", "arb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+
+ otp_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+
+ otp_cpu_version: cpu-version@1c {
+ reg = <0x1c 0x1>;
+ bits = <3 3>;
+ };
+
+ cpub0_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+
+ cpub1_leakage: cpu-leakage@18 {
+ reg = <0x18 0x1>;
+ };
+
+ cpul_leakage: cpu-leakage@19 {
+ reg = <0x19 0x1>;
+ };
+
+ log_leakage: log-leakage@1a {
+ reg = <0x1a 0x1>;
+ };
+
+ gpu_leakage: gpu-leakage@1b {
+ reg = <0x1b 0x1>;
+ };
+
+ npu_leakage: npu-leakage@28 {
+ reg = <0x28 0x1>;
+ };
+
+ codec_leakage: codec-leakage@29 {
+ reg = <0x29 0x1>;
+ };
+ };
+
dmac2: dma-controller@fed10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfed10000 0x0 0x4000>;
--
2.41.0
From 39e135bbe54da0a6ddf98d183c0b4f3f248b17b1 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sun, 4 Jun 2023 20:13:45 +0300
Subject: [PATCH 9/9] arm64: defconfig: Enable Rockchip OTP memory driver
The Rockchip one-time programmable memory driver provides access to
various SoC specific information, e.g. leakage currents of the
CPU/GPU/NPU components found on a RK3588 SoC.
Enable the driver as built-in to allow client device drivers (e.g.
cpufreq) to access the required data for proper settings adjustment.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a24609e14d50..6ef220d383d3 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1385,6 +1385,7 @@ CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_QCOM_QFPROM=y
CONFIG_NVMEM_RMEM=m
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SNVS_LPGPR=y
CONFIG_NVMEM_SPMI_SDAM=m
CONFIG_NVMEM_SUNXI_SID=y
--
2.41.0

42
patch/kernel/rockchip-rk3588-edge/0026-Add-RK3588-USB3-Support.patch → patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-USB3-Support.patch
View File

@@ -1,4 +1,4 @@
From 0a75395f2d9bac99a964668b560508daefbbd3cd Mon Sep 17 00:00:00 2001
From 983b4443be14f1b62f2f0e5ccf3e7d3894f71081 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 17:38:57 +0200
Subject: [PATCH 1/6] dt-bindings: phy: add rockchip usbdp combo phy document
@@ -190,7 +190,7 @@ index 000000000000..dcca84d57e99
2.41.0
From 22cd81086f9197d6b7f6aa851d6338625a426fd9 Mon Sep 17 00:00:00 2001
From 98c5c2cdd1efd0d775f78af54f7b690b0f634e37 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 30 May 2023 16:40:02 +0200
Subject: [PATCH 2/6] dt-bindings: usb: rockchip,dwc3: Add RK3588 binding
@@ -351,7 +351,7 @@ index 3159f9a6a0f7..0db4dc86e506 100644
2.41.0
From e8991b26f1835f53c4e318eb02bb9953949595dc Mon Sep 17 00:00:00 2001
From 099abe585ba9ed6376355d75bc0b79bd9b6cac94 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 30 May 2023 18:49:48 +0200
Subject: [PATCH 3/6] dt-bindings: soc: rockchip: add rk3588 USB3 syscon
@@ -364,10 +364,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 65a2d5a4f28d..8d15c10a8f7e 100644
index e4fa6a07b4fa..ce1fd5b0d669 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -27,6 +27,9 @@ properties:
@@ -28,6 +28,9 @@ properties:
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
@@ -377,7 +377,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644
- rockchip,rv1108-usbgrf
- const: syscon
- items:
@@ -62,6 +65,9 @@ properties:
@@ -64,6 +67,9 @@ properties:
reg:
maxItems: 1
@@ -387,7 +387,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644
"#address-cells":
const: 1
@@ -242,6 +248,22 @@ allOf:
@@ -245,6 +251,22 @@ allOf:
unevaluatedProperties: false
@@ -414,7 +414,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644
2.41.0
From 50e9c28ab2696125dfef1f12db3a835b70a05b7f Mon Sep 17 00:00:00 2001
From 76dce9a4e101c5f961f91a3ddef99660081cadd5 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Tue, 25 Apr 2023 15:55:54 +0200
Subject: [PATCH 4/6] phy: rockchip: add usbdp combo phy driver
@@ -2207,7 +2207,7 @@ index 000000000000..414081b1247d
2.41.0
From 1a7e20bc463d7907be231c481b79bdfc5b43edd3 Mon Sep 17 00:00:00 2001
From 15e8ed9380726e7f27c886faa43df7be484f61e8 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 17:49:04 +0200
Subject: [PATCH 5/6] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes
@@ -2221,7 +2221,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2 files changed, 137 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 40fee1367b34..53a6650640ff 100644
index 5c61cce52a21..1add38695816 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -12,6 +12,38 @@ pipe_phy1_grf: syscon@fd5c0000 {
@@ -2302,10 +2302,10 @@ index 40fee1367b34..53a6650640ff 100644
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 37e323ec9d74..a4a8ac4208b9 100644
index a009c4414256..598cc3500e1f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -448,6 +448,33 @@ sys_grf: syscon@fd58c000 {
@@ -890,6 +890,33 @@ sys_grf: syscon@fd58c000 {
reg = <0x0 0xfd58c000 0x0 0x1000>;
};
@@ -2339,7 +2339,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
@@ -473,6 +500,17 @@ u2phy2_host: host-port {
@@ -915,6 +942,17 @@ u2phy2_host: host-port {
};
};
@@ -2357,7 +2357,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5dc000 0x0 0x4000>;
@@ -513,6 +551,11 @@ pipe_phy2_grf: syscon@fd5c4000 {
@@ -965,6 +1003,11 @@ pipe_phy2_grf: syscon@fd5c4000 {
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
@@ -2369,7 +2369,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2166,6 +2209,37 @@ dmac2: dma-controller@fed10000 {
@@ -2655,6 +2698,37 @@ dmac2: dma-controller@fed10000 {
#dma-cells = <1>;
};
@@ -2411,7 +2411,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644
2.41.0
From aa1ed927eddcfd728bdca5dbab9e4980b7dd5085 Mon Sep 17 00:00:00 2001
From c062260a0e652da798f7130ec25c6452957456d5 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 18:17:19 +0200
Subject: [PATCH 6/6] arm64: dts: rockchip: rk3588s: Add USB3 controllers
@@ -2425,7 +2425,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 53a6650640ff..e0992662b9c6 100644
index 1add38695816..7b7891771438 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,34 @@
@@ -2472,10 +2472,10 @@ index 53a6650640ff..e0992662b9c6 100644
u2phy1_otg: otg-port {
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a4a8ac4208b9..b46574358dd1 100644
index 598cc3500e1f..5a2469d05356 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -399,6 +399,36 @@ scmi_shmem: sram@0 {
@@ -841,6 +841,36 @@ scmi_shmem: sram@0 {
};
};
@@ -2512,7 +2512,7 @@ index a4a8ac4208b9..b46574358dd1 100644
usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -443,6 +473,35 @@ usb_host1_ohci: usb@fc8c0000 {
@@ -885,6 +915,35 @@ usb_host1_ohci: usb@fc8c0000 {
status = "disabled";
};
@@ -2548,7 +2548,7 @@ index a4a8ac4208b9..b46574358dd1 100644
sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -465,7 +524,6 @@ u2phy0: usb2-phy@0 {
@@ -907,7 +966,6 @@ u2phy0: usb2-phy@0 {
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
#clock-cells = <0>;

33
patch/kernel/rockchip-rk3588-edge/0024-enable-ethernet-for-rock-5b.patch
View File

@@ -1,33 +0,0 @@
From 2ca760c84e3764248233fe8891133f811d16aa2e Mon Sep 17 00:00:00 2001
From: Lucas Tanure <lucas.tanure@collabora.com>
Date: Thu, 23 Mar 2023 12:27:19 +0000
Subject: [PATCH] arm64: defconfig: Enable ethernet for Rock 5B
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0777bcae9104b..2982169691f31 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -221,6 +221,7 @@ CONFIG_PCIE_ALTERA=y
CONFIG_PCIE_ALTERA_MSI=y
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_ROCKCHIP_HOST=m
CONFIG_PCIE_MEDIATEK_GEN3=m
CONFIG_PCIE_BRCMSTB=m
@@ -1385,6 +1386,7 @@ CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
--
GitLab

0
patch/kernel/rockchip-rk3588-edge/0028-arm64-dts-rockchip-rk3588-add-sfc-node.patch → patch/kernel/rockchip-rk3588-edge/0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch
View File

968
patch/kernel/rockchip-rk3588-edge/0027-Add-Support-for-RK3588s-Indiedroid-Nova.patch
View File

@@ -1,968 +0,0 @@
From 091209864a90c83e11926cf484dbc4a86c34bcfe Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:16 -0500
Subject: [PATCH 1/5] arm64: dts: rockchip: add default pinctrl for rk3588 emmc
Add a default pinctrl definition for the rk3588 emmc.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a3124bd2e092..03462ae13ac7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1196,6 +1196,9 @@ sdhci: mmc@fe2e0000 {
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_data_strobe>;
+ pinctrl-names = "default";
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
--
2.41.0
From 9ac1b750fa33e5a340eaee65cf1085cad9ede25d Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:17 -0500
Subject: [PATCH 2/5] arm64: dts: rockchip: Add sdio node to rk3588
Add SDIO node for rk3588/rk3588s.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 03462ae13ac7..7b93abd8f65c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1185,6 +1185,21 @@ sdmmc: mmc@fe2c0000 {
status = "disabled";
};
+ sdio: mmc@fe2d0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x00 0xfe2d0000 0x00 0x4000>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>;
+ power-domains = <&power RK3588_PD_SDIO>;
+ status = "disabled";
+ };
+
sdhci: mmc@fe2e0000 {
compatible = "rockchip,rk3588-dwcmshc";
reg = <0x0 0xfe2e0000 0x0 0x10000>;
--
2.41.0
From 5799db8897382289eb29505050b6940ef5587628 Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:18 -0500
Subject: [PATCH 3/5] dt-bindings: vendor-prefixes: add Indiedroid
Indiedroid is a sub-brand of Ameridroid for their line of single board
computers.
https://indiedroid.us/
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 82d39ab0231b..580f32086d55 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -617,6 +617,8 @@ patternProperties:
description: Integrated Micro-Electronics Inc.
"^incircuit,.*":
description: In-Circuit GmbH
+ "^indiedroid,.*":
+ description: Indiedroid
"^inet-tek,.*":
description: Shenzhen iNet Mobile Internet Technology Co., Ltd
"^infineon,.*":
--
2.41.0
From abebfc368ca4c72ae0f789fb72a62a00fcb417f5 Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:19 -0500
Subject: [PATCH 4/5] dt-bindings: arm: rockchip: Add Indiedroid Nova
Add Indiedroid Nova, an rk3588s based single board computer.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index ec141c937b8b..3c5a204bcd81 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -542,6 +542,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Indiedroid Nova SBC
+ items:
+ - const: indiedroid,nova
+ - const: rockchip,rk3588s
+
- description: Khadas Edge2 series boards
items:
- const: khadas,edge2
--
2.41.0
From 6b199a6dfde0f0f521d88b45df884dc3b5743571 Mon Sep 17 00:00:00 2001
From: Chris Morgan <macromorgan@hotmail.com>
Date: Wed, 31 May 2023 11:12:20 -0500
Subject: [PATCH 5/5] arm64: dts: rockchip: Add Indiedroid Nova board
The Indiedroid Nova is an SBC from a sub-brand of Ameridroid that
includes the following hardware:
- A 40-pin GPIO header
- 2 USB-A 3.0 ports
- 2 USB-A 2.0 ports
- A USB-C 2.0 OTG port (used for USB power delivery)
- A USB-C 3.0 port that can do display port output.
- A Micro HDMI 2.1 port.
- A 1GB ethernet port.
- An RT8821CS based WiFi/Bluetooth module.
- A user replaceable eMMC module.
- An SDMMC card slot.
- A MIPI DSI connector.
- A MIPI CSI connector.
- A 3.5mm TRRS audio jack with microphone input.
- An 2 pin socket for an RTC battery.
- A 4 pin socket for a debug port.
- A power button (connected to PMIC), a reset button (connected to SoC
reset), a boot button, and a recovery button (both connected to the
ADC).
- 4GB, 8GB, or 16GB of system RAM.
This initial devicetree includes support for the WiFi, bluetooth,
analog audio out/in, SDMMC, eMMC, RTC, UART debugging, and has
the regulator values from the schematics. ADC, graphics output, GPU,
USB, and wired ethernet are still pending additional upstream changes.
Analog audio will require changes to handle a difference between the
requested clock frequency of 12288000 and the actual clock freqency
of 12287999 before it will work properly. This will be done in a
subsequent patch series.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/rk3588s-indiedroid-nova.dts | 764 ++++++++++++++++++
2 files changed, 765 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 2d585bbb8f3a..99f11db8158d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -94,5 +94,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
new file mode 100644
index 000000000000..add15cdafe76
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
@@ -0,0 +1,764 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Indiedroid Nova";
+ compatible = "indiedroid,nova", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clock-names = "ext_clock";
+ clocks = <&rtc_hym8563>;
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "rockchip,es8388-codec";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ routing = "LINPUT2", "Mic Jack",
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1";
+ dais = <&i2s0_8ch_p0>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&typec5v_pwren>;
+ pinctrl-names = "default";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "vcc_1v1_nldo_s3";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */
+ vcc_3v3_s0: vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s0";
+ vin-supply = <&vcc_3v3_s3>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_usb";
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_usbdcin";
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0{
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1{
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2{
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3{
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+/*
+ * Add labels for each GPIO pin exposed on the 40 pin header. Note that
+ * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by
+ * label).
+ */
+&gpio0 {
+ gpio-line-names = /* GPIO0 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 D0-D7 */
+ "HEADER_12_1v8", "", "", "HEADER_24_1v8",
+ "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A0-A7 */
+ "HEADER_27_3v3", "HEADER_28_3v3", "", "",
+ "HEADER_29_1v8", "", "HEADER_7_1v8", "",
+ /* GPIO1 B0-B7 */
+ "", "HEADER_31_1v8", "HEADER_33_1v8", "",
+ "HEADER_11_1v8", "HEADER_13_1v8", "", "",
+ /* GPIO1 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO1 D0-D7 */
+ "", "", "", "",
+ "", "", "HEADER_5_3v3", "HEADER_3_3v3";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO3 B0-B7 */
+ "HEADER_16_1v8", "HEADER_18_1v8", "", "",
+ "", "", "", "HEADER_19_1v8",
+ /* GPIO3 C0-C7 */
+ "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8",
+ "HEADER_15_1v8", "HEADER_22_1v8", "", "",
+ /* GPIO3 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A0-A7 */
+ "", "", "HEADER_37_3v3", "HEADER_32_3v3",
+ "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3",
+ /* GPIO4 B0-B7 */
+ "", "", "", "HEADER_40_3v3",
+ "HEADER_8_3v3", "HEADER_10_3v3", "", "",
+ /* GPIO4 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO4 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-ramp-delay = <2300>;
+ fcs,suspend-voltage-selector = <1>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-ramp-delay = <2300>;
+ fcs,suspend-voltage-selector = <1>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_npu_s0";
+ regulator-ramp-delay = <2300>;
+ fcs,suspend-voltage-selector = <1>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ fusb302: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&usbc0_int>;
+ pinctrl-names = "default";
+ vbus-supply = <&vbus5v0_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <1000000>;
+ };
+ };
+
+ rtc_hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&hym8563_int>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ pinctrl-0 = <&i2c7m0_xfer>;
+ status = "okay";
+
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ assigned-clock-rates = <12288000>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ AVDD-supply = <&vcc_3v3_s3>;
+ clock-names = "mclk";
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ DVDD-supply = <&vcc_1v8_s3>;
+ HPVDD-supply = <&vcc_3v3_s3>;
+ PVDD-supply = <&vcc_1v8_s3>;
+ #sound-dai-cells = <0>;
+
+ port {
+ es8388_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8388_p0_0>;
+ };
+ };
+};
+
+
+&pinctrl {
+ bluetooth-pins {
+ bt_reset: bt-reset {
+ rockchip,pins =
+ <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_dev: bt-wake-dev {
+ rockchip,pins =
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host: bt-wake-host {
+ rockchip,pins =
+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ hym8563 {
+
+ hym8563_int: hym8563-int {
+ rockchip,pins =
+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins =
+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins =
+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* HS400 modes seemed to cause io errors. */
+&sdhci {
+ bus-width = <8>;
+ no-mmc-hs400;
+ no-sd;
+ no-sdio;
+ non-removable;
+ max-frequency = <200000000>;
+ vmmc-supply = <&vcc_3v3_s0>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
+ non-removable;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ #address-cells = <1>;
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-ramp-delay = <12500>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <750000>;
+ regulator-min-microvolt = <675000>;
+ regulator-name = "vdd_logic_s0";
+ regulator-ramp-delay = <12500>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_vdenc_s0";
+ regulator-ramp-delay = <12500>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <850000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2000000>;
+ regulator-min-microvolt = <2000000>;
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <600000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcca_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "vdda_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcca_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3_pldo6: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3_pldo6";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <750000>;
+ regulator-min-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <750000>;
+ regulator-min-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* Schematics show not in use */
+ nldo-reg5 {
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* DMA seems to interfere with bluetooth device normal operation. */
+&uart9 {
+ pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>;
+ pinctrl-names = "default";
+ /delete-property/ dma-names;
+ /delete-property/ dmas;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8821cs-bt",
+ "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>;
+ pinctrl-names = "default";
+ };
+};
--
2.41.0