rockchip: put all rockchip 32 bit into uboot/v2022.04 directory

2025-09-24 19:47:06 +07:00 · 2023-03-24 18:27:17 +00:00
parent 191f4c8b67
commit 97c3448983
25 changed files with 7787 additions and 1 deletions
--- a/config/kernel/linux-rk322x-current.config.defconfig
+++ b/config/kernel/linux-rk322x-current.config.defconfig
--- a/config/kernel/linux-rk322x-edge.config.defconfig
+++ b/config/kernel/linux-rk322x-edge.config.defconfig
--- a/config/kernel/linux-rockchip-edge.config.defconfig
+++ b/config/kernel/linux-rockchip-edge.config.defconfig
--- a/config/sources/families/rk322x.conf
+++ b/config/sources/families/rk322x.conf
@@ -12,6 +12,7 @@ OVERLAY_PREFIX='rk322x'
 UBOOT_TARGET_MAP="all u-boot.itb;;u-boot-rk322x-with-spl.bin"
 BOOTDELAY=0
 BOOTBRANCH='tag:v2022.04'
+BOOTPATCHDIR='v2022.04'
 ARCH=armhf
 SERIALCON=ttyS2

--- a/config/sources/families/rockchip.conf
+++ b/config/sources/families/rockchip.conf
@@ -18,7 +18,7 @@ if [[ $BOARD == miqi ]]; then
 	BOOTPATCHDIR='legacy'
 else
 	BOOTBRANCH='tag:v2022.04'
-	BOOTPATCHDIR='v2022.07'
+	BOOTPATCHDIR='v2022.04'
 fi

 SERIALCON=ttyS2
--- a/patch/u-boot/v2022.04/board_rk322x-box/dtsi-add-generic-tvbox.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/dtsi-add-generic-tvbox.patch
--- a/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-defconfig.patch
+++ b/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-defconfig.patch
--- a/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch
+++ b/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch
--- a/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree.patch
+++ b/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree.patch
--- a/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-its.patch
+++ b/patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-its.patch
--- a/patch/u-boot/v2022.04/board_rk322x-box/rockchip-device-settings.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/rockchip-device-settings.patch
--- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch
--- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1002-support-rockchip-gmac-rmii.patch
--- a/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/u-boot-1005-support-rockchip-tee-binary.patch
--- a/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch
+++ b/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch
--- a/patch/u-boot/v2022.04/board_tinkerboard/0001-tinkerboard-defconfig-fix.patch
+++ b/patch/u-boot/v2022.04/board_tinkerboard/0001-tinkerboard-defconfig-fix.patch
@@ -0,0 +1,36 @@
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index a9c9a122..842a43fb 100644
+--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
+@@ -17,11 +17,12 @@ CONFIG_DEBUG_UART=y
+ CONFIG_SYS_LOAD_ADDR=0x800800
+ # CONFIG_ANDROID_BOOT_IMAGE is not set
+ CONFIG_USE_PREBOOT=y
+-CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
+CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
+ CONFIG_SILENT_CONSOLE=y
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+ CONFIG_SPL_I2C=y
+ CONFIG_SPL_POWER=y
+ CONFIG_CMD_GPIO=y
+@@ -75,6 +76,7 @@ CONFIG_REGULATOR_RK8XX=y
+ CONFIG_PWM_ROCKCHIP=y
+ CONFIG_RAM=y
+ CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+ CONFIG_DEBUG_UART_SHIFT=2
+ CONFIG_SYSRESET=y
+ CONFIG_USB=y
+@@ -85,6 +87,9 @@ CONFIG_USB_HOST_ETHER=y
+ CONFIG_USB_ETHER_ASIX=y
+ CONFIG_USB_ETHER_SMSC95XX=y
+ CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x7820
+ CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_DM_VIDEO=y
+ CONFIG_DISPLAY=y
--- a/patch/u-boot/v2022.04/board_tinkerboard/0002-tinkerboard-add-emmc.patch
+++ b/patch/u-boot/v2022.04/board_tinkerboard/0002-tinkerboard-add-emmc.patch
@@ -0,0 +1,48 @@
+From b89be51a2e80e7a56ddd444cc57b042594016218 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 19 Mar 2022 21:37:32 +0000
+Subject: [PATCH] rk3288: add emmc to tinkerboard dts
+
+---
+ arch/arm/dts/rk3288-tinker-u-boot.dtsi |  4 ++++
+ arch/arm/dts/rk3288-tinker.dts         | 12 ++++++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+index 56d10c82e..164c72eb7 100644
+--- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+@@ -36,6 +36,10 @@
+ 	u-boot,dm-pre-reloc;
+ };
+ 
+&emmc {
+	u-boot,dm-spl;
+};
+
+ &sdmmc {
+ 	u-boot,dm-spl;
+ };
+diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts
+index 8b1848c31..8db248412 100644
+--- a/arch/arm/dts/rk3288-tinker.dts
+++ b/arch/arm/dts/rk3288-tinker.dts
+@@ -31,3 +31,15 @@
+ 	vbus-supply = <&vcc5v0_host>;
+ 	status = "okay";
+ };
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+	max-frequency = <150000000>;
+	mmc-hs200-1_8v;
+	mmc-ddr-1_8v;
+	status = "okay";
+};
+-- 
+2.30.2
+
--- a/patch/u-boot/v2022.04/board_tinkerboard/0003-UMS-mode-on-otg-port.patch
+++ b/patch/u-boot/v2022.04/board_tinkerboard/0003-UMS-mode-on-otg-port.patch
@@ -0,0 +1,399 @@
+From 2636bc3f11c953c24b3af7334082811737bf475b Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 19 Mar 2022 21:41:38 +0000
+Subject: [PATCH] rk3288: tinkerboard: add UMS mode when USB host is connected
+ to OTG port during boot
+
+---
+ arch/arm/include/asm/arch-rockchip/gpio.h  |  22 ++++
+ arch/arm/mach-rockchip/board.c             | 115 +++++++++++++++++++++
+ arch/arm/mach-rockchip/spl.c               |  23 ++++-
+ cmd/usb_mass_storage.c                     |   9 +-
+ common/autoboot.c                          |  22 ++++
+ common/board_r.c                           |   1 +
+ drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |   1 +
+ drivers/usb/gadget/f_mass_storage.c        |  10 +-
+ include/init.h                             |   1 +
+ include/linux/usb/gadget.h                 |   3 +
+ 10 files changed, 203 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
+index 1aaec5fae..135688d3b 100644
+--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
+@@ -24,6 +24,28 @@ struct rockchip_gpio_regs {
+ };
+ check_member(rockchip_gpio_regs, ls_sync, 0x60);
+ 
+/*
+ * RK3288 IO memory map:
+ *
+ */
+#define RKIO_GPIO0_PHYS                 0xFF750000
+#define RKIO_GRF_PHYS                   0xFF770000
+#define RKIO_GPIO1_PHYS                 0xFF780000
+#define RKIO_GPIO2_PHYS                 0xFF790000
+#define RKIO_GPIO3_PHYS                 0xFF7A0000
+#define RKIO_GPIO4_PHYS                 0xFF7B0000
+#define RKIO_GPIO5_PHYS                 0xFF7C0000
+#define RKIO_GPIO6_PHYS                 0xFF7D0000
+
+/* gpio power down/up control */
+#define GRF_GPIO2A_P		0x150
+#define GRF_GPIO6A_P		0x190
+
+/* gpio input/output control */
+#define GPIO_SWPORT_DR		0x00
+#define GPIO_SWPORT_DDR		0x04
+#define GPIO_EXT_PORT		0x50
+
+ enum gpio_pu_pd {
+ 	GPIO_PULL_NORMAL = 0,
+ 	GPIO_PULL_UP,
+diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
+index ba4da72b3..5ae2c7f8f 100644
+--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
+@@ -17,10 +17,26 @@
+ #include <asm/arch-rockchip/clock.h>
+ #include <asm/arch-rockchip/periph.h>
+ #include <asm/arch-rockchip/misc.h>
+#include <asm/arch-rockchip/gpio.h>
+#include <linux/delay.h>
+ #include <power/regulator.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+enum project_id {
+	TinkerBoardS = 0,
+	TinkerBoard  = 7,
+};
+
+enum pcb_id {
+	SR,
+	ER,
+	PR,
+};
+
+extern bool force_ums;
+
+
+ __weak int rk_board_late_init(void)
+ {
+ 	return 0;
+@@ -33,6 +49,105 @@ int board_late_init(void)
+ 	return rk_board_late_init();
+ }
+ 
+/*
+*
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+*
+*/
+void usb_current_limit_ctrl(bool unlock_current)
+{
+	int tmp;
+
+	printf("%s: unlock_current = %d\n", __func__, unlock_current);
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	if(unlock_current == true)
+		writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	else
+		writel(tmp & ~0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+	writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+}
+
+/*
+*
+* eMMC maskrom mode : GPIO6_A7 (H:disable maskrom, L:enable maskrom)
+*
+*/
+void rk3288_maskrom_ctrl(bool enable_emmc)
+{
+	int tmp;
+
+	printf("%s: enable_emmc = %d\n", __func__, enable_emmc);
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	if(enable_emmc == true)
+		writel(tmp | 0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	else
+		writel(tmp & ~0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+	writel(tmp | 0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+	mdelay(10);
+}
+
+/*
+*
+* project id        : GPIO2_A3 GPIO2_A2 GPIO2_A1
+* pcb id            : GPIO2_B2 GPIO2_B1 GPIO2_B0
+* SDP/CDP           : GPIO6_A5 (H:SDP, L:CDP)
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+* eMMC maskrom mode : GPIO6_A7 (H:disable maskrom, L:enable maskrom)
+*
+* Please check TRM V1.2 part1 page 152 for the following register settings
+*
+*/
+int check_force_enter_ums_mode(void)
+{
+	int tmp;
+	enum pcb_id pcbid;
+	enum project_id projectid;
+
+	// GPIO2_A3/GPIO2_A2/GPIO2_A1 pull up enable
+	tmp = readl(RKIO_GRF_PHYS + GRF_GPIO2A_P);
+	writel((tmp&~(0x03F<<2)) | 0x3F<<(16 + 2) | 0x15<<2, RKIO_GRF_PHYS + GRF_GPIO2A_P);
+
+	// GPIO2_A3/GPIO2_A2/GPIO2_A1/GPIO2_B2/GPIO2_B1/GPIO2_B0 set to input
+	tmp = readl(RKIO_GPIO2_PHYS + GPIO_SWPORT_DDR);
+	writel(tmp & ~(0x70E), RKIO_GPIO2_PHYS + GPIO_SWPORT_DDR);
+
+	// GPIO6_A5 pull up/down disable
+	tmp = readl(RKIO_GRF_PHYS + GRF_GPIO6A_P);
+	writel((tmp&~(0x03<<10)) | 0x03<<(16 + 10), RKIO_GRF_PHYS + GRF_GPIO6A_P);
+
+	// GPIO6_A5 set to input
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+	writel(tmp & ~(0x20), RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+
+	mdelay(10);
+
+	// read GPIO2_A3/GPIO2_A2/GPIO2_A1 value
+	projectid = (readl(RKIO_GPIO2_PHYS + GPIO_EXT_PORT) & 0x0E) >>1;
+
+	// read GPIO2_B2/GPIO2_B1/GPIO2_B0 value
+	pcbid = (readl(RKIO_GPIO2_PHYS + GPIO_EXT_PORT) & 0x700) >> 8;
+
+	// only Tinker Board S and the PR stage PCB has this function
+	if(projectid!=TinkerBoard && pcbid >= ER){
+		printf("PC event = 0x%x\n", readl(RKIO_GPIO6_PHYS + GPIO_EXT_PORT)&0x20);
+		if((readl(RKIO_GPIO6_PHYS + GPIO_EXT_PORT)&0x20)==0x20) {
+			// SDP detected, enable EMMC and unlock usb current limit
+			printf("usb connected to SDP, force enter ums mode\n");
+			force_ums = true;
+			rk3288_maskrom_ctrl(true);
+			usb_current_limit_ctrl(true);
+		} else {
+			usb_current_limit_ctrl(false);
+		}
+	}
+	return 0;
+}
+
+
+ int board_init(void)
+ {
+ 	int ret;
+diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
+index f148d48b6..59daff438 100644
+--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
+@@ -106,6 +106,27 @@ __weak int arch_cpu_init(void)
+ 	return 0;
+ }
+ 
+/*
+*
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+*
+*/
+void usb_current_limit_ctrl(bool unlock_current)
+{
+	int tmp;
+
+#include <asm/arch/gpio.h>
+
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	if(unlock_current == true)
+		writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+	else
+		writel(tmp & ~0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+	tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+	writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+}
+
+ void board_init_f(ulong dummy)
+ {
+ 	int ret;
+@@ -122,7 +143,7 @@ void board_init_f(ulong dummy)
+ 	debug_uart_init();
+ 	debug("\nspl:debug uart enabled in %s\n", __func__);
+ #endif
+-
+	usb_current_limit_ctrl(true);
+ 	board_early_init_f();
+ 
+ 	ret = spl_early_init();
+diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
+index cf2f55994..d406ea453 100644
+--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
+@@ -111,7 +111,7 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
+ 		name = malloc(UMS_NAME_LEN);
+ 		if (!name)
+ 			goto cleanup;
+-		snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
+		snprintf(name, UMS_NAME_LEN, "Armbian UMS disk %d", ums_count);
+ 		ums[ums_count].name = name;
+ 		ums[ums_count].block_dev = *block_dev;
+ 
+@@ -136,7 +136,7 @@ cleanup:
+ 	return ret;
+ }
+ 
+-static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
+int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
+ 			       int argc, char *const argv[])
+ {
+ 	const char *usb_controller;
+@@ -218,6 +218,11 @@ static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
+ 		usb_gadget_handle_interrupts(controller_index);
+ 
+ 		rc = fsg_main_thread(NULL);
+
+		if (rc == -ETIMEDOUT) {
+			goto cleanup_register;
+		}
+
+ 		if (rc) {
+ 			/* Check I/O error */
+ 			if (rc == -EIO)
+diff --git a/common/autoboot.c b/common/autoboot.c
+index e628baffb..eefaa28d4 100644
+--- a/common/autoboot.c
+++ b/common/autoboot.c
+@@ -40,6 +40,9 @@ DECLARE_GLOBAL_DATA_PTR;
+ static int stored_bootdelay;
+ static int menukey;
+ 
+bool force_ums = false;
+bool getdescriptor = false;
+
+ #if !defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
+ #define CONFIG_AUTOBOOT_STOP_STR_CRYPT ""
+ #endif
+@@ -49,6 +52,10 @@ static int menukey;
+ #define AUTOBOOT_MENUKEY 0
+ #endif
+ 
+extern int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+void usb_current_limit_ctrl(bool unlock_current);
+void rk3288_maskrom_ctrl(bool enable_emmc);
+
+ /*
+  * Use a "constant-length" time compare function for this
+  * hash compare:
+@@ -363,6 +370,21 @@ void autoboot_command(const char *s)
+ {
+ 	debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+ 
+	if (force_ums) {
+		// force to enter ums mode
+		char *local_args[4];
+		char str1[]="ums", str2[]="1", str3[]="mmc", str4[]="0";
+
+		local_args[0]=str1;
+		local_args[1]=str2;
+		local_args[2]=str3;
+		local_args[3]=str4;
+		if (do_usb_mass_storage(NULL, 0, 4, local_args) == -ETIMEDOUT) {
+			rk3288_maskrom_ctrl(false);
+			usb_current_limit_ctrl(false);
+		}
+	}
+
+ 	if (s && (stored_bootdelay == -2 ||
+ 		 (stored_bootdelay != -1 && !abortboot(stored_bootdelay)))) {
+ 		bool lock;
+diff --git a/common/board_r.c b/common/board_r.c
+index 29dd7d26d..5b952d00c 100644
+--- a/common/board_r.c
+++ b/common/board_r.c
+@@ -797,6 +797,7 @@ static init_fnc_t init_sequence_r[] = {
+ #ifdef CONFIG_MMC
+ 	initr_mmc,
+ #endif
+	check_force_enter_ums_mode,
+ #ifdef CONFIG_XEN
+ 	initr_xen,
+ #endif
+diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+index f17009a29..b85b3f825 100644
+--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+@@ -1393,6 +1393,7 @@ static void dwc2_ep0_setup(struct dwc2_udc *dev)
+ 			debug_cond(DEBUG_SETUP != 0,
+ 				   "%s: *** USB_REQ_GET_DESCRIPTOR\n",
+ 				   __func__);
+			getdescriptor = true;
+ 			break;
+ 
+ 		case USB_REQ_SET_INTERFACE:
+diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
+index 45f0504b6..80706d41b 100644
+--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
+@@ -655,7 +655,7 @@ static void busy_indicator(void)
+ static int sleep_thread(struct fsg_common *common)
+ {
+ 	int	rc = 0;
+-	int i = 0, k = 0;
+	int i = 0, k = 0, j = 0;
+ 
+ 	/* Wait until a signal arrives or we are woken up */
+ 	for (;;) {
+@@ -666,6 +666,7 @@ static int sleep_thread(struct fsg_common *common)
+ 			busy_indicator();
+ 			i = 0;
+ 			k++;
+			j++;
+ 		}
+ 
+ 		if (k == 10) {
+@@ -680,6 +681,13 @@ static int sleep_thread(struct fsg_common *common)
+ 			k = 0;
+ 		}
+ 
+		if (j == 300) {  //about 3 seconds
+			if(force_ums && !getdescriptor) {
+				printf("wait for usb get descriptor cmd timeout\n");
+				return -ETIMEDOUT;
+			}
+		}
+
+ 		usb_gadget_handle_interrupts(controller_index);
+ 	}
+ 	common->thread_wakeup_needed = 0;
+diff --git a/include/init.h b/include/init.h
+index 0f48ccb57..bae1cb88e 100644
+--- a/include/init.h
+++ b/include/init.h
+@@ -261,6 +261,7 @@ int board_early_init_f(void);
+ /* manipulate the U-Boot fdt before its relocation */
+ int board_fix_fdt(void *rw_fdt_blob);
+ int board_late_init(void);
+int check_force_enter_ums_mode (void);
+ int board_postclk_init(void); /* after clocks/timebase, before env/serial */
+ int board_early_init_r(void);
+ 
+diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
+index 06292ddeb..48709f3b0 100644
+--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
+@@ -25,6 +25,9 @@
+ 
+ struct usb_ep;
+ 
+extern bool force_ums;
+extern bool getdescriptor;
+
+ /**
+  * struct usb_request - describes one i/o request
+  * @buf: Buffer used for data.  Always provide this; some controllers
+-- 
+2.30.2
+
--- a/patch/u-boot/v2022.04/board_tinkerboard/0004-make-emmc-bootable.patch
+++ b/patch/u-boot/v2022.04/board_tinkerboard/0004-make-emmc-bootable.patch
@@ -0,0 +1,53 @@
+From e8926f5e4dd307c01b59883db7ae76e67bb47894 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 19 Mar 2022 12:58:06 +0000
+Subject: [PATCH] rk3288: tinkerboard-s emmc boot
+
+---
+ include/configs/tinker_rk3288.h | 9 +--------
+ 1 file changed, 1 insertion(+), 8 deletions(-)
+
+diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
+index 269ec529..e19fa902 100644
+--- a/include/configs/tinker_rk3288.h
+++ b/include/configs/tinker_rk3288.h
+@@ -13,13 +13,6 @@
+ 
+ #include <configs/rk3288_common.h>
+ 
+-#undef BOOT_TARGET_DEVICES
+-
+-#define BOOT_TARGET_DEVICES(func) \
+-	func(MMC, mmc, 0) \
+-	func(MMC, mmc, 1) \
+-	func(USB, usb, 0) \
+-	func(PXE, pxe, na) \
+-	func(DHCP, dchp, na)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+ 
+ #endif
+
+From b8a75200b11fc0005a8e12192473159e51abd29c Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 19 Mar 2022 13:05:33 +0000
+Subject: [PATCH] rk3288: fix redefined symbol
+
+---
+ include/configs/tinker_rk3288.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
+index e19fa9021..bde7d72e6 100644
+--- a/include/configs/tinker_rk3288.h
+++ b/include/configs/tinker_rk3288.h
+@@ -13,6 +13,7 @@
+ 
+ #include <configs/rk3288_common.h>
+ 
+#undef CONFIG_SYS_MMC_ENV_DEV
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ 
+ #endif
+-- 
+2.30.2
+
--- a/patch/u-boot/v2022.04/board_tinkerboard/add-overlay-support.patch
+++ b/patch/u-boot/v2022.04/board_tinkerboard/add-overlay-support.patch
@@ -0,0 +1,13 @@
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 8a23c76d..bb1e3cb7 100644
+--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
+@@ -1321,6 +1321,8 @@ config ARCH_ROCKCHIP
+ 	select DM_SPI_FLASH
+ 	select DM_USB if USB
+ 	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select OF_LIBFDT
+	select OF_LIBFDT_OVERLAY
+ 	select OF_CONTROL
+ 	select SPI
+ 	select SPL_DM if SPL
--- a/patch/u-boot/v2022.04/board_xt-q8l-v10/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch
+++ b/patch/u-boot/v2022.04/board_xt-q8l-v10/u-boot-1000-enable-rockchip-efuse-for-rk322x-rk3288-and-rk3328.patch
@@ -0,0 +1,362 @@
+From 768ff9ab40cc54e03895a46a4818d36dec150cac Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 4 Apr 2021 10:29:29 +0000
+Subject: [PATCH] Enable rockchip efuse for rk322x, rk3288 and rk3328
+
+---
+ arch/arm/dts/rk322x.dtsi               |  14 +++
+ arch/arm/dts/rk3288.dtsi               |   3 +-
+ configs/evb-rk3229_defconfig           |   3 +
+ configs/evb-rk3328_defconfig           |   3 +
+ configs/miqi-rk3288_defconfig          |   2 +
+ configs/rock64-rk3328_defconfig        |   2 +
+ configs/tinker-rk3288_defconfig        |   1 +
+ configs/tinker-s-rk3288_defconfig      |   1 +
+ drivers/misc/rockchip-efuse.c          | 142 ++++++++++++++++++++++++-
+ include/dt-bindings/clock/rk3228-cru.h |   4 +
+ 10 files changed, 169 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
+index 4a8be5dabb..255e3a7a28 100644
+--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
+@@ -212,6 +212,20 @@
+ 		status = "disabled";
+ 	};
+ 
+	efuse: efuse@11040000 {
+		compatible = "rockchip,rk3228-efuse", "rockchip,rk3288-efuse";
+		reg = <0x11040000 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Data cells */
+		cpu_id: cpu_id@7 {
+			reg = <0x7 0x10>;
+		};
+	};
+
+ 	i2c0: i2c@11050000 {
+ 		compatible = "rockchip,rk3228-i2c";
+ 		reg = <0x11050000 0x1000>;
+diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
+index 22bb06cec5..381391360c 100644
+--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
+@@ -919,8 +919,7 @@
+ 
+ 	efuse: efuse@ffb40000 {
+ 		compatible = "rockchip,rk3288-efuse";
+-		reg = <0xffb40000 0x10000>;
+-		status = "disabled";
+		reg = <0xffb40000 0x20>;
+ 	};
+ 
+ 	gic: interrupt-controller@ffc01000 {
+diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
+index e708ed4909..e3ba0651fd 100644
+--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
+@@ -49,6 +49,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_MTD=y
+@@ -68,3 +70,4 @@ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+CONFIG_MISC_INIT_R=y
+diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
+index 9cbfeb0279..f0acfd8abd 100644
+--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
+@@ -20,6 +20,7 @@ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
+CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+@@ -56,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_SF_DEFAULT_SPEED=20000000
+diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
+index 234ced5ab0..3d42e93866 100644
+--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
+@@ -49,6 +49,8 @@ CONFIG_SPL_CLK=y
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_MTD=y
+diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
+index cb79cea821..dacb57165e 100644
+--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
+@@ -57,6 +57,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_SF_DEFAULT_SPEED=20000000
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index 8686a66d13..b7dc845451 100644
+--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
+@@ -52,6 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
+index 22714833cc..19aa314164 100644
+--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
+@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
+index 083ee65e0a..0fcbcfc69a 100644
+--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
+@@ -14,6 +14,7 @@
+ #include <linux/bitops.h>
+ #include <linux/delay.h>
+ #include <misc.h>
+#include <stdlib.h>
+ 
+ #define RK3399_A_SHIFT          16
+ #define RK3399_A_MASK           0x3ff
+@@ -27,6 +28,24 @@
+ #define RK3399_STROBE           BIT(1)
+ #define RK3399_CSB              BIT(0)
+ 
+#define RK3288_A_SHIFT          6
+#define RK3288_A_MASK           0x3ff
+#define RK3288_NFUSES           32
+#define RK3288_BYTES_PER_FUSE   1
+#define RK3288_PGENB            BIT(3)
+#define RK3288_LOAD             BIT(2)
+#define RK3288_STROBE           BIT(1)
+#define RK3288_CSB              BIT(0)
+
+#define RK3328_INT_STATUS	0x0018
+#define RK3328_DOUT		0x0020
+#define RK3328_AUTO_CTRL	0x0024
+#define RK3328_INT_FINISH	BIT(0)
+#define RK3328_AUTO_ENB		BIT(0)
+#define RK3328_AUTO_RD		BIT(1)
+
+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
+
+ struct rockchip_efuse_regs {
+ 	u32 ctrl;      /* 0x00  efuse control register */
+ 	u32 dout;      /* 0x04  efuse data out register */
+@@ -35,6 +54,10 @@ struct rockchip_efuse_regs {
+ 	u32 jtag_pass; /* 0x10  JTAG password */
+ 	u32 strobe_finish_ctrl;
+ 		       /* 0x14	efuse strobe finish control register */
+	u32 int_status;/* 0x18 */
+	u32 reserved;  /* 0x1c */
+	u32 dout2;     /* 0x20 */
+	u32 auto_ctrl; /* 0x24 */
+ };
+ 
+ struct rockchip_efuse_plat {
+@@ -53,7 +76,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
+ 	 */
+ 
+ 	struct udevice *dev;
+-	u8 fuses[128];
+	u8 fuses[128] = {0};
+ 	int ret;
+ 
+ 	/* retrieve the device */
+@@ -77,7 +100,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
+ }
+ 
+ U_BOOT_CMD(
+-	rk3399_dump_efuses, 1, 1, dump_efuses,
+	rockchip_dump_efuses, 1, 1, dump_efuses,
+ 	"Dump the content of the efuses",
+ 	""
+ );
+@@ -127,10 +150,110 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
+ 	return 0;
+ }
+ 
+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
+				      void *buf, int size)
+{
+	struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+	struct rockchip_efuse_regs *efuse =
+		(struct rockchip_efuse_regs *)plat->base;
+	u8 *buffer = buf;
+	int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
+
+	if (size > (max_size - offset))
+		size = max_size - offset;
+
+	/* Switch to read mode */
+	writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl);
+	udelay(1);
+
+	while (size--) {
+		writel(readl(&efuse->ctrl) &
+				(~(RK3288_A_MASK << RK3288_A_SHIFT)),
+				&efuse->ctrl);
+		/* set addr */
+		writel(readl(&efuse->ctrl) |
+				((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
+				&efuse->ctrl);
+		udelay(1);
+		/* strobe low to high */
+		writel(readl(&efuse->ctrl) |
+				RK3288_STROBE, &efuse->ctrl);
+		ndelay(60);
+		/* read data */
+		*buffer++ = readl(&efuse->dout);
+		/* reset strobe to low */
+		writel(readl(&efuse->ctrl) &
+				(~RK3288_STROBE), &efuse->ctrl);
+		udelay(1);
+	}
+
+	/* Switch to standby mode */
+	writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl);
+
+	return 0;
+}
+
+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
+				      void *buf, int size)
+{
+	struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+	struct rockchip_efuse_regs *efuse =
+		(struct rockchip_efuse_regs *)plat->base;
+	unsigned int addr_start, addr_end, addr_offset, addr_len;
+	u32 out_value, status;
+	u8 *buffer;
+	int ret = 0, i = 0, j = 0;
+
+	/* Max non-secure Byte */
+	if (size > 32)
+		size = 32;
+
+	/* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
+	offset += 96;
+	addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) /
+						RK3399_BYTES_PER_FUSE;
+	addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) /
+						RK3399_BYTES_PER_FUSE;
+	addr_offset = offset % RK3399_BYTES_PER_FUSE;
+	addr_len = addr_end - addr_start;
+
+	buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE);
+	if (!buffer)
+		return -ENOMEM;
+
+	for (j = 0; j < addr_len; j++) {
+		writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
+		       ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
+		         &efuse->auto_ctrl);
+		udelay(5);
+		status = readl(&efuse->int_status);
+		if (!(status & RK3328_INT_FINISH)) {
+			ret = -EIO;
+			goto err;
+		}
+		out_value = readl(&efuse->dout2);
+		writel(RK3328_INT_FINISH, &efuse->int_status);
+
+		memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE);
+		i += RK3399_BYTES_PER_FUSE;
+	}
+	memcpy(buf, buffer + addr_offset, size);
+err:
+	free(buffer);
+
+	return ret;
+}
+
+ static int rockchip_efuse_read(struct udevice *dev, int offset,
+ 			       void *buf, int size)
+ {
+-	return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+	EFUSE_READ efuse_read = NULL;
+
+	efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
+	if (!efuse_read)
+		return -ENOSYS;
+
+	return (*efuse_read)(dev, offset, buf, size);
+ }
+ 
+ static const struct misc_ops rockchip_efuse_ops = {
+@@ -146,7 +269,18 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev)
+ }
+ 
+ static const struct udevice_id rockchip_efuse_ids[] = {
+-	{ .compatible = "rockchip,rk3399-efuse" },
+	{
+		.compatible = "rockchip,rk3288-efuse",
+		.data = (ulong)&rockchip_rk3288_efuse_read,
+	},
+	{
+		.compatible = "rockchip,rk3328-efuse",
+		.data = (ulong)&rockchip_rk3328_efuse_read,
+	},
+	{
+		.compatible = "rockchip,rk3399-efuse",
+		.data = (ulong)&rockchip_rk3399_efuse_read,
+	},
+ 	{}
+ };
+ 
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index 1217d5239f..13b2f4e4a4 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -67,6 +67,10 @@
+ #define PCLK_GPIO1		321
+ #define PCLK_GPIO2		322
+ #define PCLK_GPIO3		323
+#define PCLK_VIO_H2P		324
+#define PCLK_HDCP		325
+#define PCLK_EFUSE_1024	326
+#define PCLK_EFUSE_256 	327
+ #define PCLK_GRF		329
+ #define PCLK_I2C0		332
+ #define PCLK_I2C1		333
+-- 
+2.25.1
+
--- a/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-defconfig.patch
+++ b/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-defconfig.patch
@@ -0,0 +1,103 @@
+diff --git a/configs/xt-q8l-v10-rk3288_defconfig b/configs/xt-q8l-v10-rk3288_defconfig
+new file mode 100644
+index 00000000..182451c6
+--- /dev/null
+++ b/configs/xt-q8l-v10-rk3288_defconfig
+@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-xt-q8l-v10"
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_XT_Q8L_V10_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYS_LOAD_ADDR=0x03000000
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x8000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_TPL_OF_PLATDATA is not set
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_ACT8846=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_SHA256=y
+CONFIG_ERRNO_STR=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- a/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-device-tree-makefile.patch
+++ b/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-device-tree-makefile.patch
@@ -0,0 +1,144 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 0127a91a..ae99b02a 100644
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
+ 	rk3288-rock2-square.dtb \
+ 	rk3288-tinker.dtb \
+ 	rk3288-tinker-s.dtb \
+	rk3288-xt-q8l-v10.dtb \
+ 	rk3288-veyron-jerry.dtb \
+ 	rk3288-veyron-mickey.dtb \
+ 	rk3288-veyron-minnie.dtb \
+diff --git a/board/rockchip/xt-q8l-v10_rk3288/Kconfig b/board/rockchip/xt-q8l-v10_rk3288/Kconfig
+index e69de29..176abf0 100644
+--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/Kconfig
+@@ -0,0 +1,15 @@
+if TARGET_XT_Q8L_V10_RK3288
+
+config SYS_BOARD
+	default "xt-q8l-v10_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "xt-q8l-v10_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+diff --git a/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS b/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS
+index e69de29..9a3ad97 100644
+--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS
+@@ -0,0 +1,6 @@
+XT-Q8L-V10-RK3288
+M:	Paolo Sabatino <a@b.c>
+S:	Not mainlined
+F:	board/rockchip/xt-q8l-v10_rk3288
+F:	include/configs/xt-q8l-v10_rk3288.h
+F:	configs/xt-q8l-v10-rk3288_defconfig
+diff --git a/board/rockchip/xt-q8l-v10_rk3288/Makefile b/board/rockchip/xt-q8l-v10_rk3288/Makefile
+index e69de29..852c910 100644
+--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/Makefile
+@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= xt-q8l-v10-rk3288.o
+diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
+index afb62fca..187a75ba 100644
+--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
+@@ -131,6 +131,16 @@ config TARGET_TINKER_RK3288
+ 	  8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
+ 	  I2C, SPI, UART, GPIOs.
+ 
+config TARGET_XT_Q8L_V10_RK3288
+       bool "xt-q8l-v10 tvbox board"
+       select BOARD_LATE_INIT
+       select TPL
+       help
+         xt-q8l-v10 is a RK3288 common tv box with 3 USB ports (1 OTG), HDMI,
+         micro-SD card, Gigabit Ethernet and SPDIF output. It also includes on-board
+         8GB eMMC and 2GB of SDRAM, 802.11n Wifi and Bluetooth based upon AP6330
+         WiSoC.
+
+ endchoice
+ 
+ config ROCKCHIP_FAST_SPL
+@@ -193,4 +203,6 @@ source "board/rockchip/evb_rk3288/Kconfig"
+ 
+ source "board/rockchip/tinker_rk3288/Kconfig"
+ 
+source "board/rockchip/xt-q8l-v10_rk3288/Kconfig"
+
+ endif
+diff --git a/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c b/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
+new file mode 100644
+index 00000000..f0f618a5
+--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
+@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/gpio.h>
+
+void spl_board_init(void)
+{
+
+	/*
+        * xt-q8l-v10 requires the power-hold gpio set (A11, or bank 0 pin 11
+        * if you prefer) as soon as possible.
+        * We hack it here :P
+        */
+       gpio_request(11, "power-hold");
+       gpio_direction_output(11, 1);
+
+}
+
+diff --git a/include/configs/xt-q8l-v10_rk3288.h b/include/configs/xt-q8l-v10_rk3288.h
+new file mode 100644
+index 00000000..1211875a
+--- /dev/null
+++ b/include/configs/xt-q8l-v10_rk3288.h
+@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,usbkbd\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+        func(MMC, mmc, 1) \
+        func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+        func(PXE, pxe, na) \
+        func(DHCP, dchp, na)
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
--- a/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-device-tree.patch
+++ b/patch/u-boot/v2022.04/board_xt-q8l-v10/xt-q8l-v10-device-tree.patch
@@ -0,0 +1,755 @@
+diff --git a/arch/arm/dts/rk3288-xt-q8l-v10.dts b/arch/arm/dts/rk3288-xt-q8l-v10.dts
+new file mode 100755
+index 00000000..be7a0806
+--- /dev/null
+++ b/arch/arm/dts/rk3288-xt-q8l-v10.dts
+@@ -0,0 +1,749 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
+ * 					   2018 Paolo Sabatino <paolo.sabatino@gm**l.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "XT-Q8L-V10-RK3288";
+	compatible = "generic,xt-q8l-v10-rk3288", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = &uart2;
+		/*
+		 * We leave this here for future reference, but at the moment
+		 * rk3288 does not support "same-as-spl", instead as a workaround
+		 * we define the boot order statically in:
+		 * board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
+		 *
+		 */
+		u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
+	};
+
+	config {
+		u-boot,dm-spl;
+		u-boot,boot-led = "power";
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cpu0_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp@1416000000 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1200000>;
+		};
+		opp@1512000000 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-microvolt = <1250000>;
+		};
+		opp@1608000000 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1300000>;
+		};
+
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_key>;
+
+		button@0 {
+			gpio-key,wakeup;
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			label = "GPIO Power";
+			linux,code = <116>;
+			wakeup-source;
+		};
+
+	};
+
+	leds {
+		u-boot,dm-spl;
+		compatible = "gpio-leds";
+
+		power {
+			gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+			u-boot,dm-spl;
+			label = "power";
+			pinctrl-names = "default";
+			pinctrl-0 = <&power_led>;
+		};
+
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_host_5v: usb-host-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_host_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	        regulator-boot-on;
+	        enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+
+	vcc_otg_5v: usb-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_otg_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+	io_domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+		audio-supply = <&vcca_33>;
+		bb-supply = <&vcc_io>;
+		dvp-supply = <&vcc_18>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vcc_lan>;
+		gpio30-supply = <&vcc_io>;
+		gpio1830-supply = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vcc_18>;
+	};
+
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+	operating-points-v2 = <&cpu0_opp_table>;
+	/delete-node/operating-points;
+	/*
+	// Rewrite the operating points table
+	operating-points = <
+		1608000 1350000
+		1512000 1300000
+		1416000 1200000
+		1200000 1100000
+		1008000 1050000
+		 816000 1000000
+		 696000  950000
+		 600000  900000
+	>;
+	*/
+
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_audio {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		system-power-controller;
+
+		vp1-supply = <&vcc_sys>;
+		vp2-supply = <&vcc_sys>;
+		vp3-supply = <&vcc_sys>;
+		vp4-supply = <&vcc_sys>;
+		inl1-supply = <&vcc_sys>;
+		inl2-supply = <&vcc_sys>;
+		inl3-supply = <&vcc_20>;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc_io: vcc33_lcd: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcca_18: REG7 {
+				regulator-name = "vcca_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			vcca_33: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vcc_lan: REG9 {
+				regulator-name = "vcc_lan";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vccio_wl: vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&pinctrl {
+
+	u-boot,dm-pre-reloc;
+
+	/*
+		This pin configuration enables the power led and, most important,
+		the power hold pin of the act8846 pmic. Without the power hold
+		bit set, the pmic will shut itself down after a few milliseconds,
+		turning off the whole device. Be aware that in u-boot configuration
+		"pinctrl-names" and "pinctrl-0" properties MUST NOT be stripped
+		away from SPL.
+		Note also that we set the pwr_hold GPIO in board_init_f()
+		function directly in SPL u-boot code which gets executed very soon.
+		The definition here is just a way to be sure that the bit is set
+		again later.
+	*/
+	pinctrl-names = "default";
+	pinctrl-0 = <&power_led>, <&pwr_hold>;
+
+	pcfg_output_high: pcfg-output-high {
+		u-boot,dm-spl;
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_wl: pcfg-wl {
+                bias-pull-up;
+                drive-strength = <8>;
+        };
+
+        pcfg_wl_clk: pcfg-wl-clk {
+                bias-disable;
+                drive-strength = <12>;
+        };
+
+	pcfg_wl_int: pcfg-wl-int {
+                bias-pull-up;
+        };
+
+
+	act8846 {
+
+		/*
+		 * Original q8 device tree says:
+		 *  - gpio0 11 HIGH -> power hold
+		 *  - gpio7 1 LOW -> possibly pmic-vsel, we omit it here
+		 */
+		/*pmic_vsel: pmic-vsel {
+			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+		};*/
+
+		pwr_hold: pwr-hold {
+			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	keys {
+		pwr_key: pwr-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+
+		power_led: power-led {
+			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host1 {
+
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+    };
+
+	usb_otg {
+
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&emmc {
+	/*
+	 * eMMC seems to be 52Mhz device on q8 devices, so set it here
+	 * vmmc-supply and vqmmc-supply are removed because they hang
+	 * u-boot >= v2018.03
+	 * From the original q8l firmware and eMMC datasheet it also should
+	 * support DDR highspeed mode, but using mmc-ddr-3_3v or mmc-ddr-1_8v
+	 * properties are not working
+	 */
+	clock-frequency = <50000000>;
+
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+
+	status = "okay";
+	u-boot,dm-spl;
+
+};
+
+&sdmmc {
+	bus-width = <4>;
+	supports-sd;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	//vmmc-supply = <&vcc_sd>;
+	//vqmmc-supply = <&vccio_sd>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+/*
+ * Accessible serial port for logging
+ */
+&uart2 {
+	dmas = <&dmac_bus_s 4 &dmac_bus_s 5>;
+	dma-names = "tx", "rx";
+	status = "okay";
+};
+
+/*
+ * Describing resets for usb phy is important because otherwise the USB
+ * port gets stuck in case it goes into autosuspend: plugging any device
+ * when the port is autosuspended will actually kill the port itself and
+ * require a power cycle.
+ * This is required for the usbphy1 phy, nonetheless it is a good idea to
+ * specify the proper resources for all the phys though.
+ * The reference patch which works in conjuction with the reset lines:
+ * https://patchwork.kernel.org/patch/9469811/
+ */
+&usbphy {
+	status = "okay";
+};
+
+&usbphy0 {
+    resets = <&cru SRST_USBOTG_PHY>;
+    reset-names = "phy-reset";
+    vbus-supply = <&vcc_otg_5v>;
+};
+
+&usbphy1 {
+    resets = <&cru SRST_USBHOST0_PHY>;
+    reset-names = "phy-reset";
+};
+
+&usbphy2 {
+    resets = <&cru SRST_USBHOST1_PHY>;
+    reset-names = "phy-reset";
+    vbus-supply = <&vcc_host_5v>;
+};
+
+&usb_host0_ehci {
+    dr_mode = "host";
+    reg = <0x0 0xff500000 0x0 0x20000>;
+    status = "disabled";
+};
+
+/*
+ * Enable the host only USB controller. vbus-supply property allows u-boot
+ * to turn power on for the vbus and allow booting from USB devices
+ */
+&usb_host1 {
+    dr_mode = "host";
+    vbus-supply = <&vcc_host_5v>;
+	status = "okay";
+};
+
+/*
+ * Enable the OTG USB controller. hnp-srp-disable is necessary to allow
+ * it work while in u-boot. Also we attach it to the proper regulator
+ * to enable power during boot phase and allow booting from USB devices
+ */
+&usb_otg {
+	hnp-srp-disable;
+    vbus-supply = <&vcc_otg_5v>;
+	status = "okay";
+};
+
+/*
+ * Disabling vop big because somewhere in some documentation it is stated
+ * that only one vop should be enabled to get video console
+ */
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+/*
+ * xt-q8l-v10 timing registers, dumped directly from a live instance
+ * initialized by the binary rockchip blob.
+ *
+ * pctl-timing are dumped from address 0xff6100c0 to 0xff610144
+ * phy-timing are dumped from address 0xff620030 to 0xff620050
+ * sdram-params are extracted from interconnect, in particular the
+ * service_bus/msch0 part starting at address 0xffac0000 (see section 6.4.2
+ * of the TRM V1.0 manual)
+ */
+&dmc {
+	rockchip,pctl-timing = <0x00000190 0x000000c8 0x00000000 0x00000028
+							0x00000026 0x00000005 0x00000054 0x0002000a
+							0x00000005 0x00000000 0x00000006 0x00000003
+							0x00000011 0x0000001b 0x0000000a 0x00000004
+							0x00000003 0x00000006 0x00000003 0x00000058
+							0x00000003 0x00000000 0x00000024 0x00000000
+							0x00000001 0x00000001 0x00000002 0x00000003
+							0x00000000 0x00000000 0x00000090 0x00000002
+							0x00000006 0x000001f4>;
+	rockchip,phy-timing = <0x3691aa6f 0x185408a0 0x00118c58
+							0x00000000 0x00000083 0x00000004 0x00000001>;
+	/*
+	 * rockchip,sdram-params structure:
+	 *
+	   u32 noc_timing;
+	   u32 noc_activate;
+	   u32 ddrconfig;
+	   u32 ddr_freq;
+	   u32 dramtype;
+		 * DDR Stride is address mapping for DRAM space
+		 * Stride	Ch 0 range	Ch1 range	Total
+		 * 0x00		0-256MB		256MB-512MB	512MB
+		 * 0x05		0-1GB		0-1GB		1GB
+		 * 0x09		0-2GB		0-2GB		2GB
+		 * 0x0d		0-4GB		0-4GB		4GB
+		 * 0x17		N/A		0-4GB		4GB
+		 * 0x1a		0-4GB		4GB-8GB		8GB
+	  u32 stride;
+	  u32 odt;
+
+	 */
+	rockchip,sdram-params = <0x18b1d4db 0x544 0x2 400000000 5 0x9 0>;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&i2c5 {
+	status="okay";
+	u-boot,dm-spl;
+};
+
+&pcfg_pull_up {
+	u-boot,dm-spl;
+};
+
--- a/patch/u-boot/u-boot-rk322x/zzz-usb-otg-fix.patch
+++ b/patch/u-boot/u-boot-rk322x/zzz-usb-otg-fix.patch