Adjust broken patches and move sunxi to latest tag (#3876)

* Bump sunxi kernels

* Adjust remaining patches
This commit is contained in:
Igor Pečovnik
2022-06-11 18:01:32 +02:00
committed by GitHub
parent 07d263283e
commit 85958994b5
9 changed files with 121 additions and 404 deletions

View File

@@ -13,7 +13,7 @@ case $BRANCH in
legacy)
KERNEL_VERSION_LEVEL="5.10"
KERNELSWITCHOBJ="tag=v5.10.119"
KERNELSWITCHOBJ="tag=v5.10.121"
;;
current)

View File

@@ -14,7 +14,7 @@ case $BRANCH in
legacy)
KERNEL_VERSION_LEVEL="5.10"
KERNELSWITCHOBJ="tag=v5.10.119"
KERNELSWITCHOBJ="tag=v5.10.121"
;;
current)
KERNEL_VERSION_LEVEL="5.15"

View File

@@ -0,0 +1,83 @@
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 2cc6d99..19e05ad 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/dmaengine.h>
+#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -185,6 +186,10 @@ struct rockchip_spi {
bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
};
+struct rockchip_spi_data {
+ bool cs_gpio_requested;
+};
+
static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
{
writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
@@ -455,6 +460,50 @@ static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
return 1;
}
+static int rockchip_spi_setup(struct spi_device *spi)
+{
+ int ret = 0;
+ unsigned long flags = (spi->mode & SPI_CS_HIGH) ?
+ GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
+ struct rockchip_spi_data *data = spi_get_ctldata(spi);
+
+ if (!gpio_is_valid(spi->cs_gpio))
+ return 0;
+
+ if (!data) {
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ spi_set_ctldata(spi, data);
+ }
+
+ if (!data->cs_gpio_requested) {
+ ret = gpio_request_one(spi->cs_gpio, flags,
+ dev_name(&spi->dev));
+ if (!ret)
+ data->cs_gpio_requested = 1;
+ } else
+ ret = gpio_direction_output(spi->cs_gpio, flags);
+
+ if (ret < 0)
+ dev_err(&spi->dev, "Failed to setup cs gpio(%d): %d\n",
+ spi->cs_gpio, ret);
+
+ return ret;
+}
+
+static void rockchip_spi_cleanup(struct spi_device *spi)
+{
+ struct rockchip_spi_data *data = spi_get_ctldata(spi);
+
+ if (data) {
+ if (data->cs_gpio_requested)
+ gpio_free(spi->cs_gpio);
+ kfree(data);
+ spi_set_ctldata(spi, NULL);
+ }
+}
+
static int rockchip_spi_config(struct rockchip_spi *rs,
struct spi_device *spi, struct spi_transfer *xfer,
bool use_dma)
@@ -683,6 +732,8 @@ static int rockchip_spi_probe(struct platform_device *pdev)
ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
ctlr->set_cs = rockchip_spi_set_cs;
+ ctlr->setup = rockchip_spi_setup;
+ ctlr->cleanup = rockchip_spi_cleanup;
ctlr->transfer_one = rockchip_spi_transfer_one;
ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
ctlr->handle_err = rockchip_spi_handle_err;

View File

@@ -128,39 +128,6 @@ index 65a8334a188b..f4c5ee4a1e26 100644
return 0;
}
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000
Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
The luma and chroma bit depth fields in the pps packet is 3 bits wide.
8 is wrongly added to the bit depth value written to these 3-bit fields.
Because only the 3 LSB is written the hardware is configured correctly.
Correct this by not adding 8 to the luma and chroma bit depth value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 9852c3519f56..f3ff3e709169 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
WRITE_PPS(0xff, PROFILE_IDC);
WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
- WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
- WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000

View File

@@ -98,27 +98,6 @@ index c9a551dbd9bc..6ce11b736363 100644
/*
* Assign an invalid pic_num if DPB entry at that position is inactive.
* If we assign 0 in that position hardware will treat that as a real
@@ -763,19 +767,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
u8 dpb_valid = 0;
- u8 idx = 0;
-
- switch (j) {
- case 0:
- idx = h264_ctx->reflists.p[i];
- break;
- case 1:
- idx = h264_ctx->reflists.b0[i];
- break;
- case 2:
- idx = h264_ctx->reflists.b1[i];
- break;
- }
+ u8 idx = reflists[j][i];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
@@ -143,88 +122,6 @@ index 6ce11b736363..9c3f08c94800 100644
u16 *p = (u16 *)hw_rps;
memset(hw_rps, 0, sizeof(priv_tbl->rps));
@@ -764,18 +764,71 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
p[i] = dpb[i].frame_num - max_frame_num;
}
- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
- u8 dpb_valid = 0;
- u8 idx = reflists[j][i];
+ if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) {
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
+ u8 dpb_valid = 0;
+ u8 idx = reflists[j][i];
- if (idx >= ARRAY_SIZE(dec_params->dpb))
- continue;
- dpb_valid = !!(dpb[idx].flags &
- V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ dpb_valid = !!(dpb[idx].flags &
+ V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
- set_ps_field(hw_rps, DPB_INFO(i, j),
- idx | dpb_valid << 4);
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | dpb_valid << 4);
+ }
+ }
+ return;
+ }
+
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ enum v4l2_h264_field_reference a_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
+ enum v4l2_h264_field_reference b_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
+ u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
+ i = 0;
+
+ for (k = 0; k < 2; k++) {
+ u8 a = 0;
+ u8 b = 0;
+ u32 long_term = k ? V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM : 0;
+
+ while (a < h264_ctx->reflists.num_valid || b < h264_ctx->reflists.num_valid) {
+ for (; a < h264_ctx->reflists.num_valid; a++) {
+ u8 idx = reflists[j][a];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & a_parity) == a_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ a_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ a++;
+ break;
+ }
+ }
+ for (; b < h264_ctx->reflists.num_valid; b++) {
+ u8 idx = reflists[j][b];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & b_parity) == b_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ b_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ b++;
+ break;
+ }
+ }
+ }
}
}
}
@@ -968,10 +1021,6 @@ static void config_registers(struct rkvdec_ctx *ctx,
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15);
}
@@ -431,52 +328,6 @@ index 7b56a68c176c..befa69d5c855 100644
if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 13:42:01 +0200
Subject: [PATCH] media: rkvdec: adapt to match 5.11 H.264 uapi changes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 9c3f08c94800..7238117b6cf4 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
}
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- enum v4l2_h264_field_reference a_parity =
+ u8 a_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
- enum v4l2_h264_field_reference b_parity =
+ u8 b_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
@@ -802,7 +802,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][a];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & a_parity) == a_parity &&
+ if ((dpb[idx].fields & a_parity) == a_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
@@ -817,7 +817,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][b];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & b_parity) == b_parity &&
+ if ((dpb[idx].fields & b_parity) == b_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 6 Jan 2019 01:48:37 +0800

View File

@@ -3505,10 +3505,9 @@ index da32a6350344..4fb05e8b5a54 100644
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev)
@@ -1218,5 +1255,6 @@ static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
struct resource *res;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;

View File

@@ -128,39 +128,6 @@ index 65a8334a188b..f4c5ee4a1e26 100644
return 0;
}
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000
Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
The luma and chroma bit depth fields in the pps packet is 3 bits wide.
8 is wrongly added to the bit depth value written to these 3-bit fields.
Because only the 3 LSB is written the hardware is configured correctly.
Correct this by not adding 8 to the luma and chroma bit depth value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 9852c3519f56..f3ff3e709169 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
WRITE_PPS(0xff, PROFILE_IDC);
WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
- WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
- WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000

View File

@@ -98,27 +98,6 @@ index c9a551dbd9bc..6ce11b736363 100644
/*
* Assign an invalid pic_num if DPB entry at that position is inactive.
* If we assign 0 in that position hardware will treat that as a real
@@ -763,19 +767,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
u8 dpb_valid = 0;
- u8 idx = 0;
-
- switch (j) {
- case 0:
- idx = h264_ctx->reflists.p[i];
- break;
- case 1:
- idx = h264_ctx->reflists.b0[i];
- break;
- case 2:
- idx = h264_ctx->reflists.b1[i];
- break;
- }
+ u8 idx = reflists[j][i];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
@@ -143,88 +122,6 @@ index 6ce11b736363..9c3f08c94800 100644
u16 *p = (u16 *)hw_rps;
memset(hw_rps, 0, sizeof(priv_tbl->rps));
@@ -764,18 +764,71 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
p[i] = dpb[i].frame_num - max_frame_num;
}
- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
- u8 dpb_valid = 0;
- u8 idx = reflists[j][i];
+ if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) {
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
+ u8 dpb_valid = 0;
+ u8 idx = reflists[j][i];
- if (idx >= ARRAY_SIZE(dec_params->dpb))
- continue;
- dpb_valid = !!(dpb[idx].flags &
- V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ dpb_valid = !!(dpb[idx].flags &
+ V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
- set_ps_field(hw_rps, DPB_INFO(i, j),
- idx | dpb_valid << 4);
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | dpb_valid << 4);
+ }
+ }
+ return;
+ }
+
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ enum v4l2_h264_field_reference a_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
+ enum v4l2_h264_field_reference b_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
+ u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
+ i = 0;
+
+ for (k = 0; k < 2; k++) {
+ u8 a = 0;
+ u8 b = 0;
+ u32 long_term = k ? V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM : 0;
+
+ while (a < h264_ctx->reflists.num_valid || b < h264_ctx->reflists.num_valid) {
+ for (; a < h264_ctx->reflists.num_valid; a++) {
+ u8 idx = reflists[j][a];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & a_parity) == a_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ a_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ a++;
+ break;
+ }
+ }
+ for (; b < h264_ctx->reflists.num_valid; b++) {
+ u8 idx = reflists[j][b];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & b_parity) == b_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ b_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ b++;
+ break;
+ }
+ }
+ }
}
}
}
@@ -968,10 +1021,6 @@ static void config_registers(struct rkvdec_ctx *ctx,
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15);
}
@@ -431,52 +328,6 @@ index 7b56a68c176c..befa69d5c855 100644
if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 13:42:01 +0200
Subject: [PATCH] media: rkvdec: adapt to match 5.11 H.264 uapi changes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 9c3f08c94800..7238117b6cf4 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
}
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- enum v4l2_h264_field_reference a_parity =
+ u8 a_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
- enum v4l2_h264_field_reference b_parity =
+ u8 b_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
@@ -802,7 +802,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][a];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & a_parity) == a_parity &&
+ if ((dpb[idx].fields & a_parity) == a_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
@@ -817,7 +817,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][b];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & b_parity) == b_parity &&
+ if ((dpb[idx].fields & b_parity) == b_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 6 Jan 2019 01:48:37 +0800

View File

@@ -3505,10 +3505,9 @@ index da32a6350344..4fb05e8b5a54 100644
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev)
@@ -1218,5 +1255,6 @@ static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
struct resource *res;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;