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X96Q LPDDR3 Improvements

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sicXnull
2024-09-17 18:51:43 -04:00
committed by Igor
parent 9a57760e48
commit 5e54e2beb8
4 changed files with 822 additions and 843 deletions
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650
patch/kernel/archive/sunxi-6.10/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
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@@ -1,61 +1,45 @@
From 46a827a8a3a588b0f2e211094288d9b33f2eff44 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 21 Aug 2024 15:17:50 +0300
Subject: arm64: dts: sun50i-h313-x96q-lpddr3
Add support X96Q TV Box LPDDR3 H313
Author: sicXnull <notifications@github.com>
Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-h313-x96q-lpddr3.dts | 491 ++++++++++++++++++
2 files changed, 492 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 0a0ec8a39259..454eeb5815ee 100644
index a957365..812685d 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h64-remix-mini-pc.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q-lpddr3.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
new file mode 100644
index 000000000000..5732a55c9915
index 0000000..ba48e0d
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2023 Arm Ltd.
+ * Author: piotr.oniszczuk@gmail.com
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+#include "sun50i-h616-cpu-opp.dtsi"
+#include "sun50i-h618-cpu-dvfs.dtsi"
+
+#include "sun50i-h313-cpu-opp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "X96Q TV-Box";
+ compatible = "x96q,tv-box", "allwinner,sun50i-h616";
+ model = "X96Q TV-Box LPDDR3";
+ compatible = "hechuang,x96-q", "allwinner,sun50i-h616";
+
+ aliases {
+ mmc0 = &mmc0;
+ mmc2 = &mmc2;
+ ethernet0 = &emac1;
+ ethernet1 = &wlan;
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
@@ -76,24 +60,11 @@ index 000000000000..5732a55c9915
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "green_led";
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ 100m_link {
+ label = "100m_link";
+ gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ default-state = "off";
+ };
+
+ 100m_act {
+ label = "100m_act";
+ gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ default-state = "off";
+ led-red {
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
@@ -106,24 +77,26 @@ index 000000000000..5732a55c9915
+ regulator-always-on;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ /* SY8089 DC/DC converter */
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ regulator-always-on;
+ enable-active-high;
+ /* gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; PC16 */
+ status = "okay";
+ };
+
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ reg_vcc_wifi: reg_vcc_wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 WL_REG_ON */
+ regulator-always-on;
+ vin-supply = <&reg_vcc3v3>;
+ enable-active-high;
+ status = "okay";
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
@@ -133,129 +106,19 @@ index 000000000000..5732a55c9915
+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+ ac200_pwm_clk: ac200_clk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ // pwm5 period_ns = 500 > 334 for select 24M clock.
+ pwms = <&pwm 5 500 0>;
+ clock-frequency = <2000000>;
+ status = "okay";
+ };
+
+ soc {
+ pwm: pwm@300a000 {
+ compatible = "allwinner,sun50i-h616-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ pwm-number = <6>;
+ pwm-base = <0x0>;
+ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
+ #pwm-cells = <3>;
+ status = "okay";
+ };
+
+ pwm0: pwm0@0300a000 {
+ compatible = "allwinner,sunxi-pwm0";
+ };
+
+ pwm1: pwm1@0300a000 {
+ compatible = "allwinner,sunxi-pwm1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_ph_pin>;
+ };
+
+ pwm2: pwm2@0300a000 {
+ compatible = "allwinner,sunxi-pwm2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_ph_pin>;
+ };
+
+ pwm3: pwm3@0300a000 {
+ compatible = "allwinner,sunxi-pwm3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_ph_pin>;
+ };
+
+ pwm4: pwm4@0300a000 {
+ compatible = "allwinner,sunxi-pwm4";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_ph_pin>;
+ };
+
+ pwm5: pwm5@0300a000 {
+ compatible = "allwinner,sunxi-pwm5";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm5_pin>;
+ clk_bypass_output = <0x1>;
+ status = "okay";
+ };
+ };
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&gpu {
+ mali-supply = <&reg_dcdc1>;
+ status = "disabled";
+};
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ vmmc-supply = <&reg_dldo1>;
+ max-frequency = <50000000>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc_wifi_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ mmc-ddr-1_8v;
+ status = "okay";
+};
+
+&emac0 {
+ status = "disabled";
+};
+
+&emac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&rmii_phy>;
+ phy-supply = <&reg_dldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio1 {
+ rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&ehci0 {
+ status = "disabled";
+ status = "okay";
+};
+
+&ehci1 {
@@ -270,8 +133,74 @@ index 000000000000..5732a55c9915
+ status = "okay";
+};
+
+&hdmi {
+ hvcc-supply = <&reg_aldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&gpu {
+ mali-supply = <&reg_dcdc1>;
+ status = "okay";
+};
+
+&emac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&rmii_phy>;
+ phy-supply = <&reg_aldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio1 {
+ rmii_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_dldo1>;
+ broken-cd;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_dldo1>;
+ vqmmc-supply = <&reg_vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ wlan: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 15 IRQ_TYPE_EDGE_RISING>; /* PG15 WL_HOSTWAKE*/
+ interrupt-names = "host-wake";
+ local-mac-address = [dc 44 6d c0 ff 02];
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <&reg_dldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "disabled";
+ status = "okay";
+};
+
+&ohci1 {
@@ -286,38 +215,53 @@ index 000000000000..5732a55c9915
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx_pin>;
+&r_i2c {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+ axp313a: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ wakeup-source;
+ vin1-supply = <&reg_vcc5v>;
+ vin2-supply = <&reg_vcc5v>;
+ vin3-supply = <&reg_vcc5v>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+ regulators {
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-gpu";
+ };
+
+&spi1 {
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "disabled";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3";
+ };
+ };
+ };
+};
+
@@ -327,201 +271,149 @@ index 000000000000..5732a55c9915
+ status = "okay";
+};
+
+&uart2 {
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pi_pins>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pi_pins>;
+ status = "disabled";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "disabled";
+};
+
+&i2c3 {
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pa_pins>;
+
+ ac200_x: mfd@10 {
+ compatible = "x-powers,ac200-sunxi";
+ reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
+ // ephy id
+ nvmem-cells = <&ephy_calibration>;
+ nvmem-cell-names = "calibration";
+
+ ac200_ephy: phy {
+ compatible = "x-powers,ac200-ephy-sunxi";
+ status = "okay";
+ };
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_dldo1>;
+ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_ph_pins>;
+ status = "disabled";
+};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc5v>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-beelink-gs1";
+ status = "okay";
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT";
+ status = "okay";
+};
+
+&ahub_dam_plat {
+ status = "okay";
+};
+
+&ahub1_plat {
+ status = "okay";
+};
+
+&ahub1_mach {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
--- a/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2021 Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
+
+/*
+ X96-q DDR3 vendor Android DT:
+ 480000000 900mV
+ 600000000 900mV
+ 792000000 900mV
+ 1008000000 920mV
+ 1200000000 980mV
+ 1344000000 1120mV
+ 1416000000 1140mV
+ 1512000000 1160mV
+*/
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "allwinner,sun50i-h616-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp-480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-600000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-792000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <792000000>;
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1008000000>;
+
+ opp-microvolt-speed0 = <920000 920000 1100000>;
+ opp-microvolt-speed1 = <920000 920000 1100000>;
+ opp-microvolt-speed2 = <920000 920000 1100000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+
+ opp-microvolt-speed0 = <980000 980000 1100000>;
+ opp-microvolt-speed1 = <980000 980000 1100000>;
+ opp-microvolt-speed2 = <980000 980000 1100000>;
+ };
+
+ opp-1512000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1512000000>;
+
+ opp-microvolt-speed0 = <1100000 1100000 1100000>;
+ opp-microvolt-speed1 = <1100000 1100000 1100000>;
+ opp-microvolt-speed2 = <1100000 1100000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&sid {
+ ephy_calibration: ephy-calibration@2c {
+ reg = <0x2c 0x2>;
+ };
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu_critical {
+ temperature = <100000>;
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&gpu_temp_critical {
+ temperature = <100000>;
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&ve_temp_critical {
+ temperature = <100000>;
+};
+
+&ddr_temp_critical {
+ temperature = <100000>;
+};
+
+&pio {
+ vcc-pc-supply = <&reg_dldo1>;
+ vcc-pf-supply = <&reg_dldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+ vcc-ph-supply = <&reg_dldo1>;
+ vcc-pi-supply = <&reg_dldo1>;
+
+ /omit-if-no-ref/
+ i2c0_pi_pins: i2c0-pi-pins {
+ pins = "PI5", "PI6";
+ function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c1_pi_pins: i2c1-pi-pins {
+ pins = "PI7", "PI8";
+ function = "i2c1";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pi_pins: i2c2-pi-pins {
+ pins = "PI9", "PI10";
+ function = "i2c2";
+ };
+
+ i2c3_pa_pins: i2c3-pa-pins {
+ pins = "PA10", "PA11";
+ function = "i2c3";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ i2c4_ph_pins: i2c4-ph-pins {
+ pins = "PH6", "PH7";
+ function = "i2c4";
+ };
+
+ /omit-if-no-ref/
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI5", "PI6";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart3_pi_pins: uart3-pi-pins {
+ pins = "PI9", "PI10";
+ function = "uart3";
+ };
+
+ /omit-if-no-ref/
+ uart4_pi_pins: uart4-pi-pins {
+ pins = "PI13", "PI14";
+ function = "uart4";
+ };
+
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH2", "PH3";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs1_pin: spi1-cs1-pin {
+ pins = "PH9";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ pwm1_ph_pin: pwm1-ph-pin {
+ pins = "PH3";
+ function = "pwm1";
+ };
+
+ /omit-if-no-ref/
+ pwm2_ph_pin: pwm2-ph-pin {
+ pins = "PH2";
+ function = "pwm2";
+ };
+
+ /omit-if-no-ref/
+ pwm3_ph_pin: pwm3-ph-pin {
+ pins = "PH0";
+ function = "pwm3";
+ };
+
+ /omit-if-no-ref/
+ pwm4_ph_pin: pwm4-ph-pin {
+ pins = "PH1";
+ function = "pwm4";
+ };
+
+ /omit-if-no-ref/
+ pwm5_pin: pwm5-pin {
+ pins = "PA12";
+ function = "pwm5";
+ };
+};
--
2.35.3

624
patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
View File

@@ -16,32 +16,30 @@ new file mode 100644
index 0000000..ba48e0d
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2023 Arm Ltd.
+ * Author: piotr.oniszczuk@gmail.com
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+#include "sun50i-h616-cpu-opp.dtsi"
+#include "sun50i-h618-cpu-dvfs.dtsi"
+
+#include "sun50i-h313-cpu-opp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "X96Q TV-Box";
+ compatible = "x96q,tv-box", "allwinner,sun50i-h616";
+ model = "X96Q TV-Box LPDDR3";
+ compatible = "hechuang,x96-q", "allwinner,sun50i-h616";
+
+ aliases {
+ mmc0 = &mmc0;
+ mmc2 = &mmc2;
+ ethernet0 = &emac1;
+ ethernet1 = &wlan;
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
@@ -62,24 +60,11 @@ index 0000000..ba48e0d
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "green_led";
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ 100m_link {
+ label = "100m_link";
+ gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ default-state = "off";
+ };
+
+ 100m_act {
+ label = "100m_act";
+ gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ default-state = "off";
+ led-red {
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
@@ -92,24 +77,26 @@ index 0000000..ba48e0d
+ regulator-always-on;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ /* SY8089 DC/DC converter */
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ regulator-always-on;
+ enable-active-high;
+ /* gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; PC16 */
+ status = "okay";
+ };
+
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ reg_vcc_wifi: reg_vcc_wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 WL_REG_ON */
+ regulator-always-on;
+ vin-supply = <&reg_vcc3v3>;
+ enable-active-high;
+ status = "okay";
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
@@ -119,129 +106,19 @@ index 0000000..ba48e0d
+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+ ac200_pwm_clk: ac200_clk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ // pwm5 period_ns = 500 > 334 for select 24M clock.
+ pwms = <&pwm 5 500 0>;
+ clock-frequency = <2000000>;
+ status = "okay";
+ };
+
+ soc {
+ pwm: pwm@300a000 {
+ compatible = "allwinner,sun50i-h616-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ pwm-number = <6>;
+ pwm-base = <0x0>;
+ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
+ #pwm-cells = <3>;
+ status = "okay";
+ };
+
+ pwm0: pwm0@0300a000 {
+ compatible = "allwinner,sunxi-pwm0";
+ };
+
+ pwm1: pwm1@0300a000 {
+ compatible = "allwinner,sunxi-pwm1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_ph_pin>;
+ };
+
+ pwm2: pwm2@0300a000 {
+ compatible = "allwinner,sunxi-pwm2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_ph_pin>;
+ };
+
+ pwm3: pwm3@0300a000 {
+ compatible = "allwinner,sunxi-pwm3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_ph_pin>;
+ };
+
+ pwm4: pwm4@0300a000 {
+ compatible = "allwinner,sunxi-pwm4";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_ph_pin>;
+ };
+
+ pwm5: pwm5@0300a000 {
+ compatible = "allwinner,sunxi-pwm5";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm5_pin>;
+ clk_bypass_output = <0x1>;
+ status = "okay";
+ };
+ };
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&gpu {
+ mali-supply = <&reg_dcdc1>;
+ status = "disabled";
+};
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ vmmc-supply = <&reg_dldo1>;
+ max-frequency = <50000000>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc_wifi_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ mmc-ddr-1_8v;
+ status = "okay";
+};
+
+&emac0 {
+ status = "disabled";
+};
+
+&emac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&rmii_phy>;
+ phy-supply = <&reg_dldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio1 {
+ rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&ehci0 {
+ status = "disabled";
+ status = "okay";
+};
+
+&ehci1 {
@@ -256,8 +133,74 @@ index 0000000..ba48e0d
+ status = "okay";
+};
+
+&hdmi {
+ hvcc-supply = <&reg_aldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&gpu {
+ mali-supply = <&reg_dcdc1>;
+ status = "okay";
+};
+
+&emac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&rmii_phy>;
+ phy-supply = <&reg_aldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio1 {
+ rmii_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_dldo1>;
+ broken-cd;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_dldo1>;
+ vqmmc-supply = <&reg_vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ wlan: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 15 IRQ_TYPE_EDGE_RISING>; /* PG15 WL_HOSTWAKE*/
+ interrupt-names = "host-wake";
+ local-mac-address = [dc 44 6d c0 ff 02];
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <&reg_dldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "disabled";
+ status = "okay";
+};
+
+&ohci1 {
@@ -272,38 +215,53 @@ index 0000000..ba48e0d
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx_pin>;
+&r_i2c {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+ axp313a: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ wakeup-source;
+ vin1-supply = <&reg_vcc5v>;
+ vin2-supply = <&reg_vcc5v>;
+ vin3-supply = <&reg_vcc5v>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+ regulators {
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-gpu";
+ };
+
+&spi1 {
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "disabled";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3";
+ };
+ };
+ };
+};
+
@@ -313,199 +271,149 @@ index 0000000..ba48e0d
+ status = "okay";
+};
+
+&uart2 {
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pi_pins>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pi_pins>;
+ status = "disabled";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "disabled";
+};
+
+&i2c3 {
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pa_pins>;
+
+ ac200_x: mfd@10 {
+ compatible = "x-powers,ac200-sunxi";
+ reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
+ // ephy id
+ nvmem-cells = <&ephy_calibration>;
+ nvmem-cell-names = "calibration";
+
+ ac200_ephy: phy {
+ compatible = "x-powers,ac200-ephy-sunxi";
+ status = "okay";
+ };
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_dldo1>;
+ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_ph_pins>;
+ status = "disabled";
+};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc5v>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-beelink-gs1";
+ status = "okay";
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT";
+ status = "okay";
+};
+
+&ahub_dam_plat {
+ status = "okay";
+};
+
+&ahub1_plat {
+ status = "okay";
+};
+
+&ahub1_mach {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
--- a/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2021 Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
+
+/*
+ X96-q DDR3 vendor Android DT:
+ 480000000 900mV
+ 600000000 900mV
+ 792000000 900mV
+ 1008000000 920mV
+ 1200000000 980mV
+ 1344000000 1120mV
+ 1416000000 1140mV
+ 1512000000 1160mV
+*/
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "allwinner,sun50i-h616-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp-480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-600000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-792000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <792000000>;
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
+ opp-microvolt-speed2 = <900000 900000 1100000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1008000000>;
+
+ opp-microvolt-speed0 = <920000 920000 1100000>;
+ opp-microvolt-speed1 = <920000 920000 1100000>;
+ opp-microvolt-speed2 = <920000 920000 1100000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+
+ opp-microvolt-speed0 = <980000 980000 1100000>;
+ opp-microvolt-speed1 = <980000 980000 1100000>;
+ opp-microvolt-speed2 = <980000 980000 1100000>;
+ };
+
+ opp-1512000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1512000000>;
+
+ opp-microvolt-speed0 = <1100000 1100000 1100000>;
+ opp-microvolt-speed1 = <1100000 1100000 1100000>;
+ opp-microvolt-speed2 = <1100000 1100000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&sid {
+ ephy_calibration: ephy-calibration@2c {
+ reg = <0x2c 0x2>;
+ };
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu_temp_critical {
+ temperature = <100000>;
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&gpu_temp_critical {
+ temperature = <100000>;
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&ve_temp_critical {
+ temperature = <100000>;
+};
+
+&ddr_temp_critical {
+ temperature = <100000>;
+};
+
+&pio {
+ vcc-pc-supply = <&reg_dldo1>;
+ vcc-pf-supply = <&reg_dldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+ vcc-ph-supply = <&reg_dldo1>;
+ vcc-pi-supply = <&reg_dldo1>;
+
+ /omit-if-no-ref/
+ i2c0_pi_pins: i2c0-pi-pins {
+ pins = "PI5", "PI6";
+ function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c1_pi_pins: i2c1-pi-pins {
+ pins = "PI7", "PI8";
+ function = "i2c1";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pi_pins: i2c2-pi-pins {
+ pins = "PI9", "PI10";
+ function = "i2c2";
+ };
+
+ i2c3_pa_pins: i2c3-pa-pins {
+ pins = "PA10", "PA11";
+ function = "i2c3";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ i2c4_ph_pins: i2c4-ph-pins {
+ pins = "PH6", "PH7";
+ function = "i2c4";
+ };
+
+ /omit-if-no-ref/
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI5", "PI6";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart3_pi_pins: uart3-pi-pins {
+ pins = "PI9", "PI10";
+ function = "uart3";
+ };
+
+ /omit-if-no-ref/
+ uart4_pi_pins: uart4-pi-pins {
+ pins = "PI13", "PI14";
+ function = "uart4";
+ };
+
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH2", "PH3";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs1_pin: spi1-cs1-pin {
+ pins = "PH9";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ pwm1_ph_pin: pwm1-ph-pin {
+ pins = "PH3";
+ function = "pwm1";
+ };
+
+ /omit-if-no-ref/
+ pwm2_ph_pin: pwm2-ph-pin {
+ pins = "PH2";
+ function = "pwm2";
+ };
+
+ /omit-if-no-ref/
+ pwm3_ph_pin: pwm3-ph-pin {
+ pins = "PH0";
+ function = "pwm3";
+ };
+
+ /omit-if-no-ref/
+ pwm4_ph_pin: pwm4-ph-pin {
+ pins = "PH1";
+ function = "pwm4";
+ };
+
+ /omit-if-no-ref/
+ pwm5_pin: pwm5-pin {
+ pins = "PA12";
+ function = "pwm5";
+ };
+};

186
patch/u-boot/u-boot-sunxi/arm64-sun50i-h313-add-x96q-lpddr3-defconfig.patch
View File

@@ -13,7 +13,7 @@ diff --git a/configs/x96q_lpddr3_defconfig b/configs/x96q_lpddr3_defconfig
+ new file mode 100755
+ index 000000000..306157b84
+++ b/configs/x96q_lpddr3_defconfig
@@ -0,0 +1,34 @@
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-x96q-lpddr3"
@@ -45,34 +45,34 @@ diff --git a/configs/x96q_lpddr3_defconfig b/configs/x96q_lpddr3_defconfig
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x40
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts b/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts
new file mode 100644
index 000000000..306157b84
--- /dev/null
+++ b/arch/arm/dts/sun50i-h313-x96q-lpddr3.dts
@@ -0,0 +1,181 @@
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+//*
+//* Copyright (C) 2020 Arm Ltd.
+//*
+/*
+ * Author: piotr.oniszczuk@gmail.com
+ */
+
+/dts-v1/;
+
+#include <sun50i-h616.dtsi>
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "X96Q TV-Box";
+ compatible = "x96q,tv-box", "allwinner,sun50i-h616";
+ model = "hechuang,x96q LPDDR3";
+ compatible = "hechuang,x96-q", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 = &emac0;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &mmc2;
+ ethernet0 = &emac1;
+ serial0 = &uart0;
+ };
+
@@ -83,17 +83,11 @@ index 000000000..306157b84
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ led-red {
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
@@ -105,44 +99,65 @@ index 000000000..306157b84
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ status = "okay";
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&cpu1 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&cpu2 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&cpu3 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&emac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&rmii_phy>;
+ phy-supply = <&reg_aldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio1 {
+ rmii_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+&emac0 {
+ status = "disabled";
+};
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ vmmc-supply = <&reg_dldo2>;
+ broken-cd;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci0 {
+&mmc1 {
+ vmmc-supply = <&reg_dldo2>;
+ broken-cd;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci1 {
+&mmc2 {
+ vmmc-supply = <&reg_dldo2>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
@@ -151,91 +166,50 @@ index 000000000..306157b84
+
+ axp313a: pmic@36 {
+ compatible = "x-powers,axp313a";
+ status = "okay";
+ reg = <0x36>;
+ wakeup-source;
+
+ standby_param: standby_param {
+ vcc-dram = <0x4>;
+ };
+
+ regulators{
+ regulators {
+ reg_dcdc1: dcdc1 {
+ regulator-name = "axp313a-dcdc1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-step-delay-us = <25>;
+ regulator-final-delay-us = <50>;
+ regulator-always-on;
+ regulator-min-microvolt = <1160000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = "axp313a-dcdc2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-step-delay-us = <25>;
+ regulator-final-delay-us = <50>;
+ regulator-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-min-microvolt = <1160000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "axp313a-dcdc3";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-step-delay-us = <25>;
+ regulator-final-delay-us = <50>;
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-name = "axp313a-aldo1";
+ reg_aldo1: ldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-step-delay-us = <25>;
+ regulator-final-delay-us = <50>;
+ regulator-always-on;
+ regulator-name = "vcc-sys";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-name = "axp313a-dldo1";
+ reg_dldo2: ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-step-delay-us = <25>;
+ regulator-final-delay-us = <50>;
+ regulator-always-on;
+ regulator-name = "vcc3v3-ext";
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};

205
patch/u-boot/u-boot-sunxi/sunsi-add-h616-internal-eth-phy-support.patch Normal file
View File

@@ -0,0 +1,205 @@
diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
index 74aed0d232a..091d52be962 100644
--- a/arch/arm/dts/sun50i-h616.dtsi
+++ b/arch/arm/dts/sun50i-h616.dtsi
@@ -209,6 +209,14 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ rmii_pins: rmii-pins {
+ pins = "PA0", "PA1", "PA2", "PA3", "PA4",
+ "PA5", "PA6", "PA7", "PA8", "PA9";
+ function = "emac1";
+ drive-strength = <40>;
+ };
+
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC0", "PC2", "PC4";
@@ -504,6 +512,25 @@
};
};
+ emac1: ethernet@5030000 {
+ compatible = "allwinner,sun50i-h616-emac1";
+ syscon = <&syscon 1>;
+ reg = <0x05030000 0x10000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC1>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC1>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usbotg: usb@5100000 {
compatible = "allwinner,sun50i-h616-musb",
"allwinner,sun8i-h3-musb";
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index f0da46d863c..914f16b2c46 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -13,6 +13,9 @@
#ifdef CONFIG_I2C1_ENABLE
#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
+#ifdef CONFIG_I2C3_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE
+#endif
#ifdef CONFIG_R_I2C_ENABLE
#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
#endif
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6dcbb096f74..fa9d67e09a0 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -771,6 +771,15 @@ config I2C1_ENABLE
---help---
See I2C0_ENABLE help text.
+if MACH_SUN50I_H616
+config I2C3_ENABLE
+ bool "Enable I2C/TWI controller 3"
+ default n
+ select CMD_I2C
+ ---help---
+ See I2C0_ENABLE help text.
+endif
+
if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
config R_I2C_ENABLE
bool "Enable the PRCM I2C/TWI controller"
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 391a65a5495..b44e741627e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -460,6 +460,7 @@ void board_init_f(ulong dummy)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init_board();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
#endif
sunxi_board_init();
}
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 7926394cf76..7c84d731f84 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -46,6 +46,10 @@ void clock_init_safe(void)
* DRAM initialization code.
*/
writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+
+ writel(0x10001, 0x030017ac);
+ writel(0x50, 0x0300a028);
+ writel(0x20, 0x0300a040);
}
#endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f321cd58a6e..d5633ad5ca6 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -15,6 +15,7 @@
#include <dm.h>
#include <env.h>
#include <hang.h>
+#include <i2c.h>
#include <image.h>
#include <init.h>
#include <log.h>
@@ -107,6 +108,17 @@ void i2c_init_board(void)
#endif
#endif
+#ifdef CONFIG_I2C3_ENABLE
+#if defined(CONFIG_MACH_SUN50I_H616)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(10), 2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(11), 2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(12), 2);
+ sunxi_gpio_set_pull(SUNXI_GPA(10), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_pull(SUNXI_GPA(11), SUNXI_GPIO_PULL_UP);
+ clock_twi_onoff(3, 1);
+#endif
+#endif
+
#ifdef CONFIG_R_I2C_ENABLE
#ifdef CONFIG_MACH_SUN50I
clock_twi_onoff(5, 1);
@@ -572,6 +584,7 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
void sunxi_board_init(void)
{
int power_failed = 0;
+ u8 data[2];
#ifdef CONFIG_LED_STATUS
if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
@@ -666,6 +679,23 @@ void sunxi_board_init(void)
clock_set_pll1(get_board_sys_clk());
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
+
+ i2c_set_bus_num(1);
+ data[0] = 0;
+ data[1] = 0;
+ i2c_write(0x10, 0xfe, 1, data, 2);
+ i2c_write(0x10, 2, 1, data, 2);
+ data[1] = 1;
+ i2c_write(0x10, 2, 1, data, 2);
+ data[1] = 0xf;
+ i2c_write(0x10, 0x16, 1, data, 2);
+ data[1] = 3;
+ i2c_write(0x10, 0x14, 1, data, 2);
+ data[1] = 0x60;
+ i2c_write(0x10, 0xfe, 1, data, 2);
+ data[0] = 0x08;
+ data[1] = 0x14;
+ i2c_write(0x10, 0, 1, data, 2);
}
#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 04c3274fbe1..d0b80d4cec1 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -909,6 +909,11 @@ static const struct emac_variant emac_variant_h6 = {
.support_rmii = true,
};
+static const struct emac_variant emac_variant_h616_1 = {
+ .syscon_offset = 0x34,
+ .support_rmii = true,
+};
+
static const struct udevice_id sun8i_emac_eth_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-emac",
.data = (ulong)&emac_variant_a83t },
@@ -920,6 +925,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
.data = (ulong)&emac_variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = (ulong)&emac_variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac1",
+ .data = (ulong)&emac_variant_h616_1 },
{ }
};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index e5102180902..8f4517c177f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -710,6 +710,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
{ "emac0", 2 }, /* PI0-PI16 */
+ { "emac1", 2 }, /* PA0-PA9 */
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "mmc0", 2 }, /* PF0-PF5 */