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fix compiling error of sunxi pwm and eth driver

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This commit is contained in:
chraac
2024-08-16 18:03:34 +08:00
committed by Igor
parent f912216fd0
commit 5d884120a4
4 changed files with 512 additions and 263 deletions
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2
config/kernel/linux-sunxi64-edge.config
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@@ -7549,7 +7549,7 @@ CONFIG_PWM_CLK=m
CONFIG_PWM_NTXEC=m
CONFIG_PWM_PCA9685=m
CONFIG_PWM_SUN4I=m
# CONFIG_PWM_SUNXI_ENHANCE is not set
CONFIG_PWM_SUNXI_ENHANCE=m
CONFIG_PWM_XILINX=m
#

641
patch/kernel/archive/sunxi-6.10/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
View File

@@ -1,22 +1,17 @@
From cf469142557d0f61d91a7732ce4b639760379745 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Thu, 22 Aug 2024 15:54:39 +0300
From bacdb9da06bb291ced710b2fe1f702711f97ec9e Mon Sep 17 00:00:00 2001
From: chraac <chraac@gmail.com>
Date: Fri, 15 Mar 2024 12:30:26 +0800
Subject: arm64: dts: sun50i-h618-orangepi-zero2w: Add missing nodes
The missing nodes were taken from the file:
https://github.com/armbian/build/blob/27b7f33b9c1669e4f24e03313b6c242170347e94/patch/kernel/archive/sunxi-6.7/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-add-dtb.patch#L1
This has not been tested on a working device.
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 25 +-
.../allwinner/sun50i-h618-orangepi-zero2w.dts | 369 +++++++++++++++++-
2 files changed, 385 insertions(+), 9 deletions(-)
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 30 +-
.../allwinner/sun50i-h618-orangepi-zero2w.dts | 628 ++++++++++++++++--
2 files changed, 586 insertions(+), 67 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 1448fad0793a..f84eea66655e 100644
index 1bf71a0a0202..cccdcb55eecd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -193,7 +193,7 @@ video-codec@1c0e000 {
@@ -197,7 +197,7 @@ video-codec@1c0e000 {
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h616-system-control";
@@ -25,7 +20,7 @@ index 1448fad0793a..f84eea66655e 100644
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -748,19 +748,28 @@ ths: thermal-sensor@5070400 {
@@ -770,19 +770,28 @@ ths: thermal-sensor@5070400 {
};
emac1: ethernet@5030000 {
@@ -34,7 +29,7 @@ index 1448fad0793a..f84eea66655e 100644
- reg = <0x05030000 0x10000>;
+ compatible = "allwinner,sunxi-gmac";
+ reg = <0x05030000 0x10000>,
+ <0x03000034 0x4>;
+ <0x03000034 0x4>;
+ reg-names = "gmac1_reg","ephy_reg";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
@@ -62,10 +57,10 @@ index 1448fad0793a..f84eea66655e 100644
#size-cells = <0>;
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
index 6a4f0da97233..17b315f071d9 100644
index 6a4f0da97233..bdfc3a1af689 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
@@ -7,6 +7,7 @@
@@ -7,10 +7,15 @@
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
@@ -73,7 +68,15 @@ index 6a4f0da97233..17b315f071d9 100644
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -18,19 +19,48 @@ / {
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+
/ {
model = "OrangePi Zero 2W";
@@ -18,19 +23,48 @@ / {
aliases {
serial0 = &uart0;
@@ -122,11 +125,14 @@ index 6a4f0da97233..17b315f071d9 100644
};
};
@@ -52,26 +82,192 @@ reg_vcc3v3: vcc3v3 {
@@ -52,91 +86,377 @@ reg_vcc3v3: vcc3v3 {
vin-supply = <&reg_vcc5v>;
regulator-always-on;
};
+
-};
-&cpu0 {
- cpu-supply = <&reg_dcdc2>;
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ compatible = "regulator-fixed";
@@ -203,71 +209,226 @@ index 6a4f0da97233..17b315f071d9 100644
+ clk_bypass_output = <0x1>;
+ status = "okay";
+ };
+
+ bus@1000000 {
+ compatible = "allwinner,sun50i-h616-de33",
+ "allwinner,sun50i-a64-de2";
+ reg = <0x1000000 0x400000>;
+ allwinner,sram = <&de3_sram 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000000 0x400000>;
+
+ display_clocks: clock@8000 {
+ compatible = "allwinner,sun50i-h616-de33-clk";
+ reg = <0x8000 0x100>;
+ clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@100000 {
+ compatible = "allwinner,sun50i-h616-de33-mixer-0";
+ reg = <0x100000 0x100000>,
+ <0x8100 0x40>,
+ <0x280000 0x20000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+ };
+
+ hdmi: hdmi@6000000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h616-dw-hdmi",
+ "allwinner,sun50i-h6-dw-hdmi";
+ reg = <0x06000000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
+ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
+ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
+ "hdcp-bus";
+ resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>;
+ reset-names = "ctrl", "hdcp";
+ phys = <&hdmi_phy>;
+ phy-names = "phy";
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@6010000 {
+ compatible = "allwinner,sun50i-h616-hdmi-phy";
+ reg = <0x06010000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_HDMI_SUB>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ tcon_top: tcon-top@6510000 {
+ compatible = "allwinner,sun50i-h6-tcon-top";
+ reg = <0x06510000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
+ <&ccu CLK_TCON_TV0>;
+ clock-names = "bus",
+ "tcon-tv0";
+ clock-output-names = "tcon-top-tv0";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_top_mixer0_out_tcon_tv: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_tv_out_tcon_top>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+
+ tcon_top_hdmi_out_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_tcon_top>;
+ };
+ };
+ };
+ };
+
+ tcon_tv: lcd-controller@6515000 {
+ compatible = "allwinner,sun50i-h6-tcon-tv",
+ "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x06515000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv_in: port@0 {
+ reg = <0>;
+
+ tcon_tv_in_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
+ };
+ };
+
+ tcon_tv_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv_out_tcon_top: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
+ };
+ };
+ };
+ };
+
+ addr_mgt: addr-mgt {
+ compatible = "allwinner,sunxi-addr_mgt";
+ type_addr_wifi = <0x2>;
+ type_addr_bt = <0x2>;
+ type_addr_eth = <0x2>;
+ status = "okay";
+ };
+ };
+
+ de: display-engine {
+ compatible = "allwinner,sun50i-h6-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "okay";
+ };
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
+&sid {
+ ephy_calibration: ephy-calibration@2c {
+ reg = <0x2c 0x2>;
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
-&ehci1 {
- status = "okay";
+&gpu {
+ mali-supply = <&reg_dcdc1>;
+ status = "disabled";
+};
+
+&ehci0 {
+ status = "disabled";
+};
+
&ehci1 {
status = "okay";
};
+&ehci2 {
+ status = "okay";
-/* USB 2 & 3 are on the FPC connector (or the exansion board) */
+&sram_c {
+ de3_sram: sram-section@0 {
+ compatible = "allwinner,sun50i-h616-sram-c",
+ "allwinner,sun50i-a64-sram-c";
+ reg = <0x0000 0x1e000>;
+ };
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "disabled";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
/* USB 2 & 3 are on the FPC connector (or the exansion board) */
&mmc0 {
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -300,26 +461,223 @@ index 6a4f0da97233..17b315f071d9 100644
+ phy-supply = <&reg_dldo1>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
status = "okay";
};
-&pio {
- vcc-pc-supply = <&reg_dldo1>;
- vcc-pf-supply = <&reg_dldo1>; /* internally via VCC-IO */
- vcc-pg-supply = <&reg_aldo1>;
- vcc-ph-supply = <&reg_dldo1>; /* internally via VCC-IO */
- vcc-pi-supply = <&reg_dldo1>;
+&mdio1 {
+ rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
-&r_i2c {
+&ehci0 {
+ status = "disabled";
+};
+
+&ehci1 {
status = "okay";
+};
- axp313: pmic@36 {
- compatible = "x-powers,axp313a";
- reg = <0x36>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&pio>;
- interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
+&ehci2 {
+ status = "okay";
+};
- vin1-supply = <&reg_vcc5v>;
- vin2-supply = <&reg_vcc5v>;
- vin3-supply = <&reg_vcc5v>;
+&ehci3 {
+ status = "okay";
+};
- regulators {
- /* Supplies VCC-PLL and DRAM */
- reg_aldo1: aldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8";
- };
+&ohci0 {
+ status = "disabled";
+};
- /* Supplies VCC-IO, so needs to be always on. */
- reg_dldo1: dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3";
- };
+&ohci1 {
+ status = "okay";
+};
- reg_dcdc1: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <990000>;
- regulator-name = "vdd-gpu-sys";
- };
+&ohci2 {
+ status = "okay";
+};
- reg_dcdc2: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-cpu";
- };
+&ohci3 {
+ status = "okay";
+};
- reg_dcdc3: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-dram";
- };
- };
- };
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx_pin>;
+ status = "okay";
};
&spi0 {
@@ -153,12 +473,77 @@ flash@0 {
};
};
+&spi1 {
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
+
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "disabled";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
@@ -81,6 +277,96 @@ &pio {
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>; /* internally via VCC-IO */
vcc-pi-supply = <&reg_dldo1>;
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pi_pins>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pi_pins>;
+ status = "disabled";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "disabled";
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pa_pins>;
+
+ ac200_x: mfd@10 {
+ compatible = "x-powers,ac200-sunxi";
+ reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
+ // ephy id
+ nvmem-cells = <&ephy_calibration>;
+ nvmem-cell-names = "calibration";
+
+ ac200_ephy: phy {
+ compatible = "x-powers,ac200-ephy-sunxi";
+ status = "okay";
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_ph_pins>;
+ status = "disabled";
+};
+
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
@@ -179,3 +564,128 @@ &usbphy {
usb1_vbus-supply = <&reg_vcc5v>;
status = "okay";
};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+ status = "okay";
+};
+
+&sid {
+ ephy_calibration: ephy-calibration@2c {
+ reg = <0x2c 0x2>;
+ };
+};
+
+&cpu_critical {
+ temperature = <100000>;
+};
+
+&gpu_temp_critical {
+ temperature = <100000>;
+};
+
+&ve_temp_critical {
+ temperature = <100000>;
+};
+
+&ddr_temp_critical {
+ temperature = <100000>;
+};
+
+&pio {
+ vcc-pc-supply = <&reg_dldo1>;
+ vcc-pf-supply = <&reg_dldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+ vcc-ph-supply = <&reg_dldo1>;
+ vcc-pi-supply = <&reg_dldo1>;
+
+ /omit-if-no-ref/
+ i2c0_pi_pins: i2c0-pi-pins {
@@ -339,11 +697,11 @@ index 6a4f0da97233..17b315f071d9 100644
+ function = "i2c2";
+ };
+
+ i2c3_pa_pins: i2c3-pa-pins {
+ pins = "PA10", "PA11";
+ function = "i2c3";
+ bias-pull-up;
+ };
+ i2c3_pa_pins: i2c3-pa-pins {
+ pins = "PA10", "PA11";
+ function = "i2c3";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ i2c4_ph_pins: i2c4-ph-pins {
@@ -410,113 +768,6 @@ index 6a4f0da97233..17b315f071d9 100644
+ pins = "PA12";
+ function = "pwm5";
+ };
};
&r_i2c {
@@ -139,6 +425,32 @@ reg_dcdc3: dcdc3 {
};
};
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pa_pins>;
+
+ ac200_x: mfd@10 {
+ compatible = "x-powers,ac200-sunxi";
+ reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
+ // ephy id
+ nvmem-cells = <&ephy_calibration>;
+ nvmem-cell-names = "calibration";
+
+ ac200_ephy: phy {
+ compatible = "x-powers,ac200-ephy-sunxi";
+ status = "okay";
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_ph_pins>;
+ status = "disabled";
+};
+
&spi0 {
status = "okay";
pinctrl-names = "default";
@@ -153,12 +465,51 @@ flash@0 {
};
};
+&spi1 {
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
+
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "disabled";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pi_pins>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pi_pins>;
+ status = "disabled";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "disabled";
+};
+
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
@@ -179,3 +530,19 @@ &usbphy {
usb1_vbus-supply = <&reg_vcc5v>;
status = "okay";
};
+
+&cpu_critical {
+ temperature = <100000>;
+};
+
+&gpu_temp_critical {
+ temperature = <100000>;
+};
+
+&ve_temp_critical {
+ temperature = <100000>;
+};
+
+&ddr_temp_critical {
+ temperature = <100000>;
+};
--
2.35.3

13
patch/kernel/archive/sunxi-6.10/patches.armbian/driver-allwinner-h618-emac.patch
View File

@@ -1,10 +1,8 @@
From 235c057309af6b2d9e62109279a12138ae434ebc Mon Sep 17 00:00:00 2001
From 67f590e9b88e5af4dbe78bb4f4451b818f90359c Mon Sep 17 00:00:00 2001
From: chraac <chraac@gmail.com>
Date: Wed, 1 May 2024 14:32:00 +0800
Date: Fri, 16 Aug 2024 16:44:41 +0800
Subject: driver: allwinner h618 emac
commit:
97b476246bc79756423cf6c1d4907606c9633d4b
---
drivers/gpio/gpiolib-of.c | 29 +-
drivers/mfd/Kconfig | 10 +
@@ -431,7 +429,7 @@ index ddd5a5079e8a..56b9c434a5b8 100644
+obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.c b/drivers/net/ethernet/allwinner/sunxi-gmac.c
new file mode 100644
index 000000000000..d31b86fc1e8c
index 000000000000..30efda8038f2
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sunxi-gmac.c
@@ -0,0 +1,2219 @@
@@ -2268,7 +2266,7 @@ index 000000000000..d31b86fc1e8c
+static void geth_ethtool_getdrvinfo(struct net_device *ndev,
+ struct ethtool_drvinfo *info)
+{
+ strlcpy(info->driver, "sunxi_geth", sizeof(info->driver));
+ strscpy(info->driver, "sunxi_geth", sizeof(info->driver));
+
+#define DRV_MODULE_VERSION "SUNXI Gbgit driver V1.1"
+
@@ -4515,5 +4513,4 @@ index d0f66a5e1b2a..71349cac1a67 100644
#include <linux/errno.h>
--
2.35.3
GitLab

119
patch/kernel/archive/sunxi-6.10/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
View File

@@ -1,16 +1,14 @@
From 7da43664c90ff957da24dfbad4e9fa5811da28d7 Mon Sep 17 00:00:00 2001
From 2ece6b65c03422edc7c3b31df0d19b5b5ac5b534 Mon Sep 17 00:00:00 2001
From: chraac <chraac@gmail.com>
Date: Wed, 1 May 2024 14:24:51 +0800
Date: Thu, 15 Aug 2024 23:38:44 +0800
Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616
linux-orangepi commit:
c68ef342eba3673c7f1f5aa1ab819b06da1f60c6
---
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sunxi-enhance.c | 1193 +++++++++++++++++++++++++++++++
drivers/pwm/pwm-sunxi-enhance.c | 1196 +++++++++++++++++++++++++++++++
drivers/pwm/pwm-sunxi-enhance.h | 60 ++
4 files changed, 1263 insertions(+)
4 files changed, 1266 insertions(+)
create mode 100644 drivers/pwm/pwm-sunxi-enhance.c
create mode 100644 drivers/pwm/pwm-sunxi-enhance.h
@@ -48,10 +46,10 @@ index 90913519f11a..ff177f6b73b6 100644
obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
diff --git a/drivers/pwm/pwm-sunxi-enhance.c b/drivers/pwm/pwm-sunxi-enhance.c
new file mode 100644
index 000000000000..5786d1825dad
index 000000000000..1216cae54856
--- /dev/null
+++ b/drivers/pwm/pwm-sunxi-enhance.c
@@ -0,0 +1,1193 @@
@@ -0,0 +1,1196 @@
+/*
+ * Allwinnertech pulse-width-modulation controller driver
+ *
@@ -116,7 +114,6 @@ index 000000000000..5786d1825dad
+
+struct sunxi_pwm_chip
+{
+ struct pwm_chip chip;
+ void __iomem *base;
+ struct sunxi_pwm_config *config;
+ struct clk *bus_clk;
@@ -126,7 +123,7 @@ index 000000000000..5786d1825dad
+
+static inline struct sunxi_pwm_chip *to_sunxi_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct sunxi_pwm_chip, chip);
+ return pwmchip_get_drvdata(chip);
+}
+
+static inline u32 sunxi_pwm_readl(struct pwm_chip *chip, u32 offset)
@@ -223,7 +220,7 @@ index 000000000000..5786d1825dad
+ unsigned int reg_offset, reg_shift, reg_width;
+ u32 sel = 0;
+
+ sel = pwm->pwm - chip->base;
+ sel = pwm->hwpwm;
+ reg_offset = PWM_PCR_BASE + sel * 0x20;
+ reg_shift = PWM_ACT_STA_SHIFT;
+ reg_width = PWM_ACT_STA_WIDTH;
@@ -244,8 +241,8 @@ index 000000000000..5786d1825dad
+ unsigned int reg_offset[2], reg_shift[2], reg_width[2];
+ u32 sel[2] = {0};
+
+ sel[0] = pwm->pwm - chip->base;
+ sel[1] = bind_num - chip->base;
+ sel[0] = pwm->hwpwm;
+ sel[1] = bind_num - (int)chip->id;
+ /* config current pwm*/
+ reg_offset[0] = PWM_PCR_BASE + sel[0] * 0x20;
+ reg_shift[0] = PWM_ACT_STA_SHIFT;
@@ -280,7 +277,7 @@ index 000000000000..5786d1825dad
+ int bind_num;
+ struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
+
+ bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
+ bind_num = pc->config[pwm->hwpwm].bind_pwm;
+ if (bind_num == 255)
+ sunxi_pwm_set_polarity_single(chip, pwm, polarity);
+ else
@@ -375,7 +372,7 @@ index 000000000000..5786d1825dad
+ {8, 256},
+ };
+
+ sel = pwm->pwm - chip->base;
+ sel = pwm->hwpwm;
+
+ get_pccr_reg_offset(sel, &reg_offset);
+ if ((sel % 2) == 0)
@@ -407,7 +404,7 @@ index 000000000000..5786d1825dad
+ /* if freq between 3M~100M, then select 100M as clock */
+ c = 100000000;
+ /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
+ if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
+ if (pc->config[pwm->hwpwm].clk_bypass_output == 1) {
+ temp = sunxi_pwm_readl(chip, reg_offset);
+ temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
+ sunxi_pwm_writel(chip, reg_offset, temp);
@@ -422,7 +419,7 @@ index 000000000000..5786d1825dad
+ /* if freq < 3M, then select 24M clock */
+ c = 24000000;
+ /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
+ if (pc->config[pwm->pwm - chip->base].clk_bypass_output == 1) {
+ if (pc->config[pwm->hwpwm].clk_bypass_output == 1) {
+ temp = sunxi_pwm_readl(chip, reg_offset);
+ temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
+ sunxi_pwm_writel(chip, reg_offset, temp);
@@ -526,8 +523,8 @@ index 000000000000..5786d1825dad
+ unsigned int pwm_index[2] = {0};
+ struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
+
+ pwm_index[0] = pwm->pwm - chip->base;
+ pwm_index[1] = bind_num - chip->base;
+ pwm_index[0] = pwm->hwpwm;
+ pwm_index[1] = bind_num - (int)chip->id;
+
+ /* if duty time < dead time,it is wrong. */
+ dead_time = pc->config[pwm_index[0]].dead_time;
@@ -704,7 +701,7 @@ index 000000000000..5786d1825dad
+
+ struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
+
+ bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
+ bind_num = pc->config[pwm->hwpwm].bind_pwm;
+ if (bind_num == 255) {
+ sunxi_pwm_config_single(chip, pwm, duty_ns, period_ns);
+ }
@@ -723,8 +720,8 @@ index 000000000000..5786d1825dad
+ struct platform_device *pwm_pdevice;
+ int ret;
+
+ index = pwm->pwm - chip->base;
+ sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
+ index = pwm->hwpwm;
+ sub_np = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", index);
+ if (IS_ERR_OR_NULL(sub_np))
+ {
+ pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
@@ -766,11 +763,11 @@ index 000000000000..5786d1825dad
+ int i = 0, ret = 0;
+ unsigned int pwm_index[2] = {0};
+
+ pwm_index[0] = pwm->pwm - chip->base;
+ pwm_index[1] = bind_num - chip->base;
+ pwm_index[0] = pwm->hwpwm;
+ pwm_index[1] = bind_num - (int)chip->id;
+
+ /*set current pwm pin state*/
+ sub_np[0] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[0]);
+ sub_np[0] = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", pwm_index[0]);
+ if (IS_ERR_OR_NULL(sub_np[0]))
+ {
+ pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
@@ -784,7 +781,7 @@ index 000000000000..5786d1825dad
+ }
+
+ /*set bind pwm pin state*/
+ sub_np[1] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[1]);
+ sub_np[1] = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", pwm_index[1]);
+ if (IS_ERR_OR_NULL(sub_np[1]))
+ {
+ pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
@@ -835,7 +832,7 @@ index 000000000000..5786d1825dad
+ int ret = 0;
+ struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
+
+ bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
+ bind_num = pc->config[pwm->hwpwm].bind_pwm;
+ if (bind_num == 255)
+ ret = sunxi_pwm_enable_single(chip, pwm);
+ else
@@ -853,8 +850,8 @@ index 000000000000..5786d1825dad
+ struct device_node *sub_np;
+ struct platform_device *pwm_pdevice;
+
+ index = pwm->pwm - chip->base;
+ sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
+ index = pwm->hwpwm;
+ sub_np = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", index);
+ if (IS_ERR_OR_NULL(sub_np))
+ {
+ pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
@@ -906,11 +903,11 @@ index 000000000000..5786d1825dad
+ int i = 0;
+ unsigned int pwm_index[2] = {0};
+
+ pwm_index[0] = pwm->pwm - chip->base;
+ pwm_index[1] = bind_num - chip->base;
+ pwm_index[0] = pwm->hwpwm;
+ pwm_index[1] = bind_num - (int)chip->id;
+
+ /* get current index pwm device */
+ sub_np[0] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[0]);
+ sub_np[0] = of_parse_phandle(pwmchip_parent(chip)->of_node, "pwms", pwm_index[0]);
+ if (IS_ERR_OR_NULL(sub_np[0]))
+ {
+ pr_err("%s: can't parse \"pwms\" property\n", __func__);
@@ -923,7 +920,7 @@ index 000000000000..5786d1825dad
+ return;
+ }
+ /* get bind pwm device */
+ sub_np[1] = of_parse_phandle(chip->dev->of_node, "pwms", pwm_index[1]);
+ sub_np[1] = of_parse_phandle(pwmchip_parent(chip)->of_node, "pwms", pwm_index[1]);
+ if (IS_ERR_OR_NULL(sub_np[1]))
+ {
+ pr_err("%s: can't parse \"pwms\" property\n", __func__);
@@ -976,7 +973,7 @@ index 000000000000..5786d1825dad
+ int bind_num;
+ struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
+
+ bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
+ bind_num = pc->config[pwm->hwpwm].bind_pwm;
+ if (bind_num == 255)
+ sunxi_pwm_disable_single(chip, pwm);
+ else
@@ -1039,18 +1036,29 @@ index 000000000000..5786d1825dad
+static int sunxi_pwm_probe(struct platform_device *pdev)
+{
+ int ret;
+ unsigned int npwm;
+ struct pwm_chip *chip;
+ struct sunxi_pwm_chip *pwm;
+ struct device_node *np = pdev->dev.of_node;
+ int i;
+ struct platform_device *pwm_pdevice;
+ struct device_node *sub_np;
+
+ pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ /* read property pwm-number */
+ ret = of_property_read_u32(np, "pwm-number", &npwm);
+ if (ret < 0)
+ {
+ dev_err(&pdev->dev, "failed to allocate memory!\n");
+ return -ENOMEM;
+ dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
+ /* force to one pwm if read property fail */
+ npwm = 1;
+ }
+
+ chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*pwm));
+ if (IS_ERR(chip)) {
+ return PTR_ERR(chip);
+ }
+
+ pwm = to_sunxi_pwm_chip(chip);
+
+ /* io map pwm base */
+ pwm->base = (void __iomem *)of_iomap(pdev->dev.of_node, 0);
@@ -1061,43 +1069,35 @@ index 000000000000..5786d1825dad
+ goto err_iomap;
+ }
+
+ /* read property pwm-number */
+ ret = of_property_read_u32(np, "pwm-number", &pwm->chip.npwm);
+ if (ret < 0)
+ {
+ dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
+ /* force to one pwm if read property fail */
+ pwm->chip.npwm = 1;
+ }
+
+ /* read property pwm-base */
+ ret = of_property_read_u32(np, "pwm-base", &pwm->chip.base);
+ ret = of_property_read_u32(np, "pwm-base", &chip->id);
+ if (ret < 0)
+ {
+ dev_err(&pdev->dev, "failed to get pwm-base: %d, force to -1 !\n", ret);
+ /* force to one pwm if read property fail */
+ pwm->chip.base = -1;
+ chip->id = -1;
+ }
+ pwm->chip.dev = &pdev->dev;
+ pwm->chip.ops = &sunxi_pwm_ops;
+
+ chip->dev.parent = &pdev->dev;
+ chip->ops = &sunxi_pwm_ops;
+
+ /* add pwm chip to pwm-core */
+ ret = pwmchip_add(&pwm->chip);
+ ret = pwmchip_add(chip);
+ if (ret < 0)
+ {
+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+ goto err_add;
+ }
+ platform_set_drvdata(pdev, pwm);
+ platform_set_drvdata(pdev, chip);
+
+ pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * pwm->chip.npwm, GFP_KERNEL);
+ pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * npwm, GFP_KERNEL);
+ if (!pwm->config)
+ {
+ dev_err(&pdev->dev, "failed to allocate memory!\n");
+ goto err_alloc;
+ }
+
+ for (i = 0; i < pwm->chip.npwm; i++)
+ for (i = 0; i < npwm; i++)
+ {
+ sub_np = of_parse_phandle(np, "sunxi-pwms", i);
+ if (IS_ERR_OR_NULL(sub_np))
@@ -1159,7 +1159,7 @@ index 000000000000..5786d1825dad
+
+err_get_config:
+err_alloc:
+ pwmchip_remove(&pwm->chip);
+ pwmchip_remove(chip);
+err_add:
+ iounmap(pwm->base);
+err_iomap:
@@ -1168,11 +1168,12 @@ index 000000000000..5786d1825dad
+
+static int sunxi_pwm_remove(struct platform_device *pdev)
+{
+ struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
+ struct pwm_chip *chip = platform_get_drvdata(pdev);
+ struct sunxi_pwm_chip *pwm = to_sunxi_pwm_chip(chip);
+ clk_disable(pwm->clk);
+ clk_disable(pwm->bus_clk);
+ reset_control_assert(pwm->pwm_rst_clk);
+ pwmchip_remove(&pwm->chip);
+ pwmchip_remove(chip);
+
+ return 0;
+}
@@ -1312,5 +1313,5 @@ index 000000000000..e25e10bf5a3d
+#endif
+
--
2.35.3
GitLab