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odroidn2: u-boot: fix eMMC stability
This includes a patch that sets the maximum frequency to 24 MHz in U-Boot which improves reliability as previously U-Boot would randomly fail reading from the eMMC. Signed-off-by: Martin Pietryka <martin@pietryka.at>
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@@ -0,0 +1,42 @@
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From dc847a8091517dea6b4c07f7ed3b11cb8123b726 Mon Sep 17 00:00:00 2001
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From: Martin Pietryka <martin@pietryka.at>
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Date: Fri, 26 Apr 2024 15:43:21 +0200
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Subject: [PATCH] mmc: meson_gx_mmc: limit f_max to 24 MHz
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This fixes issues on the Odroid N2+ where reading from the eMMC is
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unreliable in U-Boot and probably being temperature dependent.
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Changing the clock phase to CLK_CO_PHASE_270 also improved stability, but
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a mailing-list post indicates that this could lead to other instabilities
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with other eMMC cards, see:
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- https://lists.denx.de/pipermail/u-boot/2020-December/434954.html
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Signed-off-by: Martin Pietryka <martin@pietryka.at>
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---
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drivers/mmc/meson_gx_mmc.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index fcf4f03d1e..9ecffccee4 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -279,7 +279,15 @@ static int meson_mmc_probe(struct udevice *dev)
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cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
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MMC_MODE_HS_52MHz | MMC_MODE_HS;
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cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
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- cfg->f_max = 100000000; /* 100 MHz */
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+
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+ /*
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+ * Some SoCs have issues with higher frequencies and combinations
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+ * of CLK_CO_PHASE_* values. So limit it to 24 MHz, which according
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+ * to a mailing list post seems to be more stable:
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+ * - https://lists.denx.de/pipermail/u-boot/2020-December/434954.html
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+ */
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+ cfg->f_max = 24000000; /* 24 MHz */
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+
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cfg->b_max = 511; /* max 512 - 1 blocks */
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cfg->name = dev->name;
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--
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2.44.0
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