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rockchip64: rk3568: add PLL rate for 33.3MHz

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Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
mode of 800x480

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
This commit is contained in:
Vasily Khoruzhick
2025-03-17 22:22:46 -07:00
committed by JohnTheCoolingFan
parent e9708b8c33
commit 49e7d58ecf
2 changed files with 56 additions and 0 deletions
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28
patch/kernel/archive/rockchip64-6.12/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch Normal file
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@@ -0,0 +1,28 @@
From ca7b6ebfe6f8a718cdb14b3fdc82ad1e5a26b4c9 Mon Sep 17 00:00:00 2001
From: Vasily Khoruzhick <anarsoul@gmail.com>
Date: Mon, 17 Mar 2025 22:22:46 -0700
Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 33.3MHz
Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
mode of 800x480
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 53d10b1c627b..1c73e18a9862 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
{ /* sentinel */ },
};
--
2.49.0

28
patch/kernel/archive/rockchip64-6.14/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch Normal file
View File

@@ -0,0 +1,28 @@
From ca7b6ebfe6f8a718cdb14b3fdc82ad1e5a26b4c9 Mon Sep 17 00:00:00 2001
From: Vasily Khoruzhick <anarsoul@gmail.com>
Date: Mon, 17 Mar 2025 22:22:46 -0700
Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 33.3MHz
Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
mode of 800x480
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 53d10b1c627b..1c73e18a9862 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
{ /* sentinel */ },
};
--
2.49.0