move kernel media to current 6.0 and edge 6.1 (#4566)

config/sources/families/media.conf

@@ -72,30 +72,17 @@ case $BRANCH in
 		;;
 
 	current)
-
-		KERNELBRANCH="branch:linux-5.19.y"
+		KERNELBRANCH="branch:linux-6.0.y"
 		LINUXCONFIG='linux-media-'$BRANCH
-
-		if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == quartz64a || $BOARD == bananapir2pro ]]; then
-			KERNELPATCHDIR='station-p2-'$BRANCH
-			LINUXFAMILY=station-p2
-		else
 		KERNELPATCHDIR='media-'$BRANCH
 		LINUXFAMILY=media
-#			if [[ $BOARD == jetson-nano ]]; then
-#				MODULES_INITRD="jetson-nano-current"
-#			fi
-		fi
 		;;
 
 	edge)
-		KERNELBRANCH="branch:linux-6.0.y"
+		KERNELBRANCH="branch:linux-6.1.y"
 		KERNELPATCHDIR='media-'$BRANCH
 		LINUXFAMILY=media
 		LINUXCONFIG='linux-media-'$BRANCH
-#		if [[ $BOARD == jetson-nano ]]; then
-#			MODULES_INITRD="jetson-nano-edge"
-#		fi
 		;;
 esac
 

patch/kernel/archive/media-5.19/00410-general-disable-mtu-validation.patch

@@ -1,51 +0,0 @@
-From bf80eaa34a1b9f503a779b13deed2fda642a1e87 Mon Sep 17 00:00:00 2001
-From: Igor Pecovnik <igor.pecovnik@gmail.com>
-Date: Wed, 21 Jul 2021 20:59:39 +0000
-Subject: [PATCH] Disable MTU validation
-
-This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98
-
-It works around following issues:
- - no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac)
-
-Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
-Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ------------
- 1 file changed, 12 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 91cd5073d..b409a7598 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -5435,14 +5435,8 @@ static void stmmac_set_rx_mode(struct net_device *dev)
- static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
- {
- 	struct stmmac_priv *priv = netdev_priv(dev);
--	int txfifosz = priv->plat->tx_fifo_size;
- 	const int mtu = new_mtu;
- 
--	if (txfifosz == 0)
--		txfifosz = priv->dma_cap.tx_fifo_size;
--
--	txfifosz /= priv->plat->tx_queues_to_use;
--
- 	if (netif_running(dev)) {
- 		netdev_err(priv->dev, "must be stopped to change its MTU\n");
- 		return -EBUSY;
-@@ -5453,12 +5447,6 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
- 		return -EINVAL;
- 	}
- 
--	new_mtu = STMMAC_ALIGN(new_mtu);
--
--	/* If condition true, FIFO is too small or MTU too large */
--	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
--		return -EINVAL;
--
- 	dev->mtu = mtu;
- 
- 	netdev_update_features(dev);
--- 
-Created with Armbian build tools https://github.com/armbian/build
-

patch/kernel/archive/media-5.19/00560-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch

@@ -1,19 +0,0 @@
-diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
-index 415d8ece242a..1d1f9dbd9e93 100644
---- a/net/dsa/tag_mtk.c
-+++ b/net/dsa/tag_mtk.c
-@@ -25,6 +25,14 @@ static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
- 	u8 xmit_tpid;
- 	u8 *mtk_tag;
- 
-+	/* The Ethernet switch we are interfaced with needs packets to be at
-+	 * least 64 bytes (including FCS) otherwise their padding might be
-+	 * corrupted. With tags enabled, we need to make sure that packets are
-+	 * at least 68 bytes (including FCS and tag).
-+	 */
-+	if (__skb_put_padto(skb, ETH_ZLEN + MTK_HDR_LEN, false))
-+		return NULL;
-+
- 	/* Build the special tag after the MAC Source Address. If VLAN header
- 	 * is present, it's required that VLAN header and special tag is
- 	 * being combined. Only in this way we can allow the switch can parse

patch/kernel/archive/media-5.19/00570-pwm-fan-fix.patch

@@ -1,60 +0,0 @@
-diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
-index f7405a58877e..73303458e886 100644
---- a/drivers/clk/tegra/clk-tegra114.c
-+++ b/drivers/clk/tegra/clk-tegra114.c
-@@ -1166,6 +1166,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
- 	{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
- 	{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
- 	{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
-+	{ TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 },
- 	/* must be the last entry */
- 	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
- };
-diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
-index a9d4efcef2d4..6c46592d794e 100644
---- a/drivers/clk/tegra/clk-tegra124.c
-+++ b/drivers/clk/tegra/clk-tegra124.c
-@@ -1330,6 +1330,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
- 	{ TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
- 	{ TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
- 	{ TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
-+	{ TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 },
- 	/* must be the last entry */
- 	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
- };
-diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
-index 8a4514f6d503..422d78247553 100644
---- a/drivers/clk/tegra/clk-tegra20.c
-+++ b/drivers/clk/tegra/clk-tegra20.c
-@@ -1044,6 +1044,7 @@ static struct tegra_clk_init_table init_table[] = {
- 	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
- 	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
- 	{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
-+	{ TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },
- 	/* must be the last entry */
- 	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
- };
-diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
-index 499f999e91e1..a3488aaac3f7 100644
---- a/drivers/clk/tegra/clk-tegra210.c
-+++ b/drivers/clk/tegra/clk-tegra210.c
-@@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
- 	{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
- 	{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
- 	{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
-+	{ TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 },
- 	/* This MUST be the last entry. */
- 	{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
- };
-diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
-index 168c07d5a5f2..60f1534711f1 100644
---- a/drivers/clk/tegra/clk-tegra30.c
-+++ b/drivers/clk/tegra/clk-tegra30.c
-@@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] = {
- 	{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
- 	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
- 	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
-+	{ TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },
- 	/* must be the last entry */
- 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
- };

patch/kernel/archive/media-5.19/00590-board-helios64-dts-fix-stability-issues.patch

@@ -1,12 +0,0 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-index e666bd5ae..df1fc943b 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-@@ -478,6 +478,7 @@ rk808: pmic@1b {
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pmic_int_l>;
- 		rockchip,system-power-controller;
-+		max-buck-steps-per-change = <4>;
- 		wakeup-source;
- 
- 		vcc1-supply = <&vcc5v0_sys>;

patch/kernel/archive/media-5.19/00600-board-helios64-remove-overclock.patch

@@ -1,32 +0,0 @@
-From aca2e1df74ae43ddaa3870b31a6eba129148bdcf Mon Sep 17 00:00:00 2001
-From: Aditya Prayoga <aditya@kobol.io>
-Date: Mon, 7 Sep 2020 20:29:43 +0700
-Subject: [PATCH] Remove overclock from helios64
-
-Signed-off-by: Aditya Prayoga <aditya@kobol.io>
----
- arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-index ba8ff5d4c..c065ba82d 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-@@ -1078,4 +1078,12 @@
- 
- &vopl_mmu {
- 	status = "okay";
--};
-\ No newline at end of file
-+};
-+
-+&cluster0_opp {
-+	/delete-node/ opp06;
-+};
-+
-+&cluster1_opp {
-+	/delete-node/ opp08;
-+};
--- 
-Created with Armbian build tools https://github.com/armbian/build
-

patch/kernel/archive/media-5.19/00610-board-helios64-remove-pcie-ep-gpios.patch

@@ -1,25 +0,0 @@
-From e7e9a3a959927094d59b67f46ecc1c5d50190ce8 Mon Sep 17 00:00:00 2001
-From: Aditya Prayoga <aditya@kobol.io>
-Date: Tue, 15 Sep 2020 13:42:02 +0700
-Subject: [PATCH] Remove PCIE ep-gpios from Helios64
-
-Signed-off-by: Aditya Prayoga <aditya@kobol.io>
----
- arch/arm64/boot/dts/rockchip/rk3399-helios64.dts | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-index c065ba82d..002c93912 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-@@ -721,7 +721,6 @@
- };
-
- &pcie0 {
--	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- 	num-lanes = <2>;
- 	max-link-speed = <2>;
- 	pinctrl-names = "default";
---
-Created with Armbian build tools https://github.com/armbian/build
-

patch/kernel/archive/media-6.0/00120-v91-rk356x-vpu.patch

@@ -1,32 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -617,6 +617,28 @@
- 		#cooling-cells = <2>;
- 		power-domains = <&power RK3568_PD_GPU>;
- 		status = "disabled";
-+	};
-+
-+	vpu: video-codec@fdea0400 {
-+		compatible = "rockchip,rk3328-vpu";
-+		reg = <0x0 0xfdea0000 0x0 0x800>;
-+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "vdpu";
-+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vdpu_mmu>;
-+		power-domains = <&power RK3568_PD_VPU>;
-+	};
-+
-+	vdpu_mmu: iommu@fdea0800 {
-+		compatible = "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdea0800 0x0 0x40>;
-+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "vdpu_mmu";
-+		clock-names = "aclk", "iface";
-+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-+		power-domains = <&power RK3568_PD_VPU>;
-+		#iommu-cells = <0>;
- 	};
- 
- 	sdmmc2: mmc@fe000000 {
-

patch/kernel/media-current

@@ -1 +0,0 @@
-archive/media-5.19

patch/kernel/media-current/00180-linux-0002-rockchip-from-list.patch

@@ -270,10 +270,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 8 insertions(+)
 
 diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
-index 4b70cbfc6d5d..5329f983db15 100644
+index ef53a2578824..d4c53074154a 100644
 --- a/drivers/mmc/core/core.c
 +++ b/drivers/mmc/core/core.c
-@@ -1356,6 +1356,14 @@ void mmc_power_off(struct mmc_host *host)
+@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host)
  	if (host->ios.power_mode == MMC_POWER_OFF)
  		return;
  

patch/kernel/media-current/00190-linux-0011-v4l2-from-list.patch

@@ -17,10 +17,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 38 insertions(+), 39 deletions(-)
 
 diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
-index df34b2a283bc..287488016ff2 100644
+index e0fbe6ba4b6c..cb2f1acab7cf 100644
 --- a/drivers/media/v4l2-core/v4l2-common.c
 +++ b/drivers/media/v4l2-core/v4l2-common.c
-@@ -336,6 +336,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
+@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
  	return info->block_h[plane];
  }
  
@@ -54,7 +54,7 @@ index df34b2a283bc..287488016ff2 100644
  void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
  				    const struct v4l2_frmsize_stepwise *frmsize)
  {
-@@ -371,37 +398,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
  
  	if (info->mem_planes == 1) {
  		plane = &pixfmt->plane_fmt[0];
@@ -99,7 +99,7 @@ index df34b2a283bc..287488016ff2 100644
  		}
  	}
  	return 0;
-@@ -425,22 +434,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
+@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
  	pixfmt->width = width;
  	pixfmt->height = height;
  	pixfmt->pixelformat = pixelformat;
@@ -154,12 +154,12 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  3 files changed, 8 insertions(+)
 
 diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
-index 287488016ff2..01f8a50586eb 100644
+index cb2f1acab7cf..8446a1deffd8 100644
 --- a/drivers/media/v4l2-core/v4l2-common.c
 +++ b/drivers/media/v4l2-core/v4l2-common.c
-@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
- 		{ .format = V4L2_PIX_FMT_NV24,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
+@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
  		{ .format = V4L2_PIX_FMT_NV42,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
+ 		{ .format = V4L2_PIX_FMT_P010,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
  
 +		{ .format = V4L2_PIX_FMT_NV15,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
 +		{ .format = V4L2_PIX_FMT_NV20,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
@@ -168,25 +168,25 @@ index 287488016ff2..01f8a50586eb 100644
  		{ .format = V4L2_PIX_FMT_YVU410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
  		{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 },
 diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
-index 21470de62d72..cb7496c084f6 100644
+index e6fd355a2e92..24771edaa4f2 100644
 --- a/drivers/media/v4l2-core/v4l2-ioctl.c
 +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
-@@ -1306,6 +1306,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
- 	case V4L2_PIX_FMT_NV61:		descr = "Y/CrCb 4:2:2"; break;
+@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
  	case V4L2_PIX_FMT_NV24:		descr = "Y/CbCr 4:4:4"; break;
  	case V4L2_PIX_FMT_NV42:		descr = "Y/CrCb 4:4:4"; break;
+ 	case V4L2_PIX_FMT_P010:		descr = "10-bit Y/CbCr 4:2:0"; break;
 +	case V4L2_PIX_FMT_NV15:		descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
 +	case V4L2_PIX_FMT_NV20:		descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break;
  	case V4L2_PIX_FMT_NV12_4L4:	descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
  	case V4L2_PIX_FMT_NV12_16L16:	descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
  	case V4L2_PIX_FMT_NV12_32L32:   descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
 diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
-index 343b95107fce..3a5d6290a379 100644
+index 01e630f2ec78..cea44992aea3 100644
 --- a/include/uapi/linux/videodev2.h
 +++ b/include/uapi/linux/videodev2.h
-@@ -603,6 +603,9 @@ struct v4l2_pix_format {
- #define V4L2_PIX_FMT_NV24    v4l2_fourcc('N', 'V', '2', '4') /* 24  Y/CbCr 4:4:4  */
+@@ -628,6 +628,9 @@ struct v4l2_pix_format {
  #define V4L2_PIX_FMT_NV42    v4l2_fourcc('N', 'V', '4', '2') /* 24  Y/CrCb 4:4:4  */
+ #define V4L2_PIX_FMT_P010    v4l2_fourcc('P', '0', '1', '0') /* 24  Y/CbCr 4:2:0 10-bit per component */
  
 +#define V4L2_PIX_FMT_NV15    v4l2_fourcc('N', 'V', '1', '5') /* 15  Y/CbCr 4:2:0 10-bit packed */
 +#define V4L2_PIX_FMT_NV20    v4l2_fourcc('N', 'V', '2', '0') /* 20  Y/CbCr 4:2:2 10-bit packed */
@@ -212,10 +212,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 2992fb87cf72..54fc3a6d0902 100644
+index 4fc167b42cf0..a8635105e387 100644
 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c
 +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -915,9 +915,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
+@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
  	dma_addr_t rlc_addr;
  	dma_addr_t refer_addr;
  	u32 rlc_len;
@@ -228,7 +228,7 @@ index 2992fb87cf72..54fc3a6d0902 100644
  	u32 yuv_virstride = 0;
  	u32 offset;
  	dma_addr_t dst_addr;
-@@ -928,8 +928,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
+@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
  
  	f = &ctx->decoded_fmt;
  	dst_fmt = &f->fmt.pix_mp;
@@ -487,10 +487,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  2 files changed, 37 insertions(+), 15 deletions(-)
 
 diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 54fc3a6d0902..af530b05a789 100644
+index a8635105e387..0069d3d198db 100644
 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c
 +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -1044,19 +1044,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
  {
  	unsigned int width, height;
  
@@ -514,7 +514,7 @@ index 54fc3a6d0902..af530b05a789 100644
  		return -EINVAL;
  
  	width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
-@@ -1077,6 +1072,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
+@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
  	return 0;
  }
  
@@ -540,7 +540,7 @@ index 54fc3a6d0902..af530b05a789 100644
  static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
  {
  	struct rkvdec_dev *rkvdec = ctx->dev;
-@@ -1198,6 +1212,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
  
  const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
  	.adjust_fmt = rkvdec_h264_adjust_fmt,
@@ -624,7 +624,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 7 insertions(+), 6 deletions(-)
 
 diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index af530b05a789..f31b7c021d82 100644
+index 0069d3d198db..2c27acaba85e 100644
 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c
 +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
 @@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,

patch/kernel/media-current/00200-linux-0020-drm-from-list.patch

@@ -43,7 +43,7 @@ index 07741b678798..5ec38456dc5d 100644
  		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
  		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
 diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
-index f1972154a594..b972d0adfa2e 100644
+index 0206f812c569..fa49ee98f275 100644
 --- a/include/uapi/drm/drm_fourcc.h
 +++ b/include/uapi/drm/drm_fourcc.h
 @@ -285,6 +285,8 @@ extern "C" {
@@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang <hjc@rock-chips.com>
  3 files changed, 54 insertions(+), 8 deletions(-)
 
 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-index 74562d40f639..9560f82ce880 100644
+index d32117633efe..9e71263ac770 100644
 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
 +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -274,6 +274,18 @@ static bool has_uv_swapped(uint32_t format)
+@@ -280,6 +280,18 @@ static bool has_uv_swapped(uint32_t format)
  	}
  }
  
@@ -98,7 +98,7 @@ index 74562d40f639..9560f82ce880 100644
  static enum vop_data_format vop_convert_format(uint32_t format)
  {
  	switch (format) {
-@@ -289,12 +301,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
+@@ -295,12 +307,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
  	case DRM_FORMAT_BGR565:
  		return VOP_FMT_RGB565;
  	case DRM_FORMAT_NV12:
@@ -114,7 +114,7 @@ index 74562d40f639..9560f82ce880 100644
  	case DRM_FORMAT_NV42:
  		return VOP_FMT_YUV444SP;
  	default:
-@@ -948,7 +963,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+@@ -954,7 +969,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
  	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
  	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
  
@@ -128,7 +128,7 @@ index 74562d40f639..9560f82ce880 100644
  	offset += (src->y1 >> 16) * fb->pitches[0];
  	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
  
-@@ -974,6 +994,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+@@ -980,6 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
  	}
  
  	VOP_WIN_SET(vop, win, format, format);
@@ -136,7 +136,7 @@ index 74562d40f639..9560f82ce880 100644
  	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
  	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
  	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
-@@ -990,7 +1011,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
+@@ -996,7 +1017,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
  		uv_obj = fb->obj[1];
  		rk_uv_obj = to_rockchip_obj(uv_obj);
  
@@ -150,10 +150,10 @@ index 74562d40f639..9560f82ce880 100644
  
  		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-index ba88addc1a75..567f226930b2 100644
+index 8502849833d9..b6eea31109d5 100644
 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
 +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -179,6 +179,7 @@ struct vop_win_phy {
+@@ -181,6 +181,7 @@ struct vop_win_phy {
  	struct vop_reg enable;
  	struct vop_reg gate;
  	struct vop_reg format;
@@ -162,7 +162,7 @@ index ba88addc1a75..567f226930b2 100644
  	struct vop_reg uv_swap;
  	struct vop_reg act_info;
 diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-index d03dd0402923..3b39b5a5f100 100644
+index 014f99e8928e..16e6aa01e400 100644
 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
 +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
 @@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] = {
@@ -219,7 +219,7 @@ index d03dd0402923..3b39b5a5f100 100644
  	.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
  	.uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15),
  	.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
-@@ -906,11 +925,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
+@@ -924,11 +943,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
  
  static const struct vop_win_phy rk3399_win01_data = {
  	.scl = &rk3288_win_full_scl,

patch/kernel/media-current/00220-linux-1001-v4l2-rockchip.patch

@@ -1,39 +1,3 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sat, 23 May 2020 10:18:16 +0000
-Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding
- finish
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 4f5436c89e08..06c23512e1a7 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -1016,7 +1016,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
- 	state = (status & RKVDEC_RDY_STA) ?
- 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
- 
--	writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT);
-+	writel(RKVDEC_CONFIG_DEC_CLK_GATE_E,
-+	       rkvdec->regs + RKVDEC_REG_INTERRUPT);
- 	if (cancel_delayed_work(&rkvdec->watchdog_work)) {
- 		struct rkvdec_ctx *ctx;
- 
-@@ -1037,7 +1038,8 @@ static void rkvdec_watchdog_func(struct work_struct *work)
- 	ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
- 	if (ctx) {
- 		dev_err(rkvdec->dev, "Frame processing timed out!\n");
--		writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
-+		writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS,
-+		       rkvdec->regs + RKVDEC_REG_INTERRUPT);
- 		writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
- 		rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
- 	}
-
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Sat, 23 May 2020 10:16:01 +0000
@@ -46,10 +10,10 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 06c23512e1a7..630ef09ab70b 100644
+index 4f5436c89e08..eaf2f133a264 100644
 --- a/drivers/staging/media/rkvdec/rkvdec.c
 +++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -1127,9 +1127,9 @@ static int rkvdec_remove(struct platform_device *pdev)
+@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev)
  {
  	struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev);
  
@@ -235,7 +199,7 @@ index 15b9bee92016..3acc914888f6 100644
  #define RKVDEC_REG_SYSCTRL				0x008
  #define RKVDEC_IN_ENDIAN				BIT(0)
 diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 630ef09ab70b..b6d5b26a93c2 100644
+index eaf2f133a264..f55abb7c377f 100644
 --- a/drivers/staging/media/rkvdec/rkvdec.c
 +++ b/drivers/staging/media/rkvdec/rkvdec.c
 @@ -10,12 +10,15 @@
@@ -300,7 +264,7 @@ index 630ef09ab70b..b6d5b26a93c2 100644
  
  	ret = pm_runtime_resume_and_get(rkvdec->dev);
  	if (ret < 0) {
-@@ -1021,6 +1056,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
+@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
  	if (cancel_delayed_work(&rkvdec->watchdog_work)) {
  		struct rkvdec_ctx *ctx;
  
@@ -312,15 +276,15 @@ index 630ef09ab70b..b6d5b26a93c2 100644
  		ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
  		rkvdec_job_finish(ctx, state);
  	}
-@@ -1038,6 +1078,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
+@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
  	ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
  	if (ctx) {
  		dev_err(rkvdec->dev, "Frame processing timed out!\n");
 +		rkvdec->reset_mask |= RESET_HARD;
- 		writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS,
- 		       rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ 		writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
  		writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
-@@ -1107,6 +1148,18 @@ static int rkvdec_probe(struct platform_device *pdev)
+ 		rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
+@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev)
  		return ret;
  	}
  
@@ -389,7 +353,7 @@ Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399
  1 file changed, 9 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index b0620c45820c..e797271ef6b4 100644
+index 980b12cb0a49..6e3149e587c5 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 @@ -1062,7 +1062,10 @@ power-domain@RK3399_PD_VCODEC {
@@ -428,7 +392,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index e797271ef6b4..748eb7368e6a 100644
+index 6e3149e587c5..093ebe070775 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 @@ -1341,7 +1341,7 @@ vpu_mmu: iommu@ff650800 {
@@ -454,7 +418,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 11 insertions(+), 3 deletions(-)
 
 diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index fc96501f3bc8..f31550c21172 100644
+index 8de6fd2e8eef..002b1a600f93 100644
 --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
 +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
 @@ -15,7 +15,8 @@
@@ -467,7 +431,7 @@ index fc96501f3bc8..f31550c21172 100644
  
  /*
   * Supported formats.
-@@ -273,13 +274,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
+@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
  	return 0;
  }
  
@@ -489,7 +453,7 @@ index fc96501f3bc8..f31550c21172 100644
  static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
  {
  	struct hantro_dev *vpu = ctx->dev;
-@@ -507,7 +515,7 @@ const struct hantro_variant rk3288_vpu_variant = {
+@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = {
  	.codec_ops = rk3288_vpu_codec_ops,
  	.irqs = rockchip_vpu1_irqs,
  	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
@@ -499,29 +463,6 @@ index fc96501f3bc8..f31550c21172 100644
  	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
  };
 
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sun, 3 Apr 2022 13:45:57 +0200
-Subject: [PATCH] media: hantro: rockchip: Enable H.264 codec for RK3399
-
----
- drivers/staging/media/hantro/rockchip_vpu_hw.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index f31550c21172..304d7b359295 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -544,7 +544,7 @@ const struct hantro_variant rk3399_vpu_variant = {
- 	.dec_fmts = rk3399_vpu_dec_fmts,
- 	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
- 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
--		 HANTRO_VP8_DECODER,
-+		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
- 	.codec_ops = rk3399_vpu_codec_ops,
- 	.irqs = rockchip_vpu2_irqs,
- 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
-
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Alex Bee <knaerzche@gmail.com>
 Date: Sun, 4 Jul 2021 15:19:44 +0200
@@ -548,7 +489,7 @@ index 3acc914888f6..265f5234f4eb 100644
  #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND		0x450
  
 diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
-index 311a12656072..ea270262bbed 100644
+index d8c1c0db15c7..a289bc968e91 100644
 --- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
 +++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
 @@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
@@ -574,31 +515,6 @@ index 311a12656072..ea270262bbed 100644
  	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
  	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
 
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Thu, 16 Jun 2022 13:15:09 +0200
-Subject: [PATCH] arm64: dts: use correct PLL for vdec core
-
-vdec core should use codec pll for proper operation, by default
-it uses general pll (GPLL) - as all other clocks would
----
- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 748eb7368e6a..658ec3b00445 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1346,6 +1346,8 @@ vdec: video-codec@ff660000 {
- 		clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
- 			 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
- 		clock-names = "axi", "ahb", "cabac", "core";
-+		assigned-clocks = <&cru ACLK_VDU>;
-+		assigned-clock-parents = <&cru PLL_CPLL>;
- 		iommus = <&vdec_mmu>;
- 		power-domains = <&power RK3399_PD_VDU>;
- 		resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
-
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Alex Bee <knaerzche@gmail.com>
 Date: Thu, 16 Jun 2022 13:18:22 +0200

patch/kernel/media-current/00230-linux-1002-for-libreelec.patch

@@ -6,16 +6,48 @@ Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and
 
 Note: since the regulator that supplies the GPU usually also supplies
 other SoC components, we have to make sure voltage is never lower then
-1050 mV - also disable 500 MHz for now, since it will crash if rkvdec
+1075 mV - also disable 500 MHz for now, since it will crash if rkvdec
 is running at the same time (voltage to high)
 
 Signed-off-by: Alex Bee <knaerzche@gmail.com>
 ---
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 ++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
+ .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts |  4 +++
+ .../arm64/boot/dts/rockchip/rk3328-rock64.dts |  4 +++
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi      | 35 +++++++++++++++++++
+ 3 files changed, 43 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index aa22a0c22265..51c7723d6762 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -166,6 +166,10 @@ &gmac2io {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_logic>;
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+index f69a38f42d2d..c198a8a7f95a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+@@ -162,6 +162,10 @@ &gmac2io {
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_logic>;
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-index 431c4ec198be..e4977669b16a 100644
+index 431c4ec198be..eec03adf0902 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 @@ -300,6 +300,11 @@ power: power-controller {
@@ -57,15 +89,15 @@ index 431c4ec198be..e4977669b16a 100644
 +
 +		opp-200000000 {
 +			opp-hz = /bits/ 64 <200000000>;
-+			opp-microvolt = <1050000>;
++			opp-microvolt = <1075000>;
 +		};
 +		opp-300000000 {
 +			opp-hz = /bits/ 64 <300000000>;
-+			opp-microvolt = <1050000>;
++			opp-microvolt = <1075000>;
 +		};
 +		opp-400000000 {
 +			opp-hz = /bits/ 64 <400000000>;
-+			opp-microvolt = <1050000>;
++			opp-microvolt = <1075000>;
 +		};
 +		opp-500000000 {
 +			opp-hz = /bits/ 64 <500000000>;
@@ -137,10 +169,10 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
-index 9c1e38c54eae..ee332fc9cf1f 100644
+index 09618bb7d872..db9106a3dd22 100644
 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi
 +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
-@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq {
+@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq {
  	sound {
  		compatible = "simple-audio-card";
  		simple-audio-card,format = "i2s";
@@ -150,10 +182,10 @@ index 9c1e38c54eae..ee332fc9cf1f 100644
  
  		simple-audio-card,codec {
 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 658ec3b00445..925d320dea86 100644
+index 093ebe070775..a10fe60b7680 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1892,7 +1892,7 @@ hdmi_sound: hdmi-sound {
+@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound {
  		compatible = "simple-audio-card";
  		simple-audio-card,format = "i2s";
  		simple-audio-card,mclk-fs = <256>;
@@ -174,10 +206,10 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
-index eb0c2d041f13..9256eadb8a3e 100644
+index ad068865ba20..9deb8d1d291d 100644
 --- a/drivers/gpu/drm/drm_gem.c
 +++ b/drivers/gpu/drm/drm_gem.c
-@@ -1053,7 +1053,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
+@@ -1038,7 +1038,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
  		ret = obj->funcs->mmap(obj, vma);
  		if (ret)
  			goto err_drm_gem_object_put;
@@ -197,7 +229,7 @@ Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation
  1 file changed, 52 insertions(+), 61 deletions(-)
 
 diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
-index b773466619b2..e53950e85631 100644
+index 5679102de91f..f0cd183f7873 100644
 --- a/sound/soc/codecs/hdmi-codec.c
 +++ b/sound/soc/codecs/hdmi-codec.c
 @@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
@@ -395,7 +427,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 14 insertions(+)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-index aa22a0c22265..a78fbddd21df 100644
+index 51c7723d6762..cf321302daec 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
 @@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator {
@@ -412,7 +444,7 @@ index aa22a0c22265..a78fbddd21df 100644
  	leds {
  		compatible = "gpio-leds";
  
-@@ -308,6 +315,13 @@ &io_domains {
+@@ -312,6 +319,13 @@ &io_domains {
  };
  
  &pinctrl {
@@ -553,10 +585,10 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 925d320dea86..037732441f92 100644
+index a10fe60b7680..dbe6a9cb98a5 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1478,7 +1478,7 @@ cru: clock-controller@ff760000 {
+@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 {
  			<1000000000>,
  			 <150000000>,   <75000000>,
  			  <37500000>,
@@ -609,7 +641,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
-index f50b47ac11a8..d9b3c8c29e6f 100644
+index a2f0860b20bb..8961f9c7885d 100644
 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
 +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
 @@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
@@ -634,3 +666,47 @@ index f50b47ac11a8..d9b3c8c29e6f 100644
  	.audio_startup  = dw_hdmi_i2s_audio_startup,
  	.audio_shutdown	= dw_hdmi_i2s_audio_shutdown,
  	.get_eld	= dw_hdmi_i2s_get_eld,
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 18 Sep 2022 10:35:52 +0200
+Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc
+
+As it will lead to an unbootable device in case one if those ports
+is used to power up the device.
+See https://lkml.org/lkml/2022/6/20/413
+---
+ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+index 2f4b1b2e3ac7..7217ead94d39 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+@@ -215,7 +215,7 @@ vdd_log: vdd-log {
+ 		regulator-name = "vdd_log";
+ 		regulator-always-on;
+ 		regulator-boot-on;
+-		regulator-min-microvolt = <450000>;
++		regulator-min-microvolt = <430000>;
+ 		regulator-max-microvolt = <1400000>;
+ 		pwm-supply = <&vcc3v3_sys>;
+ 	};
+@@ -536,7 +536,7 @@ fusb1: usb-typec@22 {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&fusb1_int>;
+ 		vbus-supply = <&vcc_vbus_typec1>;
+-		status = "okay";
++		status = "disabled";
+ 	};
+ };
+ 
+@@ -553,7 +553,7 @@ fusb0: usb-typec@22 {
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&fusb0_int>;
+ 		vbus-supply = <&vcc_vbus_typec0>;
+-		status = "okay";
++		status = "disabled";
+ 	};
+ 
+ 	mp8859: regulator@66 {

patch/kernel/media-current/00250-linux-2001-v4l2-wip-iep-driver.patch

@@ -1687,7 +1687,7 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 22 insertions(+)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-index e4977669b16a..6c0cbc9cea61 100644
+index eec03adf0902..5455a46c9a6b 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 @@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 {
@@ -1731,10 +1731,10 @@ Signed-off-by: Alex Bee <knaerzche@gmail.com>
  1 file changed, 12 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 037732441f92..d90c90406a49 100644
+index dbe6a9cb98a5..f0629b7a81c6 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1367,14 +1367,25 @@ vdec_mmu: iommu@ff660480 {
+@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 {
  		#iommu-cells = <0>;
  	};
  

patch/kernel/media-current/00590-add-driver-for-Motorcomm-YT85xx+PHYs.patch

@@ -0,0 +1,656 @@
+From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001
+From: baiywt <baiywt_gj@163.com>
+Date: Fri, 18 Feb 2022 16:38:43 +0800
+Subject: [PATCH] Add yt8531c support. 
+Adapted from orangepi-xunlong/openwrt - 600-Add-yt8531c-support.patch by schwar3kat
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/motorcomm.c   | 1540 +++++++++++++++++++++++++++++++++
+ drivers/net/phy/yt8614-phy.h  |  491 +++++++++++
+ include/linux/motorcomm_phy.h |  119 +++
+ 5 files changed, 2156 insertions(+)
+ create mode 100644 drivers/net/phy/motorcomm.c
+ create mode 100644 drivers/net/phy/yt8614-phy.h
+ create mode 100644 include/linux/motorcomm_phy.h
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index ce030fcb1..ff4861847 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -297,6 +297,11 @@ config MICROSEMI_PHY
+ 	help
+ 	  Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
+ 
++config MOTORCOMM_PHY
++        tristate "Motorcomm PHYs"
++        help
++          Supports the YT8010, YT8510, YT8511, YT8512 YT8521 YT8531 PHYs.
++
+ config NATIONAL_PHY
+ 	tristate "National Semiconductor PHYs"
+ 	help
+diff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h
+new file mode 100644
+index 000000000..56a398338
+--- /dev/null
++++ b/drivers/net/phy/yt8614-phy.h
+@@ -0,0 +1,491 @@
++#ifndef _PHY_H_
++#define _PHY_H_
++
++
++/* configuration for driver */
++
++#define YT8614_MAX_LPORT_ID		3
++
++#define YT8614_PHY_MODE_FIBER	1 //fiber mode only
++#define YT8614_PHY_MODE_UTP		2 //utp mode only
++#define YT8614_PHY_MODE_POLL	3 //fiber and utp, poll mode
++
++/* please make choice according to system design
++ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1
++ * for UTP only system, please define YT8614_PHY_MODE_CURR 2
++ * for combo system, please define YT8614_PHY_MODE_CURR 3 
++ */
++#define YT8614_PHY_MODE_CURR	3
++
++
++
++/* pls dont modify below lines */
++
++#define PHY_ID_YT8614  0x4F51E899 //serdes
++#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff
++
++#ifndef BOOL
++#define BOOL unsigned int
++#endif
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef SPEED_1000M
++#define SPEED_1000M     2
++#endif
++#ifndef SPEED_100M
++#define SPEED_100M     	1
++#endif
++#ifndef SPEED_10M
++#define SPEED_10M     	0
++#endif
++
++#ifndef SPEED_UNKNOWN
++#define SPEED_UNKNOWN   0xffff
++#endif
++
++#ifndef DUPLEX_FULL
++#define DUPLEX_FULL		1	
++#endif
++#ifndef DUPLEX_HALF
++#define DUPLEX_HALF		0	
++#endif
++
++#ifndef BIT
++#define BIT(n) (0x1<<(n))
++#endif
++#ifndef s32
++typedef int  s32;
++typedef unsigned int  u32;
++typedef unsigned short  u16;
++typedef unsigned char  u8;
++#endif
++
++#ifndef REG_PHY_SPEC_STATUS
++#define REG_PHY_SPEC_STATUS		0x11
++#define REG_DEBUG_ADDR_OFFSET		0x1e
++#define REG_DEBUG_DATA			0x1f
++#endif
++
++/**********YT8614************************************************/
++
++#define YT8614_SMI_SEL_PHY        0x0
++#define YT8614_SMI_SEL_SDS_QSGMII 0x02
++#define YT8614_SMI_SEL_SDS_SGMII  0x03
++
++/* yt8614 register type */
++#define YT8614_TYPE_COMMON         0x01
++#define YT8614_TYPE_UTP_MII        0x02
++#define YT8614_TYPE_UTP_EXT        0x03
++#define YT8614_TYPE_LDS_MII        0x04
++#define YT8614_TYPE_UTP_MMD        0x05
++#define YT8614_TYPE_SDS_QSGMII_MII 0x06
++#define YT8614_TYPE_SDS_SGMII_MII  0x07
++#define YT8614_TYPE_SDS_QSGMII_EXT 0x08
++#define YT8614_TYPE_SDS_SGMII_EXT  0x09
++
++/* YT8614 extended common register */
++#define YT8614_REG_COM_SMI_MUX        0xA000
++#define YT8614_REG_COM_SLED_CFG0      0xA001
++#define YT8614_REG_COM_PHY_ID         0xA002
++#define YT8614_REG_COM_CHIP_VER       0xA003
++#define YT8614_REG_COM_SLED_CFG       0xA004
++#define YT8614_REG_COM_MODE_CHG_RESET 0xA005
++#define YT8614_REG_COM_SYNCE0_CFG     0xA006
++#define YT8614_REG_COM_CHIP_MODE      0xA007
++
++#define YT8614_REG_COM_HIDE_SPEED     0xA009
++
++#define YT8614_REG_COM_SYNCE1_CFG     0xA00E
++
++#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019
++
++
++#define YT8614_REG_COM_HIDE_SEL1      0xA054
++#define YT8614_REG_COM_HIDE_LED_CFG2  0xB8
++#define YT8614_REG_COM_HIDE_LED_CFG3  0xB9
++#define YT8614_REG_COM_HIDE_LED_CFG5  0xBB
++
++#define YT8614_REG_COM_HIDE_LED_CFG4  0xBA //not used currently
++
++#if 0
++#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently
++#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061
++#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062
++#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063
++#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064
++#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065
++#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066
++#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067
++#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068
++#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069
++#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A
++#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B
++#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C
++#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D
++#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E
++#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F
++#endif
++
++#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070
++#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071
++#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072
++#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073
++#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074
++#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075
++#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076
++#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077
++
++#define YT8614_REG_COM_PKG_CFG0       0xA0A0
++#define YT8614_REG_COM_PKG_CFG1       0xA0A1
++#define YT8614_REG_COM_PKG_CFG2       0xA0A2
++#define YT8614_REG_COM_PKG_RX_VALID0  0xA0A3
++#define YT8614_REG_COM_PKG_RX_VALID1  0xA0A4
++#define YT8614_REG_COM_PKG_RX_OS0     0xA0A5
++#define YT8614_REG_COM_PKG_RX_OS1     0xA0A6
++#define YT8614_REG_COM_PKG_RX_US0     0xA0A7
++#define YT8614_REG_COM_PKG_RX_US1     0xA0A8
++#define YT8614_REG_COM_PKG_RX_ERR     0xA0A9
++#define YT8614_REG_COM_PKG_RX_OS_BAD  0xA0AA
++#define YT8614_REG_COM_PKG_RX_FRAG    0xA0AB
++#define YT8614_REG_COM_PKG_RX_NOSFD   0xA0AC
++#define YT8614_REG_COM_PKG_TX_VALID0  0xA0AD
++#define YT8614_REG_COM_PKG_TX_VALID1  0xA0AE
++#define YT8614_REG_COM_PKG_TX_OS0     0xA0AF
++
++#define YT8614_REG_COM_PKG_TX_OS1     0xA0B0
++#define YT8614_REG_COM_PKG_TX_US0     0xA0B1
++#define YT8614_REG_COM_PKG_TX_US1     0xA0B2
++#define YT8614_REG_COM_PKG_TX_ERR     0xA0B3
++#define YT8614_REG_COM_PKG_TX_OS_BAD  0xA0B4
++#define YT8614_REG_COM_PKG_TX_FRAG    0xA0B5
++#define YT8614_REG_COM_PKG_TX_NOSFD   0xA0B6
++#define YT8614_REG_COM_PKG_CFG3       0xA0B7
++#define YT8614_REG_COM_PKG_AZ_CFG     0xA0B8
++#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9
++
++#define YT8614_REG_COM_MANU_HW_RESET  0xA0C0
++
++/* YT8614 UTP MII register: same as generic phy register definitions */
++#define REG_MII_BMCR          0x00    /* Basic mode control register */
++#define REG_MII_BMSR          0x01    /* Basic mode status register  */
++#define REG_MII_PHYSID1       0x02    /* PHYS ID 1                   */
++#define REG_MII_PHYSID2       0x03    /* PHYS ID 2                   */
++#define REG_MII_ADVERTISE     0x04    /* Advertisement control reg   */
++#define REG_MII_LPA           0x05    /* Link partner ability reg    */
++#define REG_MII_EXPANSION     0x06    /* Expansion register          */
++#define REG_MII_NEXT_PAGE     0x07    /* Next page register          */
++#define REG_MII_LPR_NEXT_PAGE 0x08    /* LPR next page register      */
++#define REG_MII_CTRL1000      0x09    /* 1000BASE-T control          */
++#define REG_MII_STAT1000      0x0A    /* 1000BASE-T status           */
++
++#define REG_MII_MMD_CTRL      0x0D    /* MMD access control register */
++#define REG_MII_MMD_DATA      0x0E    /* MMD access data register    */
++
++#define REG_MII_ESTATUS       0x0F    /* Extended Status             */
++#define REG_MII_SPEC_CTRL     0x10    /* PHY specific func control   */
++#define REG_MII_SPEC_STATUS   0x11    /* PHY specific status         */
++#define REG_MII_INT_MASK      0x12    /* Interrupt mask register     */
++#define REG_MII_INT_STATUS    0x13    /* Interrupt status register   */
++#define REG_MII_DOWNG_CTRL    0x14    /* Speed auto downgrade control*/
++#define REG_MII_RERRCOUNTER   0x15    /* Receive error counter       */
++
++#define REG_MII_EXT_ADDR      0x1E    /* Extended reg's address      */
++#define REG_MII_EXT_DATA      0x1F    /* Extended reg's date         */
++
++#ifndef MII_BMSR
++#define MII_BMSR						REG_MII_BMSR
++#endif
++
++#ifndef YT8614_SPEED_MODE_BIT
++#define YT8614_SPEED_MODE		0xc000
++#define YT8614_DUPLEX			0x2000
++#define YT8614_SPEED_MODE_BIT		14
++#define YT8614_DUPLEX_BIT		13
++#define YT8614_LINK_STATUS_BIT		10
++
++#endif
++
++#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI		0x2000
++
++/* YT8614 UTP MMD register  */
++#define YT8614_REG_UTP_MMD_CTRL1           0x00    /* PCS control 1 register     */
++#define YT8614_REG_UTP_MMD_STATUS1         0x01    /* PCS status 1 register      */
++#define YT8614_REG_UTP_MMD_EEE_CTRL        0x14    /* EEE control and capability */
++#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT  0x16    /* EEE wake error counter     */
++#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI   0x3C    /* local device EEE ability   */
++#define YT8614_REG_UTP_MMD_EEE_LP_ABI      0x3D    /* link partner EEE ability   */
++#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000  /* autoneg result of EEE      */
++
++/* YT8614 UTP EXT register  */
++#define YT8614_REG_UTP_EXT_LPBK        0x0A
++#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27
++#define YT8614_REG_UTP_EXT_DEBUG_MON1  0x5A
++#define YT8614_REG_UTP_EXT_DEBUG_MON2  0x5B
++#define YT8614_REG_UTP_EXT_DEBUG_MON3  0x5C
++#define YT8614_REG_UTP_EXT_DEBUG_MON4  0x5D
++
++/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */
++#define REG_SDS_BMCR          0x00    /* Basic mode control register */
++#define REG_SDS_BMSR          0x01    /* Basic mode status register  */
++#define REG_SDS_PHYSID1       0x02    /* PHYS ID 1                   */
++#define REG_SDS_PHYSID2       0x03    /* PHYS ID 2                   */
++#define REG_SDS_ADVERTISE     0x04    /* Advertisement control reg   */
++#define REG_SDS_LPA           0x05    /* Link partner ability reg    */
++#define REG_SDS_EXPANSION     0x06    /* Expansion register          */
++#define REG_SDS_NEXT_PAGE     0x07    /* Next page register          */
++#define REG_SDS_LPR_NEXT_PAGE 0x08    /* LPR next page register      */
++
++#define REG_SDS_ESTATUS       0x0F    /* Extended Status             */
++#define REG_SDS_SPEC_STATUS   0x11    /* SDS specific status         */
++
++#define REG_SDS_100FX_CFG     0x14    /* 100fx cfg                   */
++#define REG_SDS_RERRCOUNTER   0x15    /* Receive error counter       */
++#define REG_SDS_LINT_FAIL_CNT 0x16    /* Lint fail counter mon       */
++
++/* YT8614 SDS(5G) EXT register */
++#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02    /* sds analog digital interface cfg */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG1   0x05    /* sds prbs cfg1 */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06    /* sds prbs cfg2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07    /* sds prbs cfg2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON1   0x08    /* sds prbs mon1 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON2   0x09    /* sds prbs mon2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON3   0x0A    /* sds prbs mon3 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON4   0x0B    /* sds prbs mon4 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON5   0x0C    /* sds prbs mon5 */
++#define YT8614_REG_QSGMII_EXT_ANA_CFG2    0xA1    /* Analog cfg2   */
++
++/* YT8614 SDS(1.25G) EXT register */
++#define YT8614_REG_SGMII_EXT_PRBS_CFG1    0x05    /* sds prbs cfg1 */
++#define YT8614_REG_SGMII_EXT_PRBS_CFG2    0x06    /* sds prbs cfg2 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON1    0x08    /* sds prbs mon1 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON2    0x09    /* sds prbs mon2 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON3    0x0A    /* sds prbs mon3 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON4    0x0B    /* sds prbs mon4 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON5    0x0C    /* sds prbs mon5 */
++#define YT8614_REG_SGMII_EXT_ANA_CFG2     0xA1    /* Analog cfg2   */
++#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5   /* Fiber auto sensing */
++
++////////////////////////////////////////////////////////////////////
++#define YT8614_MMD_DEV_ADDR1     0x1
++#define YT8614_MMD_DEV_ADDR3     0x3
++#define YT8614_MMD_DEV_ADDR7     0x7
++#define YT8614_MMD_DEV_ADDR_NONE 0xFF
++
++/**********YT8521S************************************************/
++/* Basic mode control register(0x00) */
++#define BMCR_RESV         0x003f  /* Unused...                   */
++#define BMCR_SPEED1000    0x0040  /* MSB of Speed (1000)         */
++#define BMCR_CTST         0x0080  /* Collision test              */
++#define BMCR_FULLDPLX     0x0100  /* Full duplex                 */
++#define BMCR_ANRESTART    0x0200  /* Auto negotiation restart    */
++#define BMCR_ISOLATE      0x0400  /* Disconnect DP83840 from MII */
++#define BMCR_PDOWN        0x0800  /* Powerdown the DP83840       */
++#define BMCR_ANENABLE     0x1000  /* Enable auto negotiation     */
++#define BMCR_SPEED100     0x2000  /* Select 100Mbps              */
++#define BMCR_LOOPBACK     0x4000  /* TXD loopback bits           */
++#define BMCR_RESET        0x8000  /* Reset the DP83840           */
++
++/* Basic mode status register(0x01) */
++#define BMSR_ERCAP        0x0001  /* Ext-reg capability          */
++#define BMSR_JCD          0x0002  /* Jabber detected             */
++#define BMSR_LSTATUS      0x0004  /* Link status                 */
++#define BMSR_ANEGCAPABLE  0x0008  /* Able to do auto-negotiation */
++#define BMSR_RFAULT       0x0010  /* Remote fault detected       */
++#define BMSR_ANEGCOMPLETE 0x0020  /* Auto-negotiation complete   */
++#define BMSR_RESV         0x00c0  /* Unused...                   */
++#define BMSR_ESTATEN      0x0100  /* Extended Status in R15      */
++#define BMSR_100HALF2     0x0200  /* Can do 100BASE-T2 HDX       */
++#define BMSR_100FULL2     0x0400  /* Can do 100BASE-T2 FDX       */
++#define BMSR_10HALF       0x0800  /* Can do 10mbps, half-duplex  */
++#define BMSR_10FULL       0x1000  /* Can do 10mbps, full-duplex  */
++#define BMSR_100HALF      0x2000  /* Can do 100mbps, half-duplex */
++#define BMSR_100FULL      0x4000  /* Can do 100mbps, full-duplex */
++#define BMSR_100BASE4     0x8000  /* Can do 100mbps, 4k packets  */
++
++/* Advertisement control register(0x04) */
++#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
++#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
++#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
++#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
++#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
++#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
++#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
++#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
++#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
++#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
++#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
++#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
++#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
++#define ADVERTISE_RESV          0x1000  /* Unused...                   */
++#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
++#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
++#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
++
++#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
++#define ADVERTISE_ALL  (ADVERTISE_10HALF  | ADVERTISE_10FULL | \
++                        ADVERTISE_100HALF | ADVERTISE_100FULL)
++
++/* Link partner ability register(0x05) */
++#define LPA_SLCT              0x001f  /* Same as advertise selector    */
++#define LPA_10HALF            0x0020  /* Can do 10mbps half-duplex     */
++#define LPA_1000XFULL         0x0020  /* Can do 1000BASE-X full-duplex */
++#define LPA_10FULL            0x0040  /* Can do 10mbps full-duplex     */
++#define LPA_1000XHALF         0x0040  /* Can do 1000BASE-X half-duplex */
++#define LPA_100HALF           0x0080  /* Can do 100mbps half-duplex    */
++#define LPA_1000XPAUSE        0x0080  /* Can do 1000BASE-X pause       */
++#define LPA_100FULL           0x0100  /* Can do 100mbps full-duplex    */
++#define LPA_1000XPAUSE_ASYM   0x0100  /* Can do 1000BASE-X pause asym  */
++#define LPA_100BASE4          0x0200  /* Can do 100mbps 4k packets     */
++#define LPA_PAUSE_CAP         0x0400  /* Can pause                     */
++#define LPA_PAUSE_ASYM        0x0800  /* Can pause asymetrically       */
++#define LPA_RESV              0x1000  /* Unused...                     */
++#define LPA_RFAULT            0x2000  /* Link partner faulted          */
++#define LPA_LPACK             0x4000  /* Link partner acked us         */
++#define LPA_NPAGE             0x8000  /* Next page bit                 */
++
++/* 1000BASE-T Control register(0x09) */
++#define ADVERTISE_1000FULL    0x0200  /* Advertise 1000BASE-T full duplex */
++#define ADVERTISE_1000HALF    0x0100  /* Advertise 1000BASE-T half duplex */
++#define CTL1000_AS_MASTER     0x0800
++#define CTL1000_ENABLE_MASTER 0x1000
++
++/* 1000BASE-T Status register(0x0A) */
++#define LPA_1000LOCALRXOK     0x2000  /* Link partner local receiver status  */
++#define LPA_1000REMRXOK       0x1000  /* Link partner remote receiver status */
++#define LPA_1000FULL          0x0800  /* Link partner 1000BASE-T full duplex */
++#define LPA_1000HALF          0x0400  /* Link partner 1000BASE-T half duplex */
++
++/**********YT8614************************************************/
++/* Basic mode control register(0x00) */
++#define FIBER_BMCR_RESV        0x001f  /* b[4:0] Unused...                      */
++#define FIBER_BMCR_EN_UNIDIR   0x0020  /* b[5]   Valid when bit 0.12 is zero and bit 0.8 is one */
++#define FIBER_BMCR_SPEED1000   0x0040  /* b[6]   MSB of Speed (1000)            */
++#define FIBER_BMCR_CTST        0x0080  /* b[7]   Collision test                 */
++#define FIBER_BMCR_DUPLEX_MODE 0x0100  /* b[8]   Duplex mode                    */
++#define FIBER_BMCR_ANRESTART   0x0200  /* b[9]   Auto negotiation restart       */
++#define FIBER_BMCR_ISOLATE     0x0400  /* b[10]  Isolate phy from RGMII/SGMII/FIBER */
++#define FIBER_BMCR_PDOWN       0x0800  /* b[11]  1: Power down                  */
++#define FIBER_BMCR_ANENABLE    0x1000  /* b[12]  Enable auto negotiation        */
++#define FIBER_BMCR_SPEED100    0x2000  /* b[13]  LSB of Speed (100)             */
++#define FIBER_BMCR_LOOPBACK    0x4000  /* b[14]  Internal loopback control      */
++#define FIBER_BMCR_RESET       0x8000  /* b[15]  PHY Software Reset(self-clear) */
++
++/* Sds specific status register(0x11) */
++#define FIBER_SSR_ERCAP          0x0001  /* b[0]     realtime syncstatus */
++#define FIBER_SSR_XMIT           0x000E  /* b[3:1]   realtime transmit statemachine.
++                                                     001: Xmit Idle;
++                                                     010: Xmit Config; 
++                                                     100: Xmit Data. */
++#define FIBER_SSR_SER_MODE_CFG   0x0030  /* b[5:4]   realtime serdes working mode.
++                                                     00: SG_MAC;
++                                                     01: SG_PHY;
++                                                     10: FIB_1000;
++                                                     11: FIB_100. */
++#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040  /* b[6]     realtime en_flowctrl_tx */
++#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080  /* b[7]     realtime en_flowctrl_rx */
++#define FIBER_SSR_DUPLEX_ERROR   0x0100  /* b[8]     realtime deplex error */
++#define FIBER_SSR_RX_LPI_ACTIVE  0x0200  /* b[9]     rx lpi is active */
++#define FIBER_SSR_LSTATUS        0x0400  /* b[10]    Link status real-time */
++#define FIBER_SSR_PAUSE          0x1800  /* b[12:11] Pause to mac */
++#define FIBER_SSR_DUPLEX         0x2000  /* b[13]    This status bit is valid only when bit10 is 1.
++                                                     1: full duplex 
++                                                     0: half duplex */
++#define FIBER_SSR_SPEED_MODE     0xC000  /* b[15:14] These status bits are valid only when bit10 is 1.
++                                                     10---1000M 
++                                                     01---100M */
++
++/* SLED cfg0 (ext 0xA001) */
++#define FIBER_SLED_CFG0_EN_CTRL  0x00FF  /* b[7:0]   Control to enable the eight ports' SLED */
++#define FIBER_SLED_CFG0_BIT_MASK 0x0700  /* b[10:8]  1: enable the pin output */
++#define FIBER_SLED_CFG0_ACT_LOW  0x0800  /* b[11]    control SLED's polarity. 1: active low; 0: active high */
++#define FIBER_SLED_CFG0_MANU_ST  0x7000  /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */
++#define FIBER_SLED_CFG0_MANU_EN  0x8000  /* b[15]    to control serial LEDs status manually */
++
++/**********YT8614************************************************/
++/* Fiber auto sensing(sgmii ext 0xA5) */
++#define FIBER_AUTO_SEN_ENABLE    0x8000  /* b[15]  Enable fiber auto sensing */
++
++/* Fiber force speed(common ext 0xA009) */
++#define FIBER_FORCE_1000M        0x0001  /* b[0]  1:1000BX 0:100FX */
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++/* errno */
++enum ytphy_8614_errno_e
++{
++	SYS_E_NONE,
++	SYS_E_PARAM,
++	SYS_E_MAX
++};
++
++/* errno */
++enum ytphy_8614_combo_speed_e
++{
++	YT8614_COMBO_FIBER_1000M,
++	YT8614_COMBO_FIBER_100M,
++	YT8614_COMBO_UTP_ONLY,
++	YT8614_COMBO_SPEED_MAX
++};
++
++/* definition for porting */
++/* phy registers access */
++typedef struct
++{
++    u16 reg;     /* the offset of the phy internal address */
++    u16 val;     /* the value of the register */
++    u8  regType; /* register type */
++} phy_data_s;
++
++/* for porting use.
++ * pls over-write member function read/write for mdio access
++ */
++typedef struct phy_info_str
++{
++#if 0
++    struct phy_device *phydev;
++	int mdio_base;
++#endif
++	unsigned int lport;
++	unsigned int bus_id;
++	unsigned int phy_addr;
++
++    s32 (*read)(struct phy_info_str *info, phy_data_s *param);
++    s32 (*write)(struct phy_info_str *info, phy_data_s *param);
++}phy_info_s;
++
++/* get phy access method */
++s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param);
++s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param);
++s32 yt8614_phy_soft_reset(u32 lport);
++s32 yt8614_phy_init(u32 lport);
++s32 yt8614_fiber_enable(u32 lport, BOOL enable);
++s32 yt8614_utp_enable(u32 lport, BOOL enable);
++s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable);
++s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable);
++s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed);
++s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii);
++int yt8614_combo_media_priority_set (u32 lport, int fiber);
++int yt8614_combo_media_priority_get (u32 lport, int *fiber);
++s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable);
++s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask);
++s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask);
++s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full);
++s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full);
++s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed);
++s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed);
++int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg);
++int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media);
++
++#endif
+diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h
+new file mode 100644
+index 000000000..9e01fc205
+--- /dev/null
++++ b/include/linux/motorcomm_phy.h
+@@ -0,0 +1,119 @@
++/*
++ * include/linux/motorcomm_phy.h
++ *
++ * Motorcomm PHY IDs
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef _MOTORCOMM_PHY_H
++#define _MOTORCOMM_PHY_H
++
++#define MOTORCOMM_PHY_ID_MASK	0x00000fff
++#define MOTORCOMM_PHY_ID_8531_MASK	0xffffffff
++#define MOTORCOMM_MPHY_ID_MASK	0x0000ffff
++
++#define PHY_ID_YT8010		0x00000309
++#define PHY_ID_YT8510		0x00000109
++#define PHY_ID_YT8511		0x0000010a
++#define PHY_ID_YT8512		0x00000118
++#define PHY_ID_YT8512B		0x00000128
++#define PHY_ID_YT8521		0x0000011a
++#define PHY_ID_YT8531S		0x4f51e91a
++#define PHY_ID_YT8531		0x4f51e91b
++//#define PHY_ID_YT8614		0x0000e899
++#define PHY_ID_YT8618		0x0000e889
++
++#define REG_PHY_SPEC_STATUS		0x11
++#define REG_DEBUG_ADDR_OFFSET		0x1e
++#define REG_DEBUG_DATA			0x1f
++
++#define YT8512_EXTREG_AFE_PLL		0x50
++#define YT8512_EXTREG_EXTEND_COMBO	0x4000
++#define YT8512_EXTREG_LED0		0x40c0
++#define YT8512_EXTREG_LED1		0x40c3
++
++#define YT8512_EXTREG_SLEEP_CONTROL1	0x2027
++
++#define YT_SOFTWARE_RESET		0x8000
++
++#define YT8512_CONFIG_PLL_REFCLK_SEL_EN	0x0040
++#define YT8512_CONTROL1_RMII_EN		0x0001
++#define YT8512_LED0_ACT_BLK_IND		0x1000
++#define YT8512_LED0_DIS_LED_AN_TRY	0x0001
++#define YT8512_LED0_BT_BLK_EN		0x0002
++#define YT8512_LED0_HT_BLK_EN		0x0004
++#define YT8512_LED0_COL_BLK_EN		0x0008
++#define YT8512_LED0_BT_ON_EN		0x0010
++#define YT8512_LED1_BT_ON_EN		0x0010
++#define YT8512_LED1_TXACT_BLK_EN	0x0100
++#define YT8512_LED1_RXACT_BLK_EN	0x0200
++#define YT8512_SPEED_MODE		0xc000
++#define YT8512_DUPLEX			0x2000
++
++#define YT8512_SPEED_MODE_BIT		14
++#define YT8512_DUPLEX_BIT		13
++#define YT8512_EN_SLEEP_SW_BIT		15
++
++#define YT8521_EXTREG_SLEEP_CONTROL1	0x27
++#define YT8521_EN_SLEEP_SW_BIT		15
++
++#define YT8521_SPEED_MODE		0xc000
++#define YT8521_DUPLEX			0x2000
++#define YT8521_SPEED_MODE_BIT		14
++#define YT8521_DUPLEX_BIT		13
++#define YT8521_LINK_STATUS_BIT		10
++
++/* based on yt8521 wol config register */
++#define YTPHY_UTP_INTR_REG             0x12
++/* WOL Event Interrupt Enable */
++#define YTPHY_WOL_INTR            BIT(6)
++
++/* Magic Packet MAC address registers */
++#define YTPHY_MAGIC_PACKET_MAC_ADDR2                 0xa007
++#define YTPHY_MAGIC_PACKET_MAC_ADDR1                 0xa008
++#define YTPHY_MAGIC_PACKET_MAC_ADDR0                 0xa009
++
++#define YTPHY_WOL_CFG_REG		0xa00a
++#define YTPHY_WOL_CFG_TYPE		BIT(0)	/* WOL TYPE */
++#define YTPHY_WOL_CFG_EN		BIT(3)	/* WOL Enable */
++#define YTPHY_WOL_CFG_INTR_SEL	BIT(6)	/* WOL Event Interrupt Enable */
++#define YTPHY_WOL_CFG_WIDTH1	BIT(1)	/* WOL Pulse Width */
++#define YTPHY_WOL_CFG_WIDTH2	BIT(2)
++
++#define YTPHY_REG_SPACE_UTP             0
++#define YTPHY_REG_SPACE_FIBER           2
++
++enum ytphy_wol_type_e
++{
++    YTPHY_WOL_TYPE_LEVEL,
++    YTPHY_WOL_TYPE_PULSE,
++    YTPHY_WOL_TYPE_MAX
++};
++typedef enum ytphy_wol_type_e ytphy_wol_type_t;
++
++enum ytphy_wol_width_e
++{
++    YTPHY_WOL_WIDTH_84MS,
++    YTPHY_WOL_WIDTH_168MS,
++    YTPHY_WOL_WIDTH_336MS,
++    YTPHY_WOL_WIDTH_672MS,
++    YTPHY_WOL_WIDTH_MAX
++};
++typedef enum ytphy_wol_width_e ytphy_wol_width_t;
++
++struct ytphy_wol_cfg_s
++{
++    int enable;
++    int type;
++    int width;
++};
++typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;
++
++#endif /* _MOTORCOMM_PHY_H */
++
++
+-- 
+2.25.1
+

patch/kernel/media-current/00980-builddeb.patch

@@ -71,7 +71,7 @@
  cat >> $tmpdir/DEBIAN/postinst <<- EOT
  	ln -sf $(basename $installed_image_path) /boot/$image_name 2> /dev/null || cp /$installed_image_path /boot/$image_name
 +	cd /boot
-+	ln -sfT linux-image-$version dtb 2> /dev/null || mv linux-image-$version dtb
++	ln -sfT linux-image-$version dtb 2> /dev/null || cp linux-image-$version dtb
  	touch /boot/.next
  	exit 0
  EOT

patch/kernel/media-edge

@@ -1 +0,0 @@
-archive/media-6.0

patch/kernel/media-edge/00100-v91-i2s-mclk.patch

@@ -0,0 +1,84 @@
+diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
+index 606ae6cd918b..ee8924ac0093 100644
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -13,6 +13,8 @@
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include "clk.h"
+ 
++#define RK3568_GRF_SOC_CON1	0x504
++#define RK3568_GRF_SOC_CON2	0x508
+ #define RK3568_GRF_SOC_STATUS0	0x580
+ 
+ enum rk3568_pmu_plls {
+@@ -247,13 +249,13 @@ PNAME(dpll_gpll_cpll_p)			= { "dpll", "gpll", "cpll" };
+ PNAME(clk_ddr1x_p)			= { "clk_ddrphy1x_src", "dpll" };
+ PNAME(gpll200_gpll150_gpll100_xin24m_p)	= { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
+ PNAME(gpll100_gpll75_gpll50_p)		= { "gpll_100m", "gpll_75m", "cpll_50m" };
+-PNAME(i2s0_mclkout_tx_p)		= { "clk_i2s0_8ch_tx", "xin_osc0_half" };
+-PNAME(i2s0_mclkout_rx_p)		= { "clk_i2s0_8ch_rx", "xin_osc0_half" };
+-PNAME(i2s1_mclkout_tx_p)		= { "clk_i2s1_8ch_tx", "xin_osc0_half" };
+-PNAME(i2s1_mclkout_rx_p)		= { "clk_i2s1_8ch_rx", "xin_osc0_half" };
+-PNAME(i2s2_mclkout_p)			= { "clk_i2s2_2ch", "xin_osc0_half" };
+-PNAME(i2s3_mclkout_tx_p)		= { "clk_i2s3_2ch_tx", "xin_osc0_half" };
+-PNAME(i2s3_mclkout_rx_p)		= { "clk_i2s3_2ch_rx", "xin_osc0_half" };
++PNAME(i2s0_mclkout_tx_p)		= { "mclk_i2s0_8ch_tx", "xin_osc0_half" };
++PNAME(i2s0_mclkout_rx_p)		= { "mclk_i2s0_8ch_rx", "xin_osc0_half" };
++PNAME(i2s1_mclkout_tx_p)		= { "mclk_i2s1_8ch_tx", "xin_osc0_half" };
++PNAME(i2s1_mclkout_rx_p)		= { "mclk_i2s1_8ch_rx", "xin_osc0_half" };
++PNAME(i2s2_mclkout_p)			= { "mclk_i2s2_2ch", "xin_osc0_half" };
++PNAME(i2s3_mclkout_tx_p)		= { "mclk_i2s3_2ch_tx", "xin_osc0_half" };
++PNAME(i2s3_mclkout_rx_p)		= { "mclk_i2s3_2ch_rx", "xin_osc0_half" };
+ PNAME(mclk_pdm_p)			= { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
+ PNAME(clk_i2c_p)			= { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
+ PNAME(gpll200_gpll150_gpll100_p)	= { "gpll_200m", "gpll_150m", "gpll_100m" };
+@@ -307,6 +309,12 @@ PNAME(clk_mac_2top_p)			= { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
+ PNAME(clk_pwm0_p)			= { "xin24m", "clk_pdpmu" };
+ PNAME(aclk_rkvdec_pre_p)		= { "gpll", "cpll" };
+ PNAME(clk_rkvdec_core_p)		= { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
++PNAME(i2s1_mclkout_p)			= { "i2s1_mclkout_rx", "i2s1_mclkout_tx" };
++PNAME(i2s3_mclkout_p)			= { "i2s3_mclkout_rx", "i2s3_mclkout_tx" };
++PNAME(i2s1_mclk_rx_ioe_p)		= { "i2s1_mclkin_rx", "i2s1_mclkout_rx" };
++PNAME(i2s1_mclk_tx_ioe_p)		= { "i2s1_mclkin_tx", "i2s1_mclkout_tx" };
++PNAME(i2s2_mclk_ioe_p)			= { "i2s2_mclkin", "i2s2_mclkout" };
++PNAME(i2s3_mclk_ioe_p)			= { "i2s3_mclkin", "i2s3_mclkout" };
+ 
+ static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
+ 	[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll",  mux_pll_p,
+@@ -704,6 +712,19 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
+ 			RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
+ 			RK3568_CLKGATE_CON(7), 11, GFLAGS),
+ 
++	MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
++	MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
++	MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
++	MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
++	MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
++	MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
++
+ 	GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
+ 			RK3568_CLKGATE_CON(5), 14, GFLAGS),
+ 	COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
+diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
+index d29890865150..251445cf7632 100644
+--- a/include/dt-bindings/clock/rk3568-cru.h
++++ b/include/dt-bindings/clock/rk3568-cru.h
+@@ -479,6 +479,12 @@
+ #define CPLL_25M		416
+ #define CPLL_100M		417
+ #define SCLK_DDRCLK		418
++#define I2S1_MCLKOUT		419
++#define I2S3_MCLKOUT		420
++#define I2S1_MCLK_RX_IOE	421
++#define I2S1_MCLK_TX_IOE	422
++#define I2S2_MCLK_IOE		423
++#define I2S3_MCLK_IOE		424
+ 
+ #define PCLK_CORE_PVTM		450
+ 

patch/kernel/media-edge/00110-v91-irq-gic-v3-its.patch

@@ -0,0 +1,192 @@
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -45,6 +45,7 @@
+ 
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
++#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE	(1 << 2)
+ 
+ #define RD_LOCAL_LPI_ENABLED                    BIT(0)
+ #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
+@@ -2176,6 +2177,11 @@
+ {
+ 	struct page *prop_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+ 		return NULL;
+@@ -2299,6 +2305,7 @@
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+ 	void *base;
++	gfp_t gfp_flags;
+ 
+ 	psz = baser->psz;
+ 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
+@@ -2310,7 +2317,10 @@
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2356,6 +2366,13 @@
+ 
+ 	its_write_baser(its, baser, val);
+ 	tmp = baser->val;
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		if (tmp & GITS_BASER_SHAREABILITY_MASK)
++			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++		else
++			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
++	}
+ 
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+@@ -2939,6 +2956,10 @@
+ {
+ 	struct page *pend_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3083,6 +3104,9 @@
+ 
+ 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+ 
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+@@ -3108,6 +3132,9 @@
+ 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -3271,7 +3298,12 @@
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
++		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++			gfp_flags |= GFP_DMA;
++		}
++
++		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3360,6 +3392,7 @@
+ 	int nr_lpis;
+ 	int nr_ites;
+ 	int sz;
++	gfp_t gfp_flags;
+ 
+ 	if (!its_alloc_device_table(its, dev_id))
+ 		return NULL;
+@@ -3367,7 +3400,11 @@
+ 	if (WARN_ON(!is_power_of_2(nvecs)))
+ 		nvecs = roundup_pow_of_two(nvecs);
+ 
+-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	gfp_flags = GFP_KERNEL;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++
++	dev = kzalloc(sizeof(*dev), gfp_flags);
+ 	/*
+ 	 * Even if the device wants a single LPI, the ITT must be
+ 	 * sized as a power of two (and you need at least one bit...).
+@@ -3375,7 +3412,8 @@
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++
++	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -4695,6 +4733,13 @@
+ 	 * page. Trick it into doing the right thing...
+ 	 */
+ 	its->vlpi_redist_offset = SZ_128K;
++	return true;
++}
++
++static bool __maybe_unused its_enable_quirk_rk3568(void *data)
++{
++	gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
++
+ 	return true;
+ }
+ 
+@@ -4745,6 +4790,13 @@
+ 	},
+ #endif
+ 	{
++		.desc	= "ITS: Rockchip RK3568 force no_local_cache",
++		.iidr	= 0x0201743b,
++		.mask	= 0xffffffff,
++		.init	= its_enable_quirk_rk3568,
++	},
++
++	{
+ 	}
+ };
+ 
+@@ -4999,6 +5051,7 @@
+ 	struct page *page;
+ 	u32 ctlr;
+ 	int err;
++	gfp_t gfp_flags;
+ 
+ 	its_base = its_map_one(res, &err);
+ 	if (!its_base)
+@@ -5052,7 +5105,11 @@
+ 
+ 	its->numa_node = numa_node;
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
++//	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++//		gfp_flags |= GFP_DMA;
++
++	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
+@@ -5082,6 +5139,9 @@
+ 
+ 	gits_write_cbaser(baser, its->base + GITS_CBASER);
+ 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+ 
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+

patch/kernel/media-edge/00120-rk356x-dtsi.patch

@@ -0,0 +1,38 @@
+--- v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -287,7 +287,7 @@
+ 			 <&cru ACLK_USB3OTG0>;
+ 		clock-names = "ref_clk", "suspend_clk",
+ 			      "bus_clk";
+-		dr_mode = "otg";
++		dr_mode = "host";
+ 		phy_type = "utmi_wide";
+ 		power-domains = <&power RK3568_PD_PIPE>;
+ 		resets = <&cru SRST_USB3OTG0>;
+@@ -1031,6 +1031,25 @@
+ 		status = "disabled";
+ 	};
+ 
++	i2s2_2ch: i2s@fe420000 {
++		compatible = "rockchip,rk3568-i2s-tdm";
++		reg = <0x0 0xfe420000 0x0 0x1000>;
++		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		dmas = <&dmac1 4>, <&dmac1 5>;
++		dma-names = "tx", "rx";
++		rockchip,cru = <&cru>;
++		rockchip,grf = <&grf>;
++		pinctrl-0 = <&i2s2m0_sclktx
++			     &i2s2m0_lrcktx
++			     &i2s2m0_sdi
++			     &i2s2m0_sdo>;
++		pinctrl-names = "default";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
+ 	i2s3_2ch: i2s@fe430000 {
+ 		compatible = "rockchip,rk3568-i2s-tdm";
+ 		reg = <0x0 0xfe430000 0x0 0x1000>;
+

patch/kernel/media-edge/00140-v95-make.patch

@@ -0,0 +1,9 @@
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -1,4 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-firefly-roc-pc.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-firefly-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb

patch/kernel/media-edge/00150-v95-rk3566-firefly-roc-pc.patch

@@ -0,0 +1,779 @@
+new file mode 100644
+index 000000000..fac2db500
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts
+@@ -0,0 +1,773 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ *
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++
++/ {
++	model = "Firefly rk3566-roc-pc";
++	compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
++
++	aliases {
++		ethernet0 = &gmac1;
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++		mmc2 = &sdmmc1;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	vcc5v0_in: vcc5v0_in {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_in";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_sys: vcc5v0_sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_in>;
++	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_host";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_otg: vcc5v0-otg-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_otg";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_otg_en>;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_enable_h>;
++		regulator-name = "vcc3v3_pcie_p";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_3v3>;
++	};
++
++	firefly_leds: leds {
++		compatible = "gpio-leds";
++		power_led: power {
++		label = "firefly:blue:power";
++		linux,default-trigger = "ir-power-click";
++		default-state = "on";
++		gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&led_power>;
++	};
++
++	user_led: user {
++		label = "firefly:yellow:user";
++		linux,default-trigger = "ir-user-click";
++		default-state = "off";
++		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&led_user>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
++	};
++
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Analog RK809";
++		simple-audio-card,mclk-fs = <256>;
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
++	rk_headset: rk-headset {
++		compatible = "rockchip_headset";
++		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det>;
++		io-channels = <&saradc 2>;    //HP_HOOK pin
++	};
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu_thermal {
++	trips {
++		cpu_hot: cpu_hot {
++			temperature = <55000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++	};
++};
++
++&gmac1 {
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_3v3>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m0_miim
++		     &gmac1m0_tx_bus2
++		     &gmac1m0_rx_bus2
++		     &gmac1m0_rgmii_clk
++		     &gmac1m0_clkinout
++		     &gmac1m0_rgmii_bus>;
++	snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++	tx_delay = <0x4e>;
++	rx_delay = <0x2c>;
++	phy-handle = <&rgmii_phy1>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint@0 {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		vin-supply = <&vcc5v0_sys>;
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-boot-on;
++		regulator-always-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
++		assigned-clock-rates = <12288000>;
++		assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
++		#clock-cells = <1>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT>;
++		pinctrl-names = "default", "pmic-sleep",
++				"pmic-power-off", "pmic-reset";
++		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
++
++		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
++		clock-output-names = "rk808-clkout1", "rk808-clkout2";
++		//fb-inner-reg-idxs = <2>;
++		/* 1: rst regs (default in codes), 0: rst the pmic */
++		pmic-reset-func = <0>;
++		/* not save the PMIC_POWER_EN register in uboot */
++		not-save-power-en = <1>;
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		wakeup-source;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vdd_gpu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-name = "vdda0v9_image";
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vccio_acodec";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_1v8";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++
++		codec {
++			mic-in-differential;
++		};
++	};
++};
++
++&i2s0_8ch {
++	status = "okay";
++};
++
++&i2s1_8ch {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s1m0_sclktx
++		     &i2s1m0_lrcktx
++		     &i2s1m0_sdi0
++		     &i2s1m0_sdo0>;
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
++	};
++};
++
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie_p>;
++	status = "okay";
++};
++
++&pinctrl {
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	bt {
++		bt_enable_h: bt-enable-h {
++			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_host_wake_l: bt-host-wake-l {
++			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		bt_wake_l: bt-wake-l {
++			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic_int {
++			rockchip,pins =
++				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_otg_en: vcc5v0-otg-en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pcie {
++		pcie_enable_h: pcie-enable-h {
++			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_reset_h: pcie-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	leds {
++		led_power: led-power {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		led_user: led-user {
++			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio2-supply = <&vcc_1v8>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs200-1_8v;
++	non-removable;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	status = "okay";
++};
++
++&sdmmc1 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	disable-wp;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	vmmc-supply = <&vcc3v3_sys>;
++	vqmmc-supply = <&vcca1v8_pmu>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>;
++	status = "okay";
++};
++
++&sdmmc2 {
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	bus-width = <4>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcca1v8_pmu>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&uart0 {
++//	pinctrl-names = "default";
++//	pinctrl-0 = <&uart0_xfer>;
++	status = "disabled";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
++	status = "okay";
++	uart-has-rtscts;
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&rk809 1>;
++		clock-names = "lpo";
++		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcca1v8_pmu>;
++	};
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	vbus-supply = <&vcc5v0_otg>;
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&vop {
++	compatible = "rockchip,rk3568-vop";
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
+

patch/kernel/media-edge/00160-v95-rk3568-bpi-r2pro.patch

@@ -0,0 +1,190 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -6,6 +6,7 @@
+ 
+ /dts-v1/;
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pwm/pwm.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/soc/rockchip,vop2.h>
+@@ -53,6 +54,14 @@
+ 		regulator-boot-on;
+ 		regulator-min-microvolt = <12000000>;
+ 		regulator-max-microvolt = <12000000>;
++	};
++
++	fan: gpio_fan {
++		compatible = "gpio-fan";
++		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
++		gpio-fan,speed-map = <0    0
++				      4500 1>;
++		#cooling-cells = <2>;
+ 	};
+ 
+ 	hdmi-con {
+@@ -119,6 +128,28 @@
+ 		regulator-max-microvolt = <5000000>;
+ 		vin-supply = <&vcc5v0_usb>;
+ 	};
++
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Analog RK809";
++		simple-audio-card,mclk-fs = <256>;
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
++	rk_headset: rk-headset {
++		compatible = "rockchip_headset";
++		headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det>;
++		io-channels = <&saradc 2>;    //HP_HOOK pin
++	};
+ };
+ 
+ &combphy0 {
+@@ -134,6 +165,39 @@
+ &combphy2 {
+ 	/* used for SATA */
+ 	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu_thermal {
++	trips {
++		cpu_hot: cpu_hot {
++			temperature = <55000>;
++			hysteresis = <2000>;
++			type = "active";
++		};
++	};
++
++	cooling-maps {
++		map1 {
++			trip = <&cpu_hot>;
++			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++		};
++	};
+ };
+ 
+ &gmac0 {
+@@ -216,15 +280,49 @@
+ &i2c0 {
+ 	status = "okay";
+ 
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		vin-supply = <&vcc5v0_sys>;
++		regulator-compatible = "fan53555-reg";
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1390000>;
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-boot-on;
++		regulator-always-on;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
+ 	rk809: pmic@20 {
+ 		compatible = "rockchip,rk809";
+ 		reg = <0x20>;
+ 		interrupt-parent = <&gpio0>;
+ 		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
++		assigned-clock-rates = <12288000>;
++		assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
+ 		#clock-cells = <1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT>;
++		pinctrl-names = "default", "pmic-sleep",
++				"pmic-power-off", "pmic-reset";
++		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
++
+ 		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
++		clock-output-names = "rk808-clkout1", "rk808-clkout2";
++		//fb-inner-reg-idxs = <2>;
++		/* 1: rst regs (default in codes), 0: rst the pmic */
++		pmic-reset-func = <0>;
++		/* not save the PMIC_POWER_EN register in uboot */
++		not-save-power-en = <1>;
++
+ 		vcc1-supply = <&vcc3v3_sys>;
+ 		vcc2-supply = <&vcc3v3_sys>;
+ 		vcc3-supply = <&vcc3v3_sys>;
+@@ -427,6 +525,10 @@
+ 					regulator-off-in-suspend;
+ 				};
+ 			};
++		};
++
++		codec {
++			mic-in-differential;
+ 		};
+ 	};
+ };
+@@ -458,6 +560,18 @@
+ 	status = "okay";
+ };
+ 
++&i2s1_8ch {
++	/* headphone */
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s1m0_sclktx
++		     &i2s1m0_lrcktx
++		     &i2s1m0_sdi0
++		     &i2s1m0_sdo0>;
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++
+ &mdio0 {
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+@@ -543,6 +657,12 @@
+ 
+ 		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ };
+