From 276f346ee9c21cdcd627e54676334f4d5a9292b6 Mon Sep 17 00:00:00 2001 From: Oleg Date: Wed, 14 Dec 2022 12:17:09 +0300 Subject: [PATCH] move kernel media to current 6.0 and edge 6.1 (#4566) --- config/kernel/linux-media-current.config | 496 +- config/kernel/linux-media-edge.config | 465 +- config/sources/families/media.conf | 21 +- ...00410-general-disable-mtu-validation.patch | 51 - ...a-tag_mtk-add-padding-for-tx-packets.patch | 19 - .../media-5.19/00570-pwm-fan-fix.patch | 60 - .../media-5.19/00580-add-board-helios64.patch | 1175 ---- ...rd-helios64-dts-fix-stability-issues.patch | 12 - ...0600-board-helios64-remove-overclock.patch | 32 - ...-board-helios64-remove-pcie-ep-gpios.patch | 25 - ...add-driver-for-Motorcomm-YT85xx+PHYs.patch | 2202 ------- .../media-6.0/00120-v91-rk356x-vpu.patch | 32 - .../media-6.0/00280-add-fusb30x-driver.patch | 4047 ------------ ...add-driver-for-Motorcomm-YT85xx+PHYs.patch | 2202 ------- patch/kernel/media-current | 1 - .../00100-v91-i2s-mclk.patch | 0 .../00110-v91-irq-gic-v3-its.patch | 0 .../00120-rk356x-dtsi.patch} | 0 .../00130-v95-make.patch} | 0 .../00140-v95-rk3566-firefly-roc-pc.patch} | 0 .../00150-v95-rk3568-bpi-r2pro.patch} | 0 .../00160-v95-rk3568-firefly-roc-pc.patch} | 0 .../00170-linux-0001-rockchip-from-6.1.patch | 5829 +++++++++++++++++ ...00180-linux-0002-rockchip-from-list.patch} | 4 +- .../00190-linux-0011-v4l2-from-list.patch} | 42 +- .../00200-linux-0020-drm-from-list.patch} | 22 +- .../00210-linux-1000-drm-rockchip.patch} | 1014 ++- .../00220-linux-1001-v4l2-rockchip.patch} | 112 +- .../00230-linux-1002-for-libreelec.patch} | 114 +- ...240-linux-2000-v4l2-wip-rkvdec-hevc.patch} | 839 +-- ...0250-linux-2001-v4l2-wip-iep-driver.patch} | 6 +- .../00260-linux-90100-add-clock.patch} | 0 .../00270-linux-90101-add-rt5651-konf.patch} | 0 .../00280-linux-90102-rt5651.patch} | 0 .../00290-linux-90103-nanopc-t4-5651.patch} | 0 .../00300-linux-90104-all-codec.patch} | 0 ...-90117-add-rk3399-roc-pc-plus-sound.patch} | 0 ...-linux-90200-rk3328-roc-pc-wifi-fix.patch} | 0 ...-net-ipx.h-and-uapi-linux-ipx.h-hea.patch} | 0 .../00340-add-fusb30x-driver.patch} | 0 .../00350-add-rk3328-usb3-phy-driver.patch} | 0 ...oc-rk3399-pc-fix-fusb302-compatible.patch} | 0 ...general-add-dwc3-xhci-usb-trb-quirk.patch} | 0 .../00380-general-add-miniDP-dt-doc.patch} | 0 ...0-general-add-miniDP-virtual-extcon.patch} | 0 ...ral-add-overlay-compilation-support.patch} | 0 .../00410-general-add-overlay-configfs.patch} | 0 ...etooth-02-add-support-for-RTL8723CS.patch} | 0 ...oth-03-hci_h5-add-binding-RTL8723CS.patch} | 0 ...-general-bluetooth-04-add-rtl8703bs.patch} | 0 ...450-general-bluetooth-add-new-quirk.patch} | 0 ...460-general-fix-es8316-kernel-panic.patch} | 0 ...DMA_block_memory_allocation_to_2048.patch} | 0 ...-possibility-of-disabling-rk808-rtc.patch} | 0 ...8-configurable-switch-voltage-steps.patch} | 0 ...neral-workaround-broadcom-bt-serdev.patch} | 0 ...0-rk3328-dtsi-usb3-reset-properties.patch} | 0 .../00520-rk3328-roc-pc-bt.patch} | 0 ...3399-enable-dwc3-xhci-usb-trb-quirk.patch} | 0 .../00540-rk3399-nanopc-t4-emmc.patch} | 0 ...chip-support-ep-gpio-undefined-case.patch} | 0 ...lement-rockchip-PCIe-bus-scan-delay.patch} | 0 .../00570-rk3399-sd-drive-level-8ma.patch} | 0 .../00580-rk3399-unlock-temperature.patch} | 0 ...add-driver-for-Motorcomm-YT85xx+PHYs.patch | 656 ++ .../00600-board-pbp-fix-wonky-wifi-bt.patch} | 0 .../00610-board-firefly-rk3399-dts.patch} | 0 .../00980-builddeb.patch | 2 +- .../00981-mkdebian.patch | 0 patch/kernel/media-edge | 1 - .../media-edge/00100-v91-i2s-mclk.patch | 84 + .../media-edge/00110-v91-irq-gic-v3-its.patch | 192 + .../kernel/media-edge/00120-rk356x-dtsi.patch | 38 + .../00130-board-firefly-rk3399-dts.patch} | 0 patch/kernel/media-edge/00140-v95-make.patch | 9 + .../00150-v95-rk3566-firefly-roc-pc.patch | 779 +++ .../00160-v95-rk3568-bpi-r2pro.patch | 190 + .../00170-v95-rk3568-firefly-roc-pc.patch | 1050 +++ ...00180-linux-0002-rockchip-from-list.patch} | 0 .../00190-linux-90100-add-clock.patch} | 0 .../00200-linux-90101-add-rt5651-konf.patch} | 0 .../00210-linux-90102-rt5651.patch} | 0 .../00220-linux-90103-nanopc-t4-5651.patch} | 0 .../00230-linux-90104-all-codec.patch} | 0 ...-90117-add-rk3399-roc-pc-plus-sound.patch} | 0 ...-linux-90200-rk3328-roc-pc-wifi-fix.patch} | 0 ...-net-ipx.h-and-uapi-linux-ipx.h-hea.patch} | 0 .../00270-add-rk3328-usb3-phy-driver.patch} | 0 .../00280-add-rockchip-iep-driver.patch} | 0 ...oc-rk3399-pc-fix-fusb302-compatible.patch} | 0 ...general-add-dwc3-xhci-usb-trb-quirk.patch} | 0 .../00310-general-add-miniDP-dt-doc.patch} | 0 ...0-general-add-miniDP-virtual-extcon.patch} | 0 ...ral-add-overlay-compilation-support.patch} | 0 .../00340-general-add-overlay-configfs.patch} | 0 .../00350-general-add-pll-hdmi-timings.patch} | 0 ...etooth-02-add-support-for-RTL8723CS.patch} | 0 ...oth-03-hci_h5-add-binding-RTL8723CS.patch} | 0 ...-general-bluetooth-04-add-rtl8703bs.patch} | 0 ...390-general-bluetooth-add-new-quirk.patch} | 0 ...400-general-fix-es8316-kernel-panic.patch} | 0 ...DMA_block_memory_allocation_to_2048.patch} | 0 ...-possibility-of-disabling-rk808-rtc.patch} | 0 ...8-configurable-switch-voltage-steps.patch} | 0 ...neral-workaround-broadcom-bt-serdev.patch} | 0 ...0-rk3328-dtsi-usb3-reset-properties.patch} | 0 .../00460-rk3328-roc-pc-bt.patch} | 0 ...3399-enable-dwc3-xhci-usb-trb-quirk.patch} | 0 .../00480-rk3399-nanopc-t4-emmc.patch} | 0 ...chip-support-ep-gpio-undefined-case.patch} | 0 ...lement-rockchip-PCIe-bus-scan-delay.patch} | 0 .../00510-rk3399-sd-drive-level-8ma.patch} | 0 .../00520-rk3399-unlock-temperature.patch} | 0 .../00530-board-pbp-fix-wonky-wifi-bt.patch} | 0 .../09980-builddeb.patch} | 2 +- .../09981-mkdebian.patch} | 0 patch/kernel/media-legacy | 1 - .../00980-builddeb.patch | 2 +- .../00981-mkdebian.patch | 0 patch/kernel/station-p2-current | 1 - 120 files changed, 10189 insertions(+), 11640 deletions(-) delete mode 100644 patch/kernel/archive/media-5.19/00410-general-disable-mtu-validation.patch delete mode 100644 patch/kernel/archive/media-5.19/00560-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch delete mode 100644 patch/kernel/archive/media-5.19/00570-pwm-fan-fix.patch delete mode 100644 patch/kernel/archive/media-5.19/00580-add-board-helios64.patch delete mode 100644 patch/kernel/archive/media-5.19/00590-board-helios64-dts-fix-stability-issues.patch delete mode 100644 patch/kernel/archive/media-5.19/00600-board-helios64-remove-overclock.patch delete mode 100644 patch/kernel/archive/media-5.19/00610-board-helios64-remove-pcie-ep-gpios.patch delete mode 100644 patch/kernel/archive/media-5.19/00620-add-driver-for-Motorcomm-YT85xx+PHYs.patch delete mode 100644 patch/kernel/archive/media-6.0/00120-v91-rk356x-vpu.patch delete mode 100644 patch/kernel/archive/media-6.0/00280-add-fusb30x-driver.patch delete mode 100644 patch/kernel/archive/media-6.0/00550-add-driver-for-Motorcomm-YT85xx+PHYs.patch delete mode 120000 patch/kernel/media-current rename patch/kernel/{archive/media-6.0 => media-current}/00100-v91-i2s-mclk.patch (100%) rename patch/kernel/{archive/media-6.0 => media-current}/00110-v91-irq-gic-v3-its.patch (100%) rename patch/kernel/{archive/media-6.0/00130-rk356x-dtsi.patch => media-current/00120-rk356x-dtsi.patch} (100%) rename patch/kernel/{archive/media-6.0/00150-v95-make.patch => media-current/00130-v95-make.patch} (100%) rename patch/kernel/{archive/media-6.0/00160-v95-rk3566-firefly-roc-pc.patch => media-current/00140-v95-rk3566-firefly-roc-pc.patch} (100%) rename patch/kernel/{archive/media-6.0/00170-v95-rk3568-bpi-r2pro.patch => media-current/00150-v95-rk3568-bpi-r2pro.patch} (100%) rename patch/kernel/{archive/media-6.0/00180-v95-rk3568-firefly-roc-pc.patch => media-current/00160-v95-rk3568-firefly-roc-pc.patch} (100%) create mode 100644 patch/kernel/media-current/00170-linux-0001-rockchip-from-6.1.patch rename patch/kernel/{archive/media-5.19/00110-linux-0002-rockchip-from-list.patch => media-current/00180-linux-0002-rockchip-from-list.patch} (99%) rename patch/kernel/{archive/media-5.19/00120-linux-0011-v4l2-from-list.patch => media-current/00190-linux-0011-v4l2-from-list.patch} (94%) rename patch/kernel/{archive/media-5.19/00130-linux-0020-drm-from-list.patch => media-current/00200-linux-0020-drm-from-list.patch} (93%) rename patch/kernel/{archive/media-5.19/00140-linux-1000-drm-rockchip.patch => media-current/00210-linux-1000-drm-rockchip.patch} (84%) rename patch/kernel/{archive/media-5.19/00150-linux-1001-v4l2-rockchip.patch => media-current/00220-linux-1001-v4l2-rockchip.patch} (80%) rename patch/kernel/{archive/media-5.19/00160-linux-1002-for-libreelec.patch => media-current/00230-linux-1002-for-libreelec.patch} (86%) rename patch/kernel/{archive/media-5.19/00170-linux-2000-v4l2-wip-rkvdec-hevc.patch => media-current/00240-linux-2000-v4l2-wip-rkvdec-hevc.patch} (92%) rename patch/kernel/{archive/media-5.19/00180-linux-2001-v4l2-wip-iep-driver.patch => media-current/00250-linux-2001-v4l2-wip-iep-driver.patch} (99%) rename patch/kernel/{archive/media-5.19/00190-linux-90100-add-clock.patch => media-current/00260-linux-90100-add-clock.patch} (100%) rename patch/kernel/{archive/media-5.19/00200-linux-90101-add-rt5651-konf.patch => media-current/00270-linux-90101-add-rt5651-konf.patch} (100%) rename patch/kernel/{archive/media-5.19/00210-linux-90102-rt5651.patch => media-current/00280-linux-90102-rt5651.patch} (100%) rename patch/kernel/{archive/media-5.19/00220-linux-90103-nanopc-t4-5651.patch => media-current/00290-linux-90103-nanopc-t4-5651.patch} (100%) rename patch/kernel/{archive/media-5.19/00240-linux-90104-all-codec.patch => media-current/00300-linux-90104-all-codec.patch} (100%) rename patch/kernel/{archive/media-5.19/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch => media-current/00310-linux-90117-add-rk3399-roc-pc-plus-sound.patch} (100%) rename patch/kernel/{archive/media-5.19/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch => media-current/00320-linux-90200-rk3328-roc-pc-wifi-fix.patch} (100%) rename patch/kernel/{archive/media-5.19/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch => media-current/00330-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch} (100%) rename patch/kernel/{archive/media-5.19/00280-add-fusb30x-driver.patch => media-current/00340-add-fusb30x-driver.patch} (100%) rename patch/kernel/{archive/media-5.19/00290-add-rk3328-usb3-phy-driver.patch => media-current/00350-add-rk3328-usb3-phy-driver.patch} (100%) rename patch/kernel/{archive/media-5.19/00300-board-roc-rk3399-pc-fix-fusb302-compatible.patch => media-current/00360-board-roc-rk3399-pc-fix-fusb302-compatible.patch} (100%) rename patch/kernel/{archive/media-5.19/00310-general-add-dwc3-xhci-usb-trb-quirk.patch => media-current/00370-general-add-dwc3-xhci-usb-trb-quirk.patch} (100%) rename patch/kernel/{archive/media-5.19/00320-general-add-miniDP-dt-doc.patch => media-current/00380-general-add-miniDP-dt-doc.patch} (100%) rename patch/kernel/{archive/media-5.19/00340-general-add-miniDP-virtual-extcon.patch => media-current/00390-general-add-miniDP-virtual-extcon.patch} (100%) rename patch/kernel/{archive/media-5.19/00350-general-add-overlay-compilation-support.patch => media-current/00400-general-add-overlay-compilation-support.patch} (100%) rename patch/kernel/{archive/media-5.19/00360-general-add-overlay-configfs.patch => media-current/00410-general-add-overlay-configfs.patch} (100%) rename patch/kernel/{archive/media-5.19/00370-general-bluetooth-02-add-support-for-RTL8723CS.patch => media-current/00420-general-bluetooth-02-add-support-for-RTL8723CS.patch} (100%) rename patch/kernel/{archive/media-5.19/00380-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch => media-current/00430-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch} (100%) rename patch/kernel/{archive/media-5.19/00390-general-bluetooth-04-add-rtl8703bs.patch => media-current/00440-general-bluetooth-04-add-rtl8703bs.patch} (100%) rename patch/kernel/{archive/media-5.19/00400-general-bluetooth-add-new-quirk.patch => media-current/00450-general-bluetooth-add-new-quirk.patch} (100%) rename patch/kernel/{archive/media-5.19/00420-general-fix-es8316-kernel-panic.patch => media-current/00460-general-fix-es8316-kernel-panic.patch} (100%) rename patch/kernel/{archive/media-5.19/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch => media-current/00470-general-increasing_DMA_block_memory_allocation_to_2048.patch} (100%) rename patch/kernel/{archive/media-5.19/00450-general-possibility-of-disabling-rk808-rtc.patch => media-current/00480-general-possibility-of-disabling-rk808-rtc.patch} (100%) rename patch/kernel/{archive/media-5.19/00460-general-rk808-configurable-switch-voltage-steps.patch => media-current/00490-general-rk808-configurable-switch-voltage-steps.patch} (100%) rename patch/kernel/{archive/media-5.19/00470-general-workaround-broadcom-bt-serdev.patch => media-current/00500-general-workaround-broadcom-bt-serdev.patch} (100%) rename patch/kernel/{archive/media-5.19/00480-rk3328-dtsi-usb3-reset-properties.patch => media-current/00510-rk3328-dtsi-usb3-reset-properties.patch} (100%) rename patch/kernel/{archive/media-5.19/00490-rk3328-roc-pc-bt.patch => media-current/00520-rk3328-roc-pc-bt.patch} (100%) rename patch/kernel/{archive/media-5.19/00500-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch => media-current/00530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch} (100%) rename patch/kernel/{archive/media-5.19/00510-rk3399-nanopc-t4-emmc.patch => media-current/00540-rk3399-nanopc-t4-emmc.patch} (100%) rename patch/kernel/{archive/media-5.19/00520-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch => media-current/00550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch} (100%) rename patch/kernel/{archive/media-5.19/00530-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch => media-current/00560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch} (100%) rename patch/kernel/{archive/media-5.19/00540-rk3399-sd-drive-level-8ma.patch => media-current/00570-rk3399-sd-drive-level-8ma.patch} (100%) rename patch/kernel/{archive/media-5.19/00550-rk3399-unlock-temperature.patch => media-current/00580-rk3399-unlock-temperature.patch} (100%) create mode 100644 patch/kernel/media-current/00590-add-driver-for-Motorcomm-YT85xx+PHYs.patch rename patch/kernel/{archive/media-5.19/00630-board-pbp-fix-wonky-wifi-bt.patch => media-current/00600-board-pbp-fix-wonky-wifi-bt.patch} (100%) rename patch/kernel/{archive/media-5.19/00100-board-firefly-rk3399-dts.patch => media-current/00610-board-firefly-rk3399-dts.patch} (100%) rename patch/kernel/{archive/media-5.10 => media-current}/00980-builddeb.patch (97%) rename patch/kernel/{archive/media-5.10 => media-current}/00981-mkdebian.patch (100%) delete mode 120000 patch/kernel/media-edge create mode 100644 patch/kernel/media-edge/00100-v91-i2s-mclk.patch create mode 100644 patch/kernel/media-edge/00110-v91-irq-gic-v3-its.patch create mode 100644 patch/kernel/media-edge/00120-rk356x-dtsi.patch rename patch/kernel/{archive/media-6.0/00140-board-firefly-rk3399-dts.patch => media-edge/00130-board-firefly-rk3399-dts.patch} (100%) create mode 100644 patch/kernel/media-edge/00140-v95-make.patch create mode 100644 patch/kernel/media-edge/00150-v95-rk3566-firefly-roc-pc.patch create mode 100644 patch/kernel/media-edge/00160-v95-rk3568-bpi-r2pro.patch create mode 100644 patch/kernel/media-edge/00170-v95-rk3568-firefly-roc-pc.patch rename patch/kernel/{archive/media-6.0/00190-linux-0002-rockchip-from-list.patch => media-edge/00180-linux-0002-rockchip-from-list.patch} (100%) rename patch/kernel/{archive/media-6.0/00200-linux-90100-add-clock.patch => media-edge/00190-linux-90100-add-clock.patch} (100%) rename patch/kernel/{archive/media-6.0/00210-linux-90101-add-rt5651-konf.patch => media-edge/00200-linux-90101-add-rt5651-konf.patch} (100%) rename patch/kernel/{archive/media-6.0/00220-linux-90102-rt5651.patch => media-edge/00210-linux-90102-rt5651.patch} (100%) rename patch/kernel/{archive/media-6.0/00230-linux-90103-nanopc-t4-5651.patch => media-edge/00220-linux-90103-nanopc-t4-5651.patch} (100%) rename patch/kernel/{archive/media-6.0/00240-linux-90104-all-codec.patch => media-edge/00230-linux-90104-all-codec.patch} (100%) rename patch/kernel/{archive/media-6.0/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch => media-edge/00240-linux-90117-add-rk3399-roc-pc-plus-sound.patch} (100%) rename patch/kernel/{archive/media-6.0/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch => media-edge/00250-linux-90200-rk3328-roc-pc-wifi-fix.patch} (100%) rename patch/kernel/{archive/media-6.0/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch => media-edge/00260-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch} (100%) rename patch/kernel/{archive/media-6.0/00290-rk3328-usb3-phy-driver.patch => media-edge/00270-add-rk3328-usb3-phy-driver.patch} (100%) rename patch/kernel/{archive/media-6.0/00300-add-rockchip-iep-driver.patch => media-edge/00280-add-rockchip-iep-driver.patch} (100%) rename patch/kernel/{archive/media-6.0/00310-board-roc-rk3399-pc-fix-fusb302-compatible.patch => media-edge/00290-board-roc-rk3399-pc-fix-fusb302-compatible.patch} (100%) rename patch/kernel/{archive/media-6.0/00320-general-add-dwc3-xhci-usb-trb-quirk.patch => media-edge/00300-general-add-dwc3-xhci-usb-trb-quirk.patch} (100%) rename patch/kernel/{archive/media-6.0/00330-general-add-miniDP-dt-doc.patch => media-edge/00310-general-add-miniDP-dt-doc.patch} (100%) rename patch/kernel/{archive/media-6.0/00340-general-add-miniDP-virtual-extcon.patch => media-edge/00320-general-add-miniDP-virtual-extcon.patch} (100%) rename patch/kernel/{archive/media-6.0/00350-general-add-overlay-compilation-support.patch => media-edge/00330-general-add-overlay-compilation-support.patch} (100%) rename patch/kernel/{archive/media-6.0/00360-general-add-overlay-configfs.patch => media-edge/00340-general-add-overlay-configfs.patch} (100%) rename patch/kernel/{archive/media-6.0/00370-general-add-pll-hdmi-timings.patch => media-edge/00350-general-add-pll-hdmi-timings.patch} (100%) rename patch/kernel/{archive/media-6.0/00380-general-bluetooth-02-add-support-for-RTL8723CS.patch => media-edge/00360-general-bluetooth-02-add-support-for-RTL8723CS.patch} (100%) rename patch/kernel/{archive/media-6.0/00390-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch => media-edge/00370-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch} (100%) rename patch/kernel/{archive/media-6.0/00400-general-bluetooth-04-add-rtl8703bs.patch => media-edge/00380-general-bluetooth-04-add-rtl8703bs.patch} (100%) rename patch/kernel/{archive/media-6.0/00410-general-bluetooth-add-new-quirk.patch => media-edge/00390-general-bluetooth-add-new-quirk.patch} (100%) rename patch/kernel/{archive/media-6.0/00420-general-fix-es8316-kernel-panic.patch => media-edge/00400-general-fix-es8316-kernel-panic.patch} (100%) rename patch/kernel/{archive/media-6.0/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch => media-edge/00410-general-increasing_DMA_block_memory_allocation_to_2048.patch} (100%) rename patch/kernel/{archive/media-6.0/00440-general-possibility-of-disabling-rk808-rtc.patch => media-edge/00420-general-possibility-of-disabling-rk808-rtc.patch} (100%) rename patch/kernel/{archive/media-6.0/00450-general-rk808-configurable-switch-voltage-steps.patch => media-edge/00430-general-rk808-configurable-switch-voltage-steps.patch} (100%) rename patch/kernel/{archive/media-6.0/00460-general-workaround-broadcom-bt-serdev.patch => media-edge/00440-general-workaround-broadcom-bt-serdev.patch} (100%) rename patch/kernel/{archive/media-6.0/00470-rk3328-dtsi-usb3-reset-properties.patch => media-edge/00450-rk3328-dtsi-usb3-reset-properties.patch} (100%) rename patch/kernel/{archive/media-6.0/00480-rk3328-roc-pc-bt.patch => media-edge/00460-rk3328-roc-pc-bt.patch} (100%) rename patch/kernel/{archive/media-6.0/00490-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch => media-edge/00470-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch} (100%) rename patch/kernel/{archive/media-6.0/00500-rk3399-nanopc-t4-emmc.patch => media-edge/00480-rk3399-nanopc-t4-emmc.patch} (100%) rename patch/kernel/{archive/media-6.0/00510-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch => media-edge/00490-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch} (100%) rename patch/kernel/{archive/media-6.0/00520-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch => media-edge/00500-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch} (100%) rename patch/kernel/{archive/media-6.0/00530-rk3399-sd-drive-level-8ma.patch => media-edge/00510-rk3399-sd-drive-level-8ma.patch} (100%) rename patch/kernel/{archive/media-6.0/00540-rk3399-unlock-temperature.patch => media-edge/00520-rk3399-unlock-temperature.patch} (100%) rename patch/kernel/{archive/media-6.0/00560-board-pbp-fix-wonky-wifi-bt.patch => media-edge/00530-board-pbp-fix-wonky-wifi-bt.patch} (100%) rename patch/kernel/{archive/media-5.19/00980-builddeb.patch => media-edge/09980-builddeb.patch} (97%) rename patch/kernel/{archive/media-5.19/00981-mkdebian.patch => media-edge/09981-mkdebian.patch} (100%) delete mode 120000 patch/kernel/media-legacy rename patch/kernel/{archive/media-6.0 => media-legacy}/00980-builddeb.patch (97%) rename patch/kernel/{archive/media-6.0 => media-legacy}/00981-mkdebian.patch (100%) delete mode 120000 patch/kernel/station-p2-current diff --git a/config/kernel/linux-media-current.config b/config/kernel/linux-media-current.config index 0bb5e0719..0c5c07b88 100644 --- a/config/kernel/linux-media-current.config +++ b/config/kernel/linux-media-current.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.17 Kernel Configuration +# Linux/arm64 6.0.9 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=122 @@ -74,6 +73,8 @@ CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_TIME_KUNIT_TEST=m +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -172,6 +173,7 @@ CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -306,6 +308,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -320,6 +323,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -370,7 +374,7 @@ CONFIG_ARM64_ERRATUM_1463225=y CONFIG_ARM64_ERRATUM_1542419=y CONFIG_ARM64_ERRATUM_1508412=y CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2077057=y +# CONFIG_ARM64_ERRATUM_2077057 is not set CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y CONFIG_ARM64_ERRATUM_2054223=y CONFIG_ARM64_ERRATUM_2067961=y @@ -483,7 +487,6 @@ CONFIG_ARM64_TLB_RANGE=y CONFIG_AS_HAS_ARMV8_5=y CONFIG_ARM64_BTI=y CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y # end of ARMv8.5 architectural features # @@ -526,6 +529,7 @@ CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -559,7 +563,6 @@ CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers @@ -594,10 +597,9 @@ CONFIG_ACPI_CPPC_CPUFREQ=y CONFIG_ACPI_CPPC_CPUFREQ_FIE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=m -CONFIG_ARM_TEGRA20_CPUFREQ=m +# CONFIG_ARM_TEGRA20_CPUFREQ is not set CONFIG_ARM_TEGRA124_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=m -CONFIG_ARM_TEGRA194_CPUFREQ=m # end of CPU Frequency scaling # end of CPU Power Management @@ -612,6 +614,7 @@ CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_VIDEO=y CONFIG_ACPI_FAN=y # CONFIG_ACPI_TAD is not set CONFIG_ACPI_DOCK=y @@ -651,6 +654,7 @@ CONFIG_ACPI_PPTT=y CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y CONFIG_ACPI_VIOT=y +CONFIG_ACPI_PRMT=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_IRQCHIP=y @@ -678,9 +682,10 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_ARM64_CE=m CONFIG_CRYPTO_SM4_ARM64_CE=m -CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m -CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y @@ -688,8 +693,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_POLY1305_NEON=m -CONFIG_CRYPTO_NHPOLY1305_NEON=m +CONFIG_CRYPTO_POLY1305_NEON=y +CONFIG_CRYPTO_NHPOLY1305_NEON=y CONFIG_CRYPTO_AES_ARM64_BS=y # @@ -704,6 +709,7 @@ CONFIG_JUMP_LABEL=y CONFIG_UPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_KRETPROBES=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -750,7 +756,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -791,6 +797,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -827,7 +834,7 @@ CONFIG_MODULE_SIG_HASH="sha1" # CONFIG_MODULE_COMPRESS_GZIP is not set CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MODULE_COMPRESS_ZSTD is not set -CONFIG_MODULE_DECOMPRESS=y +# CONFIG_MODULE_DECOMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -995,9 +1002,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y # CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y @@ -1006,7 +1015,7 @@ CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y @@ -1015,18 +1024,18 @@ CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y +CONFIG_GET_FREE_REGION=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y # CONFIG_GUP_TEST is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y -CONFIG_ANON_VMA_NAME=y +# CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set # @@ -1038,6 +1047,7 @@ CONFIG_DAMON_PADDR=y # CONFIG_DAMON_SYSFS is not set # CONFIG_DAMON_DBGFS is not set CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options @@ -1262,6 +1272,7 @@ CONFIG_NFT_FIB_NETDEV=m CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XTABLES_COMPAT=y @@ -1604,6 +1615,7 @@ CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_RTL8_4=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m @@ -1772,10 +1784,7 @@ CONFIG_NET_NSH=m CONFIG_HSR=m CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_QRTR_MHI=m +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y @@ -1824,71 +1833,6 @@ CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m # CONFIG_CAN_ISOTP is not set - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_DEV=m -CONFIG_CAN_CALC_BITTIMING=y -# CONFIG_CAN_FLEXCAN is not set -CONFIG_CAN_GRCAN=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_XILINXCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_ISA=m -CONFIG_CAN_CC770_PLATFORM=m -CONFIG_CAN_CTUCANFD=m -CONFIG_CAN_CTUCANFD_PCI=m -CONFIG_CAN_CTUCANFD_PLATFORM=m -# CONFIG_CAN_IFI_CANFD is not set -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCIEC=y -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m - -# -# CAN SPI interfaces -# -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -# CONFIG_CAN_MCP251XFD_SANITY is not set -# end of CAN SPI interfaces - -# -# CAN USB interfaces -# -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_ETAS_ES58X=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -# end of CAN USB interfaces - -# CONFIG_CAN_DEBUG_DEVICES is not set -# end of CAN Device Drivers - CONFIG_BT=m CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m @@ -2065,9 +2009,9 @@ CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y # CONFIG_PAGE_POOL_STATS is not set -CONFIG_FAILOVER=m +CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_NETDEV_ADDR_LIST_TEST=m +# CONFIG_NETDEV_ADDR_LIST_TEST is not set # # Device Drivers @@ -2100,6 +2044,7 @@ CONFIG_PCI_QUIRKS=y CONFIG_PCI_STUB=y # CONFIG_PCI_PF_STUB is not set CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y CONFIG_PCI_ECAM=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y @@ -2151,9 +2096,6 @@ CONFIG_PCI_HISI=y CONFIG_PCIE_ROCKCHIP_DW_HOST=y # CONFIG_PCIE_KIRIN is not set # CONFIG_PCI_MESON is not set -CONFIG_PCIE_TEGRA194=m -CONFIG_PCIE_TEGRA194_HOST=m -CONFIG_PCIE_TEGRA194_EP=m # CONFIG_PCIE_AL is not set # end of DesignWare PCI Core Support @@ -2194,6 +2136,7 @@ CONFIG_CXL_ACPI=m CONFIG_CXL_MEM=m CONFIG_CXL_PORT=m CONFIG_CXL_SUSPEND=y +CONFIG_CXL_REGION=y # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -2292,6 +2235,7 @@ CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y @@ -2353,7 +2297,7 @@ CONFIG_GNSS_SERIAL=m CONFIG_GNSS_MTK_SERIAL=m CONFIG_GNSS_SIRF_SERIAL=m CONFIG_GNSS_UBX_SERIAL=m -CONFIG_GNSS_USB=m +# CONFIG_GNSS_USB is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -2384,7 +2328,7 @@ CONFIG_RFD_FTL=m CONFIG_SSFDC=m CONFIG_SM_FTL=m # CONFIG_MTD_OOPS is not set -CONFIG_MTD_PSTORE=m +# CONFIG_MTD_PSTORE is not set CONFIG_MTD_SWAP=m # CONFIG_MTD_PARTITIONED_MASTER is not set @@ -2539,7 +2483,7 @@ CONFIG_PNP_DEBUG_MESSAGES=y CONFIG_PNPACPI=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_CDROM=m +CONFIG_CDROM=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set CONFIG_ZRAM=m CONFIG_ZRAM_DEF_COMP_LZORLE=y @@ -2556,8 +2500,7 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=m # CONFIG_DRBD_FAULT_INJECTION is not set CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_SX8=m -CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set @@ -2566,10 +2509,12 @@ CONFIG_XEN_BLKDEV_FRONTEND=m CONFIG_XEN_BLKDEV_BACKEND=m CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_UBLK=m # # NVME Support # +CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y CONFIG_NVME_MULTIPATH=y @@ -2578,12 +2523,14 @@ CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=m CONFIG_NVME_FC=m CONFIG_NVME_TCP=m +CONFIG_NVME_AUTH=y CONFIG_NVME_TARGET=m CONFIG_NVME_TARGET_PASSTHRU=y CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # @@ -2616,6 +2563,7 @@ CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=m # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +CONFIG_VCPU_STALL_DETECTOR=m # CONFIG_C2PORT is not set # @@ -2673,8 +2621,8 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=m CONFIG_SCSI_ENCLOSURE=m @@ -2689,7 +2637,7 @@ CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m CONFIG_SCSI_ISCSI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SCSI_SAS_LIBSAS=m CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=m @@ -2712,9 +2660,7 @@ CONFIG_SCSI_HPSA=m # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set -CONFIG_SCSI_HISI_SAS=y -CONFIG_SCSI_HISI_SAS_PCI=m -# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set +# CONFIG_SCSI_HISI_SAS is not set CONFIG_SCSI_MVSAS=m # CONFIG_SCSI_MVSAS_DEBUG is not set CONFIG_SCSI_MVSAS_TASKLET=y @@ -2730,10 +2676,12 @@ CONFIG_MEGARAID_SAS=m CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 -CONFIG_SCSI_MPT2SAS=m +# CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_HPTIOP is not set +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_FLASHPOINT=y # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set # CONFIG_XEN_SCSI_FRONTEND is not set @@ -2796,7 +2744,7 @@ CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_CEVA=y -CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_TEGRA=m CONFIG_AHCI_XGENE=y CONFIG_AHCI_QORIQ=y CONFIG_SATA_INIC162X=m @@ -2893,7 +2841,7 @@ CONFIG_MD_RAID456=m CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_MD_CLUSTER=m -CONFIG_BCACHE=y +CONFIG_BCACHE=m # CONFIG_BCACHE_DEBUG is not set # CONFIG_BCACHE_CLOSURES_DEBUG is not set # CONFIG_BCACHE_ASYNC_REGISTRATION is not set @@ -2986,7 +2934,7 @@ CONFIG_BAREUDP=m CONFIG_GTP=m CONFIG_AMT=m CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y @@ -3042,22 +2990,19 @@ CONFIG_NET_DSA_LANTIQ_GSWIP=m CONFIG_NET_DSA_MT7530=m CONFIG_NET_DSA_MV88E6060=m CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477=m CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m -CONFIG_NET_DSA_MICROCHIP_KSZ8795=m -CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_DSA_MV88E6XXX_PTP is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_QCA8K=m CONFIG_NET_DSA_SJA1105=m # CONFIG_NET_DSA_SJA1105_PTP is not set CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m -CONFIG_NET_DSA_QCA8K=m CONFIG_NET_DSA_REALTEK=m CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m @@ -3098,8 +3043,7 @@ CONFIG_AQTION=m CONFIG_NET_VENDOR_ARC=y # CONFIG_EMAC_ROCKCHIP is not set CONFIG_NET_VENDOR_ASIX=y -CONFIG_SPI_AX88796C=m -# CONFIG_SPI_AX88796C_COMPRESSION is not set +# CONFIG_SPI_AX88796C is not set CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=m CONFIG_ATL1=m @@ -3157,8 +3101,7 @@ CONFIG_SUNDANCE=m CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set CONFIG_NET_VENDOR_ENGLEDER=y -CONFIG_TSNEP=m -# CONFIG_TSNEP_SELFTESTS is not set +# CONFIG_TSNEP is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_FUNGIBLE=y @@ -3202,6 +3145,8 @@ CONFIG_I40EVF=m # CONFIG_ICE is not set CONFIG_FM10K=m # CONFIG_IGC is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_TXGBE is not set CONFIG_JME=m CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=m @@ -3216,7 +3161,7 @@ CONFIG_OCTEONTX2_MBOX=m # CONFIG_OCTEONTX2_AF is not set CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m -CONFIG_OCTEON_EP=m +# CONFIG_OCTEON_EP is not set # CONFIG_PRESTERA is not set CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=m @@ -3253,7 +3198,7 @@ CONFIG_ENC28J60=m CONFIG_ENC28J60_WRITEVERIFY=y # CONFIG_ENCX24J600 is not set # CONFIG_LAN743X is not set -CONFIG_LAN966X_SWITCH=m +# CONFIG_LAN966X_SWITCH is not set CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_MSCC_OCELOT_SWITCH_LIB=m CONFIG_MSCC_OCELOT_SWITCH=m @@ -3268,7 +3213,6 @@ CONFIG_NATSEMI=m CONFIG_NS83820=m CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set CONFIG_NET_VENDOR_8390=y @@ -3319,11 +3263,7 @@ CONFIG_NET_VENDOR_SIS=y CONFIG_NET_VENDOR_SOLARFLARE=y # CONFIG_SFC is not set # CONFIG_SFC_FALCON is not set -CONFIG_SFC_SIENA=m -CONFIG_SFC_SIENA_MTD=y -CONFIG_SFC_SIENA_MCDI_MON=y -# CONFIG_SFC_SIENA_SRIOV is not set -CONFIG_SFC_SIENA_MCDI_LOGGING=y +# CONFIG_SFC_SIENA is not set CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC91X=y # CONFIG_EPIC100 is not set @@ -3331,12 +3271,12 @@ CONFIG_SMSC911X=y # CONFIG_SMSC9420 is not set CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y -CONFIG_STMMAC_ETH=m +CONFIG_STMMAC_ETH=y # CONFIG_STMMAC_SELFTESTS is not set -CONFIG_STMMAC_PLATFORM=m +CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set -CONFIG_DWMAC_GENERIC=m -CONFIG_DWMAC_ROCKCHIP=m +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_ROCKCHIP=y # CONFIG_DWMAC_INTEL_PLAT is not set CONFIG_DWMAC_LOONGSON=m # CONFIG_STMMAC_PCI is not set @@ -3353,7 +3293,7 @@ CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set CONFIG_NET_VENDOR_VERTEXCOM=y -CONFIG_MSE102X=m +# CONFIG_MSE102X is not set CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_RHINE is not set # CONFIG_VIA_VELOCITY is not set @@ -3388,6 +3328,7 @@ CONFIG_BCM7XXX_PHY=m CONFIG_BCM84881_PHY=m CONFIG_BCM87XX_PHY=m CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m CONFIG_CICADA_PHY=m # CONFIG_CORTINA_PHY is not set CONFIG_DAVICOM_PHY=m @@ -3410,7 +3351,7 @@ CONFIG_NXP_C45_TJA11XX_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=m CONFIG_QSEMI_PHY=m -CONFIG_REALTEK_PHY=m +CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set CONFIG_ROCKCHIP_PHY=y CONFIG_SMSC_PHY=m @@ -3425,6 +3366,67 @@ CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +# CONFIG_CAN_FLEXCAN is not set +CONFIG_CAN_GRCAN=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_XILINXCAN=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_CC770=m +CONFIG_CAN_CC770_ISA=m +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +# CONFIG_CAN_IFI_CANFD is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y @@ -3455,7 +3457,7 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y # # PCS device drivers # -CONFIG_PCS_XPCS=m +CONFIG_PCS_XPCS=y # end of PCS device drivers CONFIG_PPP=m @@ -3580,7 +3582,7 @@ CONFIG_WCN36XX=m # CONFIG_WCN36XX_DEBUGFS is not set CONFIG_ATH11K=m CONFIG_ATH11K_AHB=m -CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_PCI is not set # CONFIG_ATH11K_DEBUG is not set # CONFIG_ATH11K_TRACING is not set CONFIG_WLAN_VENDOR_ATMEL=y @@ -3731,7 +3733,7 @@ CONFIG_WILC1000_SDIO=m CONFIG_WILC1000_SPI=m # CONFIG_WILC1000_HW_OOB_INTR is not set CONFIG_WLAN_VENDOR_PURELIFI=y -CONFIG_PLFXLC=m +# CONFIG_PLFXLC is not set CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m @@ -3880,8 +3882,8 @@ CONFIG_WWAN_DEBUGFS=y CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m -# CONFIG_RPMSG_WWAN_CTRL is not set -# CONFIG_MTK_T7XX is not set +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_MTK_T7XX=m # end of Wireless WAN CONFIG_XEN_NETDEV_FRONTEND=m @@ -3889,7 +3891,7 @@ CONFIG_XEN_NETDEV_BACKEND=m CONFIG_VMXNET3=m CONFIG_FUJITSU_ES=m CONFIG_NETDEVSIM=m -CONFIG_NET_FAILOVER=m +CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set # @@ -3938,7 +3940,7 @@ CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set -CONFIG_KEYBOARD_TEGRA=m +# CONFIG_KEYBOARD_TEGRA is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set @@ -3950,7 +3952,7 @@ CONFIG_KEYBOARD_IQS62X=m CONFIG_KEYBOARD_CROS_EC=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_BCM is not set -CONFIG_KEYBOARD_CYPRESS_SF=m +# CONFIG_KEYBOARD_CYPRESS_SF is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -4030,7 +4032,7 @@ CONFIG_TOUCHSCREEN_BU21013=m CONFIG_TOUCHSCREEN_BU21029=m CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m -# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +CONFIG_TOUCHSCREEN_CY8CTMA140=m CONFIG_TOUCHSCREEN_CY8CTMG110=m CONFIG_TOUCHSCREEN_CYTTSP_CORE=m CONFIG_TOUCHSCREEN_CYTTSP_I2C=m @@ -4176,7 +4178,7 @@ CONFIG_RMI4_F55=y # Hardware I/O ports # CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_SERPORT=y CONFIG_SERIO_AMBAKMI=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y @@ -4227,7 +4229,6 @@ CONFIG_SERIAL_8250_NR_UARTS=8 CONFIG_SERIAL_8250_RUNTIME_UARTS=8 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set CONFIG_SERIAL_8250_RSA=y @@ -4235,7 +4236,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_8250_PERICOM=y CONFIG_SERIAL_8250_TEGRA=y CONFIG_SERIAL_OF_PLATFORM=y @@ -4247,9 +4248,7 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y -CONFIG_SERIAL_TEGRA_TCU_CONSOLE=y +CONFIG_SERIAL_TEGRA_TCU=m # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set @@ -4316,11 +4315,11 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_OPTEE=y +CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m -CONFIG_HW_RANDOM_CN10K=m +CONFIG_HW_RANDOM_CN10K=y # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y @@ -4328,6 +4327,7 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C is not set CONFIG_TCG_TIS_I2C_CR50=m # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y @@ -4338,9 +4338,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_TCG_CRB=y # CONFIG_TCG_VTPM_PROXY is not set # CONFIG_TCG_FTPM_TEE is not set -CONFIG_TCG_TIS_ST33ZP24=m -CONFIG_TCG_TIS_ST33ZP24_I2C=m -CONFIG_TCG_TIS_ST33ZP24_SPI=m +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set CONFIG_XILLYBUS_CLASS=m # CONFIG_XILLYBUS is not set CONFIG_XILLYUSB=m @@ -4356,7 +4355,7 @@ CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=m +CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support @@ -4486,6 +4485,7 @@ CONFIG_SPI_NXP_FLEXSPI=m CONFIG_SPI_GPIO=m CONFIG_SPI_FSL_LIB=m CONFIG_SPI_FSL_SPI=m +CONFIG_SPI_MICROCHIP_CORE=m CONFIG_SPI_OC_TINY=m CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set @@ -4495,9 +4495,7 @@ CONFIG_SPI_ROCKCHIP_SFC=m # CONFIG_SPI_SIFIVE is not set CONFIG_SPI_MXIC=m CONFIG_SPI_TEGRA210_QUAD=m -# CONFIG_SPI_TEGRA114 is not set -CONFIG_SPI_TEGRA20_SFLASH=y -CONFIG_SPI_TEGRA20_SLINK=m +# CONFIG_SPI_TEGRA20_SFLASH is not set # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set @@ -4577,7 +4575,6 @@ CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_TEGRA=y CONFIG_PINCTRL_TEGRA124=y CONFIG_PINCTRL_TEGRA210=y -CONFIG_PINCTRL_TEGRA194=y CONFIG_PINCTRL_TEGRA_XUSB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 @@ -4609,7 +4606,6 @@ CONFIG_GPIO_LOGICVC=m CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_PL061=y CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SAMA5D2_PIOBU=m # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y CONFIG_GPIO_TEGRA=y @@ -4679,7 +4675,7 @@ CONFIG_GPIO_XRA1403=m CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_MOCKUP=m CONFIG_GPIO_VIRTIO=m -CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers CONFIG_W1=m @@ -4772,7 +4768,7 @@ CONFIG_CHARGER_LT3651=m CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_DETECTOR_MAX14656=m CONFIG_CHARGER_MAX77650=m -CONFIG_CHARGER_MAX77976=m +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -4802,7 +4798,6 @@ CONFIG_HWMON_VID=m CONFIG_SENSORS_AD7314=m CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m CONFIG_SENSORS_ADM1029=m @@ -4871,7 +4866,6 @@ CONFIG_SENSORS_MAX31730=m CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6642=m CONFIG_SENSORS_MAX6650=m CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m @@ -4907,7 +4901,7 @@ CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m CONFIG_SENSORS_NZXT_KRAKEN2=m -CONFIG_SENSORS_NZXT_SMART2=m +# CONFIG_SENSORS_NZXT_SMART2 is not set CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m @@ -4917,7 +4911,7 @@ CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_ADM1275=m CONFIG_SENSORS_BEL_PFE=m CONFIG_SENSORS_BPA_RS600=m -CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set CONFIG_SENSORS_FSP_3Y=m CONFIG_SENSORS_IBM_CFFPS=m CONFIG_SENSORS_DPS920AB=m @@ -4930,6 +4924,7 @@ CONFIG_SENSORS_IRPS5401=m CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m # CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LT7182S=m CONFIG_SENSORS_LTC2978=m CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=m @@ -4943,7 +4938,7 @@ CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m CONFIG_SENSORS_MP2888=m # CONFIG_SENSORS_MP2975 is not set -CONFIG_SENSORS_MP5023=m +# CONFIG_SENSORS_MP5023 is not set CONFIG_SENSORS_PIM4328=m # CONFIG_SENSORS_PLI1209BC is not set CONFIG_SENSORS_PM6764TR=m @@ -4986,7 +4981,7 @@ CONFIG_SENSORS_ADS7871=m CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_INA209=m CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA238=m +# CONFIG_SENSORS_INA238 is not set CONFIG_SENSORS_INA3221=m CONFIG_SENSORS_TC74=m CONFIG_SENSORS_THMC50=m @@ -5300,7 +5295,7 @@ CONFIG_REGULATOR_MAX77650=m CONFIG_REGULATOR_MAX8893=m # CONFIG_REGULATOR_MAX8952 is not set CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MAX20086=m +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_MP5416=m @@ -5536,7 +5531,6 @@ CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=m -CONFIG_USB_STKWEBCAM=m CONFIG_VIDEO_USBTV=m CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -5883,6 +5877,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_APTINA_PLL=m CONFIG_VIDEO_CCS_PLL=m +# CONFIG_VIDEO_AR0521 is not set CONFIG_VIDEO_HI556=m CONFIG_VIDEO_HI846=m # CONFIG_VIDEO_HI847 is not set @@ -5924,7 +5919,7 @@ CONFIG_VIDEO_OV5647=m CONFIG_VIDEO_OV5648=m CONFIG_VIDEO_OV5670=m CONFIG_VIDEO_OV5675=m -CONFIG_VIDEO_OV5693=m +# CONFIG_VIDEO_OV5693 is not set CONFIG_VIDEO_OV5695=m CONFIG_VIDEO_OV6650=m CONFIG_VIDEO_OV7251=m @@ -6302,6 +6297,7 @@ CONFIG_DVB_DUMMY_FE=m # # Graphics support # +CONFIG_APERTURE_HELPERS=y CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y CONFIG_TEGRA_HOST1X=m CONFIG_TEGRA_HOST1X_FIREWALL=y @@ -6376,7 +6372,7 @@ CONFIG_DRM_QXL=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_DRM_TEGRA=m # CONFIG_DRM_TEGRA_DEBUG is not set -CONFIG_DRM_TEGRA_STAGING=y +# CONFIG_DRM_TEGRA_STAGING is not set CONFIG_DRM_PANEL=y # @@ -6385,13 +6381,14 @@ CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_ABT_Y030XX067A=m CONFIG_DRM_PANEL_ARM_VERSATILE=m # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set CONFIG_DRM_PANEL_BOE_HIMAX8279D=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m @@ -6401,7 +6398,7 @@ CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m CONFIG_DRM_PANEL_JDI_LT070ME05000=m -CONFIG_DRM_PANEL_JDI_R63452=m +# CONFIG_DRM_PANEL_JDI_R63452 is not set CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set @@ -6444,7 +6441,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7701=m # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set CONFIG_DRM_PANEL_SONY_ACX565AKM=m -CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m @@ -6488,6 +6485,7 @@ CONFIG_DRM_TOSHIBA_TC358764=m # CONFIG_DRM_TOSHIBA_TC358767 is not set CONFIG_DRM_TOSHIBA_TC358768=m # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set CONFIG_DRM_TI_SN65DSI83=m # CONFIG_DRM_TI_SN65DSI86 is not set @@ -6512,8 +6510,10 @@ CONFIG_DRM_ETNAVIV=m CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_LOGICVC=m CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_BOCHS=m # CONFIG_DRM_CIRRUS_QEMU is not set @@ -6521,7 +6521,7 @@ CONFIG_DRM_GM12U320=m CONFIG_DRM_PANEL_MIPI_DBI=m CONFIG_DRM_SIMPLEDRM=m CONFIG_TINYDRM_HX8357D=m -CONFIG_TINYDRM_ILI9163=m +# CONFIG_TINYDRM_ILI9163 is not set CONFIG_TINYDRM_ILI9225=m CONFIG_TINYDRM_ILI9341=m CONFIG_TINYDRM_ILI9486=m @@ -6695,7 +6695,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +CONFIG_SND_CTL_INPUT_VALIDATION=y CONFIG_SND_VMASTER=y CONFIG_SND_CTL_LED=m CONFIG_SND_SEQUENCER=m @@ -6804,6 +6806,7 @@ CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=1 CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_SCODEC_CS35L41=m +CONFIG_SND_HDA_CS_DSP_CONTROLS=m CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m CONFIG_SND_HDA_CODEC_REALTEK=m @@ -6852,12 +6855,14 @@ CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y CONFIG_SND_SOC_UTILS_KUNIT_TEST=m +CONFIG_SND_SOC_ACPI=m CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_ADI_AXI_I2S=m CONFIG_SND_SOC_ADI_AXI_SPDIF=m CONFIG_SND_SOC_AMD_ACP=m CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m # CONFIG_SND_AMD_ACP_CONFIG is not set CONFIG_SND_ATMEL_SOC=m CONFIG_SND_SOC_MIKROE_PROTO=m @@ -6882,6 +6887,7 @@ CONFIG_SND_SOC_FSL_ESAI=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_EASRC=m CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m CONFIG_SND_SOC_FSL_RPMSG=m CONFIG_SND_SOC_IMX_AUDMUX=m # end of SoC Audio for Freescale CPUs @@ -6926,6 +6932,7 @@ CONFIG_SND_SOC_TEGRA30_I2S=m CONFIG_SND_SOC_TEGRA210_AHUB=m CONFIG_SND_SOC_TEGRA210_DMIC=m CONFIG_SND_SOC_TEGRA210_I2S=m +CONFIG_SND_SOC_TEGRA210_OPE=m CONFIG_SND_SOC_TEGRA186_ASRC=m CONFIG_SND_SOC_TEGRA186_DSPK=m CONFIG_SND_SOC_TEGRA210_ADMAIF=m @@ -7071,6 +7078,7 @@ CONFIG_SND_SOC_ES8328_SPI=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_HDAC_HDMI=m CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDA=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_INNO_RK3036=m CONFIG_SND_SOC_ISABELLE=m @@ -7159,7 +7167,7 @@ CONFIG_SND_SOC_RT711_SDCA_SDW=m CONFIG_SND_SOC_RT715=m CONFIG_SND_SOC_RT715_SDW=m CONFIG_SND_SOC_RT715_SDCA_SDW=m -CONFIG_SND_SOC_RT9120=m +# CONFIG_SND_SOC_RT9120 is not set CONFIG_SND_SOC_SDW_MOCKUP=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SI476X=m @@ -7184,6 +7192,7 @@ CONFIG_SND_SOC_TAS2552=m CONFIG_SND_SOC_TAS2562=m CONFIG_SND_SOC_TAS2764=m CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m CONFIG_SND_SOC_TAS5086=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TAS5720=m @@ -7277,6 +7286,7 @@ CONFIG_SND_SOC_WM9705=m CONFIG_SND_SOC_WM9712=m CONFIG_SND_SOC_WM9713=m CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m CONFIG_SND_SOC_ZL38060=m CONFIG_SND_SOC_LM4857=m CONFIG_SND_SOC_MAX9759=m @@ -7379,7 +7389,7 @@ CONFIG_HID_KENSINGTON=m CONFIG_HID_LCPOWER=m CONFIG_HID_LED=m CONFIG_HID_LENOVO=m -CONFIG_HID_LETSKETCH=m +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=m CONFIG_HID_LOGITECH_DJ=m CONFIG_HID_LOGITECH_HIDPP=m @@ -7432,6 +7442,7 @@ CONFIG_HID_SMARTJOYPLUS=m CONFIG_SMARTJOYPLUS_FF=y CONFIG_HID_TIVO=m CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m CONFIG_HID_THINGM=m CONFIG_HID_THRUSTMASTER=m CONFIG_THRUSTMASTER_FF=y @@ -7462,6 +7473,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_I2C_HID_ACPI=m CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m CONFIG_I2C_HID_OF_GOODIX=m # end of I2C HID support @@ -7502,13 +7514,13 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_XHCI_TEGRA=y +CONFIG_USB_XHCI_TEGRA=m CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_EHCI_FSL=m -CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_EHCI_TEGRA=m CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OXU210HP_HCD=m CONFIG_USB_ISP116X_HCD=m @@ -7525,7 +7537,7 @@ CONFIG_USB_R8A66597_HCD=m CONFIG_USB_HCD_BCMA=m CONFIG_USB_HCD_SSB=m CONFIG_USB_HCD_TEST_MODE=y -CONFIG_USB_XEN_HCD=m +# CONFIG_USB_XEN_HCD is not set # # USB Device Class drivers @@ -7624,7 +7636,7 @@ CONFIG_USB_CHIPIDEA_PCI=y CONFIG_USB_CHIPIDEA_MSM=y CONFIG_USB_CHIPIDEA_IMX=y CONFIG_USB_CHIPIDEA_GENERIC=y -CONFIG_USB_CHIPIDEA_TEGRA=y +CONFIG_USB_CHIPIDEA_TEGRA=m CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1761_UDC=y @@ -7720,6 +7732,7 @@ CONFIG_USB_HSIC_USB3503=y CONFIG_USB_HSIC_USB4604=m CONFIG_USB_LINK_LAYER_TEST=m CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ONBOARD_HUB=m CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m @@ -7733,7 +7746,7 @@ CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_GPIO_VBUS=m CONFIG_USB_ISP1301=m -CONFIG_USB_TEGRA_PHY=y +CONFIG_USB_TEGRA_PHY=m CONFIG_USB_ULPI=y CONFIG_USB_ULPI_VIEWPORT=y # end of USB Physical Layer drivers @@ -7860,7 +7873,9 @@ CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m CONFIG_UCSI_CCG=m CONFIG_UCSI_ACPI=m +CONFIG_UCSI_STM32G0=m CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m @@ -7903,10 +7918,11 @@ CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_ASPEED=m +CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y CONFIG_MMC_SDHCI_OF_AT91=m CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_SDHCI_TEGRA=m CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MMC_SDHCI_MILBEAUT=m CONFIG_MMC_ALCOR=m @@ -8056,9 +8072,9 @@ CONFIG_EDAC_DMC520=m CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc1" +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc1" +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" # CONFIG_RTC_DEBUG is not set CONFIG_RTC_LIB_KUNIT_TEST=m CONFIG_RTC_NVMEM=y @@ -8086,8 +8102,9 @@ CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_HYM8563=y # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_NCT3018Y=m CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set CONFIG_RTC_DRV_ISL12026=m @@ -8174,7 +8191,7 @@ CONFIG_RTC_DRV_PL030=m CONFIG_RTC_DRV_PL031=m CONFIG_RTC_DRV_CADENCE=m # CONFIG_RTC_DRV_FTRTC010 is not set -CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_R7301 is not set # @@ -8204,8 +8221,8 @@ CONFIG_HISI_DMA=m CONFIG_MV_XOR_V2=y CONFIG_PL330_DMA=y CONFIG_PLX_DMA=m -CONFIG_TEGRA186_GPC_DMA=m -CONFIG_TEGRA20_APB_DMA=y +# CONFIG_TEGRA186_GPC_DMA is not set +# CONFIG_TEGRA20_APB_DMA is not set CONFIG_TEGRA210_ADMA=m # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set @@ -8411,20 +8428,21 @@ CONFIG_SERIO_NVEC_PS2=m CONFIG_NVEC_POWER=m CONFIG_NVEC_PAZ00=m CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_ROCKCHIP=y -CONFIG_VIDEO_MAX96712=m -CONFIG_VIDEO_ROCKCHIP_VDEC=m -CONFIG_VIDEO_ZORAN=m -# CONFIG_VIDEO_ZORAN_DC30 is not set -# CONFIG_VIDEO_ZORAN_ZR36060 is not set -CONFIG_VIDEO_TEGRA=m -CONFIG_VIDEO_TEGRA_TPG=y CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_STKWEBCAM=m +CONFIG_VIDEO_TEGRA=m +# CONFIG_VIDEO_TEGRA_TPG is not set +CONFIG_VIDEO_ZORAN=m +# CONFIG_VIDEO_ZORAN_DC30 is not set +# CONFIG_VIDEO_ZORAN_ZR36060 is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set CONFIG_COMMON_CLK_XLNX_CLKWZRD=m @@ -8470,10 +8488,7 @@ CONFIG_HMS_ANYBUSS_BUS=m # CONFIG_ARCX_ANYBUS_CONTROLLER is not set # CONFIG_HMS_PROFINET is not set # CONFIG_QLGE is not set - -# -# VME Device Drivers -# +# CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CHROMEOS_ACPI=m @@ -8493,6 +8508,7 @@ CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_EC_TYPEC=m CONFIG_CROS_USBPD_NOTIFY=y # CONFIG_CHROMEOS_PRIVACY_SCREEN is not set +# CONFIG_CROS_KUNIT is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y # CONFIG_SURFACE_3_POWER_OPREGION is not set @@ -8557,6 +8573,7 @@ CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_ROCKCHIP_TIMER=y CONFIG_TEGRA_TIMER=y +# CONFIG_TEGRA186_TIMER is not set CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -8656,6 +8673,12 @@ CONFIG_SOC_BRCMSTB=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# CONFIG_A64FX_DIAG is not set +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -8680,8 +8703,8 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y +# CONFIG_ARCH_TEGRA_194_SOC is not set +# CONFIG_ARCH_TEGRA_234_SOC is not set CONFIG_SOC_TEGRA_FUSE=y CONFIG_SOC_TEGRA_FLOWCTRL=y CONFIG_SOC_TEGRA_PMC=y @@ -8708,7 +8731,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=m # # DEVFREQ Drivers # -CONFIG_ARM_TEGRA_DEVFREQ=y +CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_ARM_RK3399_DMC_DEVFREQ=y CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y @@ -8731,7 +8754,8 @@ CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_TEGRA_MC=y -# CONFIG_TEGRA210_EMC is not set +CONFIG_TEGRA210_EMC_TABLE=y +CONFIG_TEGRA210_EMC=m CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=m @@ -8886,7 +8910,7 @@ CONFIG_XILINX_XADC=m # # Analog to digital and digital to analog converters # -CONFIG_AD74413R=m +# CONFIG_AD74413R is not set # end of Analog to digital and digital to analog converters # @@ -8963,7 +8987,7 @@ CONFIG_IIO_ST_SENSORS_CORE=m # # Digital to analog converters # -CONFIG_AD3552R=m +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -8985,7 +9009,7 @@ CONFIG_AD5758=m CONFIG_AD5766=m CONFIG_AD5770R=m # CONFIG_AD5791 is not set -CONFIG_AD7293=m +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -9015,7 +9039,7 @@ CONFIG_IIO_SIMPLE_DUMMY=m # # Filters # -CONFIG_ADMV8818=m +# CONFIG_ADMV8818 is not set # end of Filters # @@ -9033,7 +9057,7 @@ CONFIG_AD9523=m # # CONFIG_ADF4350 is not set CONFIG_ADF4371=m -CONFIG_ADMV1013=m +# CONFIG_ADMV1013 is not set # CONFIG_ADMV1014 is not set # CONFIG_ADMV4420 is not set CONFIG_ADRF6780=m @@ -9216,6 +9240,8 @@ CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # end of Inclinometer sensors +CONFIG_IIO_FORMAT_KUNIT_TEST=m + # # Triggers - standalone # @@ -9329,11 +9355,11 @@ CONFIG_MAX31865=m # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set @@ -9341,7 +9367,7 @@ CONFIG_PWM_DWC=m CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_TEGRA=y +CONFIG_PWM_TEGRA=m CONFIG_PWM_XILINX=m # @@ -9364,7 +9390,9 @@ CONFIG_PARTITION_PERCPU=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y +CONFIG_RESET_SIMPLE=y # CONFIG_RESET_TI_SYSCON is not set +CONFIG_RESET_TI_TPS380X=m CONFIG_RESET_TEGRA_BPMP=y # @@ -9388,7 +9416,7 @@ CONFIG_PHY_CADENCE_SIERRA=m # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set -CONFIG_PHY_LAN966X_SERDES=m +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_MAPPHONE_MDM6600=m # CONFIG_PHY_OCELOT_SERDES is not set @@ -9400,15 +9428,14 @@ CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_INNO_USB3=m CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PHY_SAMSUNG_USB2=y -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PHY_TEGRA194_P2U=m +CONFIG_PHY_TEGRA_XUSB=m # CONFIG_PHY_TUSB1210 is not set # end of PHY Subsystem @@ -9430,7 +9457,8 @@ CONFIG_ARM_SMMU_V3_PMU=m # CONFIG_ARM_SPE_PMU is not set CONFIG_ARM_DMC620_PMU=m CONFIG_HISI_PMU=y -CONFIG_HISI_PCIE_PMU=m +# CONFIG_HISI_PCIE_PMU is not set +CONFIG_HNS3_PMU=m # end of Performance monitor support CONFIG_RAS=y @@ -9439,7 +9467,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -9475,6 +9503,7 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m # CONFIG_FPGA_DFL is not set +CONFIG_FPGA_MGR_MICROCHIP_SPI=m # CONFIG_FSI is not set CONFIG_TEE=y CONFIG_OPTEE=y @@ -9930,6 +9959,7 @@ CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=m CONFIG_DLM=m +CONFIG_DLM_DEPRECATED_API=y # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y # CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set @@ -9979,9 +10009,12 @@ CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" # CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y -# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y # CONFIG_SECURITY_LOADPIN is not set CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y @@ -10106,7 +10139,7 @@ CONFIG_CRYPTO_ENGINE=m # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y -# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m @@ -10138,8 +10171,9 @@ CONFIG_CRYPTO_OFB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_NHPOLY1305=m +CONFIG_CRYPTO_NHPOLY1305=y CONFIG_CRYPTO_ADIANTUM=m +# CONFIG_CRYPTO_HCTR2 is not set CONFIG_CRYPTO_ESSIV=m # @@ -10192,6 +10226,7 @@ CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_ARIA is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m # CONFIG_CRYPTO_SM4_GENERIC is not set @@ -10215,8 +10250,8 @@ CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y @@ -10227,13 +10262,20 @@ CONFIG_CRYPTO_USER_API_RNG=m # CONFIG_CRYPTO_USER_API_RNG_CAVP is not set CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y -CONFIG_CRYPTO_STATS=y +# CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m # CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m @@ -10251,7 +10293,7 @@ CONFIG_CRYPTO_DEV_HISI_TRNG=m CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y -CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_SIGNED_PE_FILE_VERIFICATION=y @@ -10296,6 +10338,7 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_INDIRECT_PIO=y +# CONFIG_TRACE_MMIO_ACCESS is not set # # Crypto library routines @@ -10310,10 +10353,11 @@ CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -10452,12 +10496,13 @@ CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_ASN1_ENCODER=y +CONFIG_POLYNOMIAL=m # # Kernel hacking @@ -10546,6 +10591,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -10691,6 +10737,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set # CONFIG_SAMPLES is not set CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set @@ -10718,6 +10765,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set +# CONFIG_CPUMASK_KUNIT_TEST is not set # CONFIG_TEST_LIST_SORT is not set CONFIG_TEST_MIN_HEAP=m # CONFIG_TEST_SORT is not set diff --git a/config/kernel/linux-media-edge.config b/config/kernel/linux-media-edge.config index 15d7da9a6..bfb8e583b 100644 --- a/config/kernel/linux-media-edge.config +++ b/config/kernel/linux-media-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.0.9 Kernel Configuration +# Linux/arm64 6.1.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -175,7 +175,6 @@ CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -305,30 +304,24 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_APPLE is not set -# CONFIG_ARCH_BCM2835 is not set -# CONFIG_ARCH_BCM4908 is not set -# CONFIG_ARCH_BCM_IPROC is not set -# CONFIG_ARCH_BCMBCA is not set +# CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set -# CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_SPARX5 is not set # CONFIG_ARCH_K3 is not set -# CONFIG_ARCH_LAYERSCAPE is not set # CONFIG_ARCH_LG1K is not set # CONFIG_ARCH_HISI is not set # CONFIG_ARCH_KEEMBAY is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set -# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NXP is not set # CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_ROCKCHIP=y -# CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set @@ -375,6 +368,7 @@ CONFIG_ARM64_ERRATUM_1542419=y CONFIG_ARM64_ERRATUM_1508412=y CONFIG_ARM64_ERRATUM_2051678=y # CONFIG_ARM64_ERRATUM_2077057 is not set +CONFIG_ARM64_ERRATUM_2658417=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y CONFIG_ARM64_ERRATUM_2054223=y CONFIG_ARM64_ERRATUM_2067961=y @@ -430,7 +424,7 @@ CONFIG_CRASH_DUMP=y CONFIG_TRANS_TABLE=y CONFIG_XEN_DOM0=y CONFIG_XEN=y -CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y @@ -438,6 +432,7 @@ CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_COMPAT=y CONFIG_KUSER_HELPERS=y +CONFIG_COMPAT_ALIGNMENT_FIXUPS=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -597,9 +592,10 @@ CONFIG_ACPI_CPPC_CPUFREQ=y CONFIG_ACPI_CPPC_CPUFREQ_FIE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=m -# CONFIG_ARM_TEGRA20_CPUFREQ is not set +CONFIG_ARM_TEGRA20_CPUFREQ=m CONFIG_ARM_TEGRA124_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=m +CONFIG_ARM_TEGRA194_CPUFREQ=m # end of CPU Frequency scaling # end of CPU Power Management @@ -673,29 +669,6 @@ CONFIG_KVM_XFER_TO_GUEST_WORK=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y # CONFIG_NVHE_EL2_DEBUG is not set -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_SM4_ARM64_CE=m -# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_POLY1305_NEON=y -CONFIG_CRYPTO_NHPOLY1305_NEON=y -CONFIG_CRYPTO_AES_ARM64_BS=y # # General architecture-dependent options @@ -763,9 +736,12 @@ CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 @@ -990,6 +966,7 @@ CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y @@ -1037,6 +1014,9 @@ CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set # # Data Access Monitoring @@ -1117,6 +1097,7 @@ CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m # CONFIG_INET_ESPINTCP is not set CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=m @@ -1510,13 +1491,6 @@ CONFIG_IP6_NF_TARGET_NPT=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m - -# -# DECnet: Netfilter Configuration -# -CONFIG_DECNET_NF_GRABULATOR=m -# end of DECnet: Netfilter Configuration - CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m @@ -1623,8 +1597,6 @@ CONFIG_NET_DSA_TAG_XRS700X=m CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y CONFIG_LLC=y CONFIG_LLC2=m CONFIG_ATALK=m @@ -2096,6 +2068,9 @@ CONFIG_PCI_HISI=y CONFIG_PCIE_ROCKCHIP_DW_HOST=y # CONFIG_PCIE_KIRIN is not set # CONFIG_PCI_MESON is not set +CONFIG_PCIE_TEGRA194=m +CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_TEGRA194_EP=m # CONFIG_PCIE_AL is not set # end of DesignWare PCI Core Support @@ -2263,6 +2238,7 @@ CONFIG_EFI_SOFT_RESERVE=y CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set CONFIG_EFI_ARMSTUB_DTB_LOADER=y CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=m @@ -2603,6 +2579,7 @@ CONFIG_MISC_RTSX_USB=m CONFIG_HABANA_AI=m CONFIG_UACCE=m # CONFIG_PVPANIC is not set +CONFIG_GP_PCI1XXXX=m # end of Misc devices # @@ -2727,7 +2704,6 @@ CONFIG_SCSI_DH_EMC=m CONFIG_SCSI_DH_ALUA=m # end of SCSI device support -CONFIG_HAVE_PATA_PLATFORM=y CONFIG_ATA=y CONFIG_SATA_HOST=y CONFIG_PATA_TIMINGS=y @@ -2743,8 +2719,9 @@ CONFIG_SATA_PMP=y CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_DWC=y CONFIG_AHCI_CEVA=y -CONFIG_AHCI_TEGRA=m +CONFIG_AHCI_TEGRA=y CONFIG_AHCI_XGENE=y CONFIG_AHCI_QORIQ=y CONFIG_SATA_INIC162X=m @@ -3146,8 +3123,11 @@ CONFIG_I40EVF=m CONFIG_FM10K=m # CONFIG_IGC is not set CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NGBE=m # CONFIG_TXGBE is not set CONFIG_JME=m +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=m CONFIG_NET_VENDOR_MARVELL=y @@ -3181,6 +3161,7 @@ CONFIG_MLX5_CLS_ACT=y CONFIG_MLX5_TC_SAMPLE=y CONFIG_MLX5_CORE_EN_DCB=y # CONFIG_MLX5_CORE_IPOIB is not set +# CONFIG_MLX5_EN_MACSEC is not set # CONFIG_MLX5_EN_IPSEC is not set # CONFIG_MLX5_EN_TLS is not set CONFIG_MLX5_SW_STEERING=y @@ -3366,6 +3347,8 @@ CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_PSE_CONTROLLER=y +CONFIG_PSE_REGULATOR=m CONFIG_CAN_DEV=m CONFIG_CAN_VCAN=m CONFIG_CAN_VXCAN=m @@ -3458,6 +3441,7 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y # PCS device drivers # CONFIG_PCS_XPCS=y +CONFIG_PCS_ALTERA_TSE=m # end of PCS device drivers CONFIG_PPP=m @@ -3832,10 +3816,10 @@ CONFIG_WLCORE_SDIO=m CONFIG_WILINK_PLATFORM_DATA=y CONFIG_RTL8723DU=m CONFIG_RTL8723DS=m -CONFIG_RTL8822CS=m -CONFIG_RTL8822BU=m -CONFIG_RTL8821CU=m -CONFIG_88XXAU=m +# CONFIG_RTL8822CS is not set +# CONFIG_RTL8822BU is not set +# CONFIG_RTL8821CU is not set +# CONFIG_88XXAU is not set CONFIG_RTL8192EU=m CONFIG_RTL8189FS=m CONFIG_RTL8189ES=m @@ -3883,6 +3867,7 @@ CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_IOSM=m CONFIG_MTK_T7XX=m # end of Wireless WAN @@ -3940,8 +3925,9 @@ CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_TEGRA is not set +CONFIG_KEYBOARD_TEGRA=m # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set @@ -4117,6 +4103,7 @@ CONFIG_TOUCHSCREEN_SX8654=m CONFIG_TOUCHSCREEN_TPS6507X=m CONFIG_TOUCHSCREEN_ZET6223=m CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m CONFIG_TOUCHSCREEN_ROHM_BU21023=m CONFIG_TOUCHSCREEN_IQS5XX=m CONFIG_TOUCHSCREEN_ZINITIX=m @@ -4148,6 +4135,7 @@ CONFIG_INPUT_RK805_PWRKEY=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set CONFIG_INPUT_DA7280_HAPTICS=m # CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IBM_PANEL is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set CONFIG_INPUT_IQS626A=m @@ -4159,6 +4147,7 @@ CONFIG_INPUT_SOC_BUTTON_ARRAY=m # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set CONFIG_INPUT_RAVE_SP_PWRBUTTON=m +CONFIG_INPUT_RT5120_PWRKEY=m CONFIG_RMI4_CORE=m CONFIG_RMI4_I2C=m CONFIG_RMI4_SPI=m @@ -4248,7 +4237,9 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y -CONFIG_SERIAL_TEGRA_TCU=m +CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_TEGRA_TCU=y +CONFIG_SERIAL_TEGRA_TCU_CONSOLE=y # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set @@ -4273,6 +4264,7 @@ CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_RP2=m CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=m +# CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set CONFIG_SERIAL_FSL_LINFLEXUART=m CONFIG_SERIAL_CONEXANT_DIGICOLOR=m CONFIG_SERIAL_SPRD=m @@ -4435,6 +4427,7 @@ CONFIG_I2C_XILINX=m # CONFIG_I2C_DIOLAN_U2C=m CONFIG_I2C_CP2615=m +CONFIG_I2C_PCI1XXXX=m CONFIG_I2C_ROBOTFUZZ_OSIF=m CONFIG_I2C_TAOS_EVM=m CONFIG_I2C_TINY_USB=m @@ -4486,6 +4479,7 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_FSL_LIB=m CONFIG_SPI_FSL_SPI=m CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m CONFIG_SPI_OC_TINY=m CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set @@ -4495,7 +4489,9 @@ CONFIG_SPI_ROCKCHIP_SFC=m # CONFIG_SPI_SIFIVE is not set CONFIG_SPI_MXIC=m CONFIG_SPI_TEGRA210_QUAD=m -# CONFIG_SPI_TEGRA20_SFLASH is not set +# CONFIG_SPI_TEGRA114 is not set +CONFIG_SPI_TEGRA20_SFLASH=y +CONFIG_SPI_TEGRA20_SLINK=m # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set @@ -4557,6 +4553,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_AMD is not set CONFIG_PINCTRL_AS3722=m CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CY8C95X0=m CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -4575,6 +4572,7 @@ CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_TEGRA=y CONFIG_PINCTRL_TEGRA124=y CONFIG_PINCTRL_TEGRA210=y +CONFIG_PINCTRL_TEGRA194=y CONFIG_PINCTRL_TEGRA_XUSB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 @@ -4618,7 +4616,6 @@ CONFIG_GPIO_AMD_FCH=m # # I2C GPIO expanders # -CONFIG_GPIO_ADP5588=m CONFIG_GPIO_ADNP=m CONFIG_GPIO_GW_PLD=m CONFIG_GPIO_MAX7300=m @@ -4769,6 +4766,7 @@ CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_DETECTOR_MAX14656=m CONFIG_CHARGER_MAX77650=m # CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MT6370 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -4777,6 +4775,7 @@ CONFIG_CHARGER_MAX77650=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m CONFIG_CHARGER_SMB347=m # CONFIG_BATTERY_GAUGE_LTC2941 is not set CONFIG_BATTERY_GOLDFISH=m @@ -4818,7 +4817,6 @@ CONFIG_SENSORS_ASC7621=m CONFIG_SENSORS_AXI_FAN_CONTROL=m CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m -CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m # CONFIG_SENSORS_CORSAIR_CPRO is not set CONFIG_SENSORS_CORSAIR_PSU=m @@ -4863,6 +4861,7 @@ CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m @@ -4947,6 +4946,7 @@ CONFIG_SENSORS_Q54SJ108A2=m CONFIG_SENSORS_STPDDC60=m CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m CONFIG_SENSORS_XDPE152=m @@ -4966,6 +4966,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_EMC1403=m CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m CONFIG_SENSORS_EMC6W201=m CONFIG_SENSORS_SMSC47M1=m CONFIG_SENSORS_SMSC47M192=m @@ -5080,6 +5081,7 @@ CONFIG_TEGRA_WATCHDOG=m CONFIG_ARM_SMC_WATCHDOG=y # CONFIG_ALIM7101_WDT is not set # CONFIG_I6300ESB_WDT is not set +# CONFIG_HP_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set # CONFIG_XEN_WDT is not set @@ -5170,8 +5172,10 @@ CONFIG_MFD_MAX77650=m # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set # CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set +CONFIG_MFD_OCELOT=m # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set @@ -5179,9 +5183,11 @@ CONFIG_MFD_NTXEC=m # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set CONFIG_UCB1400_CORE=m +CONFIG_MFD_SY7636A=m CONFIG_MFD_RDC321X=m CONFIG_MFD_RT4831=m CONFIG_MFD_RT5033=m +CONFIG_MFD_RT5120=m CONFIG_MFD_RC5T583=y CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=m @@ -5304,6 +5310,7 @@ CONFIG_REGULATOR_MP886X=m CONFIG_REGULATOR_MPQ7920=m # CONFIG_REGULATOR_MT6311 is not set CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6370=m CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m @@ -5321,6 +5328,7 @@ CONFIG_REGULATOR_ROHM=m # CONFIG_REGULATOR_RT4801 is not set CONFIG_REGULATOR_RT4831=m CONFIG_REGULATOR_RT5033=m +CONFIG_REGULATOR_RT5120=m # CONFIG_REGULATOR_RT5190A is not set CONFIG_REGULATOR_RT5759=m CONFIG_REGULATOR_RT6160=m @@ -5476,7 +5484,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_VIDEO_CPIA2=m CONFIG_USB_GSPCA=m CONFIG_USB_GSPCA_BENQ=m CONFIG_USB_GSPCA_CONEX=m @@ -5534,7 +5541,6 @@ CONFIG_USB_S2255=m CONFIG_VIDEO_USBTV=m CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m # # Analog TV USB devices @@ -5561,9 +5567,6 @@ CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y CONFIG_VIDEO_CX231XX_ALSA=m CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_TM6000=m -CONFIG_VIDEO_TM6000_ALSA=m -CONFIG_VIDEO_TM6000_DVB=m # # Digital TV USB devices @@ -5641,6 +5644,9 @@ CONFIG_VIDEO_SOLO6X10=m # CONFIG_VIDEO_TW5864 is not set CONFIG_VIDEO_TW68=m # CONFIG_VIDEO_TW686X is not set +CONFIG_VIDEO_ZORAN=m +# CONFIG_VIDEO_ZORAN_DC30 is not set +# CONFIG_VIDEO_ZORAN_ZR36060 is not set # # Media capture/analog TV support @@ -5649,9 +5655,6 @@ CONFIG_VIDEO_DT3155=m CONFIG_VIDEO_IVTV=m CONFIG_VIDEO_IVTV_ALSA=m CONFIG_VIDEO_FB_IVTV=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_MXB=m # # Media capture/analog/hybrid TV support @@ -5695,10 +5698,6 @@ CONFIG_DVB_PLUTO2=m CONFIG_DVB_PT1=m CONFIG_DVB_PT3=m CONFIG_DVB_SMIPCIE=m -CONFIG_DVB_BUDGET_CORE=m -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_CI=m -CONFIG_DVB_BUDGET_AV=m CONFIG_RADIO_ADAPTERS=m CONFIG_RADIO_MAXIRADIO=m CONFIG_RADIO_SAA7706H=m @@ -5792,7 +5791,6 @@ CONFIG_VIDEO_TEGRA_VDE=m # # Rockchip media platform drivers # -CONFIG_VIDEO_ROCKCHIP_IEP=m CONFIG_VIDEO_ROCKCHIP_RGA=m CONFIG_VIDEO_ROCKCHIP_ISP1=m @@ -5812,6 +5810,12 @@ CONFIG_VIDEO_ROCKCHIP_ISP1=m # Texas Instruments drivers # +# +# Verisilicon media platform drivers +# +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_ROCKCHIP=y + # # VIA media platform drivers # @@ -5847,8 +5851,6 @@ CONFIG_TTPCI_EEPROM=m CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_VIDEO_SAA7146=m -CONFIG_VIDEO_SAA7146_VV=m CONFIG_SMS_SIANO_MDTV=m CONFIG_SMS_SIANO_RC=y # CONFIG_SMS_SIANO_DEBUGFS is not set @@ -6304,7 +6306,8 @@ CONFIG_TEGRA_HOST1X_FIREWALL=y CONFIG_DRM=m CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y -# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_USE_DYNAMIC_DEBUG=y +CONFIG_DRM_KUNIT_TEST=m CONFIG_DRM_KMS_HELPER=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set @@ -6320,9 +6323,10 @@ CONFIG_DRM_DISPLAY_HDMI_HELPER=y # CONFIG_DRM_DP_AUX_CHARDEV is not set CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=m +CONFIG_DRM_BUDDY=m CONFIG_DRM_VRAM_HELPER=m CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_GEM_CMA_HELPER=m +CONFIG_DRM_GEM_DMA_HELPER=m CONFIG_DRM_GEM_SHMEM_HELPER=m CONFIG_DRM_SCHED=m @@ -6367,12 +6371,12 @@ CONFIG_DRM_AST=m CONFIG_DRM_MGAG200=m # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_USE_LVDS is not set -# CONFIG_DRM_RCAR_MIPI_DSI is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set CONFIG_DRM_QXL=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_DRM_TEGRA=m # CONFIG_DRM_TEGRA_DEBUG is not set -# CONFIG_DRM_TEGRA_STAGING is not set +CONFIG_DRM_TEGRA_STAGING=y CONFIG_DRM_PANEL=y # @@ -6545,8 +6549,10 @@ CONFIG_DRM_LEGACY=y # CONFIG_DRM_MGA is not set # CONFIG_DRM_VIA is not set # CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y +CONFIG_DRM_LIB_RANDOM=y # # Frame buffer Devices @@ -6633,6 +6639,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_RT4831=m CONFIG_BACKLIGHT_ADP5520=m @@ -7030,12 +7037,14 @@ CONFIG_SND_SOC_CS35L45_TABLES=m CONFIG_SND_SOC_CS35L45=m CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS42L42_CORE=m CONFIG_SND_SOC_CS42L42=m CONFIG_SND_SOC_CS42L51=m CONFIG_SND_SOC_CS42L51_I2C=m CONFIG_SND_SOC_CS42L52=m CONFIG_SND_SOC_CS42L56=m CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS4234=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_CS4270=m @@ -7072,6 +7081,7 @@ CONFIG_SND_SOC_HDMI_CODEC=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m @@ -7177,6 +7187,8 @@ CONFIG_SND_SOC_SIGMADSP_REGMAP=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_SIMPLE_MUX=m CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SRC4XXX=m CONFIG_SND_SOC_SSM2305=m CONFIG_SND_SOC_SSM2518=m CONFIG_SND_SOC_SSM2602=m @@ -7379,6 +7391,7 @@ CONFIG_HID_KYE=m CONFIG_HID_UCLOGIC=m CONFIG_HID_WALTOP=m CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m CONFIG_HID_XIAOMI=m CONFIG_HID_GYRATION=m CONFIG_HID_ICADE=m @@ -7421,6 +7434,7 @@ CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PXRC=m # CONFIG_HID_RAZER is not set CONFIG_HID_PRIMAX=m CONFIG_HID_RETRODE=m @@ -7514,13 +7528,13 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_XHCI_TEGRA=m +CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_EHCI_FSL=m -CONFIG_USB_EHCI_TEGRA=m +CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OXU210HP_HCD=m CONFIG_USB_ISP116X_HCD=m @@ -7868,6 +7882,7 @@ CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MT6370=m CONFIG_TYPEC_TCPCI_MAXIM=m CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m @@ -7917,12 +7932,10 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_ASPEED=m -CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y CONFIG_MMC_SDHCI_OF_AT91=m CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_TEGRA=m +CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MMC_SDHCI_MILBEAUT=m CONFIG_MMC_ALCOR=m @@ -8191,7 +8204,7 @@ CONFIG_RTC_DRV_PL030=m CONFIG_RTC_DRV_PL031=m CONFIG_RTC_DRV_CADENCE=m # CONFIG_RTC_DRV_FTRTC010 is not set -CONFIG_RTC_DRV_TEGRA=m +CONFIG_RTC_DRV_TEGRA=y # CONFIG_RTC_DRV_R7301 is not set # @@ -8221,8 +8234,8 @@ CONFIG_HISI_DMA=m CONFIG_MV_XOR_V2=y CONFIG_PL330_DMA=y CONFIG_PLX_DMA=m -# CONFIG_TEGRA186_GPC_DMA is not set -# CONFIG_TEGRA20_APB_DMA is not set +CONFIG_TEGRA186_GPC_DMA=m +CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA210_ADMA=m # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set @@ -8389,12 +8402,6 @@ CONFIG_VT6656=m # CONFIG_ADT7316 is not set # end of Analog digital bi-direction converters -# -# Capacitance to digital converters -# -# CONFIG_AD7746 is not set -# end of Capacitance to digital converters - # # Direct Digital Synthesis # @@ -8428,24 +8435,33 @@ CONFIG_SERIO_NVEC_PS2=m CONFIG_NVEC_POWER=m CONFIG_NVEC_PAZ00=m CONFIG_STAGING_MEDIA=y +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_TEGRA=m +CONFIG_VIDEO_TEGRA_TPG=y +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_ROCKCHIP=y -# CONFIG_VIDEO_MAX96712 is not set -CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m CONFIG_VIDEO_STKWEBCAM=m -CONFIG_VIDEO_TEGRA=m -# CONFIG_VIDEO_TEGRA_TPG is not set -CONFIG_VIDEO_ZORAN=m -# CONFIG_VIDEO_ZORAN_DC30 is not set -# CONFIG_VIDEO_ZORAN_ZR36060 is not set +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -CONFIG_COMMON_CLK_XLNX_CLKWZRD=m CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m @@ -8508,6 +8524,7 @@ CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_EC_TYPEC=m CONFIG_CROS_USBPD_NOTIFY=y # CONFIG_CHROMEOS_PRIVACY_SCREEN is not set +CONFIG_CROS_TYPEC_SWITCH=m # CONFIG_CROS_KUNIT is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y @@ -8548,6 +8565,7 @@ CONFIG_COMMON_CLK_XGENE=y CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_RS9_PCIE is not set CONFIG_COMMON_CLK_VC5=y +# CONFIG_COMMON_CLK_VC7 is not set CONFIG_COMMON_CLK_BD718XX=m CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_COMMON_CLK_ROCKCHIP=y @@ -8560,6 +8578,7 @@ CONFIG_CLK_RK3568=y CONFIG_CLK_TEGRA_BPMP=y CONFIG_TEGRA_CLK_DFLL=y CONFIG_XILINX_VCU=m +CONFIG_COMMON_CLK_XLNX_CLKWZRD=m CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_GATE_KUNIT_TEST=m CONFIG_HWSPINLOCK=y @@ -8573,7 +8592,7 @@ CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_ROCKCHIP_TIMER=y CONFIG_TEGRA_TIMER=y -# CONFIG_TEGRA186_TIMER is not set +CONFIG_TEGRA186_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -8606,6 +8625,7 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y # CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set @@ -8703,12 +8723,13 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_186_SOC=y -# CONFIG_ARCH_TEGRA_194_SOC is not set -# CONFIG_ARCH_TEGRA_234_SOC is not set +CONFIG_ARCH_TEGRA_194_SOC=y +CONFIG_ARCH_TEGRA_234_SOC=y CONFIG_SOC_TEGRA_FUSE=y CONFIG_SOC_TEGRA_FLOWCTRL=y CONFIG_SOC_TEGRA_PMC=y CONFIG_SOC_TEGRA_POWERGATE_BPMP=y +CONFIG_SOC_TEGRA_CBB=y CONFIG_SOC_TI=y # @@ -8731,7 +8752,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=m # # DEVFREQ Drivers # -CONFIG_ARM_TEGRA_DEVFREQ=m +CONFIG_ARM_TEGRA_DEVFREQ=y CONFIG_ARM_RK3399_DMC_DEVFREQ=y CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y @@ -8754,8 +8775,7 @@ CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_TEGRA_MC=y -CONFIG_TEGRA210_EMC_TABLE=y -CONFIG_TEGRA210_EMC=m +# CONFIG_TEGRA210_EMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=m @@ -8827,6 +8847,7 @@ CONFIG_MMA8452=m CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m CONFIG_MMA9553=m +# CONFIG_MSA311 is not set CONFIG_MXC4005=m CONFIG_MXC6255=m CONFIG_SCA3000=m @@ -8875,6 +8896,7 @@ CONFIG_LTC2496=m # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +CONFIG_MAX11205=m # CONFIG_MAX1241 is not set CONFIG_MAX1363=m CONFIG_MAX9611=m @@ -8887,6 +8909,7 @@ CONFIG_MCP3911=m # CONFIG_QCOM_SPMI_ADC5 is not set CONFIG_RN5T618_ADC=m CONFIG_ROCKCHIP_SARADC=y +CONFIG_RICHTEK_RTQ6056=m # CONFIG_SD_ADC_MODULATOR is not set CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=m @@ -8931,6 +8954,7 @@ CONFIG_HMC425=m # Capacitance to digital converters # # CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set # end of Capacitance to digital converters # @@ -9127,6 +9151,8 @@ CONFIG_ADIS16460=m # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_BOSCH_BNO055_SERIAL is not set +# CONFIG_BOSCH_BNO055_I2C is not set CONFIG_FXOS8700=m CONFIG_FXOS8700_I2C=m CONFIG_FXOS8700_SPI=m @@ -9175,6 +9201,7 @@ CONFIG_JSA1212=m CONFIG_RPR0521=m CONFIG_SENSORS_LM3533=m CONFIG_LTR501=m +# CONFIG_LTRF216A is not set CONFIG_LV0104CS=m CONFIG_MAX44000=m CONFIG_MAX44009=m @@ -9367,7 +9394,7 @@ CONFIG_PWM_DWC=m CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_TEGRA=m +CONFIG_PWM_TEGRA=y CONFIG_PWM_XILINX=m # @@ -9432,10 +9459,12 @@ CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_INNO_USB3=m CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PHY_SAMSUNG_USB2=y -CONFIG_PHY_TEGRA_XUSB=m +CONFIG_PHY_TEGRA_XUSB=y +CONFIG_PHY_TEGRA194_P2U=m # CONFIG_PHY_TUSB1210 is not set # end of PHY Subsystem @@ -9456,6 +9485,7 @@ CONFIG_ARM_SMMU_V3_PMU=m # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set CONFIG_ARM_DMC620_PMU=m +CONFIG_ALIBABA_UNCORE_DRW_PMU=m CONFIG_HISI_PMU=y # CONFIG_HISI_PCIE_PMU is not set CONFIG_HNS3_PMU=m @@ -9477,17 +9507,19 @@ CONFIG_DEV_DAX_HMEM=m CONFIG_DEV_DAX_HMEM_DEVICES=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y -CONFIG_NVMEM_SPMI_SDAM=m -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_ROCKCHIP_OTP=m -CONFIG_RAVE_SP_EEPROM=m +CONFIG_NVMEM_RAVE_SP_EEPROM=m CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_ROCKCHIP_EFUSE=m +CONFIG_NVMEM_ROCKCHIP_OTP=m +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_U_BOOT_ENV=m # # HW tracing support # # CONFIG_STM is not set # CONFIG_INTEL_TH is not set +CONFIG_HISI_PTT=m # end of HW tracing support CONFIG_FPGA=y @@ -9711,7 +9743,7 @@ CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=m +CONFIG_EFIVAR_FS=y # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y @@ -9813,27 +9845,6 @@ CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y # CONFIG_EROFS_FS_ZIP is not set -CONFIG_AUFS_FS=m -CONFIG_AUFS_BRANCH_MAX_127=y -# CONFIG_AUFS_BRANCH_MAX_511 is not set -# CONFIG_AUFS_BRANCH_MAX_1023 is not set -# CONFIG_AUFS_BRANCH_MAX_32767 is not set -CONFIG_AUFS_SBILIST=y -CONFIG_AUFS_HNOTIFY=y -CONFIG_AUFS_HFSNOTIFY=y -CONFIG_AUFS_EXPORT=y -CONFIG_AUFS_INO_T_64=y -CONFIG_AUFS_XATTR=y -CONFIG_AUFS_FHSM=y -CONFIG_AUFS_RDU=y -CONFIG_AUFS_DIRREN=y -CONFIG_AUFS_SHWH=y -CONFIG_AUFS_BR_RAMFS=y -CONFIG_AUFS_BR_FUSE=y -CONFIG_AUFS_POLL=y -CONFIG_AUFS_BR_HFSPLUS=y -CONFIG_AUFS_BDEV_LOOP=y -# CONFIG_AUFS_DEBUG is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V2=m @@ -10133,6 +10144,7 @@ CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper # # Public-key cryptography @@ -10146,75 +10158,15 @@ CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography # -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_AEGIS128_SIMD=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_OFB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_NHPOLY1305=y -CONFIG_CRYPTO_ADIANTUM=m -# CONFIG_CRYPTO_HCTR2 is not set -CONFIG_CRYPTO_ESSIV=m - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRC64_ROCKSOFT=y -CONFIG_CRYPTO_GHASH=y -CONFIG_CRYPTO_POLY1305=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_SM3=m -# CONFIG_CRYPTO_SM3_GENERIC is not set -CONFIG_CRYPTO_STREEBOG=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers +# Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ARIA is not set CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m @@ -10224,15 +10176,81 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m -# CONFIG_CRYPTO_ARIA is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m # CONFIG_CRYPTO_SM4_GENERIC is not set CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=y +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_SIMD=y +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_SM3_GENERIC is not set +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=y +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) # # Compression @@ -10243,9 +10261,10 @@ CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m CONFIG_CRYPTO_LZ4HC=m CONFIG_CRYPTO_ZSTD=y +# end of Compression # -# Random Number Generation +# Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y @@ -10255,6 +10274,11 @@ CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m @@ -10263,7 +10287,37 @@ CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_NHPOLY1305_NEON=y +CONFIG_CRYPTO_CHACHA20_NEON=y + +# +# Accelerated Cryptographic Algorithms for CPU (arm64) +# +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_POLY1305_NEON=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_SM4_ARM64_CE=m +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +# end of Accelerated Cryptographic Algorithms for CPU (arm64) + CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m @@ -10343,6 +10397,7 @@ CONFIG_INDIRECT_PIO=y # # Crypto library routines # +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y @@ -10361,7 +10416,6 @@ CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines -CONFIG_LIB_MEMNEQ=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -10392,6 +10446,7 @@ CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y @@ -10459,6 +10514,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y +CONFIG_FORCE_NR_CPUS=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -10671,6 +10727,7 @@ CONFIG_STACKTRACE=y # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set @@ -10758,6 +10815,7 @@ CONFIG_KUNIT=m # CONFIG_KUNIT_TEST is not set # CONFIG_KUNIT_EXAMPLE_TEST is not set # CONFIG_KUNIT_ALL_TESTS is not set +# CONFIG_KUNIT_DEFAULT_ENABLED is not set # CONFIG_NOTIFIER_ERROR_INJECTION is not set CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_FAULT_INJECTION is not set @@ -10789,6 +10847,7 @@ CONFIG_TEST_SCANF=m # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m +# CONFIG_TEST_MAPLE_TREE is not set # CONFIG_TEST_RHASHTABLE is not set # CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set @@ -10812,10 +10871,13 @@ CONFIG_CMDLINE_KUNIT_TEST=m CONFIG_SLUB_KUNIT_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m CONFIG_MEMCPY_KUNIT_TEST=m +# CONFIG_IS_SIGNED_TYPE_KUNIT_TEST is not set # CONFIG_OVERFLOW_KUNIT_TEST is not set # CONFIG_STACKINIT_KUNIT_TEST is not set +# CONFIG_FORTIFY_KUNIT_TEST is not set # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set # CONFIG_TEST_KMOD is not set CONFIG_TEST_MEMCAT_P=m # CONFIG_TEST_MEMINIT is not set @@ -10823,4 +10885,9 @@ CONFIG_TEST_MEMCAT_P=m CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking # end of Kernel hacking diff --git a/config/sources/families/media.conf b/config/sources/families/media.conf index e4bc206ad..5509047c0 100644 --- a/config/sources/families/media.conf +++ b/config/sources/families/media.conf @@ -72,30 +72,17 @@ case $BRANCH in ;; current) - - KERNELBRANCH="branch:linux-5.19.y" + KERNELBRANCH="branch:linux-6.0.y" LINUXCONFIG='linux-media-'$BRANCH - - if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == quartz64a || $BOARD == bananapir2pro ]]; then - KERNELPATCHDIR='station-p2-'$BRANCH - LINUXFAMILY=station-p2 - else - KERNELPATCHDIR='media-'$BRANCH - LINUXFAMILY=media -# if [[ $BOARD == jetson-nano ]]; then -# MODULES_INITRD="jetson-nano-current" -# fi - fi + KERNELPATCHDIR='media-'$BRANCH + LINUXFAMILY=media ;; edge) - KERNELBRANCH="branch:linux-6.0.y" + KERNELBRANCH="branch:linux-6.1.y" KERNELPATCHDIR='media-'$BRANCH LINUXFAMILY=media LINUXCONFIG='linux-media-'$BRANCH -# if [[ $BOARD == jetson-nano ]]; then -# MODULES_INITRD="jetson-nano-edge" -# fi ;; esac diff --git a/patch/kernel/archive/media-5.19/00410-general-disable-mtu-validation.patch b/patch/kernel/archive/media-5.19/00410-general-disable-mtu-validation.patch deleted file mode 100644 index 17134c1fa..000000000 --- a/patch/kernel/archive/media-5.19/00410-general-disable-mtu-validation.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bf80eaa34a1b9f503a779b13deed2fda642a1e87 Mon Sep 17 00:00:00 2001 -From: Igor Pecovnik -Date: Wed, 21 Jul 2021 20:59:39 +0000 -Subject: [PATCH] Disable MTU validation - -This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98 - -It works around following issues: - - no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac) - -Signed-off-by: Piotr Szczepanik -Signed-off-by: Igor Pecovnik ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ------------ - 1 file changed, 12 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 91cd5073d..b409a7598 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5435,14 +5435,8 @@ static void stmmac_set_rx_mode(struct net_device *dev) - static int stmmac_change_mtu(struct net_device *dev, int new_mtu) - { - struct stmmac_priv *priv = netdev_priv(dev); -- int txfifosz = priv->plat->tx_fifo_size; - const int mtu = new_mtu; - -- if (txfifosz == 0) -- txfifosz = priv->dma_cap.tx_fifo_size; -- -- txfifosz /= priv->plat->tx_queues_to_use; -- - if (netif_running(dev)) { - netdev_err(priv->dev, "must be stopped to change its MTU\n"); - return -EBUSY; -@@ -5453,12 +5447,6 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu) - return -EINVAL; - } - -- new_mtu = STMMAC_ALIGN(new_mtu); -- -- /* If condition true, FIFO is too small or MTU too large */ -- if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) -- return -EINVAL; -- - dev->mtu = mtu; - - netdev_update_features(dev); --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/archive/media-5.19/00560-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch b/patch/kernel/archive/media-5.19/00560-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch deleted file mode 100644 index bb910db9d..000000000 --- a/patch/kernel/archive/media-5.19/00560-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c -index 415d8ece242a..1d1f9dbd9e93 100644 ---- a/net/dsa/tag_mtk.c -+++ b/net/dsa/tag_mtk.c -@@ -25,6 +25,14 @@ static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb, - u8 xmit_tpid; - u8 *mtk_tag; - -+ /* The Ethernet switch we are interfaced with needs packets to be at -+ * least 64 bytes (including FCS) otherwise their padding might be -+ * corrupted. With tags enabled, we need to make sure that packets are -+ * at least 68 bytes (including FCS and tag). -+ */ -+ if (__skb_put_padto(skb, ETH_ZLEN + MTK_HDR_LEN, false)) -+ return NULL; -+ - /* Build the special tag after the MAC Source Address. If VLAN header - * is present, it's required that VLAN header and special tag is - * being combined. Only in this way we can allow the switch can parse diff --git a/patch/kernel/archive/media-5.19/00570-pwm-fan-fix.patch b/patch/kernel/archive/media-5.19/00570-pwm-fan-fix.patch deleted file mode 100644 index 64a54fd17..000000000 --- a/patch/kernel/archive/media-5.19/00570-pwm-fan-fix.patch +++ /dev/null @@ -1,60 +0,0 @@ -diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c -index f7405a58877e..73303458e886 100644 ---- a/drivers/clk/tegra/clk-tegra114.c -+++ b/drivers/clk/tegra/clk-tegra114.c -@@ -1166,6 +1166,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { - { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, - { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, - { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, -+ { TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 }, - /* must be the last entry */ - { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 }, - }; -diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c -index a9d4efcef2d4..6c46592d794e 100644 ---- a/drivers/clk/tegra/clk-tegra124.c -+++ b/drivers/clk/tegra/clk-tegra124.c -@@ -1330,6 +1330,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { - { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, - { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, - { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, -+ { TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 }, - /* must be the last entry */ - { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, - }; -diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c -index 8a4514f6d503..422d78247553 100644 ---- a/drivers/clk/tegra/clk-tegra20.c -+++ b/drivers/clk/tegra/clk-tegra20.c -@@ -1044,6 +1044,7 @@ static struct tegra_clk_init_table init_table[] = { - { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, - { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, - { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, -+ { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, - /* must be the last entry */ - { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, - }; -diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c -index 499f999e91e1..a3488aaac3f7 100644 ---- a/drivers/clk/tegra/clk-tegra210.c -+++ b/drivers/clk/tegra/clk-tegra210.c -@@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { - { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, - { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, - { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, -+ { TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 }, - /* This MUST be the last entry. */ - { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, - }; -diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c -index 168c07d5a5f2..60f1534711f1 100644 ---- a/drivers/clk/tegra/clk-tegra30.c -+++ b/drivers/clk/tegra/clk-tegra30.c -@@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] = { - { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, - { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, - { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, -+ { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, - /* must be the last entry */ - { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, - }; diff --git a/patch/kernel/archive/media-5.19/00580-add-board-helios64.patch b/patch/kernel/archive/media-5.19/00580-add-board-helios64.patch deleted file mode 100644 index aabf099ae..000000000 --- a/patch/kernel/archive/media-5.19/00580-add-board-helios64.patch +++ /dev/null @@ -1,1175 +0,0 @@ -From 8f81af6941883fdc1d238d85bf282c2a61ffa349 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Tue, 15 Sep 2020 20:04:22 +0700 -Subject: [PATCH] Add board Helios64 - -Signed-off-by: Aditya Prayoga ---- - .../boot/dts/rockchip/rk3399-kobol-helios64.dts | 1084 +++++++++++++++++ - 2 files changed, 1085 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -new file mode 100644 -index 000000000..fae17f416 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -0,0 +1,1154 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Aditya Prayoga (aditya@kobol.io) -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Helios64"; -+ compatible = "kobol,helios64", "rockchip,rk3399"; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ user2-button { -+ label = "User Button 2"; -+ linux,code = ; -+ press-threshold-microvolt = <100000>; -+ }; -+ }; -+ -+ beeper: beeper { -+ compatible = "gpio-beeper"; -+ gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc12v_dcin_bkup: vcc12v-dcin-bkup { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin_bkup"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc12v_hdd: vcc12v-hdd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_hdd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_sys_s0: vcc1v8-sys-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8_sys_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc1v8_sys_s3>; -+ }; -+ -+ vcc0v9_s3: vcc0v9-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc0v9_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ avdd_0v9_s0: avdd-0v9-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "avdd_0v9_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc1v8_sys_s3>; -+ }; -+ -+ avdd_1v8_s0: avdd-1v8-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "avdd_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ pcie_power: pcie-power { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pwr_en>; -+ regulator-name = "pcie_power"; -+ regulator-boot-on; -+ startup-delay-us = <10000>; -+ vin-supply = <&vcc5v0_perdev>; -+ }; -+ -+ vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v0_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_en>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_perdev>; -+ }; -+ -+ vcc5v0_typec: vcc5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_vbus_en>; -+ regulator-name = "vcc5v0_typec"; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_perdev: vcc5v0-perdev { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_perdev"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ }; -+ -+ vcc5v0_hdd: vcc5v0-hdd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_hdd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <830000>; -+ regulator-max-microvolt = <1400000>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ power_hdd_a: power-hdd-a { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdd_a_power>; -+ regulator-name = "power_hdd_a"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ power_hdd_b: power-hdd-b { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdd_b_power>; -+ regulator-name = "power_hdd_b"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ usblan_power: usblan-power { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_lan_en>; -+ regulator-name = "usblan_power"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ fan1: p7-fan { -+ compatible = "pwm-fan"; -+ pwms = <&pwm0 0 40000 0>; -+ cooling-min-state = <0>; -+ cooling-max-state = <3>; -+ #cooling-cells = <2>; -+ cooling-levels = <0 80 170 255>; -+ }; -+ -+ fan2: p6-fan { -+ compatible = "pwm-fan"; -+ pwms = <&pwm1 0 40000 0>; -+ cooling-min-state = <0>; -+ cooling-max-state = <3>; -+ #cooling-cells = <2>; -+ cooling-levels = <0 80 170 255>; -+ }; -+ -+ gpio-charger { -+ compatible = "gpio-charger"; -+ charger-type = "mains"; -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ charge-status-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ac_present_ap>, <&charger_status>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn>, <&user1btn>, <&wake_on_lan>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ -+ user1-button { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; -+ label = "User Button 1"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ hdmi_dp_sound: hdmi-dp-sound { -+ status = "okay"; -+ compatible = "rockchip,rk3399-hdmi-dp"; -+ rockchip,cpu = <&i2s2>; -+ rockchip,codec = <&cdn_dp>; -+ }; -+ -+ io_leds: io-gpio-leds { -+ status = "okay"; -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&network_act>, <&usb3_act>, -+ <&sata_act>, <&sata_err_led>; -+ -+ network { -+ label = "helios64:blue:net"; -+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "netdev"; -+ default-state = "off"; -+ }; -+ -+ sata { -+ label = "helios64:blue:hdd-status"; -+ gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "disk-activity"; -+ default-state = "off"; -+ }; -+ -+ sata_err1 { -+ label = "helios64:red:ata1-err"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err2 { -+ label = "helios64:red:ata2-err"; -+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err3 { -+ label = "helios64:red:ata3-err"; -+ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err4 { -+ label = "helios64:red:ata4-err"; -+ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err5 { -+ label = "helios64:red:ata5-err"; -+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ usb3 { -+ label = "helios64:blue:usb3"; -+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ trigger-sources = <&int_hub_port1>, -+ <&int_hub_port2>, -+ <&int_hub_port3>; -+ linux,default-trigger = "usbport"; -+ default-state = "off"; -+ }; -+ }; -+ -+ pwmleds { -+ compatible = "pwm-leds"; -+ status = "okay"; -+ -+ power-led { -+ label = "helios64:blue:power-status"; -+ pwms = <&pwm3 0 2000000000 0>; -+ max-brightness = <255>; -+ }; -+ }; -+ -+ system_leds: system-gpio-leds { -+ status = "okay"; -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&system_led>; -+ -+ status-led { -+ label = "helios64::status"; -+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "none"; -+ default-state = "on"; -+ mode = <0x23>; -+ }; -+ -+ fault-led { -+ label = "helios64:red:fault"; -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "panic"; -+ default-state = "keep"; -+ mode = <0x23>; -+ }; -+ }; -+}; -+ -+&cdn_dp { -+ status = "okay"; -+ extcon = <&fusb0>; -+ phys = <&tcphy0_dp>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_lan>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins &rgmii_phy_reset>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x20>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ interrupt-parent = <&gpio0>; -+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc3v3_sys_s3>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys_s3>; -+ vddio-supply = <&vcc3v0_s3>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr_s3: DCDC_REG3 { -+ regulator-name = "vcc_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_sys_s3: DCDC_REG4 { -+ regulator-name = "vcc1v8_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ /* not used */ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ }; -+ -+ /* not used */ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-name = "vcc3v0_touch"; -+ }; -+ -+ vcc1v8_s3: LDO_REG3 { -+ regulator-name = "vcc1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio_s0: LDO_REG4 { -+ regulator-name = "vcc_sdio_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ /* not used */ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ }; -+ -+ vcc1v5_s3: LDO_REG6 { -+ regulator-name = "vcc1v5_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ /* not used */ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-name = "vcca1v8_codec"; -+ }; -+ -+ vcc3v0_s3: LDO_REG8 { -+ regulator-name = "vcc3v0_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_sys_s0: SWITCH_REG1 { -+ regulator-name = "vcc3v3_sys_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* not used */ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-name = "vcc3v3_s0"; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_gpio>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <40000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_gpio>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ gpio-expander@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pca0_pins>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ vcc-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ temp@4c { -+ compatible = "onnn,lm75"; -+ reg = <0x4c>; -+ }; -+}; -+ -+&i2c4 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ vbus-supply = <&vcc5v0_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <5000000>; -+ -+ extcon-cables = <1 2 5 6 9 10 12 44>; -+ typec-altmodes = <0xff01 1 0x001c0000 1>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usb_con_hs: endpoint { -+ remote-endpoint = <&u2phy0_typec_hs>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ usb_con_ss: endpoint { -+ remote-endpoint = <&tcphy0_typec_ss>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ usb_con_sbu: endpoint { -+ remote-endpoint = <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* I2C on UEXT */ -+&i2c7 { -+ status = "okay"; -+}; -+ -+/* External I2C */ -+&i2c8 { -+ status = "okay"; -+}; -+ -+&i2s2 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ status = "okay"; -+ bt656-supply = <&vcc1v8_sys_s0>; -+ audio-supply = <&vcc1v8_sys_s0>; -+ sdmmc-supply = <&vcc_sdio_s0>; -+ gpio1830-supply = <&vcc3v0_s3>; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; -+ num-lanes = <2>; -+ max-link-speed = <2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_prst &pcie_clkreqn_cpm>; -+ vpcie12v-supply = <&vcc12v_dcin>; -+ vpcie3v3-supply = <&pcie_power>; -+ vpcie1v8-supply = <&avdd_1v8_s0>; -+ vpcie0v9-supply = <&avdd_0v9_s0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pinctrl { -+ buttons { -+ pwrbtn: pwrbtn { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ user1btn: usr1btn { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ charger { -+ ac_present_ap: ac-present-ap { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ charger_status: charger-status { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fan { -+ fan1_sense: fan1-sense { -+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ fan2_sense: fan2-sense { -+ rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = -+ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ fusb0_vbus_en: fusb0-vbus-en { -+ rockchip,pins = -+ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gmac { -+ rgmii_phy_reset: rgmii-phy-reset { -+ rockchip,pins = -+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; -+ }; -+ }; -+ -+ leds { -+ network_act: network-act { -+ rockchip,pins = -+ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ usb3_act: usb3-act { -+ rockchip,pins = -+ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ sata_act: sata-act { -+ rockchip,pins = -+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ system_led: sys-led { -+ rockchip,pins = -+ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>, -+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ sata_err_led: sata-err-led { -+ rockchip,pins = -+ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ misc { -+ pca0_pins: pca0-pins { -+ rockchip,pins = -+ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wake_on_lan: wake-on-lan { -+ rockchip,pins = -+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_prst: pcie-prst { -+ rockchip,pins = -+ <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_pwr_en: pcie-pwr-en { -+ rockchip,pins = -+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = -+ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = -+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = -+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ power { -+ hdd_a_power: hdd-a-power { -+ rockchip,pins = -+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ hdd_b_power: hdd-b-power { -+ rockchip,pins = -+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_en: vcc5v0-usb-en { -+ rockchip,pins = -+ <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = -+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; -+ }; -+ -+ usb_lan_en: usb-lan-en { -+ rockchip,pins = -+ <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc3v0_s3>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ assigned-clock-rates = <150000000>; -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ // hs400 is broken on Helios64 since 5.10.60 -+ // mmc-hs400-1_8v; -+ // mmc-hs400-enhanced-strobe; -+ supports-emmc; -+ non-removable; -+ disable-wp; -+ status = "okay"; -+ vqmmc-supply = <&vcc1v8_sys_s0>; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // TODO: verify what needs to be done to use implicit CD definition -+ disable-wp; -+ sd-uhs-sdr104; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio_s0>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ status = "okay"; -+}; -+ -+/* UEXT connector */ -+&spi2 { -+ status = "okay"; -+}; -+ -+&spi5 { -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ extcon = <&fusb0>; -+ status = "okay"; -+}; -+ -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&usb_con_sbu>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&usb_con_ss>; -+ }; -+ }; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ phy-supply = <&vcc5v0_usb>; -+ status = "okay"; -+ }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&usb_con_hs>; -+ }; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ dr_mode = "otg"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ status = "okay"; -+ dr_mode = "host"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_hub: hub@1 { -+ compatible = "usb2109,0815"; -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_hub_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ int_hub_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ int_hub_port3: port@3 { -+ reg = <3>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ usb_lan: device@4 { -+ compatible = "usbbda,8156"; -+ reg = <4>; -+ -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ interface@0 { /* interface 0 of configuration 1 */ -+ compatible = "usbbda,8156.config1.0"; -+ reg = <0 1>; -+ }; -+ }; -+ }; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -\ No newline at end of file --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/archive/media-5.19/00590-board-helios64-dts-fix-stability-issues.patch b/patch/kernel/archive/media-5.19/00590-board-helios64-dts-fix-stability-issues.patch deleted file mode 100644 index bc64c1a70..000000000 --- a/patch/kernel/archive/media-5.19/00590-board-helios64-dts-fix-stability-issues.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index e666bd5ae..df1fc943b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -478,6 +478,7 @@ rk808: pmic@1b { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; -+ max-buck-steps-per-change = <4>; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; diff --git a/patch/kernel/archive/media-5.19/00600-board-helios64-remove-overclock.patch b/patch/kernel/archive/media-5.19/00600-board-helios64-remove-overclock.patch deleted file mode 100644 index c99b7fa1d..000000000 --- a/patch/kernel/archive/media-5.19/00600-board-helios64-remove-overclock.patch +++ /dev/null @@ -1,32 +0,0 @@ -From aca2e1df74ae43ddaa3870b31a6eba129148bdcf Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Mon, 7 Sep 2020 20:29:43 +0700 -Subject: [PATCH] Remove overclock from helios64 - -Signed-off-by: Aditya Prayoga ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index ba8ff5d4c..c065ba82d 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -1078,4 +1078,12 @@ - - &vopl_mmu { - status = "okay"; --}; -\ No newline at end of file -+}; -+ -+&cluster0_opp { -+ /delete-node/ opp06; -+}; -+ -+&cluster1_opp { -+ /delete-node/ opp08; -+}; --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/archive/media-5.19/00610-board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/archive/media-5.19/00610-board-helios64-remove-pcie-ep-gpios.patch deleted file mode 100644 index d7a94963d..000000000 --- a/patch/kernel/archive/media-5.19/00610-board-helios64-remove-pcie-ep-gpios.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e7e9a3a959927094d59b67f46ecc1c5d50190ce8 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Tue, 15 Sep 2020 13:42:02 +0700 -Subject: [PATCH] Remove PCIE ep-gpios from Helios64 - -Signed-off-by: Aditya Prayoga ---- - arch/arm64/boot/dts/rockchip/rk3399-helios64.dts | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index c065ba82d..002c93912 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -721,7 +721,6 @@ - }; - - &pcie0 { -- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <2>; - max-link-speed = <2>; - pinctrl-names = "default"; --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/archive/media-5.19/00620-add-driver-for-Motorcomm-YT85xx+PHYs.patch b/patch/kernel/archive/media-5.19/00620-add-driver-for-Motorcomm-YT85xx+PHYs.patch deleted file mode 100644 index dc98bcf6d..000000000 --- a/patch/kernel/archive/media-5.19/00620-add-driver-for-Motorcomm-YT85xx+PHYs.patch +++ /dev/null @@ -1,2202 +0,0 @@ -From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001 -From: baiywt -Date: Fri, 18 Feb 2022 16:38:43 +0800 -Subject: [PATCH] Add yt8531c support. -Adapted from orangepi-xunlong/openwrt - 600-Add-yt8531c-support.patch by schwar3kat ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/motorcomm.c | 1540 +++++++++++++++++++++++++++++++++ - drivers/net/phy/yt8614-phy.h | 491 +++++++++++ - include/linux/motorcomm_phy.h | 119 +++ - 5 files changed, 2156 insertions(+) - create mode 100644 drivers/net/phy/motorcomm.c - create mode 100644 drivers/net/phy/yt8614-phy.h - create mode 100644 include/linux/motorcomm_phy.h - -diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig -index ce030fcb1..ff4861847 100644 ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -297,6 +297,11 @@ config MICROSEMI_PHY - help - Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs - -+config MOTORCOMM_PHY -+ tristate "Motorcomm PHYs" -+ help -+ Supports the YT8010, YT8510, YT8511, YT8512 YT8521 YT8531 PHYs. -+ - config NATIONAL_PHY - tristate "National Semiconductor PHYs" - help -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -new file mode 100644 -index 000000000..74eef3dfa ---- /dev/null -+++ b/drivers/net/phy/motorcomm.c -@@ -0,0 +1,1540 @@ -+/* -+ * drivers/net/phy/motorcomm.c -+ * -+ * Driver for Motorcomm PHYs -+ * -+ * Author: Leilei Zhao -+ * -+ * Copyright (c) 2019 Motorcomm, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * Support : Motorcomm Phys: -+ * Giga phys: yt8511, yt8521 -+ * 100/10 Phys : yt8512, yt8512b, yt8510 -+ * Automotive 100Mb Phys : yt8010 -+ * Automotive 100/10 hyper range Phys: yt8510 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifndef LINUX_VERSION_CODE -+#include -+#else -+#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -+#endif -+/*for wol, 20210604*/ -+#include -+ -+#include "yt8614-phy.h" -+ -+/**** configuration section begin ***********/ -+ -+/* if system depends on ethernet packet to restore from sleep, please define this macro to 1 -+ * otherwise, define it to 0. -+ */ -+#define SYS_WAKEUP_BASED_ON_ETH_PKT 1 -+ -+/* to enable system WOL of phy, please define this macro to 1 -+ * otherwise, define it to 0. -+ */ -+#define YTPHY_ENABLE_WOL 0 -+ -+/* some GMAC need clock input from PHY, for eg., 125M, please enable this macro -+ * by degault, it is set to 0 -+ * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1 -+ */ -+#define GMAC_CLOCK_INPUT_NEEDED 1 -+ -+ -+#define YT8521_PHY_MODE_FIBER 1 //fiber mode only -+#define YT8521_PHY_MODE_UTP 2 //utp mode only -+#define YT8521_PHY_MODE_POLL 3 //fiber and utp, poll mode -+ -+/* please make choice according to system design -+ * for Fiber only system, please define YT8521_PHY_MODE_CURR 1 -+ * for UTP only system, please define YT8521_PHY_MODE_CURR 2 -+ * for combo system, please define YT8521_PHY_MODE_CURR 3 -+ */ -+#define YT8521_PHY_MODE_CURR 3 -+ -+/**** configuration section end ***********/ -+ -+ -+/* no need to change below */ -+ -+#if (YTPHY_ENABLE_WOL) -+#undef SYS_WAKEUP_BASED_ON_ETH_PKT -+#define SYS_WAKEUP_BASED_ON_ETH_PKT 1 -+#endif -+ -+/* workaround for 8521 fiber 100m mode */ -+static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32. -+static int link_mode_8614[4] = {0}; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32. -+ -+/* for multiple port phy, base phy address */ -+static unsigned int yt_mport_base_phy_addr = 0xff; //0xff: invalid; for 8618 -+static unsigned int yt_mport_base_phy_addr_8614 = 0xff; //0xff: invalid; -+ -+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr); -+int yt8511_config_out_125m(struct mii_bus *bus, int phy_id); -+ -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(5,0,0) ) -+int genphy_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ printk (KERN_INFO "yzhang..read phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id); -+ -+ if(phydev->phy_id == 0x4f51e91b) -+ { -+ printk (KERN_INFO "yzhang..get YT8511, abt to set 125m clk out, phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id); -+ ret = yt8511_config_out_125m(phydev->mdio.bus, phydev->mdio.addr); -+ printk (KERN_INFO "yzhang..8511 set 125m clk out, reg=%#04x\n",phydev->mdio.bus->read(phydev->mdio.bus,phydev->mdio.addr,0x1f)/*double check as delay*/); -+ if (ret<0) -+ printk (KERN_INFO "yzhang..failed to set 125m clk out, ret=%d\n",ret); -+ -+ phy_yt8531_led_fixup(phydev->mdio.bus, phydev->mdio.addr); -+ } -+ return genphy_read_abilities(phydev); -+} -+#endif -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+static int ytphy_config_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif -+ -+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ -+static int yt8010_config_aneg(struct phy_device *phydev) -+{ -+ phydev->speed = SPEED_100; -+ return 0; -+} -+ -+static int yt8512_clk_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONTROL1_RMII_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, MII_BMCR); -+ if (val < 0) -+ return val; -+ -+ val |= YT_SOFTWARE_RESET; -+ ret = phy_write(phydev, MII_BMCR, val); -+ -+ return ret; -+} -+ -+static int yt8512_led_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int mask; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED0_ACT_BLK_IND; -+ -+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | -+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | -+ YT8512_LED0_BT_ON_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED1_BT_ON_EN; -+ -+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); -+ -+ return ret; -+} -+ -+static int yt8512_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ ret = yt8512_clk_init(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = yt8512_led_init(phydev); -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ return ret; -+} -+ -+static int yt8512_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int speed, speed_mode, duplex; -+ -+ ret = genphy_update_link(phydev); -+ if (ret) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; -+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ case 3: -+ default: -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ speed = -1; -+#else -+ speed = SPEED_UNKNOWN; -+#endif -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ -+ return 0; -+} -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+#if 0 -+int yt8521_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ return ret; -+ } -+ -+ return 0; -+} -+#else -+/* qingsong feedback 2 genphy_soft_reset will cause problem. -+ * and this is the reduction version -+ */ -+int yt8521_soft_reset(struct phy_device *phydev) -+{ -+ int ret, val; -+ -+ val = ytphy_read_ext(phydev, 0xa001); -+ ytphy_write_ext(phydev, 0xa001, (val & ~0x8000)); -+ -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+#endif -+ -+#endif -+ -+#if GMAC_CLOCK_INPUT_NEEDED -+static int ytphy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = bus->read(bus, phy_id, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int ytphy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ -+int yt8511_config_dis_txdelay(struct mii_bus *bus, int phy_id) -+{ -+ int ret; -+ int val; -+ -+ /* disable auto sleep */ -+ val = ytphy_mii_rd_ext(bus, phy_id, 0x27); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(15)); -+ -+ ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = ytphy_mii_rd_ext(bus, phy_id, 0xc); -+ if (val < 0) -+ return val; -+ -+ /* ext reg 0xc b[7:4] -+ Tx Delay time = 150ps * N - 250ps -+ */ -+ val &= ~(0xf << 4); -+ ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val); -+ printk("yt8511_config_dis_txdelay..phy txdelay, val=%#08x\n",val); -+ -+ return ret; -+} -+ -+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr) -+{ -+ printk("%s in\n", __func__); -+ -+ ytphy_mii_wr_ext(bus, addr, 0xa00d, 0x670); -+ ytphy_mii_wr_ext(bus, addr, 0xa00e, 0x2070); -+ ytphy_mii_wr_ext(bus, addr, 0xa00f, 0x7e); -+ -+ return 0; -+} -+ -+int yt8511_config_out_125m(struct mii_bus *bus, int addr) -+{ -+ int ret; -+ int val; -+ -+ mdelay(50); -+ ret = ytphy_mii_wr_ext(bus, addr, 0xa012, 0xd0); -+ -+ mdelay(100); -+ val = ytphy_mii_rd_ext(bus, addr, 0xa012); -+ -+ if(val != 0xd0) -+ { -+ printk("yt8511_config_out_125m error\n"); -+ return -1; -+ } -+ -+ /* disable auto sleep */ -+ val = ytphy_mii_rd_ext(bus, addr, 0x27); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(15)); -+ -+ ret = ytphy_mii_wr_ext(bus, addr, 0x27, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = ytphy_mii_rd_ext(bus, addr, 0xc); -+ if (val < 0) -+ return val; -+ -+ /* ext reg 0xc.b[2:1] -+ 00-----25M from pll; -+ 01---- 25M from xtl;(default) -+ 10-----62.5M from pll; -+ 11----125M from pll(here set to this value) -+ */ -+ val |= (3 << 1); -+ ret = ytphy_mii_wr_ext(bus, addr, 0xc, val); -+ printk("yt8511_config_out_125m, phy clk out, val=%#08x\n",val); -+ -+#if 0 -+ /* for customer, please enable it based on demand. -+ * configure to master -+ */ -+ val = bus->read(bus, phy_id, 0x9/*master/slave config reg*/); -+ val |= (0x3<<11); //to be manual config and force to be master -+ ret = bus->write(bus, phy_id, 0x9, val); //take effect until phy soft reset -+ if (ret < 0) -+ return ret; -+ -+ printk("yt8511_config_out_125m, phy to be master, val=%#08x\n",val); -+#endif -+ -+ return ret; -+} -+ -+EXPORT_SYMBOL(yt8511_config_out_125m); -+ -+static int yt8511_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ -+ return ret; -+} -+#endif /*GMAC_CLOCK_INPUT_NEEDED*/ -+ -+#if (YTPHY_ENABLE_WOL) -+static int ytphy_switch_reg_space(struct phy_device *phydev, int space) -+{ -+ int ret; -+ -+ if (space == YTPHY_REG_SPACE_UTP){ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ }else{ -+ ret = ytphy_write_ext(phydev, 0xa000, 2); -+ } -+ -+ return ret; -+} -+ -+static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg) -+{ -+ int ret=0; -+ int val=0; -+ -+ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG); -+ if (val < 0) -+ return val; -+ -+ if(wol_cfg.enable) { -+ val |= YTPHY_WOL_CFG_EN; -+ -+ if(wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) { -+ val &= ~YTPHY_WOL_CFG_TYPE; -+ val &= ~YTPHY_WOL_CFG_INTR_SEL; -+ } else if(wol_cfg.type == YTPHY_WOL_TYPE_PULSE) { -+ val |= YTPHY_WOL_CFG_TYPE; -+ val |= YTPHY_WOL_CFG_INTR_SEL; -+ -+ if(wol_cfg.width == YTPHY_WOL_WIDTH_84MS) { -+ val &= ~YTPHY_WOL_CFG_WIDTH1; -+ val &= ~YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_168MS) { -+ val |= YTPHY_WOL_CFG_WIDTH1; -+ val &= ~YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_336MS) { -+ val &= ~YTPHY_WOL_CFG_WIDTH1; -+ val |= YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_672MS) { -+ val |= YTPHY_WOL_CFG_WIDTH1; -+ val |= YTPHY_WOL_CFG_WIDTH2; -+ } -+ } -+ } else { -+ val &= ~YTPHY_WOL_CFG_EN; -+ val &= ~YTPHY_WOL_CFG_INTR_SEL; -+ } -+ -+ ret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) -+{ -+ int val = 0; -+ -+ wol->supported = WAKE_MAGIC; -+ wol->wolopts = 0; -+ -+ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG); -+ if (val < 0) -+ return; -+ -+ if (val & YTPHY_WOL_CFG_EN) -+ wol->wolopts |= WAKE_MAGIC; -+ -+ return; -+} -+ -+static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) -+{ -+ int ret, pre_page, val; -+ ytphy_wol_cfg_t wol_cfg; -+ struct net_device *p_attached_dev = phydev->attached_dev; -+ -+ memset(&wol_cfg,0,sizeof(ytphy_wol_cfg_t)); -+ pre_page = ytphy_read_ext(phydev, 0xa000); -+ if (pre_page < 0) -+ return pre_page; -+ -+ /* Switch to phy UTP page */ -+ ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP); -+ if (ret < 0) -+ return ret; -+ -+ if (wol->wolopts & WAKE_MAGIC) { -+ -+ /* Enable the WOL interrupt */ -+ val = phy_read(phydev, YTPHY_UTP_INTR_REG); -+ val |= YTPHY_WOL_INTR; -+ ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val); -+ if (ret < 0) -+ return ret; -+ -+ /* Set the WOL config */ -+ wol_cfg.enable = 1; //enable -+ wol_cfg.type= YTPHY_WOL_TYPE_PULSE; -+ wol_cfg.width= YTPHY_WOL_WIDTH_672MS; -+ ret = ytphy_wol_en_cfg(phydev, wol_cfg); -+ if (ret < 0) -+ return ret; -+ -+ /* Store the device address for the magic packet */ -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2, -+ ((p_attached_dev->dev_addr[0] << 8) | -+ p_attached_dev->dev_addr[1])); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1, -+ ((p_attached_dev->dev_addr[2] << 8) | -+ p_attached_dev->dev_addr[3])); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0, -+ ((p_attached_dev->dev_addr[4] << 8) | -+ p_attached_dev->dev_addr[5])); -+ if (ret < 0) -+ return ret; -+ } else { -+ wol_cfg.enable = 0; //disable -+ wol_cfg.type= YTPHY_WOL_TYPE_MAX; -+ wol_cfg.width= YTPHY_WOL_WIDTH_MAX; -+ ret = ytphy_wol_en_cfg(phydev, wol_cfg); -+ if (ret < 0) -+ return ret; -+ } -+ -+ /* Recover to previous register space page */ -+ ret = ytphy_switch_reg_space(phydev, pre_page); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+#endif /*(YTPHY_ENABLE_WOL)*/ -+ -+static int yt8521_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ phydev->irq = PHY_POLL; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); -+ -+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, 0xc); -+ if (val < 0) -+ return val; -+ val &= ~(1 << 12); -+ ret = ytphy_write_ext(phydev, 0xc, val); -+ if (ret < 0) -+ return ret; -+ -+ printk (KERN_INFO "yt8521_config_init, 8521 init call out.\n"); -+ return ret; -+} -+ -+/* -+ * for fiber mode, there is no 10M speed mode and -+ * this function is for this purpose. -+ */ -+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp) -+{ -+ int speed_mode, duplex; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ int speed = -1; -+#else -+ int speed = SPEED_UNKNOWN; -+#endif -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT; -+ speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ if (is_utp) -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ speed = SPEED_1000; -+ break; -+ case 3: -+ break; -+ default: -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ speed = -1; -+#else -+ speed = SPEED_UNKNOWN; -+#endif -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ //printk (KERN_INFO "yt8521_adjust_status call out,regval=0x%04x,mode=%s,speed=%dm...\n", val,is_utp?"utp":"fiber", phydev->speed); -+ -+ return 0; -+} -+ -+/* -+ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and -+ * this function handles this case and return 1 per linux kernel's polling. -+ */ -+int yt8521_aneg_done (struct phy_device *phydev) -+{ -+ -+ //printk("yt8521_aneg_done callin,speed=%dm,linkmoded=%d\n", phydev->speed,link_mode_8521); -+ -+ if((32 == link_mode_8521) && (SPEED_100 == phydev->speed)) -+ { -+ return 1/*link_mode_8521*/; -+ } -+ -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ return genphy_aneg_done(phydev); -+#else -+ return 1; -+#endif -+} -+ -+static int yt8521_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ volatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ /* reading UTP */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ link_mode_8521 = 1; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ /* reading Fiber */ -+ ret = ytphy_write_ext(phydev, 0xa000, 2); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ //note: below debug information is used to check multiple PHy ports. -+ //printk (KERN_INFO "yt8521_read_status, fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev); -+ -+ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case -+ * this is important for Linux kernel for that, missing linkdown event will cause problem. -+ */ -+ yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR); -+ yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR); -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val)) -+ { -+ link = 0; -+ printk (KERN_INFO "yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8521_fiber_latch_val,yt8521_fiber_curr_val); -+ } -+ -+ if (link) { -+ link_fiber = 1; -+ yt8521_adjust_status(phydev, val, 0); -+ link_mode_8521 = 32; //fiber mode -+ -+ -+ } else { -+ link_fiber = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ link_mode_8521 = 0; -+ } -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ if (link_utp) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ } -+#endif -+ -+ //printk (KERN_INFO "yzhang..8521 read status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8521 ); -+ return 0; -+} -+ -+int yt8521_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8521_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ int ret; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ /* disable auto sleep */ -+ value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); -+ if (value < 0) -+ return value; -+ -+ value &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); -+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ value = ytphy_read_ext(phydev, 0xc); -+ if (value < 0) -+ return value; -+ value &= ~(1 << 12); -+ ret = ytphy_write_ext(phydev, 0xc, value); -+ if (ret < 0) -+ return ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ ytphy_write_ext(phydev, 0xa000, 0); -+#endif -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+int yt8618_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+int yt8614_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* utp */ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* qsgmii */ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode -+ return ret; -+ } -+ -+ /* sgmii */ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode -+ return ret; -+ } -+ -+ return 0; -+} -+ -+#endif -+ -+static int yt8618_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ phydev->irq = PHY_POLL; -+ -+ if(0xff == yt_mport_base_phy_addr) -+ /* by default, we think the first phy should be the base phy addr. for mul */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ { -+ yt_mport_base_phy_addr = phydev->addr; -+ }else if (yt_mport_base_phy_addr > phydev->addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->addr); -+ } -+#else -+ { -+ yt_mport_base_phy_addr = phydev->mdio.addr; -+ }else if (yt_mport_base_phy_addr > phydev->mdio.addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->mdio.addr); -+ } -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ /* for utp to optimize signal */ -+ ret = ytphy_write_ext(phydev, 0x41, 0x33); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x42, 0x66); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x43, 0xaa); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x44, 0xd0d); -+ if (ret < 0) -+ return ret; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ if((phydev->addr > yt_mport_base_phy_addr) && ((2 == phydev->addr - yt_mport_base_phy_addr) || (5 == phydev->addr - yt_mport_base_phy_addr))) -+#else -+ if((phydev->mdio.addr > yt_mport_base_phy_addr) && ((2 == phydev->mdio.addr - yt_mport_base_phy_addr) || (5 == phydev->mdio.addr - yt_mport_base_phy_addr))) -+#endif -+ { -+ ret = ytphy_write_ext(phydev, 0x44, 0x2929); -+ if (ret < 0) -+ return ret; -+ } -+ -+ val = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, val | BMCR_RESET); -+ -+ printk (KERN_INFO "yt8618_config_init call out.\n"); -+ return ret; -+} -+ -+static int yt8614_config_init(struct phy_device *phydev) -+{ -+ int ret = 0; -+ -+ phydev->irq = PHY_POLL; -+ -+ if(0xff == yt_mport_base_phy_addr_8614) -+ /* by default, we think the first phy should be the base phy addr. for mul */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ { -+ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->addr; -+ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->addr); -+ } -+#else -+ { -+ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->mdio.addr; -+ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->mdio.addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->mdio.addr); -+ } -+#endif -+ return ret; -+} -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->addr) ? 0 : (unsigned int)((phydev)->addr) - yt_mport_base_phy_addr_8614) -+#else -+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->mdio.addr) ? 0 : (unsigned int)((phydev)->mdio.addr) - yt_mport_base_phy_addr_8614) -+#endif -+ -+int yt8618_aneg_done (struct phy_device *phydev) -+{ -+ -+ return genphy_aneg_done(phydev); -+} -+ -+int yt8614_aneg_done (struct phy_device *phydev) -+{ -+ int port = yt8614_get_port_from_phydev(phydev); -+ -+ /*it should be used for 8614 fiber*/ -+ if((32 == link_mode_8614[port]) && (SPEED_100 == phydev->speed)) -+ { -+ return 1; -+ } -+ -+ return genphy_aneg_done(phydev); -+} -+ -+static int yt8614_read_status(struct phy_device *phydev) -+{ -+ //int i; -+ int ret; -+ volatile int val, yt8614_fiber_latch_val, yt8614_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ int port = yt8614_get_port_from_phydev(phydev); -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ /* switch to utp and reading regs */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ // here is same as 8521 and re-use the function; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+#endif //(YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ /* reading Fiber/sgmii */ -+ ret = ytphy_write_ext(phydev, 0xa000, 3); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ //printk (KERN_INFO "yzhang..8614 read fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev); -+ -+ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case */ -+ yt8614_fiber_latch_val = phy_read(phydev, MII_BMSR); -+ yt8614_fiber_curr_val = phy_read(phydev, MII_BMSR); -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if((link) && (yt8614_fiber_latch_val != yt8614_fiber_curr_val)) -+ { -+ link = 0; -+ printk (KERN_INFO "yt8614_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8614_fiber_latch_val,yt8614_fiber_curr_val); -+ } -+ -+ if (link) { -+ link_fiber = 1; -+ yt8521_adjust_status(phydev, val, 0); -+ link_mode_8614[port] = 32; //fiber mode -+ -+ -+ } else { -+ link_fiber = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ link_mode_8614[port] = 0; -+ } -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ if (link_utp) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ } -+#endif -+ //printk (KERN_INFO "yt8614_read_status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8614[port] ); -+ -+ return 0; -+} -+ -+static int yt8618_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ volatile int val; //maybe for 8614 yt8521_fiber_latch_val, yt8521_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ -+ /* switch to utp and reading regs */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ } -+ -+ return 0; -+} -+ -+int yt8618_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8618_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8614_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8614_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+ -+static struct phy_driver ytphy_drvs[] = { -+ { -+ .phy_id = PHY_ID_YT8010, -+ .name = "YT8010 Automotive Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = yt8010_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8510, -+ .name = "YT8510 100/10Mb Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8511, -+ .name = "YT8511 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_GBIT_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if GMAC_CLOCK_INPUT_NEEDED -+ .config_init = yt8511_config_init, -+#else -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+#endif -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512, -+ .name = "YT8512 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512B, -+ .name = "YT8512B Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8521, -+ .name = "YT8521 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8521_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8521_aneg_done, -+#endif -+ .config_init = yt8521_config_init, -+ .read_status = yt8521_read_status, -+ .suspend = yt8521_suspend, -+ .resume = yt8521_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ },{ -+ /* same as 8521 */ -+ .phy_id = PHY_ID_YT8531S, -+ .name = "YT8531S Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8521_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8521_aneg_done, -+#endif -+ .config_init = yt8521_config_init, -+ .read_status = yt8521_read_status, -+ .suspend = yt8521_suspend, -+ .resume = yt8521_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ }, { -+ /* same as 8511 */ -+ .phy_id = PHY_ID_YT8531, -+ .name = "YT8531 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ }, { -+ .phy_id = PHY_ID_YT8618, -+ .name = "YT8618 Ethernet", -+ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8618_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8618_aneg_done, -+#endif -+ .config_init = yt8618_config_init, -+ .read_status = yt8618_read_status, -+ .suspend = yt8618_suspend, -+ .resume = yt8618_resume, -+ }, { -+ .phy_id = PHY_ID_YT8614, -+ .name = "YT8614 Ethernet", -+ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK_8614, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8614_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8614_aneg_done, -+#endif -+ .config_init = yt8614_config_init, -+ .read_status = yt8614_read_status, -+ .suspend = yt8614_suspend, -+ .resume = yt8614_resume, -+ }, -+}; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+static int ytphy_drivers_register(struct phy_driver* phy_drvs, int size) -+{ -+ int i, j; -+ int ret; -+ -+ for (i = 0; i < size; i++) { -+ ret = phy_driver_register(&phy_drvs[i]); -+ if (ret) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ for (j = 0; j < i; j++) -+ phy_driver_unregister(&phy_drvs[j]); -+ -+ return ret; -+} -+ -+static void ytphy_drivers_unregister(struct phy_driver* phy_drvs, int size) -+{ -+ int i; -+ -+ for (i = 0; i < size; i++) { -+ phy_driver_unregister(&phy_drvs[i]); -+ } -+} -+ -+static int __init ytphy_init(void) -+{ -+ printk("motorcomm phy register\n"); -+ return ytphy_drivers_register(ytphy_drvs, ARRAY_SIZE(ytphy_drvs)); -+} -+ -+static void __exit ytphy_exit(void) -+{ -+ printk("motorcomm phy unregister\n"); -+ ytphy_drivers_unregister(ytphy_drvs, ARRAY_SIZE(ytphy_drvs)); -+} -+ -+module_init(ytphy_init); -+module_exit(ytphy_exit); -+#else -+/* for linux 4.x */ -+module_phy_driver(ytphy_drvs); -+#endif -+ -+MODULE_DESCRIPTION("Motorcomm PHY driver"); -+MODULE_AUTHOR("Leilei Zhao"); -+MODULE_LICENSE("GPL"); -+ -+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { -+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK }, -+ { PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK }, -+ { PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK }, -+ { PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); -+ -+ -diff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h -new file mode 100644 -index 000000000..56a398338 ---- /dev/null -+++ b/drivers/net/phy/yt8614-phy.h -@@ -0,0 +1,491 @@ -+#ifndef _PHY_H_ -+#define _PHY_H_ -+ -+ -+/* configuration for driver */ -+ -+#define YT8614_MAX_LPORT_ID 3 -+ -+#define YT8614_PHY_MODE_FIBER 1 //fiber mode only -+#define YT8614_PHY_MODE_UTP 2 //utp mode only -+#define YT8614_PHY_MODE_POLL 3 //fiber and utp, poll mode -+ -+/* please make choice according to system design -+ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1 -+ * for UTP only system, please define YT8614_PHY_MODE_CURR 2 -+ * for combo system, please define YT8614_PHY_MODE_CURR 3 -+ */ -+#define YT8614_PHY_MODE_CURR 3 -+ -+ -+ -+/* pls dont modify below lines */ -+ -+#define PHY_ID_YT8614 0x4F51E899 //serdes -+#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff -+ -+#ifndef BOOL -+#define BOOL unsigned int -+#endif -+ -+#ifndef FALSE -+#define FALSE 0 -+#endif -+ -+#ifndef TRUE -+#define TRUE 1 -+#endif -+ -+#ifndef SPEED_1000M -+#define SPEED_1000M 2 -+#endif -+#ifndef SPEED_100M -+#define SPEED_100M 1 -+#endif -+#ifndef SPEED_10M -+#define SPEED_10M 0 -+#endif -+ -+#ifndef SPEED_UNKNOWN -+#define SPEED_UNKNOWN 0xffff -+#endif -+ -+#ifndef DUPLEX_FULL -+#define DUPLEX_FULL 1 -+#endif -+#ifndef DUPLEX_HALF -+#define DUPLEX_HALF 0 -+#endif -+ -+#ifndef BIT -+#define BIT(n) (0x1<<(n)) -+#endif -+#ifndef s32 -+typedef int s32; -+typedef unsigned int u32; -+typedef unsigned short u16; -+typedef unsigned char u8; -+#endif -+ -+#ifndef REG_PHY_SPEC_STATUS -+#define REG_PHY_SPEC_STATUS 0x11 -+#define REG_DEBUG_ADDR_OFFSET 0x1e -+#define REG_DEBUG_DATA 0x1f -+#endif -+ -+/**********YT8614************************************************/ -+ -+#define YT8614_SMI_SEL_PHY 0x0 -+#define YT8614_SMI_SEL_SDS_QSGMII 0x02 -+#define YT8614_SMI_SEL_SDS_SGMII 0x03 -+ -+/* yt8614 register type */ -+#define YT8614_TYPE_COMMON 0x01 -+#define YT8614_TYPE_UTP_MII 0x02 -+#define YT8614_TYPE_UTP_EXT 0x03 -+#define YT8614_TYPE_LDS_MII 0x04 -+#define YT8614_TYPE_UTP_MMD 0x05 -+#define YT8614_TYPE_SDS_QSGMII_MII 0x06 -+#define YT8614_TYPE_SDS_SGMII_MII 0x07 -+#define YT8614_TYPE_SDS_QSGMII_EXT 0x08 -+#define YT8614_TYPE_SDS_SGMII_EXT 0x09 -+ -+/* YT8614 extended common register */ -+#define YT8614_REG_COM_SMI_MUX 0xA000 -+#define YT8614_REG_COM_SLED_CFG0 0xA001 -+#define YT8614_REG_COM_PHY_ID 0xA002 -+#define YT8614_REG_COM_CHIP_VER 0xA003 -+#define YT8614_REG_COM_SLED_CFG 0xA004 -+#define YT8614_REG_COM_MODE_CHG_RESET 0xA005 -+#define YT8614_REG_COM_SYNCE0_CFG 0xA006 -+#define YT8614_REG_COM_CHIP_MODE 0xA007 -+ -+#define YT8614_REG_COM_HIDE_SPEED 0xA009 -+ -+#define YT8614_REG_COM_SYNCE1_CFG 0xA00E -+ -+#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019 -+ -+ -+#define YT8614_REG_COM_HIDE_SEL1 0xA054 -+#define YT8614_REG_COM_HIDE_LED_CFG2 0xB8 -+#define YT8614_REG_COM_HIDE_LED_CFG3 0xB9 -+#define YT8614_REG_COM_HIDE_LED_CFG5 0xBB -+ -+#define YT8614_REG_COM_HIDE_LED_CFG4 0xBA //not used currently -+ -+#if 0 -+#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently -+#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061 -+#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062 -+#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063 -+#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064 -+#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065 -+#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066 -+#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067 -+#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068 -+#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069 -+#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A -+#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B -+#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C -+#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D -+#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E -+#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F -+#endif -+ -+#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070 -+#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071 -+#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072 -+#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073 -+#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074 -+#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075 -+#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076 -+#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077 -+ -+#define YT8614_REG_COM_PKG_CFG0 0xA0A0 -+#define YT8614_REG_COM_PKG_CFG1 0xA0A1 -+#define YT8614_REG_COM_PKG_CFG2 0xA0A2 -+#define YT8614_REG_COM_PKG_RX_VALID0 0xA0A3 -+#define YT8614_REG_COM_PKG_RX_VALID1 0xA0A4 -+#define YT8614_REG_COM_PKG_RX_OS0 0xA0A5 -+#define YT8614_REG_COM_PKG_RX_OS1 0xA0A6 -+#define YT8614_REG_COM_PKG_RX_US0 0xA0A7 -+#define YT8614_REG_COM_PKG_RX_US1 0xA0A8 -+#define YT8614_REG_COM_PKG_RX_ERR 0xA0A9 -+#define YT8614_REG_COM_PKG_RX_OS_BAD 0xA0AA -+#define YT8614_REG_COM_PKG_RX_FRAG 0xA0AB -+#define YT8614_REG_COM_PKG_RX_NOSFD 0xA0AC -+#define YT8614_REG_COM_PKG_TX_VALID0 0xA0AD -+#define YT8614_REG_COM_PKG_TX_VALID1 0xA0AE -+#define YT8614_REG_COM_PKG_TX_OS0 0xA0AF -+ -+#define YT8614_REG_COM_PKG_TX_OS1 0xA0B0 -+#define YT8614_REG_COM_PKG_TX_US0 0xA0B1 -+#define YT8614_REG_COM_PKG_TX_US1 0xA0B2 -+#define YT8614_REG_COM_PKG_TX_ERR 0xA0B3 -+#define YT8614_REG_COM_PKG_TX_OS_BAD 0xA0B4 -+#define YT8614_REG_COM_PKG_TX_FRAG 0xA0B5 -+#define YT8614_REG_COM_PKG_TX_NOSFD 0xA0B6 -+#define YT8614_REG_COM_PKG_CFG3 0xA0B7 -+#define YT8614_REG_COM_PKG_AZ_CFG 0xA0B8 -+#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9 -+ -+#define YT8614_REG_COM_MANU_HW_RESET 0xA0C0 -+ -+/* YT8614 UTP MII register: same as generic phy register definitions */ -+#define REG_MII_BMCR 0x00 /* Basic mode control register */ -+#define REG_MII_BMSR 0x01 /* Basic mode status register */ -+#define REG_MII_PHYSID1 0x02 /* PHYS ID 1 */ -+#define REG_MII_PHYSID2 0x03 /* PHYS ID 2 */ -+#define REG_MII_ADVERTISE 0x04 /* Advertisement control reg */ -+#define REG_MII_LPA 0x05 /* Link partner ability reg */ -+#define REG_MII_EXPANSION 0x06 /* Expansion register */ -+#define REG_MII_NEXT_PAGE 0x07 /* Next page register */ -+#define REG_MII_LPR_NEXT_PAGE 0x08 /* LPR next page register */ -+#define REG_MII_CTRL1000 0x09 /* 1000BASE-T control */ -+#define REG_MII_STAT1000 0x0A /* 1000BASE-T status */ -+ -+#define REG_MII_MMD_CTRL 0x0D /* MMD access control register */ -+#define REG_MII_MMD_DATA 0x0E /* MMD access data register */ -+ -+#define REG_MII_ESTATUS 0x0F /* Extended Status */ -+#define REG_MII_SPEC_CTRL 0x10 /* PHY specific func control */ -+#define REG_MII_SPEC_STATUS 0x11 /* PHY specific status */ -+#define REG_MII_INT_MASK 0x12 /* Interrupt mask register */ -+#define REG_MII_INT_STATUS 0x13 /* Interrupt status register */ -+#define REG_MII_DOWNG_CTRL 0x14 /* Speed auto downgrade control*/ -+#define REG_MII_RERRCOUNTER 0x15 /* Receive error counter */ -+ -+#define REG_MII_EXT_ADDR 0x1E /* Extended reg's address */ -+#define REG_MII_EXT_DATA 0x1F /* Extended reg's date */ -+ -+#ifndef MII_BMSR -+#define MII_BMSR REG_MII_BMSR -+#endif -+ -+#ifndef YT8614_SPEED_MODE_BIT -+#define YT8614_SPEED_MODE 0xc000 -+#define YT8614_DUPLEX 0x2000 -+#define YT8614_SPEED_MODE_BIT 14 -+#define YT8614_DUPLEX_BIT 13 -+#define YT8614_LINK_STATUS_BIT 10 -+ -+#endif -+ -+#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI 0x2000 -+ -+/* YT8614 UTP MMD register */ -+#define YT8614_REG_UTP_MMD_CTRL1 0x00 /* PCS control 1 register */ -+#define YT8614_REG_UTP_MMD_STATUS1 0x01 /* PCS status 1 register */ -+#define YT8614_REG_UTP_MMD_EEE_CTRL 0x14 /* EEE control and capability */ -+#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT 0x16 /* EEE wake error counter */ -+#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI 0x3C /* local device EEE ability */ -+#define YT8614_REG_UTP_MMD_EEE_LP_ABI 0x3D /* link partner EEE ability */ -+#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000 /* autoneg result of EEE */ -+ -+/* YT8614 UTP EXT register */ -+#define YT8614_REG_UTP_EXT_LPBK 0x0A -+#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27 -+#define YT8614_REG_UTP_EXT_DEBUG_MON1 0x5A -+#define YT8614_REG_UTP_EXT_DEBUG_MON2 0x5B -+#define YT8614_REG_UTP_EXT_DEBUG_MON3 0x5C -+#define YT8614_REG_UTP_EXT_DEBUG_MON4 0x5D -+ -+/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */ -+#define REG_SDS_BMCR 0x00 /* Basic mode control register */ -+#define REG_SDS_BMSR 0x01 /* Basic mode status register */ -+#define REG_SDS_PHYSID1 0x02 /* PHYS ID 1 */ -+#define REG_SDS_PHYSID2 0x03 /* PHYS ID 2 */ -+#define REG_SDS_ADVERTISE 0x04 /* Advertisement control reg */ -+#define REG_SDS_LPA 0x05 /* Link partner ability reg */ -+#define REG_SDS_EXPANSION 0x06 /* Expansion register */ -+#define REG_SDS_NEXT_PAGE 0x07 /* Next page register */ -+#define REG_SDS_LPR_NEXT_PAGE 0x08 /* LPR next page register */ -+ -+#define REG_SDS_ESTATUS 0x0F /* Extended Status */ -+#define REG_SDS_SPEC_STATUS 0x11 /* SDS specific status */ -+ -+#define REG_SDS_100FX_CFG 0x14 /* 100fx cfg */ -+#define REG_SDS_RERRCOUNTER 0x15 /* Receive error counter */ -+#define REG_SDS_LINT_FAIL_CNT 0x16 /* Lint fail counter mon */ -+ -+/* YT8614 SDS(5G) EXT register */ -+#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02 /* sds analog digital interface cfg */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06 /* sds prbs cfg2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07 /* sds prbs cfg2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ -+#define YT8614_REG_QSGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ -+ -+/* YT8614 SDS(1.25G) EXT register */ -+#define YT8614_REG_SGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ -+#define YT8614_REG_SGMII_EXT_PRBS_CFG2 0x06 /* sds prbs cfg2 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ -+#define YT8614_REG_SGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ -+#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5 /* Fiber auto sensing */ -+ -+//////////////////////////////////////////////////////////////////// -+#define YT8614_MMD_DEV_ADDR1 0x1 -+#define YT8614_MMD_DEV_ADDR3 0x3 -+#define YT8614_MMD_DEV_ADDR7 0x7 -+#define YT8614_MMD_DEV_ADDR_NONE 0xFF -+ -+/**********YT8521S************************************************/ -+/* Basic mode control register(0x00) */ -+#define BMCR_RESV 0x003f /* Unused... */ -+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ -+#define BMCR_CTST 0x0080 /* Collision test */ -+#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -+#define BMCR_RESET 0x8000 /* Reset the DP83840 */ -+ -+/* Basic mode status register(0x01) */ -+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -+#define BMSR_JCD 0x0002 /* Jabber detected */ -+#define BMSR_LSTATUS 0x0004 /* Link status */ -+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -+#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -+#define BMSR_RESV 0x00c0 /* Unused... */ -+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -+#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ -+#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ -+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ -+ -+/* Advertisement control register(0x04) */ -+#define ADVERTISE_SLCT 0x001f /* Selector bits */ -+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ -+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ -+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ -+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ -+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ -+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ -+#define ADVERTISE_RESV 0x1000 /* Unused... */ -+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ -+ -+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) -+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ -+ ADVERTISE_100HALF | ADVERTISE_100FULL) -+ -+/* Link partner ability register(0x05) */ -+#define LPA_SLCT 0x001f /* Same as advertise selector */ -+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ -+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ -+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ -+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */ -+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -+#define LPA_PAUSE_CAP 0x0400 /* Can pause */ -+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ -+#define LPA_RESV 0x1000 /* Unused... */ -+#define LPA_RFAULT 0x2000 /* Link partner faulted */ -+#define LPA_LPACK 0x4000 /* Link partner acked us */ -+#define LPA_NPAGE 0x8000 /* Next page bit */ -+ -+/* 1000BASE-T Control register(0x09) */ -+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ -+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ -+#define CTL1000_AS_MASTER 0x0800 -+#define CTL1000_ENABLE_MASTER 0x1000 -+ -+/* 1000BASE-T Status register(0x0A) */ -+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ -+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ -+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ -+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ -+ -+/**********YT8614************************************************/ -+/* Basic mode control register(0x00) */ -+#define FIBER_BMCR_RESV 0x001f /* b[4:0] Unused... */ -+#define FIBER_BMCR_EN_UNIDIR 0x0020 /* b[5] Valid when bit 0.12 is zero and bit 0.8 is one */ -+#define FIBER_BMCR_SPEED1000 0x0040 /* b[6] MSB of Speed (1000) */ -+#define FIBER_BMCR_CTST 0x0080 /* b[7] Collision test */ -+#define FIBER_BMCR_DUPLEX_MODE 0x0100 /* b[8] Duplex mode */ -+#define FIBER_BMCR_ANRESTART 0x0200 /* b[9] Auto negotiation restart */ -+#define FIBER_BMCR_ISOLATE 0x0400 /* b[10] Isolate phy from RGMII/SGMII/FIBER */ -+#define FIBER_BMCR_PDOWN 0x0800 /* b[11] 1: Power down */ -+#define FIBER_BMCR_ANENABLE 0x1000 /* b[12] Enable auto negotiation */ -+#define FIBER_BMCR_SPEED100 0x2000 /* b[13] LSB of Speed (100) */ -+#define FIBER_BMCR_LOOPBACK 0x4000 /* b[14] Internal loopback control */ -+#define FIBER_BMCR_RESET 0x8000 /* b[15] PHY Software Reset(self-clear) */ -+ -+/* Sds specific status register(0x11) */ -+#define FIBER_SSR_ERCAP 0x0001 /* b[0] realtime syncstatus */ -+#define FIBER_SSR_XMIT 0x000E /* b[3:1] realtime transmit statemachine. -+ 001: Xmit Idle; -+ 010: Xmit Config; -+ 100: Xmit Data. */ -+#define FIBER_SSR_SER_MODE_CFG 0x0030 /* b[5:4] realtime serdes working mode. -+ 00: SG_MAC; -+ 01: SG_PHY; -+ 10: FIB_1000; -+ 11: FIB_100. */ -+#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040 /* b[6] realtime en_flowctrl_tx */ -+#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080 /* b[7] realtime en_flowctrl_rx */ -+#define FIBER_SSR_DUPLEX_ERROR 0x0100 /* b[8] realtime deplex error */ -+#define FIBER_SSR_RX_LPI_ACTIVE 0x0200 /* b[9] rx lpi is active */ -+#define FIBER_SSR_LSTATUS 0x0400 /* b[10] Link status real-time */ -+#define FIBER_SSR_PAUSE 0x1800 /* b[12:11] Pause to mac */ -+#define FIBER_SSR_DUPLEX 0x2000 /* b[13] This status bit is valid only when bit10 is 1. -+ 1: full duplex -+ 0: half duplex */ -+#define FIBER_SSR_SPEED_MODE 0xC000 /* b[15:14] These status bits are valid only when bit10 is 1. -+ 10---1000M -+ 01---100M */ -+ -+/* SLED cfg0 (ext 0xA001) */ -+#define FIBER_SLED_CFG0_EN_CTRL 0x00FF /* b[7:0] Control to enable the eight ports' SLED */ -+#define FIBER_SLED_CFG0_BIT_MASK 0x0700 /* b[10:8] 1: enable the pin output */ -+#define FIBER_SLED_CFG0_ACT_LOW 0x0800 /* b[11] control SLED's polarity. 1: active low; 0: active high */ -+#define FIBER_SLED_CFG0_MANU_ST 0x7000 /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */ -+#define FIBER_SLED_CFG0_MANU_EN 0x8000 /* b[15] to control serial LEDs status manually */ -+ -+/**********YT8614************************************************/ -+/* Fiber auto sensing(sgmii ext 0xA5) */ -+#define FIBER_AUTO_SEN_ENABLE 0x8000 /* b[15] Enable fiber auto sensing */ -+ -+/* Fiber force speed(common ext 0xA009) */ -+#define FIBER_FORCE_1000M 0x0001 /* b[0] 1:1000BX 0:100FX */ -+ -+#ifndef NULL -+#define NULL 0 -+#endif -+ -+/* errno */ -+enum ytphy_8614_errno_e -+{ -+ SYS_E_NONE, -+ SYS_E_PARAM, -+ SYS_E_MAX -+}; -+ -+/* errno */ -+enum ytphy_8614_combo_speed_e -+{ -+ YT8614_COMBO_FIBER_1000M, -+ YT8614_COMBO_FIBER_100M, -+ YT8614_COMBO_UTP_ONLY, -+ YT8614_COMBO_SPEED_MAX -+}; -+ -+/* definition for porting */ -+/* phy registers access */ -+typedef struct -+{ -+ u16 reg; /* the offset of the phy internal address */ -+ u16 val; /* the value of the register */ -+ u8 regType; /* register type */ -+} phy_data_s; -+ -+/* for porting use. -+ * pls over-write member function read/write for mdio access -+ */ -+typedef struct phy_info_str -+{ -+#if 0 -+ struct phy_device *phydev; -+ int mdio_base; -+#endif -+ unsigned int lport; -+ unsigned int bus_id; -+ unsigned int phy_addr; -+ -+ s32 (*read)(struct phy_info_str *info, phy_data_s *param); -+ s32 (*write)(struct phy_info_str *info, phy_data_s *param); -+}phy_info_s; -+ -+/* get phy access method */ -+s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param); -+s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param); -+s32 yt8614_phy_soft_reset(u32 lport); -+s32 yt8614_phy_init(u32 lport); -+s32 yt8614_fiber_enable(u32 lport, BOOL enable); -+s32 yt8614_utp_enable(u32 lport, BOOL enable); -+s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable); -+s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable); -+s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed); -+s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii); -+int yt8614_combo_media_priority_set (u32 lport, int fiber); -+int yt8614_combo_media_priority_get (u32 lport, int *fiber); -+s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable); -+s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask); -+s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask); -+s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full); -+s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full); -+s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed); -+s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed); -+int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg); -+int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media); -+ -+#endif -diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h -new file mode 100644 -index 000000000..9e01fc205 ---- /dev/null -+++ b/include/linux/motorcomm_phy.h -@@ -0,0 +1,119 @@ -+/* -+ * include/linux/motorcomm_phy.h -+ * -+ * Motorcomm PHY IDs -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef _MOTORCOMM_PHY_H -+#define _MOTORCOMM_PHY_H -+ -+#define MOTORCOMM_PHY_ID_MASK 0x00000fff -+#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff -+#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff -+ -+#define PHY_ID_YT8010 0x00000309 -+#define PHY_ID_YT8510 0x00000109 -+#define PHY_ID_YT8511 0x0000010a -+#define PHY_ID_YT8512 0x00000118 -+#define PHY_ID_YT8512B 0x00000128 -+#define PHY_ID_YT8521 0x0000011a -+#define PHY_ID_YT8531S 0x4f51e91a -+#define PHY_ID_YT8531 0x4f51e91b -+//#define PHY_ID_YT8614 0x0000e899 -+#define PHY_ID_YT8618 0x0000e889 -+ -+#define REG_PHY_SPEC_STATUS 0x11 -+#define REG_DEBUG_ADDR_OFFSET 0x1e -+#define REG_DEBUG_DATA 0x1f -+ -+#define YT8512_EXTREG_AFE_PLL 0x50 -+#define YT8512_EXTREG_EXTEND_COMBO 0x4000 -+#define YT8512_EXTREG_LED0 0x40c0 -+#define YT8512_EXTREG_LED1 0x40c3 -+ -+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 -+ -+#define YT_SOFTWARE_RESET 0x8000 -+ -+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 -+#define YT8512_CONTROL1_RMII_EN 0x0001 -+#define YT8512_LED0_ACT_BLK_IND 0x1000 -+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 -+#define YT8512_LED0_BT_BLK_EN 0x0002 -+#define YT8512_LED0_HT_BLK_EN 0x0004 -+#define YT8512_LED0_COL_BLK_EN 0x0008 -+#define YT8512_LED0_BT_ON_EN 0x0010 -+#define YT8512_LED1_BT_ON_EN 0x0010 -+#define YT8512_LED1_TXACT_BLK_EN 0x0100 -+#define YT8512_LED1_RXACT_BLK_EN 0x0200 -+#define YT8512_SPEED_MODE 0xc000 -+#define YT8512_DUPLEX 0x2000 -+ -+#define YT8512_SPEED_MODE_BIT 14 -+#define YT8512_DUPLEX_BIT 13 -+#define YT8512_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 -+#define YT8521_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_SPEED_MODE 0xc000 -+#define YT8521_DUPLEX 0x2000 -+#define YT8521_SPEED_MODE_BIT 14 -+#define YT8521_DUPLEX_BIT 13 -+#define YT8521_LINK_STATUS_BIT 10 -+ -+/* based on yt8521 wol config register */ -+#define YTPHY_UTP_INTR_REG 0x12 -+/* WOL Event Interrupt Enable */ -+#define YTPHY_WOL_INTR BIT(6) -+ -+/* Magic Packet MAC address registers */ -+#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007 -+#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008 -+#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009 -+ -+#define YTPHY_WOL_CFG_REG 0xa00a -+#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */ -+#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */ -+#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */ -+#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */ -+#define YTPHY_WOL_CFG_WIDTH2 BIT(2) -+ -+#define YTPHY_REG_SPACE_UTP 0 -+#define YTPHY_REG_SPACE_FIBER 2 -+ -+enum ytphy_wol_type_e -+{ -+ YTPHY_WOL_TYPE_LEVEL, -+ YTPHY_WOL_TYPE_PULSE, -+ YTPHY_WOL_TYPE_MAX -+}; -+typedef enum ytphy_wol_type_e ytphy_wol_type_t; -+ -+enum ytphy_wol_width_e -+{ -+ YTPHY_WOL_WIDTH_84MS, -+ YTPHY_WOL_WIDTH_168MS, -+ YTPHY_WOL_WIDTH_336MS, -+ YTPHY_WOL_WIDTH_672MS, -+ YTPHY_WOL_WIDTH_MAX -+}; -+typedef enum ytphy_wol_width_e ytphy_wol_width_t; -+ -+struct ytphy_wol_cfg_s -+{ -+ int enable; -+ int type; -+ int width; -+}; -+typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t; -+ -+#endif /* _MOTORCOMM_PHY_H */ -+ -+ --- -2.25.1 - diff --git a/patch/kernel/archive/media-6.0/00120-v91-rk356x-vpu.patch b/patch/kernel/archive/media-6.0/00120-v91-rk356x-vpu.patch deleted file mode 100644 index 491f196ab..000000000 --- a/patch/kernel/archive/media-6.0/00120-v91-rk356x-vpu.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -617,6 +617,28 @@ - #cooling-cells = <2>; - power-domains = <&power RK3568_PD_GPU>; - status = "disabled"; -+ }; -+ -+ vpu: video-codec@fdea0400 { -+ compatible = "rockchip,rk3328-vpu"; -+ reg = <0x0 0xfdea0000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vdpu_mmu>; -+ power-domains = <&power RK3568_PD_VPU>; -+ }; -+ -+ vdpu_mmu: iommu@fdea0800 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdea0800 0x0 0x40>; -+ interrupts = ; -+ interrupt-names = "vdpu_mmu"; -+ clock-names = "aclk", "iface"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ power-domains = <&power RK3568_PD_VPU>; -+ #iommu-cells = <0>; - }; - - sdmmc2: mmc@fe000000 { - diff --git a/patch/kernel/archive/media-6.0/00280-add-fusb30x-driver.patch b/patch/kernel/archive/media-6.0/00280-add-fusb30x-driver.patch deleted file mode 100644 index 67233f0e9..000000000 --- a/patch/kernel/archive/media-6.0/00280-add-fusb30x-driver.patch +++ /dev/null @@ -1,4047 +0,0 @@ -diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig -index 1abf76be2..7ad8b090c 100644 ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -92,6 +92,8 @@ source "drivers/staging/fbtft/Kconfig" - - source "drivers/staging/fsl-dpaa2/Kconfig" - -+source "drivers/staging/fusb30x/Kconfig" -+ - source "drivers/staging/most/Kconfig" - - source "drivers/staging/ks7010/Kconfig" -diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile -index ab0cbe881..2e308d901 100644 ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -36,6 +36,7 @@ obj-$(CONFIG_UNISYSSPAR) += unisys/ - obj-$(CONFIG_UNISYSSPAR) += unisys/ - obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ - obj-$(CONFIG_FB_TFT) += fbtft/ -+obj-$(CONFIG_FUSB_30X) += fusb30x/ - obj-$(CONFIG_MOST) += most/ - obj-$(CONFIG_KS7010) += ks7010/ - obj-$(CONFIG_GREYBUS) += greybus/ -diff --git a/drivers/staging/fusb30x/Kconfig b/drivers/staging/fusb30x/Kconfig -new file mode 100644 -index 000000000..5bb75270f ---- /dev/null -+++ b/drivers/staging/fusb30x/Kconfig -@@ -0,0 +1,10 @@ -+config FUSB_30X -+ tristate "Fairchild FUSB30X Type-C chip driver" -+ depends on I2C -+ help -+ This is a driver for the Fairchild FUSB302 Type-C chip. It supports -+ USB Type-C PD functionality controlled using I2C. -+ -+ This driver supports extcon reporting not yet implemented in the -+ mainline FUSB302 driver. -+ -diff --git a/drivers/staging/fusb30x/Makefile b/drivers/staging/fusb30x/Makefile -new file mode 100644 -index 000000000..1c8e35df3 ---- /dev/null -+++ b/drivers/staging/fusb30x/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_FUSB_30X) += fusb30x.o -diff --git a/drivers/staging/fusb30x/fusb30x.c b/drivers/staging/fusb30x/fusb30x.c -new file mode 100644 -index 000000000..56d22648c ---- /dev/null -+++ b/drivers/staging/fusb30x/fusb30x.c -@@ -0,0 +1,3434 @@ -+/* -+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd -+ * Author: Zain Wang -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * Some ideas are from chrome ec and fairchild GPL fusb302 driver. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "fusb30x.h" -+ -+#define FUSB302_MAX_REG (FUSB_REG_FIFO + 50) -+#define FUSB_MS_TO_NS(x) ((s64)x * 1000 * 1000) -+ -+#define TYPEC_CC_VOLT_OPEN 0 -+#define TYPEC_CC_VOLT_RA 1 -+#define TYPEC_CC_VOLT_RD 2 -+#define TYPEC_CC_VOLT_RP 3 -+ -+#define EVENT_CC BIT(0) -+#define EVENT_RX BIT(1) -+#define EVENT_TX BIT(2) -+#define EVENT_REC_RESET BIT(3) -+#define EVENT_WORK_CONTINUE BIT(5) -+#define EVENT_TIMER_MUX BIT(6) -+#define EVENT_TIMER_STATE BIT(7) -+#define EVENT_DELAY_CC BIT(8) -+#define FLAG_EVENT (EVENT_RX | EVENT_TIMER_MUX | \ -+ EVENT_TIMER_STATE) -+ -+#define PACKET_IS_CONTROL_MSG(header, type) \ -+ (PD_HEADER_CNT(header) == 0 && \ -+ PD_HEADER_TYPE(header) == type) -+ -+#define PACKET_IS_DATA_MSG(header, type) \ -+ (PD_HEADER_CNT(header) != 0 && \ -+ PD_HEADER_TYPE(header) == type) -+ -+/* -+ * DisplayPort modes capabilities -+ * ------------------------------- -+ * <31:24> : Reserved (always 0). -+ * <23:16> : UFP_D pin assignment supported -+ * <15:8> : DFP_D pin assignment supported -+ * <7> : USB 2.0 signaling (0b=yes, 1b=no) -+ * <6> : Plug | Receptacle (0b == plug, 1b == receptacle) -+ * <5:2> : xxx1: Supports DPv1.3, xx1x Supports USB Gen 2 signaling -+ * Other bits are reserved. -+ * <1:0> : signal direction ( 00b=rsv, 01b=sink, 10b=src 11b=both ) -+ */ -+#define PD_DP_PIN_CAPS(x) ((((x) >> 6) & 0x1) ? (((x) >> 16) & 0x3f) \ -+ : (((x) >> 8) & 0x3f)) -+#define PD_DP_SIGNAL_GEN2(x) (((x) >> 3) & 0x1) -+ -+#define MODE_DP_PIN_A BIT(0) -+#define MODE_DP_PIN_B BIT(1) -+#define MODE_DP_PIN_C BIT(2) -+#define MODE_DP_PIN_D BIT(3) -+#define MODE_DP_PIN_E BIT(4) -+#define MODE_DP_PIN_F BIT(5) -+ -+/* Pin configs B/D/F support multi-function */ -+#define MODE_DP_PIN_MF_MASK (MODE_DP_PIN_B | MODE_DP_PIN_D | MODE_DP_PIN_F) -+/* Pin configs A/B support BR2 signaling levels */ -+#define MODE_DP_PIN_BR2_MASK (MODE_DP_PIN_A | MODE_DP_PIN_B) -+/* Pin configs C/D/E/F support DP signaling levels */ -+#define MODE_DP_PIN_DP_MASK (MODE_DP_PIN_C | MODE_DP_PIN_D | \ -+ MODE_DP_PIN_E | MODE_DP_PIN_F) -+ -+/* -+ * DisplayPort Status VDO -+ * ---------------------- -+ * <31:9> : Reserved (always 0). -+ * <8> : IRQ_HPD : 1 == irq arrived since last message otherwise 0. -+ * <7> : HPD state : 0 = HPD_LOW, 1 == HPD_HIGH -+ * <6> : Exit DP Alt mode: 0 == maintain, 1 == exit -+ * <5> : USB config : 0 == maintain current, 1 == switch to USB from DP -+ * <4> : Multi-function preference : 0 == no pref, 1 == MF preferred. -+ * <3> : enabled : is DPout on/off. -+ * <2> : power low : 0 == normal or LPM disabled, 1 == DP disabled for LPM -+ * <1:0> : connect status : 00b == no (DFP|UFP)_D is connected or disabled. -+ * 01b == DFP_D connected, 10b == UFP_D connected, 11b == both. -+ */ -+#define PD_VDO_DPSTS_HPD_IRQ(x) (((x) >> 8) & 0x1) -+#define PD_VDO_DPSTS_HPD_LVL(x) (((x) >> 7) & 0x1) -+#define PD_VDO_DPSTS_MF_PREF(x) (((x) >> 4) & 0x1) -+ -+static u8 fusb30x_port_used; -+static struct fusb30x_chip *fusb30x_port_info[256]; -+ -+static bool is_write_reg(struct device *dev, unsigned int reg) -+{ -+ if (reg >= FUSB_REG_FIFO) -+ return true; -+ else -+ return ((reg < (FUSB_REG_CONTROL4 + 1)) && (reg > 0x01)) ? -+ true : false; -+} -+ -+static bool is_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ if (reg > FUSB_REG_CONTROL4) -+ return true; -+ -+ switch (reg) { -+ case FUSB_REG_CONTROL0: -+ case FUSB_REG_CONTROL1: -+ case FUSB_REG_CONTROL3: -+ case FUSB_REG_RESET: -+ return true; -+ } -+ return false; -+} -+ -+struct regmap_config fusb302_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .writeable_reg = is_write_reg, -+ .volatile_reg = is_volatile_reg, -+ .max_register = FUSB302_MAX_REG, -+ .cache_type = REGCACHE_RBTREE, -+}; -+ -+static void dump_notify_info(struct fusb30x_chip *chip) -+{ -+ dev_dbg(chip->dev, "port %d\n", chip->port_num); -+ dev_dbg(chip->dev, "orientation %d\n", chip->notify.orientation); -+ dev_dbg(chip->dev, "power_role %d\n", chip->notify.power_role); -+ dev_dbg(chip->dev, "data_role %d\n", chip->notify.data_role); -+ dev_dbg(chip->dev, "cc %d\n", chip->notify.is_cc_connected); -+ dev_dbg(chip->dev, "pd %d\n", chip->notify.is_pd_connected); -+ dev_dbg(chip->dev, "enter_mode %d\n", chip->notify.is_enter_mode); -+ dev_dbg(chip->dev, "pin support %d\n", -+ chip->notify.pin_assignment_support); -+ dev_dbg(chip->dev, "pin def %d\n", chip->notify.pin_assignment_def); -+ dev_dbg(chip->dev, "attention %d\n", chip->notify.attention); -+} -+ -+static const unsigned int fusb302_cable[] = { -+ EXTCON_USB, -+ EXTCON_USB_HOST, -+ EXTCON_CHG_USB_SDP, -+ EXTCON_CHG_USB_CDP, -+ EXTCON_CHG_USB_DCP, -+ EXTCON_CHG_USB_SLOW, -+ EXTCON_CHG_USB_FAST, -+ EXTCON_DISP_DP, -+ EXTCON_NONE, -+}; -+ -+static void fusb_set_pos_power(struct fusb30x_chip *chip, int max_vol, -+ int max_cur) -+{ -+ int i; -+ int pos_find; -+ int tmp; -+ -+ pos_find = 0; -+ for (i = PD_HEADER_CNT(chip->rec_head) - 1; i >= 0; i--) { -+ switch (CAP_POWER_TYPE(chip->rec_load[i])) { -+ case 0: -+ /* Fixed Supply */ -+ if ((CAP_FPDO_VOLTAGE(chip->rec_load[i]) * 50) <= -+ max_vol && -+ (CAP_FPDO_CURRENT(chip->rec_load[i]) * 10) <= -+ max_cur) { -+ chip->pos_power = i + 1; -+ tmp = CAP_FPDO_VOLTAGE(chip->rec_load[i]); -+ chip->pd_output_vol = tmp * 50; -+ tmp = CAP_FPDO_CURRENT(chip->rec_load[i]); -+ chip->pd_output_cur = tmp * 10; -+ pos_find = 1; -+ } -+ break; -+ case 1: -+ /* Battery */ -+ if ((CAP_VPDO_VOLTAGE(chip->rec_load[i]) * 50) <= -+ max_vol && -+ (CAP_VPDO_CURRENT(chip->rec_load[i]) * 10) <= -+ max_cur) { -+ chip->pos_power = i + 1; -+ tmp = CAP_VPDO_VOLTAGE(chip->rec_load[i]); -+ chip->pd_output_vol = tmp * 50; -+ tmp = CAP_VPDO_CURRENT(chip->rec_load[i]); -+ chip->pd_output_cur = tmp * 10; -+ pos_find = 1; -+ } -+ break; -+ default: -+ /* not meet battery caps */ -+ break; -+ } -+ if (pos_find) -+ break; -+ } -+} -+ -+static int fusb302_set_pos_power_by_charge_ic(struct fusb30x_chip *chip) -+{ -+ struct power_supply *psy = NULL; -+ union power_supply_propval val; -+ enum power_supply_property psp; -+ int max_vol, max_cur; -+ -+ max_vol = 0; -+ max_cur = 0; -+ psy = power_supply_get_by_phandle(chip->dev->of_node, "charge-dev"); -+ if (!psy || IS_ERR(psy)) -+ return -1; -+ -+ psp = POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX; -+ if (power_supply_get_property(psy, psp, &val) == 0) -+ max_vol = val.intval / 1000; -+ -+ psp = POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT; -+ if (power_supply_get_property(psy, psp, &val) == 0) -+ max_cur = val.intval / 1000; -+ -+ if (max_vol > 0 && max_cur > 0) -+ fusb_set_pos_power(chip, max_vol, max_cur); -+ -+ return 0; -+} -+ -+void fusb_irq_disable(struct fusb30x_chip *chip) -+{ -+ unsigned long irqflags = 0; -+ -+ spin_lock_irqsave(&chip->irq_lock, irqflags); -+ if (chip->enable_irq) { -+ disable_irq_nosync(chip->gpio_int_irq); -+ chip->enable_irq = 0; -+ } else { -+ dev_warn(chip->dev, "irq have already disabled\n"); -+ } -+ spin_unlock_irqrestore(&chip->irq_lock, irqflags); -+} -+ -+void fusb_irq_enable(struct fusb30x_chip *chip) -+{ -+ unsigned long irqflags = 0; -+ -+ spin_lock_irqsave(&chip->irq_lock, irqflags); -+ if (!chip->enable_irq) { -+ enable_irq(chip->gpio_int_irq); -+ chip->enable_irq = 1; -+ } -+ spin_unlock_irqrestore(&chip->irq_lock, irqflags); -+} -+ -+static void platform_fusb_notify(struct fusb30x_chip *chip) -+{ -+ bool plugged = false, flip = false, dfp = false, ufp = false, -+ dp = false, usb_ss = false, hpd = false; -+ union extcon_property_value property; -+ -+ if (chip->notify.is_cc_connected) -+ chip->notify.orientation = -+ (chip->cc_polarity == TYPEC_POLARITY_CC1) ? -+ CC1 : CC2; -+ -+ /* avoid notify repeated */ -+ if (memcmp(&chip->notify, &chip->notify_cmp, -+ sizeof(struct notify_info))) { -+ dump_notify_info(chip); -+ chip->notify.attention = false; -+ memcpy(&chip->notify_cmp, &chip->notify, -+ sizeof(struct notify_info)); -+ -+ plugged = chip->notify.is_cc_connected || -+ chip->notify.is_pd_connected; -+ if (chip->notify.orientation != NONE) -+ flip = (chip->notify.orientation == CC1) ? false : true; -+ dp = chip->notify.is_enter_mode; -+ -+ if (dp) { -+ dfp = true; -+ usb_ss = (chip->notify.pin_assignment_def & -+ MODE_DP_PIN_MF_MASK) ? true : false; -+ hpd = GET_DP_STATUS_HPD(chip->notify.dp_status); -+ } else if (chip->notify.data_role) { -+ dfp = true; -+ usb_ss = true; -+ } else if (plugged) { -+ ufp = true; -+ usb_ss = true; -+ } -+ -+ property.intval = flip; -+ extcon_set_property(chip->extcon, EXTCON_USB, -+ EXTCON_PROP_USB_TYPEC_POLARITY, property); -+ extcon_set_property(chip->extcon, EXTCON_USB_HOST, -+ EXTCON_PROP_USB_TYPEC_POLARITY, property); -+ extcon_set_property(chip->extcon, EXTCON_DISP_DP, -+ EXTCON_PROP_USB_TYPEC_POLARITY, property); -+ -+ property.intval = usb_ss; -+ extcon_set_property(chip->extcon, EXTCON_USB, -+ EXTCON_PROP_USB_SS, property); -+ extcon_set_property(chip->extcon, EXTCON_USB_HOST, -+ EXTCON_PROP_USB_SS, property); -+ extcon_set_property(chip->extcon, EXTCON_DISP_DP, -+ EXTCON_PROP_USB_SS, property); -+ extcon_set_state(chip->extcon, EXTCON_USB, ufp); -+ extcon_set_state(chip->extcon, EXTCON_USB_HOST, dfp); -+ extcon_set_state(chip->extcon, EXTCON_DISP_DP, dp && hpd); -+ extcon_sync(chip->extcon, EXTCON_USB); -+ extcon_sync(chip->extcon, EXTCON_USB_HOST); -+ extcon_sync(chip->extcon, EXTCON_DISP_DP); -+ if (chip->notify.power_role == POWER_ROLE_SINK && -+ chip->notify.is_pd_connected && -+ chip->pd_output_vol > 0 && chip->pd_output_cur > 0) { -+ extcon_set_state(chip->extcon, EXTCON_CHG_USB_FAST, true); -+ property.intval = -+ (chip->pd_output_cur << 15 | -+ chip->pd_output_vol); -+ extcon_set_property(chip->extcon, EXTCON_CHG_USB_FAST, -+ EXTCON_PROP_USB_TYPEC_POLARITY, -+ property); -+ extcon_sync(chip->extcon, EXTCON_CHG_USB_FAST); -+ } -+ } -+} -+ -+static bool platform_get_device_irq_state(struct fusb30x_chip *chip) -+{ -+ return !gpiod_get_value(chip->gpio_int); -+} -+ -+static void fusb_timer_start(struct hrtimer *timer, int ms) -+{ -+ ktime_t ktime; -+ -+ ktime = ktime_set(0, FUSB_MS_TO_NS(ms)); -+ hrtimer_start(timer, ktime, HRTIMER_MODE_REL); -+} -+ -+static void platform_set_vbus_lvl_enable(struct fusb30x_chip *chip, int vbus_5v, -+ int vbus_other) -+{ -+ bool gpio_vbus_value = false; -+ -+ gpio_vbus_value = gpiod_get_value(chip->gpio_vbus_5v); -+ if (chip->gpio_vbus_5v) { -+ gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_5v); -+ } -+ -+ if (chip->gpio_vbus_other) -+ gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_other); -+ -+ if (chip->gpio_discharge && !vbus_5v && gpio_vbus_value) { -+ gpiod_set_value(chip->gpio_discharge, 1); -+ msleep(20); -+ gpiod_set_value(chip->gpio_discharge, 0); -+ } -+} -+ -+static void set_state(struct fusb30x_chip *chip, enum connection_state state) -+{ -+ dev_dbg(chip->dev, "port %d, state %d\n", chip->port_num, state); -+ if (!state) -+ dev_info(chip->dev, "PD disabled\n"); -+ chip->conn_state = state; -+ chip->sub_state = 0; -+ chip->val_tmp = 0; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+} -+ -+static int tcpm_get_message(struct fusb30x_chip *chip) -+{ -+ u8 buf[32]; -+ int len; -+ -+ do { -+ regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, 3); -+ chip->rec_head = (buf[1] & 0xff) | ((buf[2] << 8) & 0xff00); -+ -+ len = PD_HEADER_CNT(chip->rec_head) << 2; -+ regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, len + 4); -+ /* ignore good_crc message */ -+ } while (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_GOODCRC)); -+ -+ memcpy(chip->rec_load, buf, len); -+ -+ return 0; -+} -+ -+static void fusb302_flush_rx_fifo(struct fusb30x_chip *chip) -+{ -+ regmap_write(chip->regmap, FUSB_REG_CONTROL1, CONTROL1_RX_FLUSH); -+} -+ -+static int tcpm_get_cc(struct fusb30x_chip *chip, int *CC1, int *CC2) -+{ -+ u32 val; -+ int *CC_MEASURE; -+ u32 store; -+ -+ *CC1 = TYPEC_CC_VOLT_OPEN; -+ *CC2 = TYPEC_CC_VOLT_OPEN; -+ -+ if (chip->cc_state & CC_STATE_TOGSS_CC1) -+ CC_MEASURE = CC1; -+ else -+ CC_MEASURE = CC2; -+ -+ if (chip->cc_state & CC_STATE_TOGSS_IS_UFP) { -+ regmap_read(chip->regmap, FUSB_REG_SWITCHES0, &store); -+ /* measure cc1 first */ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 | -+ SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 | -+ SWITCHES0_PDWN1 | SWITCHES0_PDWN2, -+ SWITCHES0_PDWN1 | SWITCHES0_PDWN2 | -+ SWITCHES0_MEAS_CC1); -+ usleep_range(250, 300); -+ -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ val &= STATUS0_BC_LVL; -+ *CC1 = val ? TYPEC_CC_VOLT_RP : TYPEC_CC_VOLT_OPEN; -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 | -+ SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 | -+ SWITCHES0_PDWN1 | SWITCHES0_PDWN2, -+ SWITCHES0_PDWN1 | SWITCHES0_PDWN2 | -+ SWITCHES0_MEAS_CC2); -+ usleep_range(250, 300); -+ -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ val &= STATUS0_BC_LVL; -+ *CC2 = val ? TYPEC_CC_VOLT_RP : TYPEC_CC_VOLT_OPEN; -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2, -+ store); -+ } else { -+ regmap_read(chip->regmap, FUSB_REG_SWITCHES0, &store); -+ val = store; -+ val &= ~(SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 | -+ SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2); -+ if (chip->cc_state & CC_STATE_TOGSS_CC1) { -+ val |= SWITCHES0_MEAS_CC1 | SWITCHES0_PU_EN1; -+ } else { -+ val |= SWITCHES0_MEAS_CC2 | SWITCHES0_PU_EN2; -+ } -+ regmap_write(chip->regmap, FUSB_REG_SWITCHES0, val); -+ -+ regmap_write(chip->regmap, FUSB_REG_MEASURE, chip->cc_meas_high); -+ usleep_range(250, 300); -+ -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ if (val & STATUS0_COMP) { -+ int retry = 3; -+ int comp_times = 0; -+ -+ while (retry--) { -+ regmap_write(chip->regmap, FUSB_REG_MEASURE, chip->cc_meas_high); -+ usleep_range(250, 300); -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ if (val & STATUS0_COMP) { -+ comp_times++; -+ if (comp_times == 3) { -+ *CC_MEASURE = TYPEC_CC_VOLT_OPEN; -+ regmap_write(chip->regmap, FUSB_REG_SWITCHES0, store); -+ } -+ } -+ } -+ } else { -+ regmap_write(chip->regmap, FUSB_REG_MEASURE, chip->cc_meas_low); -+ regmap_read(chip->regmap, FUSB_REG_MEASURE, &val); -+ usleep_range(250, 300); -+ -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ -+ if (val & STATUS0_COMP) -+ *CC_MEASURE = TYPEC_CC_VOLT_RD; -+ else -+ *CC_MEASURE = TYPEC_CC_VOLT_RA; -+ } -+ regmap_write(chip->regmap, FUSB_REG_SWITCHES0, store); -+ regmap_write(chip->regmap, FUSB_REG_MEASURE, -+ chip->cc_meas_high); -+ } -+ -+ return 0; -+} -+ -+static void tcpm_set_cc_pull_mode(struct fusb30x_chip *chip, enum CC_MODE mode) -+{ -+ u8 val; -+ -+ switch (mode) { -+ case CC_PULL_UP: -+ if (chip->cc_polarity == TYPEC_POLARITY_CC1) -+ val = SWITCHES0_PU_EN1; -+ else -+ val = SWITCHES0_PU_EN2; -+ break; -+ case CC_PULL_DOWN: -+ val = SWITCHES0_PDWN1 | SWITCHES0_PDWN2; -+ break; -+ default: -+ val = 0; -+ break; -+ } -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 | -+ SWITCHES0_PDWN1 | SWITCHES0_PDWN2, -+ val); -+ -+ if (chip->cc_meas_high && mode == CC_PULL_UP) -+ regmap_write(chip->regmap, FUSB_REG_MEASURE, -+ chip->cc_meas_high); -+} -+ -+static int tcpm_set_cc(struct fusb30x_chip *chip, enum role_mode mode) -+{ -+ switch (mode) { -+ case ROLE_MODE_DFP: -+ tcpm_set_cc_pull_mode(chip, CC_PULL_UP); -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2, -+ CONTROL2_MODE | CONTROL2_TOG_RD_ONLY, -+ CONTROL2_MODE_DFP | CONTROL2_TOG_RD_ONLY); -+ break; -+ case ROLE_MODE_UFP: -+ tcpm_set_cc_pull_mode(chip, CC_PULL_UP); -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2, -+ CONTROL2_MODE | CONTROL2_TOG_RD_ONLY, -+ CONTROL2_MODE_UFP); -+ break; -+ case ROLE_MODE_DRP: -+ tcpm_set_cc_pull_mode(chip, CC_PULL_NONE); -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2, -+ CONTROL2_MODE | CONTROL2_TOG_RD_ONLY, -+ CONTROL2_MODE_DRP | CONTROL2_TOG_RD_ONLY); -+ break; -+ default: -+ dev_err(chip->dev, "%s: Unsupport cc mode %d\n", -+ __func__, mode); -+ return -EINVAL; -+ break; -+ } -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2, CONTROL2_TOGGLE, -+ CONTROL2_TOGGLE); -+ -+ return 0; -+} -+ -+static int tcpm_set_rx_enable(struct fusb30x_chip *chip, int enable) -+{ -+ u8 val = 0; -+ -+ if (enable) { -+ if (chip->cc_polarity == TYPEC_POLARITY_CC1) -+ val |= SWITCHES0_MEAS_CC1; -+ else -+ val |= SWITCHES0_MEAS_CC2; -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2, -+ val); -+ fusb302_flush_rx_fifo(chip); -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1, -+ SWITCHES1_AUTO_CRC, SWITCHES1_AUTO_CRC); -+ } else { -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2, -+ 0); -+ regmap_update_bits(chip->regmap, -+ FUSB_REG_SWITCHES1, SWITCHES1_AUTO_CRC, 0); -+ } -+ -+ return 0; -+} -+ -+static int tcpm_set_msg_header(struct fusb30x_chip *chip) -+{ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1, -+ SWITCHES1_POWERROLE | SWITCHES1_DATAROLE, -+ (chip->notify.power_role << 7) | -+ (chip->notify.data_role << 4)); -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1, -+ SWITCHES1_SPECREV, 2 << 5); -+ return 0; -+} -+ -+static int tcpm_set_polarity(struct fusb30x_chip *chip, -+ enum typec_cc_polarity polarity) -+{ -+ u8 val = 0; -+ -+ if (chip->vconn_enabled) { -+ if (polarity) -+ val |= SWITCHES0_VCONN_CC1; -+ else -+ val |= SWITCHES0_VCONN_CC2; -+ } -+ -+ if (chip->cc_state & CC_STATE_TOGSS_IS_UFP) { -+ if (polarity == TYPEC_POLARITY_CC1) -+ val |= SWITCHES0_MEAS_CC1; -+ else -+ val |= SWITCHES0_MEAS_CC2; -+ } else { -+ if (polarity == TYPEC_POLARITY_CC1) -+ val |= SWITCHES0_MEAS_CC1 | SWITCHES0_PU_EN1; -+ else -+ val |= SWITCHES0_MEAS_CC2 | SWITCHES0_PU_EN2; -+ } -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2 | -+ SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 | -+ SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2, -+ val); -+ -+ val = 0; -+ if (polarity == TYPEC_POLARITY_CC1) -+ val |= SWITCHES1_TXCC1; -+ else -+ val |= SWITCHES1_TXCC2; -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1, -+ SWITCHES1_TXCC1 | SWITCHES1_TXCC2, -+ val); -+ -+ chip->cc_polarity = polarity; -+ -+ return 0; -+} -+ -+static int tcpm_set_vconn(struct fusb30x_chip *chip, int enable) -+{ -+ u8 val = 0; -+ -+ if (enable) { -+ if (chip->cc_polarity == TYPEC_POLARITY_CC1) -+ val = SWITCHES0_VCONN_CC2; -+ else -+ val = SWITCHES0_VCONN_CC1; -+ } -+ regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, -+ SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2, -+ val); -+ chip->vconn_enabled = (bool)enable; -+ return 0; -+} -+ -+static void fusb302_pd_reset(struct fusb30x_chip *chip) -+{ -+ regmap_write(chip->regmap, FUSB_REG_RESET, RESET_PD_RESET); -+ regmap_reinit_cache(chip->regmap, &fusb302_regmap_config); -+} -+ -+static void tcpm_select_rp_value(struct fusb30x_chip *chip, u32 rp) -+{ -+ u32 control0_reg; -+ -+ regmap_read(chip->regmap, FUSB_REG_CONTROL0, &control0_reg); -+ -+ control0_reg &= ~CONTROL0_HOST_CUR; -+ /* -+ * according to the host current, the compare value is different -+ * Fusb302 datasheet Table 3 -+ */ -+ switch (rp) { -+ /* -+ * host pull up current is 80ua , high voltage is 1.596v, -+ * low is 0.21v -+ */ -+ case TYPEC_RP_USB: -+ chip->cc_meas_high = 0x26; -+ chip->cc_meas_low = 0x5; -+ control0_reg |= CONTROL0_HOST_CUR_USB; -+ break; -+ /* -+ * host pull up current is 330ua , high voltage is 2.604v, -+ * low is 0.798v -+ */ -+ case TYPEC_RP_3A0: -+ chip->cc_meas_high = 0x3e; -+ chip->cc_meas_low = 0x13; -+ control0_reg |= CONTROL0_HOST_CUR_3A0; -+ break; -+ /* -+ * host pull up current is 180ua , high voltage is 1.596v, -+ * low is 0.42v -+ */ -+ case TYPEC_RP_1A5: -+ default: -+ chip->cc_meas_high = 0x26; -+ chip->cc_meas_low = 0xa; -+ control0_reg |= CONTROL0_HOST_CUR_1A5; -+ break; -+ } -+ -+ regmap_write(chip->regmap, FUSB_REG_CONTROL0, control0_reg); -+} -+ -+static int tcpm_check_vbus(struct fusb30x_chip *chip) -+{ -+ u32 val; -+ -+ /* Read status register */ -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ -+ return (val & STATUS0_VBUSOK) ? 1 : 0; -+} -+ -+static void tcpm_init(struct fusb30x_chip *chip) -+{ -+ u8 val; -+ u32 tmp; -+ -+ regmap_read(chip->regmap, FUSB_REG_DEVICEID, &tmp); -+ chip->chip_id = (u8)tmp; -+ platform_set_vbus_lvl_enable(chip, 0, 0); -+ chip->notify.is_cc_connected = false; -+ chip->cc_state = 0; -+ -+ /* restore default settings */ -+ regmap_update_bits(chip->regmap, FUSB_REG_RESET, RESET_SW_RESET, -+ RESET_SW_RESET); -+ fusb302_pd_reset(chip); -+ /* set auto_retry and number of retries */ -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3, -+ CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES, -+ CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES), -+ -+ /* set interrupts */ -+ val = 0xff; -+ val &= ~(MASK_M_COLLISION | MASK_M_ALERT | MASK_M_VBUSOK); -+ regmap_write(chip->regmap, FUSB_REG_MASK, val); -+ -+ val = 0xff; -+ val &= ~(MASKA_M_RETRYFAIL | MASKA_M_HARDSENT | MASKA_M_TXSENT | -+ MASKA_M_HARDRST | MASKA_M_TOGDONE); -+ regmap_write(chip->regmap, FUSB_REG_MASKA, val); -+ -+ val = ~MASKB_M_GCRCSEND; -+ regmap_write(chip->regmap, FUSB_REG_MASKB, val); -+ -+ tcpm_select_rp_value(chip, TYPEC_RP_1A5); -+ /* Interrupts Enable */ -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL0, CONTROL0_INT_MASK, -+ ~CONTROL0_INT_MASK); -+ -+ tcpm_set_vconn(chip, 0); -+ -+ regmap_write(chip->regmap, FUSB_REG_POWER, 0xf); -+} -+ -+static void pd_execute_hard_reset(struct fusb30x_chip *chip) -+{ -+ chip->msg_id = 0; -+ chip->vdm_state = VDM_STATE_DISCOVERY_ID; -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_transition_default); -+ else -+ set_state(chip, policy_snk_transition_default); -+} -+ -+static void tcpc_alert(struct fusb30x_chip *chip, u32 *evt) -+{ -+ int interrupt, interrupta, interruptb; -+ u32 val; -+ static int retry; -+ -+ regmap_read(chip->regmap, FUSB_REG_INTERRUPT, &interrupt); -+ regmap_read(chip->regmap, FUSB_REG_INTERRUPTA, &interrupta); -+ regmap_read(chip->regmap, FUSB_REG_INTERRUPTB, &interruptb); -+ -+ if ((interrupt & INTERRUPT_COMP_CHNG) && -+ (!(chip->cc_state & CC_STATE_TOGSS_IS_UFP))) { -+ regmap_read(chip->regmap, FUSB_REG_STATUS0, &val); -+ if (val & STATUS0_COMP) -+ *evt |= EVENT_CC; -+ } -+ -+ if (interrupt & INTERRUPT_VBUSOK) { -+ if (chip->notify.is_cc_connected) -+ *evt |= EVENT_CC; -+ } -+ -+ if (interrupta & INTERRUPTA_TOGDONE) { -+ *evt |= EVENT_CC; -+ regmap_read(chip->regmap, FUSB_REG_STATUS1A, &val); -+ chip->cc_state = ((u8)val >> 3) & 0x07; -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2, -+ CONTROL2_TOGGLE, -+ 0); -+ } -+ -+ if (interrupta & INTERRUPTA_TXSENT) { -+ *evt |= EVENT_TX; -+ chip->tx_state = tx_success; -+ } -+ -+ if (interruptb & INTERRUPTB_GCRCSENT) -+ *evt |= EVENT_RX; -+ -+ if (interrupta & INTERRUPTA_HARDRST) { -+ fusb302_pd_reset(chip); -+ pd_execute_hard_reset(chip); -+ *evt |= EVENT_REC_RESET; -+ } -+ -+ if (interrupta & INTERRUPTA_RETRYFAIL) { -+ *evt |= EVENT_TX; -+ chip->tx_state = tx_failed; -+ } -+ -+ if (interrupta & INTERRUPTA_HARDSENT) { -+ /* -+ * The fusb PD should be reset once to sync adapter PD -+ * signal after fusb sent hard reset cmd.This is not PD -+ * device if reset failed. -+ */ -+ if (!retry) { -+ retry = 1; -+ fusb302_pd_reset(chip); -+ pd_execute_hard_reset(chip); -+ } else { -+ retry = 0; -+ chip->tx_state = tx_success; -+ chip->timer_state = T_DISABLED; -+ *evt |= EVENT_TX; -+ } -+ } -+} -+ -+static void mux_alert(struct fusb30x_chip *chip, u32 *evt) -+{ -+ if (!chip->timer_mux) { -+ *evt |= EVENT_TIMER_MUX; -+ chip->timer_mux = T_DISABLED; -+ } -+ -+ if (!chip->timer_state) { -+ *evt |= EVENT_TIMER_STATE; -+ chip->timer_state = T_DISABLED; -+ } -+ -+ if (chip->work_continue) { -+ *evt |= chip->work_continue; -+ chip->work_continue = 0; -+ } -+} -+ -+static void set_state_unattached(struct fusb30x_chip *chip) -+{ -+ dev_info(chip->dev, "connection has disconnected\n"); -+ tcpm_init(chip); -+ tcpm_set_rx_enable(chip, 0); -+ set_state(chip, unattached); -+ tcpm_set_cc(chip, chip->role); -+ -+ /* claer notify_info */ -+ memset(&chip->notify, 0, sizeof(struct notify_info)); -+ platform_fusb_notify(chip); -+ -+ if (chip->gpio_discharge) -+ gpiod_set_value(chip->gpio_discharge, 1); -+ msleep(100); -+ if (chip->gpio_discharge) -+ gpiod_set_value(chip->gpio_discharge, 0); -+ -+ regmap_update_bits(chip->regmap, FUSB_REG_MASK, -+ MASK_M_COMP_CHNG, MASK_M_COMP_CHNG); -+ chip->try_role_complete = false; -+} -+ -+static void set_mesg(struct fusb30x_chip *chip, int cmd, int is_DMT) -+{ -+ int i; -+ struct PD_CAP_INFO *pd_cap_info = &chip->pd_cap_info; -+ -+ chip->send_head = ((chip->msg_id & 0x7) << 9) | -+ ((chip->notify.power_role & 0x1) << 8) | -+ (1 << 6) | -+ ((chip->notify.data_role & 0x1) << 5); -+ -+ if (is_DMT) { -+ switch (cmd) { -+ case DMT_SOURCECAPABILITIES: -+ chip->send_head |= ((chip->n_caps_used & 0x3) << 12) | (cmd & 0xf); -+ -+ for (i = 0; i < chip->n_caps_used; i++) { -+ chip->send_load[i] = (pd_cap_info->supply_type << 30) | -+ (pd_cap_info->dual_role_power << 29) | -+ (pd_cap_info->usb_suspend_support << 28) | -+ (pd_cap_info->externally_powered << 27) | -+ (pd_cap_info->usb_communications_cap << 26) | -+ (pd_cap_info->data_role_swap << 25) | -+ (pd_cap_info->peak_current << 20) | -+ (chip->source_power_supply[i] << 10) | -+ (chip->source_max_current[i]); -+ } -+ break; -+ case DMT_REQUEST: -+ chip->send_head |= ((1 << 12) | (cmd & 0xf)); -+ /* send request with FVRDO */ -+ chip->send_load[0] = (chip->pos_power << 28) | -+ (0 << 27) | -+ (1 << 26) | -+ (0 << 25) | -+ (0 << 24); -+ -+ switch (CAP_POWER_TYPE(chip->rec_load[chip->pos_power - 1])) { -+ case 0: -+ /* Fixed Supply */ -+ chip->send_load[0] |= ((CAP_FPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff); -+ chip->send_load[0] |= (CAP_FPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff); -+ break; -+ case 1: -+ /* Battery */ -+ chip->send_load[0] |= ((CAP_VPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff); -+ chip->send_load[0] |= (CAP_VPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff); -+ break; -+ default: -+ /* not meet battery caps */ -+ break; -+ } -+ break; -+ case DMT_SINKCAPABILITIES: -+ break; -+ case DMT_VENDERDEFINED: -+ break; -+ default: -+ break; -+ } -+ } else { -+ chip->send_head |= (cmd & 0xf); -+ } -+} -+ -+/* -+ * This algorithm defaults to choosing higher pin config over lower ones in -+ * order to prefer multi-function if desired. -+ * -+ * NAME | SIGNALING | OUTPUT TYPE | MULTI-FUNCTION | PIN CONFIG -+ * ------------------------------------------------------------- -+ * A | USB G2 | ? | no | 00_0001 -+ * B | USB G2 | ? | yes | 00_0010 -+ * C | DP | CONVERTED | no | 00_0100 -+ * D | PD | CONVERTED | yes | 00_1000 -+ * E | DP | DP | no | 01_0000 -+ * F | PD | DP | yes | 10_0000 -+ * -+ * if UFP has NOT asserted multi-function preferred code masks away B/D/F -+ * leaving only A/C/E. For single-output dongles that should leave only one -+ * possible pin config depending on whether its a converter DP->(VGA|HDMI) or DP -+ * output. If UFP is a USB-C receptacle it may assert C/D/E/F. The DFP USB-C -+ * receptacle must always choose C/D in those cases. -+ */ -+static int pd_dfp_dp_get_pin_assignment(struct fusb30x_chip *chip, -+ uint32_t caps, uint32_t status) -+{ -+ uint32_t pin_caps; -+ -+ /* revisit with DFP that can be a sink */ -+ pin_caps = PD_DP_PIN_CAPS(caps); -+ -+ /* if don't want multi-function then ignore those pin configs */ -+ if (!PD_VDO_DPSTS_MF_PREF(status)) -+ pin_caps &= ~MODE_DP_PIN_MF_MASK; -+ -+ /* revisit if DFP drives USB Gen 2 signals */ -+ if (PD_DP_SIGNAL_GEN2(caps)) -+ pin_caps &= ~MODE_DP_PIN_DP_MASK; -+ else -+ pin_caps &= ~MODE_DP_PIN_BR2_MASK; -+ -+ /* if C/D present they have precedence over E/F for USB-C->USB-C */ -+ if (pin_caps & (MODE_DP_PIN_C | MODE_DP_PIN_D)) -+ pin_caps &= ~(MODE_DP_PIN_E | MODE_DP_PIN_F); -+ -+ /* returns undefined for zero */ -+ if (!pin_caps) -+ return 0; -+ -+ /* choosing higher pin config over lower ones */ -+ return 1 << (31 - __builtin_clz(pin_caps)); -+} -+ -+static void set_vdm_mesg(struct fusb30x_chip *chip, int cmd, int type, int mode) -+{ -+ chip->send_head = (chip->msg_id & 0x7) << 9; -+ chip->send_head |= (chip->notify.power_role & 0x1) << 8; -+ -+ chip->send_head = ((chip->msg_id & 0x7) << 9) | -+ ((chip->notify.power_role & 0x1) << 8) | -+ (1 << 6) | -+ ((chip->notify.data_role & 0x1) << 5) | -+ (DMT_VENDERDEFINED & 0xf); -+ -+ chip->send_load[0] = (1 << 15) | -+ (0 << 13) | -+ (type << 6) | -+ (cmd); -+ -+ switch (cmd) { -+ case VDM_DISCOVERY_ID: -+ case VDM_DISCOVERY_SVIDS: -+ case VDM_ATTENTION: -+ chip->send_load[0] |= (0xff00 << 16); -+ chip->send_head |= (1 << 12); -+ break; -+ case VDM_DISCOVERY_MODES: -+ chip->send_load[0] |= -+ (chip->vdm_svid[chip->val_tmp >> 1] << 16); -+ chip->send_head |= (1 << 12); -+ break; -+ case VDM_ENTER_MODE: -+ chip->send_head |= (1 << 12); -+ chip->send_load[0] |= (mode << 8) | (0xff01 << 16); -+ break; -+ case VDM_EXIT_MODE: -+ chip->send_head |= (1 << 12); -+ chip->send_load[0] |= (0x0f << 8) | (0xff01 << 16); -+ break; -+ case VDM_DP_STATUS_UPDATE: -+ chip->send_head |= (2 << 12); -+ chip->send_load[0] |= (1 << 8) | (0xff01 << 16); -+ chip->send_load[1] = 5; -+ break; -+ case VDM_DP_CONFIG: -+ chip->send_head |= (2 << 12); -+ chip->send_load[0] |= (1 << 8) | (0xff01 << 16); -+ -+ chip->notify.pin_assignment_def = -+ pd_dfp_dp_get_pin_assignment(chip, chip->notify.dp_caps, -+ chip->notify.dp_status); -+ -+ chip->send_load[1] = (chip->notify.pin_assignment_def << 8) | -+ (1 << 2) | 2; -+ dev_dbg(chip->dev, "DisplayPort Configurations: 0x%08x\n", -+ chip->send_load[1]); -+ break; -+ default: -+ break; -+ } -+} -+ -+static enum tx_state policy_send_hardrst(struct fusb30x_chip *chip, u32 evt) -+{ -+ switch (chip->tx_state) { -+ case 0: -+ regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3, -+ CONTROL3_SEND_HARDRESET, -+ CONTROL3_SEND_HARDRESET); -+ chip->tx_state = tx_busy; -+ chip->timer_state = T_BMC_TIMEOUT; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ break; -+ default: -+ if (evt & EVENT_TIMER_STATE) -+ chip->tx_state = tx_success; -+ break; -+ } -+ return chip->tx_state; -+} -+ -+static enum tx_state policy_send_data(struct fusb30x_chip *chip) -+{ -+ u8 senddata[40]; -+ int pos = 0; -+ u8 len; -+ -+ switch (chip->tx_state) { -+ case 0: -+ senddata[pos++] = FUSB_TKN_SYNC1; -+ senddata[pos++] = FUSB_TKN_SYNC1; -+ senddata[pos++] = FUSB_TKN_SYNC1; -+ senddata[pos++] = FUSB_TKN_SYNC2; -+ -+ len = PD_HEADER_CNT(chip->send_head) << 2; -+ senddata[pos++] = FUSB_TKN_PACKSYM | ((len + 2) & 0x1f); -+ -+ senddata[pos++] = chip->send_head & 0xff; -+ senddata[pos++] = (chip->send_head >> 8) & 0xff; -+ -+ memcpy(&senddata[pos], chip->send_load, len); -+ pos += len; -+ -+ senddata[pos++] = FUSB_TKN_JAMCRC; -+ senddata[pos++] = FUSB_TKN_EOP; -+ senddata[pos++] = FUSB_TKN_TXOFF; -+ senddata[pos++] = FUSB_TKN_TXON; -+ -+ regmap_raw_write(chip->regmap, FUSB_REG_FIFO, senddata, pos); -+ chip->tx_state = tx_busy; -+ break; -+ -+ default: -+ /* wait Tx result */ -+ break; -+ } -+ -+ return chip->tx_state; -+} -+ -+static void process_vdm_msg(struct fusb30x_chip *chip) -+{ -+ u32 vdm_header = chip->rec_load[0]; -+ int i; -+ u32 tmp; -+ -+ /* can't procee unstructed vdm msg */ -+ if (!GET_VDMHEAD_STRUCT_TYPE(vdm_header)) { -+ dev_warn(chip->dev, "unknown unstructed vdm message\n"); -+ return; -+ } -+ -+ switch (GET_VDMHEAD_CMD_TYPE(vdm_header)) { -+ case VDM_TYPE_INIT: -+ switch (GET_VDMHEAD_CMD(vdm_header)) { -+ case VDM_ATTENTION: -+ chip->notify.dp_status = GET_DP_STATUS(chip->rec_load[1]); -+ dev_info(chip->dev, "attention, dp_status %x\n", -+ chip->rec_load[1]); -+ chip->notify.attention = true; -+ platform_fusb_notify(chip); -+ break; -+ default: -+ dev_warn(chip->dev, "rec unknown init vdm msg\n"); -+ break; -+ } -+ break; -+ case VDM_TYPE_ACK: -+ switch (GET_VDMHEAD_CMD(vdm_header)) { -+ case VDM_DISCOVERY_ID: -+ chip->vdm_id = chip->rec_load[1]; -+ break; -+ case VDM_DISCOVERY_SVIDS: -+ for (i = 0; i < 6; i++) { -+ tmp = (chip->rec_load[i + 1] >> 16) & -+ 0x0000ffff; -+ if (tmp) { -+ chip->vdm_svid[i * 2] = tmp; -+ chip->vdm_svid_num++; -+ } else { -+ break; -+ } -+ -+ tmp = (chip->rec_load[i + 1] & 0x0000ffff); -+ if (tmp) { -+ chip->vdm_svid[i * 2 + 1] = tmp; -+ chip->vdm_svid_num++; -+ } else { -+ break; -+ } -+ } -+ break; -+ case VDM_DISCOVERY_MODES: -+ /* indicate there are some vdo modes */ -+ if (PD_HEADER_CNT(chip->rec_head) > 1) { -+ /* -+ * store mode config, -+ * enter first mode default -+ */ -+ tmp = chip->rec_load[1]; -+ -+ if ((!((tmp >> 8) & 0x3f)) && -+ (!((tmp >> 16) & 0x3f))) { -+ chip->val_tmp |= 1; -+ break; -+ } -+ chip->notify.dp_caps = chip->rec_load[1]; -+ chip->notify.pin_assignment_def = 0; -+ chip->notify.pin_assignment_support = -+ PD_DP_PIN_CAPS(tmp); -+ chip->val_tmp |= 1; -+ dev_dbg(chip->dev, -+ "DisplayPort Capabilities: 0x%08x\n", -+ chip->rec_load[1]); -+ } -+ break; -+ case VDM_ENTER_MODE: -+ chip->val_tmp = 1; -+ break; -+ case VDM_DP_STATUS_UPDATE: -+ chip->notify.dp_status = GET_DP_STATUS(chip->rec_load[1]); -+ dev_dbg(chip->dev, "DisplayPort Status: 0x%08x\n", -+ chip->rec_load[1]); -+ chip->val_tmp = 1; -+ break; -+ case VDM_DP_CONFIG: -+ chip->val_tmp = 1; -+ dev_info(chip->dev, -+ "DP config successful, pin_assignment 0x%x\n", -+ chip->notify.pin_assignment_def); -+ chip->notify.is_enter_mode = true; -+ break; -+ default: -+ break; -+ } -+ break; -+ case VDM_TYPE_NACK: -+ dev_warn(chip->dev, "REC NACK for 0x%x\n", -+ GET_VDMHEAD_CMD(vdm_header)); -+ /* disable vdm */ -+ chip->vdm_state = VDM_STATE_ERR; -+ break; -+ } -+} -+ -+static int vdm_send_discoveryid(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_DISCOVERY_ID, VDM_TYPE_INIT, 0); -+ chip->vdm_id = 0; -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, "VDM_DISCOVERY_ID send failed\n"); -+ /* disable auto_vdm_machine */ -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->vdm_id) { -+ chip->vdm_send_state = 0; -+ return 0; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "VDM_DISCOVERY_ID time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ return -EINPROGRESS; -+} -+ -+static int vdm_send_discoverysvid(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_DISCOVERY_SVIDS, VDM_TYPE_INIT, 0); -+ memset(chip->vdm_svid, 0, sizeof(chip->vdm_svid)); -+ chip->vdm_svid_num = 0; -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS send failed\n"); -+ /* disable auto_vdm_machine */ -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->vdm_svid_num) { -+ chip->vdm_send_state = 0; -+ return 0; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ return -EINPROGRESS; -+} -+ -+static int vdm_send_discoverymodes(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ if ((chip->val_tmp >> 1) != chip->vdm_svid_num) { -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_DISCOVERY_MODES, -+ VDM_TYPE_INIT, 0); -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, -+ "VDM_DISCOVERY_MODES send failed\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->val_tmp & 1) { -+ chip->val_tmp &= 0xfe; -+ chip->val_tmp += 2; -+ chip->vdm_send_state = 0; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, -+ "VDM_DISCOVERY_MODES time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ } else { -+ chip->val_tmp = 0; -+ return 0; -+ } -+ -+ return -EINPROGRESS; -+} -+ -+static int vdm_send_entermode(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_ENTER_MODE, VDM_TYPE_INIT, 1); -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ chip->notify.is_enter_mode = false; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, "VDM_ENTER_MODE send failed\n"); -+ /* disable auto_vdm_machine */ -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->val_tmp) { -+ chip->val_tmp = 0; -+ chip->vdm_send_state = 0; -+ return 0; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "VDM_ENTER_MODE time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ return -EINPROGRESS; -+} -+ -+static int vdm_send_getdpstatus(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_DP_STATUS_UPDATE, VDM_TYPE_INIT, 1); -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, -+ "VDM_DP_STATUS_UPDATE send failed\n"); -+ /* disable auto_vdm_machine */ -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->val_tmp) { -+ chip->val_tmp = 0; -+ chip->vdm_send_state = 0; -+ return 0; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "VDM_DP_STATUS_UPDATE time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ return -EINPROGRESS; -+} -+ -+static int vdm_send_dpconfig(struct fusb30x_chip *chip, u32 evt) -+{ -+ int tmp; -+ -+ switch (chip->vdm_send_state) { -+ case 0: -+ set_vdm_mesg(chip, VDM_DP_CONFIG, VDM_TYPE_INIT, 0); -+ chip->tx_state = 0; -+ chip->vdm_send_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->vdm_send_state++; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ dev_warn(chip->dev, "vdm_send_dpconfig send failed\n"); -+ /* disable auto_vdm_machine */ -+ chip->vdm_state = VDM_STATE_ERR; -+ return -EPIPE; -+ } -+ -+ if (chip->vdm_send_state != 2) -+ break; -+ default: -+ if (chip->val_tmp) { -+ chip->val_tmp = 0; -+ chip->vdm_send_state = 0; -+ return 0; -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "vdm_send_dpconfig time out\n"); -+ chip->vdm_state = VDM_STATE_ERR; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ return -ETIMEDOUT; -+ } -+ break; -+ } -+ return -EINPROGRESS; -+} -+ -+/* without break if success */ -+#define AUTO_VDM_HANDLE(func, chip, evt, conditions) \ -+do { \ -+ conditions = func(chip, evt); \ -+ if (!conditions) { \ -+ chip->vdm_state++; \ -+ chip->work_continue |= EVENT_WORK_CONTINUE; \ -+ } else { \ -+ if (conditions != -EINPROGRESS) \ -+ chip->vdm_state = VDM_STATE_ERR; \ -+ } \ -+} while (0) -+ -+static void auto_vdm_machine(struct fusb30x_chip *chip, u32 evt) -+{ -+ int conditions; -+ -+ switch (chip->vdm_state) { -+ case VDM_STATE_DISCOVERY_ID: -+ AUTO_VDM_HANDLE(vdm_send_discoveryid, chip, evt, conditions); -+ break; -+ case VDM_STATE_DISCOVERY_SVID: -+ AUTO_VDM_HANDLE(vdm_send_discoverysvid, chip, evt, conditions); -+ break; -+ case VDM_STATE_DISCOVERY_MODES: -+ AUTO_VDM_HANDLE(vdm_send_discoverymodes, chip, evt, conditions); -+ break; -+ case VDM_STATE_ENTER_MODE: -+ AUTO_VDM_HANDLE(vdm_send_entermode, chip, evt, conditions); -+ break; -+ case VDM_STATE_UPDATE_STATUS: -+ AUTO_VDM_HANDLE(vdm_send_getdpstatus, chip, evt, conditions); -+ break; -+ case VDM_STATE_DP_CONFIG: -+ AUTO_VDM_HANDLE(vdm_send_dpconfig, chip, evt, conditions); -+ break; -+ case VDM_STATE_NOTIFY: -+ platform_fusb_notify(chip); -+ chip->vdm_state = VDM_STATE_READY; -+ break; -+ default: -+ break; -+ } -+} -+ -+static void fusb_state_disabled(struct fusb30x_chip *chip, u32 evt) -+{ -+ /* Do nothing */ -+} -+ -+static void fusb_state_unattached(struct fusb30x_chip *chip, u32 evt) -+{ -+ chip->notify.is_cc_connected = false; -+ chip->is_pd_support = false; -+ -+ if ((evt & EVENT_CC) && chip->cc_state) { -+ if (chip->cc_state & CC_STATE_TOGSS_IS_UFP) -+ set_state(chip, attach_wait_sink); -+ else -+ set_state(chip, attach_wait_source); -+ -+ chip->vbus_begin = tcpm_check_vbus(chip); -+ -+ tcpm_set_polarity(chip, (chip->cc_state & CC_STATE_TOGSS_CC1) ? -+ TYPEC_POLARITY_CC1 : -+ TYPEC_POLARITY_CC2); -+ tcpm_get_cc(chip, &chip->cc1, &chip->cc2); -+ chip->debounce_cnt = 0; -+ chip->timer_mux = 2; -+ fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux); -+ } -+} -+ -+static void fusb_state_try_attach_set(struct fusb30x_chip *chip, -+ enum role_mode mode) -+{ -+ if (mode == ROLE_MODE_NONE || mode == ROLE_MODE_DRP || -+ mode == ROLE_MODE_ASS) -+ return; -+ -+ tcpm_init(chip); -+ tcpm_set_cc(chip, (mode == ROLE_MODE_DFP) ? -+ ROLE_MODE_DFP : ROLE_MODE_UFP); -+ chip->timer_mux = T_PD_TRY_DRP; -+ fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux); -+ set_state(chip, (mode == ROLE_MODE_DFP) ? -+ attach_try_src : attach_try_snk); -+} -+ -+static void fusb_state_attach_wait_sink(struct fusb30x_chip *chip, u32 evt) -+{ -+ int cc1, cc2; -+ -+ if (evt & EVENT_TIMER_MUX) { -+ if (tcpm_check_vbus(chip)) { -+ chip->timer_mux = T_DISABLED; -+ if (chip->role == ROLE_MODE_DRP && -+ chip->try_role == ROLE_MODE_DFP && -+ !chip->try_role_complete) { -+ fusb_state_try_attach_set(chip, ROLE_MODE_DFP); -+ return; -+ } else if (chip->try_role_complete) { -+ chip->timer_mux = T_PD_SOURCE_ON; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ set_state(chip, attached_sink); -+ return; -+ } -+ } -+ -+ tcpm_get_cc(chip, &cc1, &cc2); -+ -+ if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) { -+ chip->debounce_cnt++; -+ } else { -+ chip->cc1 = cc1; -+ chip->cc2 = cc2; -+ chip->debounce_cnt = 0; -+ } -+ -+ if (chip->debounce_cnt > N_DEBOUNCE_CNT) { -+ chip->timer_mux = T_DISABLED; -+ if ((chip->cc1 == TYPEC_CC_VOLT_RP && -+ chip->cc2 == TYPEC_CC_VOLT_OPEN) || -+ (chip->cc2 == TYPEC_CC_VOLT_RP && -+ chip->cc1 == TYPEC_CC_VOLT_OPEN)) { -+ chip->timer_mux = T_PD_SOURCE_ON; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ set_state(chip, attached_sink); -+ } else { -+ set_state_unattached(chip); -+ } -+ return; -+ } -+ -+ chip->timer_mux = 2; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ } -+} -+ -+static void fusb_state_attach_wait_source(struct fusb30x_chip *chip, u32 evt) -+{ -+ int cc1, cc2; -+ -+ if (evt & EVENT_TIMER_MUX) { -+ tcpm_get_cc(chip, &cc1, &cc2); -+ -+ if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) { -+ chip->debounce_cnt++; -+ } else { -+ chip->cc1 = cc1; -+ chip->cc2 = cc2; -+ chip->debounce_cnt = 0; -+ } -+ -+ if (chip->debounce_cnt > N_DEBOUNCE_CNT) { -+ if (((!chip->cc1) || (!chip->cc2)) && -+ ((chip->cc1 == TYPEC_CC_VOLT_RD) || -+ (chip->cc2 == TYPEC_CC_VOLT_RD))) { -+ if (chip->role == ROLE_MODE_DRP && -+ chip->try_role == ROLE_MODE_UFP && -+ !chip->try_role_complete) -+ fusb_state_try_attach_set(chip, -+ ROLE_MODE_UFP); -+ else -+ set_state(chip, attached_source); -+ } else { -+ set_state_unattached(chip); -+ } -+ return; -+ } -+ -+ chip->timer_mux = 2; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ } -+} -+ -+static void fusb_state_attached_source(struct fusb30x_chip *chip, u32 evt) -+{ -+ platform_set_vbus_lvl_enable(chip, 1, 0); -+ tcpm_set_polarity(chip, (chip->cc_state & CC_STATE_TOGSS_CC1) ? -+ TYPEC_POLARITY_CC1 : TYPEC_POLARITY_CC2); -+ tcpm_set_vconn(chip, 1); -+ -+ chip->notify.is_cc_connected = true; -+ -+ chip->notify.power_role = POWER_ROLE_SOURCE; -+ chip->notify.data_role = DATA_ROLE_DFP; -+ chip->hardrst_count = 0; -+ set_state(chip, policy_src_startup); -+ regmap_update_bits(chip->regmap, FUSB_REG_MASK, MASK_M_COMP_CHNG, 0); -+ dev_info(chip->dev, "CC connected in %s as DFP\n", -+ chip->cc_polarity ? "CC1" : "CC2"); -+} -+ -+static void fusb_state_attached_sink(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (tcpm_check_vbus(chip)) { -+ chip->timer_mux = T_DISABLED; -+ chip->timer_state = T_DISABLED; -+ if (!chip->try_role_complete && -+ chip->try_role == ROLE_MODE_DFP && -+ chip->role == ROLE_MODE_DRP) { -+ fusb_state_try_attach_set(chip, ROLE_MODE_DFP); -+ return; -+ } -+ -+ chip->try_role_complete = true; -+ chip->notify.is_cc_connected = true; -+ chip->notify.power_role = POWER_ROLE_SINK; -+ chip->notify.data_role = DATA_ROLE_UFP; -+ chip->hardrst_count = 0; -+ set_state(chip, policy_snk_startup); -+ dev_info(chip->dev, "CC connected in %s as UFP\n", -+ chip->cc_polarity ? "CC1" : "CC2"); -+ return; -+ } else if (evt & EVENT_TIMER_MUX) { -+ set_state_unattached(chip); -+ return; -+ } -+ -+ chip->timer_state = 2; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+} -+ -+static void fusb_state_try_attach(struct fusb30x_chip *chip, u32 evt, -+ enum role_mode mode) -+{ -+ if ((evt & EVENT_CC) && chip->cc_state) { -+ chip->try_role_complete = true; -+ if (chip->cc_state & CC_STATE_TOGSS_IS_UFP) -+ set_state(chip, (mode == ROLE_MODE_UFP) ? -+ attach_wait_sink : error_recovery); -+ else -+ set_state(chip, (mode == ROLE_MODE_DFP) ? -+ attach_wait_source : error_recovery); -+ -+ tcpm_set_polarity(chip, (chip->cc_state & CC_STATE_TOGSS_CC1) ? -+ TYPEC_POLARITY_CC1 : -+ TYPEC_POLARITY_CC2); -+ tcpm_get_cc(chip, &chip->cc1, &chip->cc2); -+ chip->debounce_cnt = 0; -+ chip->timer_mux = 2; -+ fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux); -+ } else if (evt & EVENT_TIMER_MUX) { -+ if (!chip->try_role_complete) { -+ chip->try_role_complete = true; -+ fusb_state_try_attach_set(chip, -+ (mode == ROLE_MODE_DFP) ? -+ ROLE_MODE_UFP : -+ ROLE_MODE_DFP); -+ } else { -+ set_state(chip, error_recovery); -+ } -+ } -+} -+ -+static void fusb_soft_reset_parameter(struct fusb30x_chip *chip) -+{ -+ chip->caps_counter = 0; -+ chip->msg_id = 0; -+ chip->vdm_state = VDM_STATE_DISCOVERY_ID; -+ chip->vdm_substate = 0; -+ chip->vdm_send_state = 0; -+ chip->val_tmp = 0; -+ chip->pos_power = 0; -+} -+ -+static void fusb_state_src_startup(struct fusb30x_chip *chip, u32 evt) -+{ -+ chip->notify.is_pd_connected = false; -+ fusb_soft_reset_parameter(chip); -+ -+ memset(chip->partner_cap, 0, sizeof(chip->partner_cap)); -+ -+ tcpm_set_msg_header(chip); -+ tcpm_set_polarity(chip, chip->cc_polarity); -+ tcpm_set_rx_enable(chip, 1); -+ -+ set_state(chip, policy_src_send_caps); -+ platform_fusb_notify(chip); -+} -+ -+static void fusb_state_src_discovery(struct fusb30x_chip *chip, u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->caps_counter++; -+ -+ if (chip->caps_counter < N_CAPS_COUNT) { -+ chip->timer_state = T_TYPEC_SEND_SOURCECAP; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state = 1; -+ } else { -+ set_state(chip, disabled); -+ } -+ break; -+ default: -+ if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_src_send_caps); -+ } else if (evt & EVENT_TIMER_MUX) { -+ if (!chip->is_pd_support) -+ set_state(chip, disabled); -+ else if (chip->hardrst_count > N_HARDRESET_COUNT) -+ set_state(chip, error_recovery); -+ else -+ set_state(chip, policy_src_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_send_caps(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, DMT_SOURCECAPABILITIES, DATAMESSAGE); -+ chip->sub_state = 1; -+ chip->tx_state = tx_idle; -+ /* without break */ -+ case 1: -+ tmp = policy_send_data(chip); -+ -+ if (tmp == tx_success) { -+ chip->hardrst_count = 0; -+ chip->caps_counter = 0; -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->timer_mux = T_DISABLED; -+ chip->sub_state++; -+ chip->is_pd_support = true; -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_discovery); -+ break; -+ } -+ -+ if (!(evt & FLAG_EVENT)) -+ break; -+ default: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_DATA_MSG(chip->rec_head, DMT_REQUEST)) { -+ set_state(chip, policy_src_negotiate_cap); -+ } else { -+ set_state(chip, policy_src_send_softrst); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ if (chip->hardrst_count <= N_HARDRESET_COUNT) -+ set_state(chip, policy_src_send_hardrst); -+ else -+ set_state(chip, disabled); -+ } else if (evt & EVENT_TIMER_MUX) { -+ if (!chip->is_pd_support) -+ set_state(chip, disabled); -+ else if (chip->hardrst_count > N_HARDRESET_COUNT) -+ set_state(chip, error_recovery); -+ else -+ set_state(chip, policy_src_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_negotiate_cap(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ /* base on evb1 */ -+ tmp = (chip->rec_load[0] >> 28) & 0x07; -+ if (tmp > chip->n_caps_used) -+ set_state(chip, policy_src_cap_response); -+ else -+ set_state(chip, policy_src_transition_supply); -+} -+ -+static void fusb_state_src_transition_supply(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->timer_state = T_SRC_TRANSITION; -+ chip->sub_state++; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_softrst); -+ } -+ break; -+ case 2: -+ if (evt & EVENT_TIMER_STATE) { -+ chip->notify.is_pd_connected = true; -+ platform_set_vbus_lvl_enable(chip, 1, 0); -+ set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ } -+ break; -+ default: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ dev_info(chip->dev, -+ "PD connected as DFP, supporting 5V\n"); -+ set_state(chip, policy_src_ready); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_softrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_cap_response(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_REJECT, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ default: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ if (chip->notify.is_pd_connected) { -+ dev_info(chip->dev, -+ "PD connected as DFP, supporting 5V\n"); -+ set_state(chip, policy_src_ready); -+ } else { -+ set_state(chip, policy_src_send_hardrst); -+ } -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_softrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_transition_default(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->notify.is_pd_connected = false; -+ platform_set_vbus_lvl_enable(chip, 0, 0); -+ if (chip->notify.data_role) -+ regmap_update_bits(chip->regmap, -+ FUSB_REG_SWITCHES1, -+ SWITCHES1_DATAROLE, -+ SWITCHES1_DATAROLE); -+ else -+ regmap_update_bits(chip->regmap, -+ FUSB_REG_SWITCHES1, -+ SWITCHES1_DATAROLE, -+ 0); -+ -+ chip->timer_state = T_SRC_RECOVER; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ break; -+ default: -+ if (evt & EVENT_TIMER_STATE) { -+ platform_set_vbus_lvl_enable(chip, 1, 0); -+ chip->timer_mux = T_NO_RESPONSE; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ set_state(chip, policy_src_startup); -+ dev_dbg(chip->dev, "reset over-> src startup\n"); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_vcs_ufp_evaluate_swap(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (chip->vconn_supported) -+ set_state(chip, policy_vcs_ufp_accept); -+ else -+ set_state(chip, policy_vcs_ufp_reject); -+} -+ -+static void fusb_state_swap_msg_process(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_PR_SWAP)) { -+ set_state(chip, policy_src_prs_evaluate); -+ } else if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_VCONN_SWAP)) { -+ if (chip->notify.data_role) -+ set_state(chip, chip->conn_state); -+ else -+ set_state(chip, policy_vcs_ufp_evaluate_swap); -+ } else if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_DR_SWAP)) { -+ if (chip->notify.data_role) -+ set_state(chip, policy_drs_dfp_evaluate); -+ else -+ set_state(chip, policy_drs_ufp_evaluate); -+ } -+ } -+} -+ -+#define VDM_IS_ACTIVE(chip) \ -+ (chip->notify.data_role && chip->vdm_state < VDM_STATE_READY) -+ -+static void fusb_state_src_ready(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_DATA_MSG(chip->rec_head, DMT_VENDERDEFINED)) { -+ process_vdm_msg(chip); -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ chip->timer_state = T_DISABLED; -+ } else if (!VDM_IS_ACTIVE(chip)) { -+ fusb_state_swap_msg_process(chip, evt); -+ } -+ } -+ -+ if (!chip->partner_cap[0]) -+ set_state(chip, policy_src_get_sink_caps); -+ else if (VDM_IS_ACTIVE(chip)) -+ auto_vdm_machine(chip, evt); -+} -+ -+static void fusb_state_prs_evaluate(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (chip->role == ROLE_MODE_DRP) -+ set_state(chip, policy_src_prs_accept); -+ else -+ set_state(chip, policy_src_prs_reject); -+} -+ -+static void fusb_state_send_simple_msg(struct fusb30x_chip *chip, u32 evt, -+ int cmd, int is_DMT, -+ enum connection_state state_success, -+ enum connection_state state_failed) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, cmd, is_DMT); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* fallthrough */ -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) -+ set_state(chip, state_success); -+ else if (tmp == tx_failed) -+ set_state(chip, state_failed); -+ } -+} -+ -+static void fusb_state_prs_reject(struct fusb30x_chip *chip, u32 evt) -+{ -+ fusb_state_send_simple_msg(chip, evt, CMT_REJECT, CONTROLMESSAGE, -+ (chip->notify.power_role) ? -+ policy_src_ready : policy_snk_ready, -+ (chip->notify.power_role) ? -+ policy_src_send_softrst : -+ policy_snk_send_softrst); -+} -+ -+static void fusb_state_prs_accept(struct fusb30x_chip *chip, u32 evt) -+{ -+ fusb_state_send_simple_msg(chip, evt, CMT_ACCEPT, CONTROLMESSAGE, -+ (chip->notify.power_role) ? -+ policy_src_prs_transition_to_off : -+ policy_snk_prs_transition_to_off, -+ (chip->notify.power_role) ? -+ policy_src_send_softrst : -+ policy_snk_send_softrst); -+} -+ -+static void fusb_state_vcs_ufp_accept(struct fusb30x_chip *chip, u32 evt) -+{ -+ fusb_state_send_simple_msg(chip, evt, CMT_ACCEPT, CONTROLMESSAGE, -+ (chip->vconn_enabled) ? -+ policy_vcs_ufp_wait_for_dfp_vconn : -+ policy_vcs_ufp_turn_on_vconn, -+ (chip->notify.power_role) ? -+ policy_src_send_softrst : -+ policy_snk_send_softrst); -+} -+ -+static void fusb_state_vcs_set_vconn(struct fusb30x_chip *chip, -+ u32 evt, bool on) -+{ -+ if (on) { -+ tcpm_set_vconn(chip, 1); -+ set_state(chip, chip->notify.data_role ? -+ policy_vcs_dfp_send_ps_rdy : -+ policy_vcs_ufp_send_ps_rdy); -+ } else { -+ tcpm_set_vconn(chip, 0); -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_ready); -+ else -+ set_state(chip, policy_snk_ready); -+ } -+} -+ -+static void fusb_state_vcs_send_ps_rdy(struct fusb30x_chip *chip, u32 evt) -+{ -+ fusb_state_send_simple_msg(chip, evt, CMT_PS_RDY, CONTROLMESSAGE, -+ (chip->notify.power_role) ? -+ policy_src_ready : policy_snk_ready, -+ (chip->notify.power_role) ? -+ policy_src_send_softrst : -+ policy_snk_send_softrst); -+} -+ -+static void fusb_state_vcs_wait_for_vconn(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->timer_state = T_PD_VCONN_SRC_ON; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ /* fallthrough */ -+ case 1: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_PS_RDY)) -+ set_state(chip, chip->notify.data_role ? -+ policy_vcs_dfp_turn_off_vconn : -+ policy_vcs_ufp_turn_off_vconn); -+ } else if (evt & EVENT_TIMER_STATE) { -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_send_hardrst); -+ else -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ } -+} -+ -+static void fusb_state_src_prs_transition_to_off(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->timer_state = T_SRC_TRANSITION; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ break; -+ case 1: -+ if (evt & EVENT_TIMER_STATE) { -+ platform_set_vbus_lvl_enable(chip, 0, 0); -+ chip->notify.power_role = POWER_ROLE_SINK; -+ tcpm_set_msg_header(chip); -+ if (chip->role == ROLE_MODE_DRP) -+ set_state(chip, policy_src_prs_assert_rd); -+ else -+ set_state(chip, policy_src_prs_source_off); -+ } -+ } -+} -+ -+static void fusb_state_src_prs_assert_rd(struct fusb30x_chip *chip, u32 evt) -+{ -+ tcpm_set_cc_pull_mode(chip, CC_PULL_DOWN); -+ set_state(chip, policy_src_prs_source_off); -+} -+ -+static void fusb_state_src_prs_source_off(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* fallthrough */ -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->timer_state = T_PD_SOURCE_ON; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ } else if (tmp == tx_failed) { -+ chip->notify.power_role = POWER_ROLE_SOURCE; -+ tcpm_set_msg_header(chip); -+ set_state(chip, policy_src_send_hardrst); -+ } -+ if (chip->sub_state != 3) -+ break; -+ case 2: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_PS_RDY)) { -+ chip->timer_state = T_DISABLED; -+ /* snk startup */ -+ chip->notify.is_pd_connected = false; -+ chip->cc_state |= CC_STATE_TOGSS_IS_UFP; -+ tcpm_set_polarity(chip, chip->cc_polarity); -+ tcpm_set_rx_enable(chip, 1); -+ set_state(chip, policy_snk_discovery); -+ } else { -+ dev_dbg(chip->dev, -+ "rec careless msg: head %x\n", -+ chip->rec_head); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ chip->notify.power_role = POWER_ROLE_SOURCE; -+ tcpm_set_msg_header(chip); -+ set_state(chip, policy_src_send_hardrst); -+ } -+ } -+} -+ -+static void fusb_state_drs_evaluate(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (chip->pd_cap_info.data_role_swap) -+ /* -+ * TODO: -+ * NOW REJECT swap when the port is DFP -+ * since we should work together with USB part -+ */ -+ set_state(chip, chip->notify.data_role ? -+ policy_drs_dfp_reject : policy_drs_ufp_accept); -+ else -+ set_state(chip, chip->notify.data_role ? -+ policy_drs_dfp_reject : policy_drs_ufp_reject); -+} -+ -+static void fusb_state_drs_send_accept(struct fusb30x_chip *chip, u32 evt) -+{ -+ fusb_state_send_simple_msg(chip, evt, CMT_ACCEPT, CONTROLMESSAGE, -+ chip->notify.power_role ? -+ policy_drs_dfp_change : -+ policy_drs_ufp_change, -+ error_recovery); -+} -+ -+static void fusb_state_drs_role_change(struct fusb30x_chip *chip, u32 evt) -+{ -+ chip->notify.data_role = chip->notify.data_role ? -+ DATA_ROLE_UFP : DATA_ROLE_DFP; -+ tcpm_set_msg_header(chip); -+ set_state(chip, chip->notify.power_role ? policy_src_ready : -+ policy_snk_ready); -+} -+ -+static void fusb_state_src_get_sink_cap(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_GETSINKCAP, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->timer_state = T_SENDER_RESPONSE; -+ chip->sub_state++; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_softrst); -+ } -+ -+ if (!(evt & FLAG_EVENT)) -+ break; -+ default: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_DATA_MSG(chip->rec_head, -+ DMT_SINKCAPABILITIES)) { -+ for (tmp = 0; -+ tmp < PD_HEADER_CNT(chip->rec_head); -+ tmp++) { -+ chip->partner_cap[tmp] = -+ chip->rec_load[tmp]; -+ } -+ set_state(chip, policy_src_ready); -+ } else { -+ chip->partner_cap[0] = 0xffffffff; -+ set_state(chip, policy_src_ready); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ dev_warn(chip->dev, "Get sink cap time out\n"); -+ chip->partner_cap[0] = 0xffffffff; -+ set_state(chip, policy_src_ready); -+ } -+ } -+} -+ -+static void fusb_state_src_send_hardreset(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ default: -+ tmp = policy_send_hardrst(chip, evt); -+ if (tmp == tx_success) { -+ chip->hardrst_count++; -+ set_state(chip, policy_src_transition_default); -+ } else if (tmp == tx_failed) { -+ /* can't reach here */ -+ set_state(chip, error_recovery); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_softreset(struct fusb30x_chip *chip) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ default: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ fusb_soft_reset_parameter(chip); -+ set_state(chip, policy_src_send_caps); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_src_send_softreset(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->timer_state = T_SENDER_RESPONSE; -+ chip->sub_state++; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_src_send_hardrst); -+ } -+ -+ if (!(evt & FLAG_EVENT)) -+ break; -+ default: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_ACCEPT)) { -+ fusb_soft_reset_parameter(chip); -+ set_state(chip, policy_src_send_caps); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_src_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_startup(struct fusb30x_chip *chip, u32 evt) -+{ -+ chip->notify.is_pd_connected = false; -+ fusb_soft_reset_parameter(chip); -+ -+ memset(chip->partner_cap, 0, sizeof(chip->partner_cap)); -+ -+ tcpm_set_msg_header(chip); -+ tcpm_set_polarity(chip, chip->cc_polarity); -+ tcpm_set_rx_enable(chip, 1); -+ set_state(chip, policy_snk_discovery); -+ platform_fusb_notify(chip); -+} -+ -+static void fusb_state_snk_discovery(struct fusb30x_chip *chip, u32 evt) -+{ -+ set_state(chip, policy_snk_wait_caps); -+ chip->timer_state = T_TYPEC_SINK_WAIT_CAP; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+} -+ -+static void fusb_state_snk_wait_caps(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_DATA_MSG(chip->rec_head, -+ DMT_SOURCECAPABILITIES)) { -+ chip->is_pd_support = true; -+ chip->timer_mux = T_DISABLED; -+ set_state(chip, policy_snk_evaluate_caps); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ if (chip->hardrst_count <= N_HARDRESET_COUNT) { -+ if (chip->vbus_begin) { -+ chip->vbus_begin = false; -+ set_state(chip, policy_snk_send_softrst); -+ } else { -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ } else { -+ if (chip->is_pd_support) -+ set_state(chip, error_recovery); -+ else -+ set_state(chip, disabled); -+ } -+ } else if ((evt & EVENT_TIMER_MUX) && -+ (chip->hardrst_count > N_HARDRESET_COUNT)) { -+ if (chip->is_pd_support) -+ set_state(chip, error_recovery); -+ else -+ set_state(chip, disabled); -+ } -+} -+ -+static void fusb_state_snk_evaluate_caps(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ chip->hardrst_count = 0; -+ chip->pos_power = 0; -+ -+ for (tmp = 0; tmp < PD_HEADER_CNT(chip->rec_head); tmp++) { -+ switch (CAP_POWER_TYPE(chip->rec_load[tmp])) { -+ case 0: -+ /* Fixed Supply */ -+ if (CAP_FPDO_VOLTAGE(chip->rec_load[tmp]) <= 100) -+ chip->pos_power = tmp + 1; -+ break; -+ case 1: -+ /* Battery */ -+ if (CAP_VPDO_VOLTAGE(chip->rec_load[tmp]) <= 100) -+ chip->pos_power = tmp + 1; -+ break; -+ default: -+ /* not meet battery caps */ -+ break; -+ } -+ } -+ fusb302_set_pos_power_by_charge_ic(chip); -+ -+ if ((!chip->pos_power) || (chip->pos_power > 7)) { -+ chip->pos_power = 0; -+ set_state(chip, policy_snk_wait_caps); -+ } else { -+ set_state(chip, policy_snk_select_cap); -+ } -+} -+ -+static void fusb_state_snk_select_cap(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, DMT_REQUEST, DATAMESSAGE); -+ chip->sub_state = 1; -+ chip->tx_state = tx_idle; -+ /* without break */ -+ case 1: -+ tmp = policy_send_data(chip); -+ -+ if (tmp == tx_success) { -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_snk_discovery); -+ break; -+ } -+ -+ if (!(evt & FLAG_EVENT)) -+ break; -+ default: -+ if (evt & EVENT_RX) { -+ if (!PD_HEADER_CNT(chip->rec_head)) { -+ switch (PD_HEADER_TYPE(chip->rec_head)) { -+ case CMT_ACCEPT: -+ set_state(chip, -+ policy_snk_transition_sink); -+ chip->timer_state = T_PS_TRANSITION; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ break; -+ case CMT_WAIT: -+ case CMT_REJECT: -+ if (chip->notify.is_pd_connected) { -+ dev_info(chip->dev, -+ "PD connected as UFP, fetching 5V\n"); -+ set_state(chip, -+ policy_snk_ready); -+ } else { -+ set_state(chip, -+ policy_snk_wait_caps); -+ /* -+ * make sure don't send -+ * hard reset to prevent -+ * infinite loop -+ */ -+ chip->hardrst_count = -+ N_HARDRESET_COUNT + 1; -+ } -+ break; -+ default: -+ break; -+ } -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_transition_sink(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_PS_RDY)) { -+ chip->notify.is_pd_connected = true; -+ dev_info(chip->dev, -+ "PD connected as UFP, fetching 5V\n"); -+ set_state(chip, policy_snk_ready); -+ } else if (PACKET_IS_DATA_MSG(chip->rec_head, -+ DMT_SOURCECAPABILITIES)) { -+ set_state(chip, policy_snk_evaluate_caps); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_snk_send_hardrst); -+ } -+} -+ -+static void fusb_state_snk_transition_default(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->notify.is_pd_connected = false; -+ chip->timer_mux = T_NO_RESPONSE; -+ fusb_timer_start(&chip->timer_mux_machine, -+ chip->timer_mux); -+ chip->timer_state = T_PS_HARD_RESET_MAX + T_SAFE_0V; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ if (chip->notify.data_role) -+ tcpm_set_msg_header(chip); -+ -+ chip->sub_state++; -+ /* fallthrough */ -+ case 1: -+ if (!tcpm_check_vbus(chip)) { -+ chip->sub_state++; -+ chip->timer_state = T_SRC_RECOVER_MAX + T_SRC_TURN_ON; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_snk_startup); -+ } -+ break; -+ default: -+ if (tcpm_check_vbus(chip)) { -+ chip->timer_state = T_DISABLED; -+ set_state(chip, policy_snk_startup); -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_snk_startup); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_ready(struct fusb30x_chip *chip, u32 evt) -+{ -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_DATA_MSG(chip->rec_head, DMT_VENDERDEFINED)) { -+ process_vdm_msg(chip); -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ chip->timer_state = T_DISABLED; -+ } else if (!VDM_IS_ACTIVE(chip)) { -+ fusb_state_swap_msg_process(chip, evt); -+ } -+ } -+ -+ if (VDM_IS_ACTIVE(chip)) -+ auto_vdm_machine(chip, evt); -+ -+ fusb_state_swap_msg_process(chip, evt); -+ platform_fusb_notify(chip); -+} -+ -+static void fusb_state_snk_send_hardreset(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ default: -+ tmp = policy_send_hardrst(chip, evt); -+ if (tmp == tx_success) { -+ chip->hardrst_count++; -+ set_state(chip, policy_snk_transition_default); -+ } else if (tmp == tx_failed) { -+ set_state(chip, error_recovery); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_send_swap(struct fusb30x_chip *chip, u32 evt, int cmd) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, cmd, CONTROLMESSAGE); -+ chip->sub_state = 1; -+ chip->tx_state = tx_idle; -+ /* fallthrough */ -+ case 1: -+ tmp = policy_send_data(chip); -+ -+ if (tmp == tx_success) { -+ chip->timer_state = T_SENDER_RESPONSE; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ } else if (tmp == tx_failed) { -+ if (cmd == CMT_DR_SWAP) { -+ set_state(chip, error_recovery); -+ return; -+ } -+ -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_send_softrst); -+ else -+ set_state(chip, policy_snk_send_softrst); -+ } -+ break; -+ case 2: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_ACCEPT)) { -+ chip->timer_state = T_DISABLED; -+ if (cmd == CMT_VCONN_SWAP) { -+ set_state(chip, chip->vconn_enabled ? -+ policy_vcs_dfp_wait_for_ufp_vconn : -+ policy_vcs_dfp_turn_on_vconn); -+ } else if (cmd == CMT_PR_SWAP) { -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_prs_transition_to_off); -+ else -+ set_state(chip, policy_snk_prs_transition_to_off); -+ chip->notify.power_role = POWER_ROLE_SOURCE; -+ tcpm_set_msg_header(chip); -+ } else if (cmd == CMT_DR_SWAP) { -+ set_state(chip, chip->notify.data_role ? -+ policy_drs_dfp_change : -+ policy_drs_ufp_change); -+ } -+ } else if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_REJECT) || -+ PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_WAIT)) { -+ chip->timer_state = T_DISABLED; -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_ready); -+ else -+ set_state(chip, policy_snk_ready); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_ready); -+ else -+ set_state(chip, policy_snk_ready); -+ } -+ } -+} -+ -+static void fusb_state_snk_prs_transition_to_off(struct fusb30x_chip *chip, -+ u32 evt) -+{ -+ switch (chip->sub_state) { -+ case 0: -+ chip->timer_state = T_PD_SOURCE_OFF; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ /* fallthrough */ -+ case 1: -+ if (evt & EVENT_RX) { -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, -+ CMT_PS_RDY)) { -+ if (chip->role == ROLE_MODE_DRP) -+ set_state(chip, -+ policy_snk_prs_assert_rp); -+ else -+ set_state(chip, -+ policy_snk_prs_source_on); -+ } else { -+ dev_dbg(chip->dev, -+ "rec careless msg: head %x\n", -+ chip->rec_head); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ chip->notify.power_role = POWER_ROLE_SINK; -+ tcpm_set_msg_header(chip); -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_prs_assert_rp(struct fusb30x_chip *chip, u32 evt) -+{ -+ tcpm_set_cc_pull_mode(chip, CC_PULL_UP); -+ set_state(chip, policy_snk_prs_source_on); -+} -+ -+static void fusb_state_snk_prs_source_on(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ /* supply power in 50ms */ -+ platform_set_vbus_lvl_enable(chip, 1, 0); -+ chip->sub_state++; -+ chip->work_continue |= EVENT_WORK_CONTINUE; -+ break; -+ case 1: -+ set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* fallthrough */ -+ case 2: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ /* PD spe 6.5.10.2 */ -+ chip->timer_state = T_PD_SWAP_SOURCE_START; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ chip->sub_state++; -+ } else if (tmp == tx_failed) { -+ chip->notify.power_role = POWER_ROLE_SINK; -+ tcpm_set_msg_header(chip); -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ break; -+ case 3: -+ if (evt & EVENT_TIMER_STATE) { -+ chip->cc_state &= ~CC_STATE_TOGSS_IS_UFP; -+ regmap_update_bits(chip->regmap, FUSB_REG_MASK, -+ MASK_M_COMP_CHNG, 0); -+ set_state(chip, policy_src_send_caps); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_softreset(struct fusb30x_chip *chip) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ /* without break */ -+ default: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ fusb_soft_reset_parameter(chip); -+ chip->timer_state = T_TYPEC_SINK_WAIT_CAP; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ set_state(chip, policy_snk_wait_caps); -+ } else if (tmp == tx_failed) { -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_state_snk_send_softreset(struct fusb30x_chip *chip, u32 evt) -+{ -+ u32 tmp; -+ -+ switch (chip->sub_state) { -+ case 0: -+ set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE); -+ chip->tx_state = tx_idle; -+ chip->sub_state++; -+ case 1: -+ tmp = policy_send_data(chip); -+ if (tmp == tx_success) { -+ chip->timer_state = T_SENDER_RESPONSE; -+ chip->sub_state++; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ } else if (tmp == tx_failed) { -+ /* can't reach here */ -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ -+ if (!(evt & FLAG_EVENT)) -+ break; -+ default: -+ if (evt & EVENT_RX) { -+ if ((!PD_HEADER_CNT(chip->rec_head)) && -+ (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT)) { -+ fusb_soft_reset_parameter(chip); -+ chip->timer_state = T_TYPEC_SINK_WAIT_CAP; -+ fusb_timer_start(&chip->timer_state_machine, -+ chip->timer_state); -+ set_state(chip, policy_snk_wait_caps); -+ } -+ } else if (evt & EVENT_TIMER_STATE) { -+ set_state(chip, policy_snk_send_hardrst); -+ } -+ break; -+ } -+} -+ -+static void fusb_try_detach(struct fusb30x_chip *chip) -+{ -+ int cc1, cc2; -+ -+ if ((chip->cc_state & CC_STATE_TOGSS_IS_UFP) && -+ (chip->conn_state != -+ policy_snk_transition_default) && -+ (chip->conn_state != -+ policy_src_prs_source_off) && -+ (chip->conn_state != policy_snk_prs_send_swap) && -+ (chip->conn_state != policy_snk_prs_assert_rp) && -+ (chip->conn_state != policy_snk_prs_source_on) && -+ (chip->conn_state != policy_snk_prs_transition_to_off)) { -+ if (!tcpm_check_vbus(chip)) -+ set_state_unattached(chip); -+ } else if ((chip->conn_state != -+ policy_src_transition_default) && -+ (chip->conn_state != -+ policy_src_prs_source_off) && -+ (chip->conn_state != policy_snk_prs_source_on)) { -+ tcpm_get_cc(chip, &cc1, &cc2); -+ if (chip->cc_state & CC_STATE_TOGSS_CC2) -+ cc1 = cc2; -+ if (cc1 == TYPEC_CC_VOLT_OPEN) -+ set_state_unattached(chip); -+ } else { -+ /* -+ * Detached may occurred at swap operations. So, DON'T ignore -+ * the EVENT_CC during swapping at all, check the connection -+ * after it. -+ */ -+ chip->work_continue |= EVENT_DELAY_CC; -+ } -+} -+ -+static void state_machine_typec(struct fusb30x_chip *chip) -+{ -+ u32 evt = 0; -+ -+ tcpc_alert(chip, &evt); -+ mux_alert(chip, &evt); -+ if (!evt) -+ goto BACK; -+ -+ if (chip->notify.is_cc_connected) -+ if (evt & (EVENT_CC | EVENT_DELAY_CC)) -+ fusb_try_detach(chip); -+ -+ if (evt & EVENT_RX) { -+ tcpm_get_message(chip); -+ if (PACKET_IS_CONTROL_MSG(chip->rec_head, CMT_SOFTRESET)) { -+ if (chip->notify.power_role) -+ set_state(chip, policy_src_softrst); -+ else -+ set_state(chip, policy_snk_softrst); -+ } -+ } -+ -+ if (evt & EVENT_TX) { -+ if (chip->tx_state == tx_success) -+ chip->msg_id++; -+ } -+ switch (chip->conn_state) { -+ case disabled: -+ fusb_state_disabled(chip, evt); -+ break; -+ case error_recovery: -+ set_state_unattached(chip); -+ break; -+ case unattached: -+ fusb_state_unattached(chip, evt); -+ break; -+ case attach_wait_sink: -+ fusb_state_attach_wait_sink(chip, evt); -+ break; -+ case attach_wait_source: -+ fusb_state_attach_wait_source(chip, evt); -+ break; -+ case attached_source: -+ fusb_state_attached_source(chip, evt); -+ break; -+ case attached_sink: -+ fusb_state_attached_sink(chip, evt); -+ break; -+ case attach_try_src: -+ fusb_state_try_attach(chip, evt, ROLE_MODE_DFP); -+ break; -+ case attach_try_snk: -+ fusb_state_try_attach(chip, evt, ROLE_MODE_UFP); -+ break; -+ -+ /* POWER DELIVERY */ -+ case policy_src_startup: -+ fusb_state_src_startup(chip, evt); -+ break; -+ case policy_src_discovery: -+ fusb_state_src_discovery(chip, evt); -+ break; -+ case policy_src_send_caps: -+ fusb_state_src_send_caps(chip, evt); -+ if (chip->conn_state != policy_src_negotiate_cap) -+ break; -+ case policy_src_negotiate_cap: -+ fusb_state_src_negotiate_cap(chip, evt); -+ -+ case policy_src_transition_supply: -+ fusb_state_src_transition_supply(chip, evt); -+ break; -+ case policy_src_cap_response: -+ fusb_state_src_cap_response(chip, evt); -+ break; -+ case policy_src_transition_default: -+ fusb_state_src_transition_default(chip, evt); -+ break; -+ case policy_src_ready: -+ fusb_state_src_ready(chip, evt); -+ break; -+ case policy_src_get_sink_caps: -+ fusb_state_src_get_sink_cap(chip, evt); -+ break; -+ case policy_src_send_hardrst: -+ fusb_state_src_send_hardreset(chip, evt); -+ break; -+ case policy_src_send_softrst: -+ fusb_state_src_send_softreset(chip, evt); -+ break; -+ case policy_src_softrst: -+ fusb_state_src_softreset(chip); -+ break; -+ -+ /* UFP */ -+ case policy_snk_startup: -+ fusb_state_snk_startup(chip, evt); -+ break; -+ case policy_snk_discovery: -+ fusb_state_snk_discovery(chip, evt); -+ break; -+ case policy_snk_wait_caps: -+ fusb_state_snk_wait_caps(chip, evt); -+ break; -+ case policy_snk_evaluate_caps: -+ fusb_state_snk_evaluate_caps(chip, evt); -+ /* without break */ -+ case policy_snk_select_cap: -+ fusb_state_snk_select_cap(chip, evt); -+ break; -+ case policy_snk_transition_sink: -+ fusb_state_snk_transition_sink(chip, evt); -+ break; -+ case policy_snk_transition_default: -+ fusb_state_snk_transition_default(chip, evt); -+ break; -+ case policy_snk_ready: -+ fusb_state_snk_ready(chip, evt); -+ break; -+ case policy_snk_send_hardrst: -+ fusb_state_snk_send_hardreset(chip, evt); -+ break; -+ case policy_snk_send_softrst: -+ fusb_state_snk_send_softreset(chip, evt); -+ break; -+ case policy_snk_softrst: -+ fusb_state_snk_softreset(chip); -+ break; -+ -+ /* -+ * PD Spec 1.0: PR SWAP: chap 8.3.3.6.3.1/2 -+ * VC SWAP: chap 8.3.3.7.1/2 -+ */ -+ case policy_src_prs_evaluate: -+ case policy_snk_prs_evaluate: -+ fusb_state_prs_evaluate(chip, evt); -+ break; -+ case policy_snk_prs_accept: -+ case policy_src_prs_accept: -+ fusb_state_prs_accept(chip, evt); -+ break; -+ case policy_snk_prs_reject: -+ case policy_src_prs_reject: -+ case policy_vcs_ufp_reject: -+ case policy_drs_dfp_reject: -+ case policy_drs_ufp_reject: -+ fusb_state_prs_reject(chip, evt); -+ break; -+ case policy_src_prs_transition_to_off: -+ fusb_state_src_prs_transition_to_off(chip, evt); -+ break; -+ case policy_src_prs_assert_rd: -+ fusb_state_src_prs_assert_rd(chip, evt); -+ break; -+ case policy_src_prs_source_off: -+ fusb_state_src_prs_source_off(chip, evt); -+ break; -+ case policy_snk_prs_send_swap: -+ case policy_src_prs_send_swap: -+ fusb_state_send_swap(chip, evt, CMT_PR_SWAP); -+ break; -+ case policy_snk_prs_transition_to_off: -+ fusb_state_snk_prs_transition_to_off(chip, evt); -+ break; -+ case policy_snk_prs_assert_rp: -+ fusb_state_snk_prs_assert_rp(chip, evt); -+ break; -+ case policy_snk_prs_source_on: -+ fusb_state_snk_prs_source_on(chip, evt); -+ break; -+ case policy_vcs_ufp_evaluate_swap: -+ fusb_state_vcs_ufp_evaluate_swap(chip, evt); -+ break; -+ case policy_vcs_ufp_accept: -+ fusb_state_vcs_ufp_accept(chip, evt); -+ break; -+ case policy_vcs_ufp_wait_for_dfp_vconn: -+ case policy_vcs_dfp_wait_for_ufp_vconn: -+ fusb_state_vcs_wait_for_vconn(chip, evt); -+ break; -+ case policy_vcs_ufp_turn_off_vconn: -+ case policy_vcs_dfp_turn_off_vconn: -+ fusb_state_vcs_set_vconn(chip, evt, false); -+ break; -+ case policy_vcs_ufp_turn_on_vconn: -+ case policy_vcs_dfp_turn_on_vconn: -+ fusb_state_vcs_set_vconn(chip, evt, true); -+ break; -+ case policy_vcs_ufp_send_ps_rdy: -+ case policy_vcs_dfp_send_ps_rdy: -+ fusb_state_vcs_send_ps_rdy(chip, evt); -+ break; -+ case policy_vcs_dfp_send_swap: -+ fusb_state_send_swap(chip, evt, CMT_VCONN_SWAP); -+ break; -+ case policy_drs_ufp_evaluate: -+ case policy_drs_dfp_evaluate: -+ fusb_state_drs_evaluate(chip, evt); -+ break; -+ case policy_drs_dfp_accept: -+ case policy_drs_ufp_accept: -+ fusb_state_drs_send_accept(chip, evt); -+ break; -+ case policy_drs_dfp_change: -+ case policy_drs_ufp_change: -+ fusb_state_drs_role_change(chip, evt); -+ break; -+ case policy_drs_ufp_send_swap: -+ case policy_drs_dfp_send_swap: -+ fusb_state_send_swap(chip, evt, CMT_DR_SWAP); -+ break; -+ -+ default: -+ break; -+ } -+ -+BACK: -+ if (chip->work_continue) { -+ queue_work(chip->fusb30x_wq, &chip->work); -+ return; -+ } -+ -+ if (!platform_get_device_irq_state(chip)) -+ fusb_irq_enable(chip); -+ else -+ queue_work(chip->fusb30x_wq, &chip->work); -+} -+ -+static irqreturn_t cc_interrupt_handler(int irq, void *dev_id) -+{ -+ struct fusb30x_chip *chip = dev_id; -+ -+ queue_work(chip->fusb30x_wq, &chip->work); -+ fusb_irq_disable(chip); -+ return IRQ_HANDLED; -+} -+ -+static int fusb_initialize_gpio(struct fusb30x_chip *chip) -+{ -+ chip->gpio_int = devm_gpiod_get_optional(chip->dev, "int-n", GPIOD_IN); -+ if (IS_ERR(chip->gpio_int)) -+ return PTR_ERR(chip->gpio_int); -+ -+ /* some board support vbus with other ways */ -+ chip->gpio_vbus_5v = devm_gpiod_get_optional(chip->dev, "vbus-5v", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(chip->gpio_vbus_5v)) -+ dev_warn(chip->dev, -+ "Could not get named GPIO for VBus5V!\n"); -+ else -+ gpiod_set_raw_value(chip->gpio_vbus_5v, 0); -+ -+ chip->gpio_vbus_other = devm_gpiod_get_optional(chip->dev, -+ "vbus-other", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(chip->gpio_vbus_other)) -+ dev_warn(chip->dev, -+ "Could not get named GPIO for VBusOther!\n"); -+ else -+ gpiod_set_raw_value(chip->gpio_vbus_other, 0); -+ -+ chip->gpio_discharge = devm_gpiod_get_optional(chip->dev, "discharge", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(chip->gpio_discharge)) { -+ dev_warn(chip->dev, -+ "Could not get named GPIO for discharge!\n"); -+ chip->gpio_discharge = NULL; -+ } -+ -+ return 0; -+} -+ -+static enum hrtimer_restart fusb_timer_handler(struct hrtimer *timer) -+{ -+ int i; -+ -+ for (i = 0; i < fusb30x_port_used; i++) { -+ if (timer == &fusb30x_port_info[i]->timer_state_machine) { -+ if (fusb30x_port_info[i]->timer_state != T_DISABLED) -+ fusb30x_port_info[i]->timer_state = 0; -+ break; -+ } -+ -+ if (timer == &fusb30x_port_info[i]->timer_mux_machine) { -+ if (fusb30x_port_info[i]->timer_mux != T_DISABLED) -+ fusb30x_port_info[i]->timer_mux = 0; -+ break; -+ } -+ } -+ -+ if (i != fusb30x_port_used) -+ queue_work(fusb30x_port_info[i]->fusb30x_wq, -+ &fusb30x_port_info[i]->work); -+ -+ return HRTIMER_NORESTART; -+} -+ -+static void fusb_initialize_timer(struct fusb30x_chip *chip) -+{ -+ hrtimer_init(&chip->timer_state_machine, CLOCK_MONOTONIC, -+ HRTIMER_MODE_REL); -+ chip->timer_state_machine.function = fusb_timer_handler; -+ -+ hrtimer_init(&chip->timer_mux_machine, CLOCK_MONOTONIC, -+ HRTIMER_MODE_REL); -+ chip->timer_mux_machine.function = fusb_timer_handler; -+ -+ chip->timer_state = T_DISABLED; -+ chip->timer_mux = T_DISABLED; -+} -+ -+static void fusb302_work_func(struct work_struct *work) -+{ -+ struct fusb30x_chip *chip; -+ -+ chip = container_of(work, struct fusb30x_chip, work); -+ state_machine_typec(chip); -+} -+ -+static int fusb30x_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct fusb30x_chip *chip; -+ struct PD_CAP_INFO *pd_cap_info; -+ int ret; -+ char *string[2]; -+ -+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); -+ if (!chip) -+ return -ENOMEM; -+ -+ if (fusb30x_port_used == 0xff) -+ return -1; -+ -+ chip->port_num = fusb30x_port_used++; -+ fusb30x_port_info[chip->port_num] = chip; -+ -+ chip->dev = &client->dev; -+ chip->regmap = devm_regmap_init_i2c(client, &fusb302_regmap_config); -+ if (IS_ERR(chip->regmap)) { -+ dev_err(&client->dev, "Failed to allocate regmap!\n"); -+ return PTR_ERR(chip->regmap); -+ } -+ -+ ret = fusb_initialize_gpio(chip); -+ if (ret) -+ return ret; -+ -+ fusb_initialize_timer(chip); -+ -+ chip->fusb30x_wq = create_workqueue("fusb302_wq"); -+ INIT_WORK(&chip->work, fusb302_work_func); -+ -+ chip->role = ROLE_MODE_NONE; -+ chip->try_role = ROLE_MODE_NONE; -+ if (!of_property_read_string(chip->dev->of_node, "fusb302,role", -+ (const char **)&string[0])) { -+ if (!strcmp(string[0], "ROLE_MODE_DRP")) -+ chip->role = ROLE_MODE_DRP; -+ else if (!strcmp(string[0], "ROLE_MODE_DFP")) -+ chip->role = ROLE_MODE_DFP; -+ else if (!strcmp(string[0], "ROLE_MODE_UFP")) -+ chip->role = ROLE_MODE_UFP; -+ } -+ -+ if (chip->role == ROLE_MODE_NONE) { -+ dev_warn(chip->dev, -+ "Can't get property of role, set role to default DRP\n"); -+ chip->role = ROLE_MODE_DRP; -+ string[0] = "ROLE_MODE_DRP"; -+ } -+ -+ if (!of_property_read_string(chip->dev->of_node, "fusb302,try_role", -+ (const char **)&string[1])) { -+ if (!strcmp(string[1], "ROLE_MODE_DFP")) -+ chip->try_role = ROLE_MODE_DFP; -+ else if (!strcmp(string[1], "ROLE_MODE_UFP")) -+ chip->try_role = ROLE_MODE_UFP; -+ } -+ -+ if (chip->try_role == ROLE_MODE_NONE) -+ string[1] = "ROLE_MODE_NONE"; -+ -+ chip->vconn_supported = true; -+ tcpm_init(chip); -+ tcpm_set_rx_enable(chip, 0); -+ chip->conn_state = unattached; -+ tcpm_set_cc(chip, chip->role); -+ -+ chip->n_caps_used = 1; -+ chip->source_power_supply[0] = 0x64; -+ chip->source_max_current[0] = 0x96; -+ -+ pd_cap_info = &chip->pd_cap_info; -+ pd_cap_info->dual_role_power = 1; -+ pd_cap_info->data_role_swap = 1; -+ -+ pd_cap_info->externally_powered = 1; -+ pd_cap_info->usb_suspend_support = 0; -+ pd_cap_info->usb_communications_cap = 0; -+ pd_cap_info->supply_type = 0; -+ pd_cap_info->peak_current = 0; -+ -+ chip->extcon = devm_extcon_dev_allocate(&client->dev, fusb302_cable); -+ if (IS_ERR(chip->extcon)) { -+ dev_err(&client->dev, "allocat extcon failed\n"); -+ return PTR_ERR(chip->extcon); -+ } -+ -+ ret = devm_extcon_dev_register(&client->dev, chip->extcon); -+ if (ret) { -+ dev_err(&client->dev, "failed to register extcon: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_USB, -+ EXTCON_PROP_USB_TYPEC_POLARITY); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set USB property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST, -+ EXTCON_PROP_USB_TYPEC_POLARITY); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set USB_HOST property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP, -+ EXTCON_PROP_USB_TYPEC_POLARITY); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set DISP_DP property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_USB, -+ EXTCON_PROP_USB_SS); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set USB USB_SS property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST, -+ EXTCON_PROP_USB_SS); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set USB_HOST USB_SS property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP, -+ EXTCON_PROP_USB_SS); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set DISP_DP USB_SS property capability: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = extcon_set_property_capability(chip->extcon, EXTCON_CHG_USB_FAST, -+ EXTCON_PROP_USB_TYPEC_POLARITY); -+ if (ret) { -+ dev_err(&client->dev, -+ "failed to set USB_PD property capability: %d\n", ret); -+ return ret; -+ } -+ -+ i2c_set_clientdata(client, chip); -+ -+ spin_lock_init(&chip->irq_lock); -+ chip->enable_irq = 1; -+ -+ chip->gpio_int_irq = gpiod_to_irq(chip->gpio_int); -+ if (chip->gpio_int_irq < 0) { -+ dev_err(&client->dev, -+ "Unable to request IRQ for INT_N GPIO! %d\n", -+ ret); -+ ret = chip->gpio_int_irq; -+ goto IRQ_ERR; -+ } -+ -+ ret = devm_request_threaded_irq(&client->dev, -+ chip->gpio_int_irq, -+ NULL, -+ cc_interrupt_handler, -+ IRQF_ONESHOT | IRQF_TRIGGER_LOW, -+ client->name, -+ chip); -+ if (ret) { -+ dev_err(&client->dev, "irq request failed\n"); -+ goto IRQ_ERR; -+ } -+ -+ dev_info(chip->dev, -+ "port %d probe success with role %s, try_role %s\n", -+ chip->port_num, string[0], string[1]); -+ -+ return 0; -+ -+IRQ_ERR: -+ destroy_workqueue(chip->fusb30x_wq); -+ return ret; -+} -+ -+static int fusb30x_remove(struct i2c_client *client) -+{ -+ struct fusb30x_chip *chip = i2c_get_clientdata(client); -+ -+ destroy_workqueue(chip->fusb30x_wq); -+ return 0; -+} -+ -+static void fusb30x_shutdown(struct i2c_client *client) -+{ -+ struct fusb30x_chip *chip = i2c_get_clientdata(client); -+ -+ if (chip->gpio_vbus_5v) -+ gpiod_set_value(chip->gpio_vbus_5v, 0); -+ if (chip->gpio_discharge) { -+ gpiod_set_value(chip->gpio_discharge, 1); -+ msleep(100); -+ gpiod_set_value(chip->gpio_discharge, 0); -+ } -+} -+ -+static const struct of_device_id fusb30x_dt_match[] = { -+ { .compatible = FUSB30X_I2C_DEVICETREE_NAME }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, fusb30x_dt_match); -+ -+static const struct i2c_device_id fusb30x_i2c_device_id[] = { -+ { FUSB30X_I2C_DRIVER_NAME, 0 }, -+ {} -+}; -+MODULE_DEVICE_TABLE(i2c, fusb30x_i2c_device_id); -+ -+static struct i2c_driver fusb30x_driver = { -+ .driver = { -+ .name = FUSB30X_I2C_DRIVER_NAME, -+ .of_match_table = of_match_ptr(fusb30x_dt_match), -+ }, -+ .probe = fusb30x_probe, -+ .remove = fusb30x_remove, -+ .shutdown = fusb30x_shutdown, -+ .id_table = fusb30x_i2c_device_id, -+}; -+ -+module_i2c_driver(fusb30x_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("zain wang "); -+MODULE_DESCRIPTION("fusb302 typec pd driver"); -diff --git a/drivers/staging/fusb30x/fusb30x.h b/drivers/staging/fusb30x/fusb30x.h -new file mode 100644 -index 000000000..4f5ca64f7 ---- /dev/null -+++ b/drivers/staging/fusb30x/fusb30x.h -@@ -0,0 +1,552 @@ -+/* -+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd -+ * Author: Zain Wang -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * Some ideas are from chrome ec and fairchild GPL fusb302 driver. -+ */ -+ -+#ifndef FUSB302_H -+#define FUSB302_H -+ -+#include -+#include -+ -+const char *FUSB_DT_INTERRUPT_INTN = "fsc_interrupt_int_n"; -+#define FUSB_DT_GPIO_INTN "fairchild,int_n" -+#define FUSB_DT_GPIO_VBUS_5V "fairchild,vbus5v" -+#define FUSB_DT_GPIO_VBUS_OTHER "fairchild,vbusOther" -+ -+#define FUSB30X_I2C_DRIVER_NAME "fusb302" -+#define FUSB30X_I2C_DEVICETREE_NAME "fairchild,fusb302" -+ -+/* FUSB300 Register Addresses */ -+#define FUSB_REG_DEVICEID 0x01 -+#define FUSB_REG_SWITCHES0 0x02 -+#define FUSB_REG_SWITCHES1 0x03 -+#define FUSB_REG_MEASURE 0x04 -+#define FUSB_REG_SLICE 0x05 -+#define FUSB_REG_CONTROL0 0x06 -+#define FUSB_REG_CONTROL1 0x07 -+#define FUSB_REG_CONTROL2 0x08 -+#define FUSB_REG_CONTROL3 0x09 -+#define FUSB_REG_MASK 0x0A -+#define FUSB_REG_POWER 0x0B -+#define FUSB_REG_RESET 0x0C -+#define FUSB_REG_OCPREG 0x0D -+#define FUSB_REG_MASKA 0x0E -+#define FUSB_REG_MASKB 0x0F -+#define FUSB_REG_CONTROL4 0x10 -+#define FUSB_REG_STATUS0A 0x3C -+#define FUSB_REG_STATUS1A 0x3D -+#define FUSB_REG_INTERRUPTA 0x3E -+#define FUSB_REG_INTERRUPTB 0x3F -+#define FUSB_REG_STATUS0 0x40 -+#define FUSB_REG_STATUS1 0x41 -+#define FUSB_REG_INTERRUPT 0x42 -+#define FUSB_REG_FIFO 0x43 -+ -+enum connection_state { -+ disabled = 0, -+ error_recovery, -+ unattached, -+ attach_wait_sink, -+ attach_wait_source, -+ attached_source, -+ attached_sink, -+ -+ policy_src_startup, -+ policy_src_send_caps, -+ policy_src_discovery, -+ policy_src_negotiate_cap, -+ policy_src_cap_response, -+ policy_src_transition_supply, -+ policy_src_transition_default, -+ -+ policy_src_ready, -+ policy_src_get_sink_caps, -+ -+ policy_src_send_softrst, -+ policy_src_softrst, -+ policy_src_send_hardrst, -+ -+ policy_snk_startup, -+ policy_snk_discovery, -+ policy_snk_wait_caps, -+ policy_snk_evaluate_caps, -+ policy_snk_select_cap, -+ policy_snk_transition_sink, -+ policy_snk_ready, -+ -+ policy_snk_send_softrst, -+ policy_snk_softrst, -+ policy_snk_send_hardrst, -+ -+ policy_snk_transition_default, -+ -+ /* PR SWAP */ -+ policy_src_prs_evaluate, -+ policy_src_prs_accept, -+ policy_src_prs_transition_to_off, -+ policy_src_prs_source_off, -+ policy_src_prs_assert_rd, -+ policy_src_prs_reject, -+ policy_src_prs_send_swap, -+ -+ policy_snk_prs_evaluate, -+ policy_snk_prs_accept, -+ policy_snk_prs_transition_to_off, -+ policy_snk_prs_source_on, -+ policy_snk_prs_assert_rp, -+ policy_snk_prs_reject, -+ policy_snk_prs_send_swap, -+ -+ /* VC SWAP */ -+ policy_vcs_dfp_send_swap, -+ policy_vcs_dfp_wait_for_ufp_vconn, -+ policy_vcs_dfp_turn_off_vconn, -+ policy_vcs_dfp_turn_on_vconn, -+ policy_vcs_dfp_send_ps_rdy, -+ -+ policy_vcs_ufp_evaluate_swap, -+ policy_vcs_ufp_reject, -+ policy_vcs_ufp_accept, -+ policy_vcs_ufp_wait_for_dfp_vconn, -+ policy_vcs_ufp_turn_off_vconn, -+ policy_vcs_ufp_turn_on_vconn, -+ policy_vcs_ufp_send_ps_rdy, -+ -+ policy_drs_ufp_evaluate, -+ policy_drs_ufp_accept, -+ policy_drs_ufp_reject, -+ policy_drs_ufp_change, -+ policy_drs_ufp_send_swap, -+ -+ policy_drs_dfp_evaluate, -+ policy_drs_dfp_accept, -+ policy_drs_dfp_reject, -+ policy_drs_dfp_change, -+ policy_drs_dfp_send_swap, -+ -+ attach_try_src, -+ attach_try_snk, -+}; -+ -+enum vdm_state { -+ VDM_STATE_DISCOVERY_ID, -+ VDM_STATE_DISCOVERY_SVID, -+ VDM_STATE_DISCOVERY_MODES, -+ VDM_STATE_ENTER_MODE, -+ VDM_STATE_UPDATE_STATUS, -+ VDM_STATE_DP_CONFIG, -+ VDM_STATE_NOTIFY, -+ VDM_STATE_READY, -+ VDM_STATE_ERR, -+}; -+ -+enum tcpm_rp_value { -+ TYPEC_RP_USB = 0, -+ TYPEC_RP_1A5 = 1, -+ TYPEC_RP_3A0 = 2, -+ TYPEC_RP_RESERVED = 3, -+}; -+ -+enum role_mode { -+ ROLE_MODE_NONE, -+ ROLE_MODE_DRP, -+ ROLE_MODE_UFP, -+ ROLE_MODE_DFP, -+ ROLE_MODE_ASS, -+}; -+ -+#define SBF(s, v) ((s) << (v)) -+#define SWITCHES0_PDWN1 SBF(1, 0) -+#define SWITCHES0_PDWN2 SBF(1, 1) -+#define SWITCHES0_MEAS_CC1 SBF(1, 2) -+#define SWITCHES0_MEAS_CC2 SBF(1, 3) -+#define SWITCHES0_VCONN_CC1 SBF(1, 4) -+#define SWITCHES0_VCONN_CC2 SBF(1, 5) -+#define SWITCHES0_PU_EN1 SBF(1, 6) -+#define SWITCHES0_PU_EN2 SBF(1, 7) -+ -+#define SWITCHES1_TXCC1 SBF(1, 0) -+#define SWITCHES1_TXCC2 SBF(1, 1) -+#define SWITCHES1_AUTO_CRC SBF(1, 2) -+#define SWITCHES1_DATAROLE SBF(1, 4) -+#define SWITCHES1_SPECREV SBF(3, 5) -+#define SWITCHES1_POWERROLE SBF(1, 7) -+ -+#define MEASURE_MDAC SBF(0x3f, 0) -+#define MEASURE_VBUS SBF(1, 6) -+ -+#define SLICE_SDAC SBF(0x3f, 0) -+#define SLICE_SDAC_HYS SBF(3, 6) -+ -+#define CONTROL0_TX_START SBF(1, 0) -+#define CONTROL0_AUTO_PRE SBF(1, 1) -+#define CONTROL0_HOST_CUR SBF(3, 2) -+#define CONTROL0_HOST_CUR_USB SBF(1, 2) -+#define CONTROL0_HOST_CUR_1A5 SBF(2, 2) -+#define CONTROL0_HOST_CUR_3A0 SBF(3, 2) -+#define CONTROL0_INT_MASK SBF(1, 5) -+#define CONTROL0_TX_FLUSH SBF(1, 6) -+ -+#define CONTROL1_ENSOP1 SBF(1, 0) -+#define CONTROL1_ENSOP2 SBF(1, 1) -+#define CONTROL1_RX_FLUSH SBF(1, 2) -+#define CONTROL1_BIST_MODE2 SBF(1, 4) -+#define CONTROL1_ENSOP1DB SBF(1, 5) -+#define CONTROL1_ENSOP2DB SBF(1, 6) -+ -+#define CONTROL2_TOGGLE SBF(1, 0) -+#define CONTROL2_MODE SBF(3, 1) -+#define CONTROL2_MODE_NONE 0 -+#define CONTROL2_MODE_DFP SBF(3, 1) -+#define CONTROL2_MODE_UFP SBF(2, 1) -+#define CONTROL2_MODE_DRP SBF(1, 1) -+#define CONTROL2_WAKE_EN SBF(1, 3) -+#define CONTROL2_TOG_RD_ONLY SBF(1, 5) -+#define CONTROL2_TOG_SAVE_PWR1 SBF(1, 6) -+#define CONTROL2_TOG_SAVE_PWR2 SBF(1, 7) -+ -+#define CONTROL3_AUTO_RETRY SBF(1, 0) -+#define CONTROL3_N_RETRIES SBF(3, 1) -+#define CONTROL3_AUTO_SOFTRESET SBF(1, 3) -+#define CONTROL3_AUTO_HARDRESET SBF(1, 4) -+#define CONTROL3_SEND_HARDRESET SBF(1, 6) -+ -+#define MASK_M_BC_LVL SBF(1, 0) -+#define MASK_M_COLLISION SBF(1, 1) -+#define MASK_M_WAKE SBF(1, 2) -+#define MASK_M_ALERT SBF(1, 3) -+#define MASK_M_CRC_CHK SBF(1, 4) -+#define MASK_M_COMP_CHNG SBF(1, 5) -+#define MASK_M_ACTIVITY SBF(1, 6) -+#define MASK_M_VBUSOK SBF(1, 7) -+ -+#define POWER_PWR SBF(0xf, 0) -+ -+#define RESET_SW_RESET SBF(1, 0) -+#define RESET_PD_RESET SBF(1, 1) -+ -+#define MASKA_M_HARDRST SBF(1, 0) -+#define MASKA_M_SOFTRST SBF(1, 1) -+#define MASKA_M_TXSENT SBF(1, 2) -+#define MASKA_M_HARDSENT SBF(1, 3) -+#define MASKA_M_RETRYFAIL SBF(1, 4) -+#define MASKA_M_SOFTFAIL SBF(1, 5) -+#define MASKA_M_TOGDONE SBF(1, 6) -+#define MASKA_M_OCP_TEMP SBF(1, 7) -+ -+#define MASKB_M_GCRCSEND SBF(1, 0) -+ -+#define CONTROL4_TOG_USRC_EXIT SBF(1, 0) -+ -+#define MDAC_1P6V 0x26 -+ -+#define STATUS0A_HARDRST SBF(1, 0) -+#define STATUS0A_SOFTRST SBF(1, 1) -+#define STATUS0A_POWER23 SBF(3, 2) -+#define STATUS0A_RETRYFAIL SBF(1, 4) -+#define STATUS0A_SOFTFAIL SBF(1, 5) -+#define STATUS0A_TOGDONE SBF(1, 6) -+#define STATUS0A_M_OCP_TEMP SBF(1, 7) -+ -+#define STATUS1A_RXSOP SBF(1, 0) -+#define STATUS1A_RXSOP1DB SBF(1, 1) -+#define STATUS1A_RXSOP2DB SBF(1, 2) -+#define STATUS1A_TOGSS SBF(7, 3) -+#define CC_STATE_TOGSS_CC1 SBF(1, 0) -+#define CC_STATE_TOGSS_CC2 SBF(1, 1) -+#define CC_STATE_TOGSS_IS_UFP SBF(1, 2) -+ -+#define INTERRUPTA_HARDRST SBF(1, 0) -+#define INTERRUPTA_SOFTRST SBF(1, 1) -+#define INTERRUPTA_TXSENT SBF(1, 2) -+#define INTERRUPTA_HARDSENT SBF(1, 3) -+#define INTERRUPTA_RETRYFAIL SBF(1, 4) -+#define INTERRUPTA_SOFTFAIL SBF(1, 5) -+#define INTERRUPTA_TOGDONE SBF(1, 6) -+#define INTERRUPTA_OCP_TEMP SBF(1, 7) -+ -+#define INTERRUPTB_GCRCSENT SBF(1, 0) -+ -+#define STATUS0_BC_LVL SBF(3, 0) -+#define STATUS0_WAKE SBF(1, 2) -+#define STATUS0_ALERT SBF(1, 3) -+#define STATUS0_CRC_CHK SBF(1, 4) -+#define STATUS0_COMP SBF(1, 5) -+#define STATUS0_ACTIVITY SBF(1, 6) -+#define STATUS0_VBUSOK SBF(1, 7) -+ -+#define STATUS1_OCP SBF(1, 0) -+#define STATUS1_OVRTEMP SBF(1, 1) -+#define STATUS1_TX_FULL SBF(1, 2) -+#define STATUS1_TX_EMPTY SBF(1, 3) -+#define STATUS1_RX_FULL SBF(1, 4) -+#define STATUS1_RX_EMPTY SBF(1, 5) -+#define STATUS1_RXSOP1 SBF(1, 6) -+#define STATUS1_RXSOP2 SBF(1, 7) -+ -+#define INTERRUPT_BC_LVL SBF(1, 0) -+#define INTERRUPT_COLLISION SBF(1, 1) -+#define INTERRUPT_WAKE SBF(1, 2) -+#define INTERRUPT_ALERT SBF(1, 3) -+#define INTERRUPT_CRC_CHK SBF(1, 4) -+#define INTERRUPT_COMP_CHNG SBF(1, 5) -+#define INTERRUPT_ACTIVITY SBF(1, 6) -+#define INTERRUPT_VBUSOK SBF(1, 7) -+ -+#define FUSB_TKN_TXON 0xa1 -+#define FUSB_TKN_SYNC1 0x12 -+#define FUSB_TKN_SYNC2 0x13 -+#define FUSB_TKN_SYNC3 0x1b -+#define FUSB_TKN_RST1 0x15 -+#define FUSB_TKN_RST2 0x16 -+#define FUSB_TKN_PACKSYM 0x80 -+#define FUSB_TKN_JAMCRC 0xff -+#define FUSB_TKN_EOP 0x14 -+#define FUSB_TKN_TXOFF 0xfe -+ -+/* USB PD Control Message Types */ -+#define CONTROLMESSAGE 0 -+#define CMT_GOODCRC 1 -+#define CMT_GOTOMIN 2 -+#define CMT_ACCEPT 3 -+#define CMT_REJECT 4 -+#define CMT_PING 5 -+#define CMT_PS_RDY 6 -+#define CMT_GETSOURCECAP 7 -+#define CMT_GETSINKCAP 8 -+#define CMT_DR_SWAP 9 -+#define CMT_PR_SWAP 10 -+#define CMT_VCONN_SWAP 11 -+#define CMT_WAIT 12 -+#define CMT_SOFTRESET 13 -+ -+/* USB PD Data Message Types */ -+#define DATAMESSAGE 1 -+#define DMT_SOURCECAPABILITIES 1 -+#define DMT_REQUEST 2 -+#define DMT_BIST 3 -+#define DMT_SINKCAPABILITIES 4 -+#define DMT_VENDERDEFINED 15 -+ -+/* VDM Command Types */ -+#define VDM_DISCOVERY_ID 0X01 -+#define VDM_DISCOVERY_SVIDS 0X02 -+#define VDM_DISCOVERY_MODES 0X03 -+#define VDM_ENTER_MODE 0X04 -+#define VDM_EXIT_MODE 0X05 -+#define VDM_ATTENTION 0X06 -+#define VDM_DP_STATUS_UPDATE 0X10 -+#define VDM_DP_CONFIG 0X11 -+ -+#define VDM_TYPE_INIT 0 -+#define VDM_TYPE_ACK 1 -+#define VDM_TYPE_NACK 2 -+#define VDM_TYPE_BUSY 3 -+ -+/* 200ms at least, 1 cycle about 6ms */ -+#define N_DEBOUNCE_CNT 33 -+#define N_CAPS_COUNT 50 -+#define N_HARDRESET_COUNT 0 -+ -+#define T_NO_RESPONSE 5000 -+#define T_SRC_RECOVER 830 -+#define T_TYPEC_SEND_SOURCECAP 100 -+#define T_SENDER_RESPONSE 30 -+#define T_SRC_TRANSITION 30 -+#define T_TYPEC_SINK_WAIT_CAP 500 -+#define T_PS_TRANSITION 500 -+#define T_BMC_TIMEOUT 5 -+#define T_PS_HARD_RESET_MAX 35 -+#define T_SAFE_0V 650 -+#define T_SRC_TURN_ON 275 -+#define T_SRC_RECOVER_MAX 1000 -+#define T_PD_SOURCE_OFF 920 -+#define T_PD_SOURCE_ON 480 -+#define T_PD_SWAP_SOURCE_START 20 -+#define T_PD_VCONN_SRC_ON 100 -+#define T_PD_TRY_DRP 75 -+ -+#define T_NO_TRIGGER 500 -+#define T_DISABLED 0xffff -+ -+#define PD_HEADER_CNT(header) (((header) >> 12) & 7) -+#define PD_HEADER_TYPE(header) ((header) & 0xF) -+#define PD_HEADER_ID(header) (((header) >> 9) & 7) -+ -+#define VDM_HEADER_TYPE(header) (((header) >> 6) & 3) -+#define VDMHEAD_CMD_TYPE_MASK (3 << 6) -+#define VDMHEAD_CMD_MASK (0x1f << 0) -+#define VDMHEAD_STRUCT_TYPE_MASK BIT(15) -+ -+#define GET_VDMHEAD_CMD_TYPE(head) ((head & VDMHEAD_CMD_TYPE_MASK) >> 6) -+#define GET_VDMHEAD_CMD(head) (head & VDMHEAD_CMD_MASK) -+#define GET_VDMHEAD_STRUCT_TYPE(head) ((head & VDMHEAD_STRUCT_TYPE_MASK) >> 15) -+ -+#define DP_STATUS_MASK 0x000000ff -+#define DP_STATUS_HPD_STATE BIT(7) -+ -+#define GET_DP_STATUS(status) (status & DP_STATUS_MASK) -+#define GET_DP_STATUS_HPD(status) ((status & DP_STATUS_HPD_STATE) >> 7) -+ -+#define VDM_IDHEAD_USBVID_MASK (0xffff << 0) -+#define VDM_IDHEAD_MODALSUPPORT_MASK BIT(26) -+#define VDM_IDHEAD_PRODUCTTYPE (7 << 27) -+#define VDM_IDHEAD_USBDEVICE BIT(30) -+#define VDM_IDHEAD_USBHOST BIT(30) -+ -+#define CAP_POWER_TYPE(PDO) ((PDO >> 30) & 3) -+#define CAP_FPDO_VOLTAGE(PDO) ((PDO >> 10) & 0x3ff) -+#define CAP_VPDO_VOLTAGE(PDO) ((PDO >> 20) & 0x3ff) -+#define CAP_FPDO_CURRENT(PDO) ((PDO >> 0) & 0x3ff) -+#define CAP_VPDO_CURRENT(PDO) ((PDO >> 0) & 0x3ff) -+ -+enum CC_ORIENTATION { -+ NONE, -+ CC1, -+ CC2, -+}; -+ -+enum typec_cc_polarity { -+ TYPEC_POLARITY_CC1, -+ TYPEC_POLARITY_CC2, -+}; -+ -+enum CC_MODE { -+ CC_PULL_UP, -+ CC_PULL_DOWN, -+ CC_PULL_NONE, -+}; -+ -+enum typec_power_role { -+ POWER_ROLE_SINK = 0, -+ POWER_ROLE_SOURCE, -+}; -+ -+enum typec_data_role { -+ DATA_ROLE_UFP = 0, -+ DATA_ROLE_DFP, -+}; -+ -+struct notify_info { -+ enum CC_ORIENTATION orientation; -+ /* 0 UFP : 1 DFP */ -+ enum typec_power_role power_role; -+ enum typec_data_role data_role; -+ -+ bool is_cc_connected; -+ bool is_pd_connected; -+ -+ bool is_enter_mode; -+ int pin_assignment_support; -+ int pin_assignment_def; -+ bool attention; -+ u32 dp_status; -+ u32 dp_caps; -+}; -+ -+enum tx_state { -+ tx_idle, -+ tx_busy, -+ tx_failed, -+ tx_success -+}; -+ -+struct PD_CAP_INFO { -+ u32 peak_current; -+ u32 specification_revision; -+ u32 externally_powered; -+ u32 usb_suspend_support; -+ u32 usb_communications_cap; -+ u32 dual_role_power; -+ u32 data_role_swap; -+ u32 supply_type; -+}; -+ -+struct fusb30x_chip { -+ struct i2c_client *client; -+ struct device *dev; -+ struct regmap *regmap; -+ struct work_struct work; -+ struct workqueue_struct *fusb30x_wq; -+ struct hrtimer timer_state_machine; -+ struct hrtimer timer_mux_machine; -+ struct PD_CAP_INFO pd_cap_info; -+ struct notify_info notify; -+ struct notify_info notify_cmp; -+ struct extcon_dev *extcon; -+ enum connection_state conn_state; -+ struct gpio_desc *gpio_vbus_5v; -+ struct gpio_desc *gpio_vbus_other; -+ struct gpio_desc *gpio_int; -+ struct gpio_desc *gpio_discharge; -+ int timer_state; -+ int timer_mux; -+ int port_num; -+ u32 work_continue; -+ spinlock_t irq_lock; -+ int gpio_int_irq; -+ int enable_irq; -+ -+ /* -+ * --------------------------------- -+ * | role 0x03 << 2, | cc_use 0x03 | -+ * | src 1 << 2, | cc1 1 | -+ * | snk 2 << 2, | cc2 2 | -+ * --------------------------------- -+ */ -+ u8 cc_state; -+ int cc1; -+ int cc2; -+ enum typec_cc_polarity cc_polarity; -+ u8 val_tmp; -+ u8 debounce_cnt; -+ int sub_state; -+ int caps_counter; -+ u32 send_load[7]; -+ u32 rec_load[7]; -+ u16 send_head; -+ u16 rec_head; -+ int msg_id; -+ enum tx_state tx_state; -+ int hardrst_count; -+ u32 source_power_supply[7]; -+ /* 50mv unit */ -+ u32 source_max_current[7]; -+ /* 10ma uint*/ -+ int pos_power; -+ /* -+ * if PartnerCap[0] == 0xffffffff -+ * show Partner Device do not support supply -+ */ -+ u32 partner_cap[7]; -+ int n_caps_used; -+ int vdm_state; -+ int vdm_substate; -+ int vdm_send_state; -+ u16 vdm_svid[12]; -+ int vdm_svid_num; -+ u32 vdm_id; -+ u8 chip_id; -+ bool vconn_enabled; -+ bool is_pd_support; -+ int pd_output_vol; -+ int pd_output_cur; -+ int cc_meas_high; -+ int cc_meas_low; -+ bool vbus_begin; -+ -+ enum role_mode role; -+ bool vconn_supported; -+ bool try_role_complete; -+ enum role_mode try_role; -+}; -+ -+#endif /* FUSB302_H */ -+ diff --git a/patch/kernel/archive/media-6.0/00550-add-driver-for-Motorcomm-YT85xx+PHYs.patch b/patch/kernel/archive/media-6.0/00550-add-driver-for-Motorcomm-YT85xx+PHYs.patch deleted file mode 100644 index dc98bcf6d..000000000 --- a/patch/kernel/archive/media-6.0/00550-add-driver-for-Motorcomm-YT85xx+PHYs.patch +++ /dev/null @@ -1,2202 +0,0 @@ -From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001 -From: baiywt -Date: Fri, 18 Feb 2022 16:38:43 +0800 -Subject: [PATCH] Add yt8531c support. -Adapted from orangepi-xunlong/openwrt - 600-Add-yt8531c-support.patch by schwar3kat ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/motorcomm.c | 1540 +++++++++++++++++++++++++++++++++ - drivers/net/phy/yt8614-phy.h | 491 +++++++++++ - include/linux/motorcomm_phy.h | 119 +++ - 5 files changed, 2156 insertions(+) - create mode 100644 drivers/net/phy/motorcomm.c - create mode 100644 drivers/net/phy/yt8614-phy.h - create mode 100644 include/linux/motorcomm_phy.h - -diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig -index ce030fcb1..ff4861847 100644 ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -297,6 +297,11 @@ config MICROSEMI_PHY - help - Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs - -+config MOTORCOMM_PHY -+ tristate "Motorcomm PHYs" -+ help -+ Supports the YT8010, YT8510, YT8511, YT8512 YT8521 YT8531 PHYs. -+ - config NATIONAL_PHY - tristate "National Semiconductor PHYs" - help -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -new file mode 100644 -index 000000000..74eef3dfa ---- /dev/null -+++ b/drivers/net/phy/motorcomm.c -@@ -0,0 +1,1540 @@ -+/* -+ * drivers/net/phy/motorcomm.c -+ * -+ * Driver for Motorcomm PHYs -+ * -+ * Author: Leilei Zhao -+ * -+ * Copyright (c) 2019 Motorcomm, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * Support : Motorcomm Phys: -+ * Giga phys: yt8511, yt8521 -+ * 100/10 Phys : yt8512, yt8512b, yt8510 -+ * Automotive 100Mb Phys : yt8010 -+ * Automotive 100/10 hyper range Phys: yt8510 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifndef LINUX_VERSION_CODE -+#include -+#else -+#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -+#endif -+/*for wol, 20210604*/ -+#include -+ -+#include "yt8614-phy.h" -+ -+/**** configuration section begin ***********/ -+ -+/* if system depends on ethernet packet to restore from sleep, please define this macro to 1 -+ * otherwise, define it to 0. -+ */ -+#define SYS_WAKEUP_BASED_ON_ETH_PKT 1 -+ -+/* to enable system WOL of phy, please define this macro to 1 -+ * otherwise, define it to 0. -+ */ -+#define YTPHY_ENABLE_WOL 0 -+ -+/* some GMAC need clock input from PHY, for eg., 125M, please enable this macro -+ * by degault, it is set to 0 -+ * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1 -+ */ -+#define GMAC_CLOCK_INPUT_NEEDED 1 -+ -+ -+#define YT8521_PHY_MODE_FIBER 1 //fiber mode only -+#define YT8521_PHY_MODE_UTP 2 //utp mode only -+#define YT8521_PHY_MODE_POLL 3 //fiber and utp, poll mode -+ -+/* please make choice according to system design -+ * for Fiber only system, please define YT8521_PHY_MODE_CURR 1 -+ * for UTP only system, please define YT8521_PHY_MODE_CURR 2 -+ * for combo system, please define YT8521_PHY_MODE_CURR 3 -+ */ -+#define YT8521_PHY_MODE_CURR 3 -+ -+/**** configuration section end ***********/ -+ -+ -+/* no need to change below */ -+ -+#if (YTPHY_ENABLE_WOL) -+#undef SYS_WAKEUP_BASED_ON_ETH_PKT -+#define SYS_WAKEUP_BASED_ON_ETH_PKT 1 -+#endif -+ -+/* workaround for 8521 fiber 100m mode */ -+static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32. -+static int link_mode_8614[4] = {0}; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32. -+ -+/* for multiple port phy, base phy address */ -+static unsigned int yt_mport_base_phy_addr = 0xff; //0xff: invalid; for 8618 -+static unsigned int yt_mport_base_phy_addr_8614 = 0xff; //0xff: invalid; -+ -+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr); -+int yt8511_config_out_125m(struct mii_bus *bus, int phy_id); -+ -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(5,0,0) ) -+int genphy_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ printk (KERN_INFO "yzhang..read phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id); -+ -+ if(phydev->phy_id == 0x4f51e91b) -+ { -+ printk (KERN_INFO "yzhang..get YT8511, abt to set 125m clk out, phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id); -+ ret = yt8511_config_out_125m(phydev->mdio.bus, phydev->mdio.addr); -+ printk (KERN_INFO "yzhang..8511 set 125m clk out, reg=%#04x\n",phydev->mdio.bus->read(phydev->mdio.bus,phydev->mdio.addr,0x1f)/*double check as delay*/); -+ if (ret<0) -+ printk (KERN_INFO "yzhang..failed to set 125m clk out, ret=%d\n",ret); -+ -+ phy_yt8531_led_fixup(phydev->mdio.bus, phydev->mdio.addr); -+ } -+ return genphy_read_abilities(phydev); -+} -+#endif -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+static int ytphy_config_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif -+ -+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = phy_write(phydev, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ -+static int yt8010_config_aneg(struct phy_device *phydev) -+{ -+ phydev->speed = SPEED_100; -+ return 0; -+} -+ -+static int yt8512_clk_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_CONTROL1_RMII_EN; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, MII_BMCR); -+ if (val < 0) -+ return val; -+ -+ val |= YT_SOFTWARE_RESET; -+ ret = phy_write(phydev, MII_BMCR, val); -+ -+ return ret; -+} -+ -+static int yt8512_led_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int mask; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED0_ACT_BLK_IND; -+ -+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | -+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | -+ YT8512_LED0_BT_ON_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); -+ if (val < 0) -+ return val; -+ -+ val |= YT8512_LED1_BT_ON_EN; -+ -+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; -+ val &= ~mask; -+ -+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); -+ -+ return ret; -+} -+ -+static int yt8512_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ ret = yt8512_clk_init(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = yt8512_led_init(phydev); -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); -+ -+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ return ret; -+} -+ -+static int yt8512_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ int speed, speed_mode, duplex; -+ -+ ret = genphy_update_link(phydev); -+ if (ret) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; -+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ case 3: -+ default: -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ speed = -1; -+#else -+ speed = SPEED_UNKNOWN; -+#endif -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ -+ return 0; -+} -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+#if 0 -+int yt8521_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ return ret; -+ } -+ -+ return 0; -+} -+#else -+/* qingsong feedback 2 genphy_soft_reset will cause problem. -+ * and this is the reduction version -+ */ -+int yt8521_soft_reset(struct phy_device *phydev) -+{ -+ int ret, val; -+ -+ val = ytphy_read_ext(phydev, 0xa001); -+ ytphy_write_ext(phydev, 0xa001, (val & ~0x8000)); -+ -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+#endif -+ -+#endif -+ -+#if GMAC_CLOCK_INPUT_NEEDED -+static int ytphy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum) -+{ -+ int ret; -+ int val; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ val = bus->read(bus, phy_id, REG_DEBUG_DATA); -+ -+ return val; -+} -+ -+static int ytphy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val) -+{ -+ int ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum); -+ if (ret < 0) -+ return ret; -+ -+ ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val); -+ -+ return ret; -+} -+ -+int yt8511_config_dis_txdelay(struct mii_bus *bus, int phy_id) -+{ -+ int ret; -+ int val; -+ -+ /* disable auto sleep */ -+ val = ytphy_mii_rd_ext(bus, phy_id, 0x27); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(15)); -+ -+ ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = ytphy_mii_rd_ext(bus, phy_id, 0xc); -+ if (val < 0) -+ return val; -+ -+ /* ext reg 0xc b[7:4] -+ Tx Delay time = 150ps * N - 250ps -+ */ -+ val &= ~(0xf << 4); -+ ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val); -+ printk("yt8511_config_dis_txdelay..phy txdelay, val=%#08x\n",val); -+ -+ return ret; -+} -+ -+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr) -+{ -+ printk("%s in\n", __func__); -+ -+ ytphy_mii_wr_ext(bus, addr, 0xa00d, 0x670); -+ ytphy_mii_wr_ext(bus, addr, 0xa00e, 0x2070); -+ ytphy_mii_wr_ext(bus, addr, 0xa00f, 0x7e); -+ -+ return 0; -+} -+ -+int yt8511_config_out_125m(struct mii_bus *bus, int addr) -+{ -+ int ret; -+ int val; -+ -+ mdelay(50); -+ ret = ytphy_mii_wr_ext(bus, addr, 0xa012, 0xd0); -+ -+ mdelay(100); -+ val = ytphy_mii_rd_ext(bus, addr, 0xa012); -+ -+ if(val != 0xd0) -+ { -+ printk("yt8511_config_out_125m error\n"); -+ return -1; -+ } -+ -+ /* disable auto sleep */ -+ val = ytphy_mii_rd_ext(bus, addr, 0x27); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(15)); -+ -+ ret = ytphy_mii_wr_ext(bus, addr, 0x27, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ val = ytphy_mii_rd_ext(bus, addr, 0xc); -+ if (val < 0) -+ return val; -+ -+ /* ext reg 0xc.b[2:1] -+ 00-----25M from pll; -+ 01---- 25M from xtl;(default) -+ 10-----62.5M from pll; -+ 11----125M from pll(here set to this value) -+ */ -+ val |= (3 << 1); -+ ret = ytphy_mii_wr_ext(bus, addr, 0xc, val); -+ printk("yt8511_config_out_125m, phy clk out, val=%#08x\n",val); -+ -+#if 0 -+ /* for customer, please enable it based on demand. -+ * configure to master -+ */ -+ val = bus->read(bus, phy_id, 0x9/*master/slave config reg*/); -+ val |= (0x3<<11); //to be manual config and force to be master -+ ret = bus->write(bus, phy_id, 0x9, val); //take effect until phy soft reset -+ if (ret < 0) -+ return ret; -+ -+ printk("yt8511_config_out_125m, phy to be master, val=%#08x\n",val); -+#endif -+ -+ return ret; -+} -+ -+EXPORT_SYMBOL(yt8511_config_out_125m); -+ -+static int yt8511_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ -+ return ret; -+} -+#endif /*GMAC_CLOCK_INPUT_NEEDED*/ -+ -+#if (YTPHY_ENABLE_WOL) -+static int ytphy_switch_reg_space(struct phy_device *phydev, int space) -+{ -+ int ret; -+ -+ if (space == YTPHY_REG_SPACE_UTP){ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ }else{ -+ ret = ytphy_write_ext(phydev, 0xa000, 2); -+ } -+ -+ return ret; -+} -+ -+static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg) -+{ -+ int ret=0; -+ int val=0; -+ -+ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG); -+ if (val < 0) -+ return val; -+ -+ if(wol_cfg.enable) { -+ val |= YTPHY_WOL_CFG_EN; -+ -+ if(wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) { -+ val &= ~YTPHY_WOL_CFG_TYPE; -+ val &= ~YTPHY_WOL_CFG_INTR_SEL; -+ } else if(wol_cfg.type == YTPHY_WOL_TYPE_PULSE) { -+ val |= YTPHY_WOL_CFG_TYPE; -+ val |= YTPHY_WOL_CFG_INTR_SEL; -+ -+ if(wol_cfg.width == YTPHY_WOL_WIDTH_84MS) { -+ val &= ~YTPHY_WOL_CFG_WIDTH1; -+ val &= ~YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_168MS) { -+ val |= YTPHY_WOL_CFG_WIDTH1; -+ val &= ~YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_336MS) { -+ val &= ~YTPHY_WOL_CFG_WIDTH1; -+ val |= YTPHY_WOL_CFG_WIDTH2; -+ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_672MS) { -+ val |= YTPHY_WOL_CFG_WIDTH1; -+ val |= YTPHY_WOL_CFG_WIDTH2; -+ } -+ } -+ } else { -+ val &= ~YTPHY_WOL_CFG_EN; -+ val &= ~YTPHY_WOL_CFG_INTR_SEL; -+ } -+ -+ ret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) -+{ -+ int val = 0; -+ -+ wol->supported = WAKE_MAGIC; -+ wol->wolopts = 0; -+ -+ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG); -+ if (val < 0) -+ return; -+ -+ if (val & YTPHY_WOL_CFG_EN) -+ wol->wolopts |= WAKE_MAGIC; -+ -+ return; -+} -+ -+static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) -+{ -+ int ret, pre_page, val; -+ ytphy_wol_cfg_t wol_cfg; -+ struct net_device *p_attached_dev = phydev->attached_dev; -+ -+ memset(&wol_cfg,0,sizeof(ytphy_wol_cfg_t)); -+ pre_page = ytphy_read_ext(phydev, 0xa000); -+ if (pre_page < 0) -+ return pre_page; -+ -+ /* Switch to phy UTP page */ -+ ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP); -+ if (ret < 0) -+ return ret; -+ -+ if (wol->wolopts & WAKE_MAGIC) { -+ -+ /* Enable the WOL interrupt */ -+ val = phy_read(phydev, YTPHY_UTP_INTR_REG); -+ val |= YTPHY_WOL_INTR; -+ ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val); -+ if (ret < 0) -+ return ret; -+ -+ /* Set the WOL config */ -+ wol_cfg.enable = 1; //enable -+ wol_cfg.type= YTPHY_WOL_TYPE_PULSE; -+ wol_cfg.width= YTPHY_WOL_WIDTH_672MS; -+ ret = ytphy_wol_en_cfg(phydev, wol_cfg); -+ if (ret < 0) -+ return ret; -+ -+ /* Store the device address for the magic packet */ -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2, -+ ((p_attached_dev->dev_addr[0] << 8) | -+ p_attached_dev->dev_addr[1])); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1, -+ ((p_attached_dev->dev_addr[2] << 8) | -+ p_attached_dev->dev_addr[3])); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0, -+ ((p_attached_dev->dev_addr[4] << 8) | -+ p_attached_dev->dev_addr[5])); -+ if (ret < 0) -+ return ret; -+ } else { -+ wol_cfg.enable = 0; //disable -+ wol_cfg.type= YTPHY_WOL_TYPE_MAX; -+ wol_cfg.width= YTPHY_WOL_WIDTH_MAX; -+ ret = ytphy_wol_en_cfg(phydev, wol_cfg); -+ if (ret < 0) -+ return ret; -+ } -+ -+ /* Recover to previous register space page */ -+ ret = ytphy_switch_reg_space(phydev, pre_page); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+#endif /*(YTPHY_ENABLE_WOL)*/ -+ -+static int yt8521_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ phydev->irq = PHY_POLL; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ /* disable auto sleep */ -+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); -+ if (val < 0) -+ return val; -+ -+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); -+ -+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = ytphy_read_ext(phydev, 0xc); -+ if (val < 0) -+ return val; -+ val &= ~(1 << 12); -+ ret = ytphy_write_ext(phydev, 0xc, val); -+ if (ret < 0) -+ return ret; -+ -+ printk (KERN_INFO "yt8521_config_init, 8521 init call out.\n"); -+ return ret; -+} -+ -+/* -+ * for fiber mode, there is no 10M speed mode and -+ * this function is for this purpose. -+ */ -+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp) -+{ -+ int speed_mode, duplex; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ int speed = -1; -+#else -+ int speed = SPEED_UNKNOWN; -+#endif -+ -+ duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT; -+ speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT; -+ switch (speed_mode) { -+ case 0: -+ if (is_utp) -+ speed = SPEED_10; -+ break; -+ case 1: -+ speed = SPEED_100; -+ break; -+ case 2: -+ speed = SPEED_1000; -+ break; -+ case 3: -+ break; -+ default: -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ speed = -1; -+#else -+ speed = SPEED_UNKNOWN; -+#endif -+ break; -+ } -+ -+ phydev->speed = speed; -+ phydev->duplex = duplex; -+ //printk (KERN_INFO "yt8521_adjust_status call out,regval=0x%04x,mode=%s,speed=%dm...\n", val,is_utp?"utp":"fiber", phydev->speed); -+ -+ return 0; -+} -+ -+/* -+ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and -+ * this function handles this case and return 1 per linux kernel's polling. -+ */ -+int yt8521_aneg_done (struct phy_device *phydev) -+{ -+ -+ //printk("yt8521_aneg_done callin,speed=%dm,linkmoded=%d\n", phydev->speed,link_mode_8521); -+ -+ if((32 == link_mode_8521) && (SPEED_100 == phydev->speed)) -+ { -+ return 1/*link_mode_8521*/; -+ } -+ -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ return genphy_aneg_done(phydev); -+#else -+ return 1; -+#endif -+} -+ -+static int yt8521_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ volatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ /* reading UTP */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ link_mode_8521 = 1; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ /* reading Fiber */ -+ ret = ytphy_write_ext(phydev, 0xa000, 2); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ //note: below debug information is used to check multiple PHy ports. -+ //printk (KERN_INFO "yt8521_read_status, fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev); -+ -+ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case -+ * this is important for Linux kernel for that, missing linkdown event will cause problem. -+ */ -+ yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR); -+ yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR); -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val)) -+ { -+ link = 0; -+ printk (KERN_INFO "yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8521_fiber_latch_val,yt8521_fiber_curr_val); -+ } -+ -+ if (link) { -+ link_fiber = 1; -+ yt8521_adjust_status(phydev, val, 0); -+ link_mode_8521 = 32; //fiber mode -+ -+ -+ } else { -+ link_fiber = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ link_mode_8521 = 0; -+ } -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ if (link_utp) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ } -+#endif -+ -+ //printk (KERN_INFO "yzhang..8521 read status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8521 ); -+ return 0; -+} -+ -+int yt8521_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8521_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ int ret; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ /* disable auto sleep */ -+ value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); -+ if (value < 0) -+ return value; -+ -+ value &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); -+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value); -+ if (ret < 0) -+ return ret; -+ -+ /* enable RXC clock when no wire plug */ -+ value = ytphy_read_ext(phydev, 0xc); -+ if (value < 0) -+ return value; -+ value &= ~(1 << 12); -+ ret = ytphy_write_ext(phydev, 0xc, value); -+ if (ret < 0) -+ return ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ ytphy_write_ext(phydev, 0xa000, 0); -+#endif -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+int yt8618_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+int yt8614_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* utp */ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* qsgmii */ -+ ytphy_write_ext(phydev, 0xa000, 2); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode -+ return ret; -+ } -+ -+ /* sgmii */ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) { -+ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode -+ return ret; -+ } -+ -+ return 0; -+} -+ -+#endif -+ -+static int yt8618_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ int val; -+ -+ phydev->irq = PHY_POLL; -+ -+ if(0xff == yt_mport_base_phy_addr) -+ /* by default, we think the first phy should be the base phy addr. for mul */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ { -+ yt_mport_base_phy_addr = phydev->addr; -+ }else if (yt_mport_base_phy_addr > phydev->addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->addr); -+ } -+#else -+ { -+ yt_mport_base_phy_addr = phydev->mdio.addr; -+ }else if (yt_mport_base_phy_addr > phydev->mdio.addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->mdio.addr); -+ } -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ ret = ytphy_config_init(phydev); -+#else -+ ret = genphy_config_init(phydev); -+#endif -+ if (ret < 0) -+ return ret; -+ -+ /* for utp to optimize signal */ -+ ret = ytphy_write_ext(phydev, 0x41, 0x33); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x42, 0x66); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x43, 0xaa); -+ if (ret < 0) -+ return ret; -+ ret = ytphy_write_ext(phydev, 0x44, 0xd0d); -+ if (ret < 0) -+ return ret; -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ if((phydev->addr > yt_mport_base_phy_addr) && ((2 == phydev->addr - yt_mport_base_phy_addr) || (5 == phydev->addr - yt_mport_base_phy_addr))) -+#else -+ if((phydev->mdio.addr > yt_mport_base_phy_addr) && ((2 == phydev->mdio.addr - yt_mport_base_phy_addr) || (5 == phydev->mdio.addr - yt_mport_base_phy_addr))) -+#endif -+ { -+ ret = ytphy_write_ext(phydev, 0x44, 0x2929); -+ if (ret < 0) -+ return ret; -+ } -+ -+ val = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, val | BMCR_RESET); -+ -+ printk (KERN_INFO "yt8618_config_init call out.\n"); -+ return ret; -+} -+ -+static int yt8614_config_init(struct phy_device *phydev) -+{ -+ int ret = 0; -+ -+ phydev->irq = PHY_POLL; -+ -+ if(0xff == yt_mport_base_phy_addr_8614) -+ /* by default, we think the first phy should be the base phy addr. for mul */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ { -+ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->addr; -+ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->addr); -+ } -+#else -+ { -+ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->mdio.addr; -+ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->mdio.addr) { -+ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->mdio.addr); -+ } -+#endif -+ return ret; -+} -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->addr) ? 0 : (unsigned int)((phydev)->addr) - yt_mport_base_phy_addr_8614) -+#else -+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->mdio.addr) ? 0 : (unsigned int)((phydev)->mdio.addr) - yt_mport_base_phy_addr_8614) -+#endif -+ -+int yt8618_aneg_done (struct phy_device *phydev) -+{ -+ -+ return genphy_aneg_done(phydev); -+} -+ -+int yt8614_aneg_done (struct phy_device *phydev) -+{ -+ int port = yt8614_get_port_from_phydev(phydev); -+ -+ /*it should be used for 8614 fiber*/ -+ if((32 == link_mode_8614[port]) && (SPEED_100 == phydev->speed)) -+ { -+ return 1; -+ } -+ -+ return genphy_aneg_done(phydev); -+} -+ -+static int yt8614_read_status(struct phy_device *phydev) -+{ -+ //int i; -+ int ret; -+ volatile int val, yt8614_fiber_latch_val, yt8614_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ int port = yt8614_get_port_from_phydev(phydev); -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ /* switch to utp and reading regs */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ // here is same as 8521 and re-use the function; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+#endif //(YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ /* reading Fiber/sgmii */ -+ ret = ytphy_write_ext(phydev, 0xa000, 3); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ //printk (KERN_INFO "yzhang..8614 read fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev); -+ -+ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case */ -+ yt8614_fiber_latch_val = phy_read(phydev, MII_BMSR); -+ yt8614_fiber_curr_val = phy_read(phydev, MII_BMSR); -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if((link) && (yt8614_fiber_latch_val != yt8614_fiber_curr_val)) -+ { -+ link = 0; -+ printk (KERN_INFO "yt8614_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8614_fiber_latch_val,yt8614_fiber_curr_val); -+ } -+ -+ if (link) { -+ link_fiber = 1; -+ yt8521_adjust_status(phydev, val, 0); -+ link_mode_8614[port] = 32; //fiber mode -+ -+ -+ } else { -+ link_fiber = 0; -+ } -+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ link_mode_8614[port] = 0; -+ } -+ -+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) -+ if (link_utp) { -+ ytphy_write_ext(phydev, 0xa000, 0); -+ } -+#endif -+ //printk (KERN_INFO "yt8614_read_status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8614[port] ); -+ -+ return 0; -+} -+ -+static int yt8618_read_status(struct phy_device *phydev) -+{ -+ int ret; -+ volatile int val; //maybe for 8614 yt8521_fiber_latch_val, yt8521_fiber_curr_val; -+ volatile int link; -+ int link_utp = 0, link_fiber = 0; -+ -+ /* switch to utp and reading regs */ -+ ret = ytphy_write_ext(phydev, 0xa000, 0); -+ if (ret < 0) -+ return ret; -+ -+ val = phy_read(phydev, REG_PHY_SPEC_STATUS); -+ if (val < 0) -+ return val; -+ -+ link = val & (BIT(YT8521_LINK_STATUS_BIT)); -+ if (link) { -+ link_utp = 1; -+ yt8521_adjust_status(phydev, val, 1); -+ } else { -+ link_utp = 0; -+ } -+ -+ if (link_utp || link_fiber) { -+ phydev->link = 1; -+ } else { -+ phydev->link = 0; -+ } -+ -+ return 0; -+} -+ -+int yt8618_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8618_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8614_suspend(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+int yt8614_resume(struct phy_device *phydev) -+{ -+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT) -+ int value; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_lock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 3); -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); -+ -+ ytphy_write_ext(phydev, 0xa000, 0); -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ mutex_unlock(&phydev->lock); -+#else -+ /* no need lock/unlock in 4.19 */ -+#endif -+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/ -+ -+ return 0; -+} -+ -+ -+static struct phy_driver ytphy_drvs[] = { -+ { -+ .phy_id = PHY_ID_YT8010, -+ .name = "YT8010 Automotive Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = yt8010_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8510, -+ .name = "YT8510 100/10Mb Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ }, { -+ .phy_id = PHY_ID_YT8511, -+ .name = "YT8511 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_GBIT_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if GMAC_CLOCK_INPUT_NEEDED -+ .config_init = yt8511_config_init, -+#else -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+#endif -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512, -+ .name = "YT8512 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8512B, -+ .name = "YT8512B Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+ .config_init = yt8512_config_init, -+ .read_status = yt8512_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_YT8521, -+ .name = "YT8521 Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8521_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8521_aneg_done, -+#endif -+ .config_init = yt8521_config_init, -+ .read_status = yt8521_read_status, -+ .suspend = yt8521_suspend, -+ .resume = yt8521_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ },{ -+ /* same as 8521 */ -+ .phy_id = PHY_ID_YT8531S, -+ .name = "YT8531S Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8521_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8521_aneg_done, -+#endif -+ .config_init = yt8521_config_init, -+ .read_status = yt8521_read_status, -+ .suspend = yt8521_suspend, -+ .resume = yt8521_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ }, { -+ /* same as 8511 */ -+ .phy_id = PHY_ID_YT8531, -+ .name = "YT8531 Gigabit Ethernet", -+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+ .config_init = ytphy_config_init, -+#else -+ .config_init = genphy_config_init, -+#endif -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+#if (YTPHY_ENABLE_WOL) -+ .get_wol = &ytphy_get_wol, -+ .set_wol = &ytphy_set_wol, -+#endif -+ }, { -+ .phy_id = PHY_ID_YT8618, -+ .name = "YT8618 Ethernet", -+ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8618_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8618_aneg_done, -+#endif -+ .config_init = yt8618_config_init, -+ .read_status = yt8618_read_status, -+ .suspend = yt8618_suspend, -+ .resume = yt8618_resume, -+ }, { -+ .phy_id = PHY_ID_YT8614, -+ .name = "YT8614 Ethernet", -+ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK_8614, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) ) -+ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES, -+#endif -+ .flags = PHY_POLL, -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+#else -+ .soft_reset = yt8614_soft_reset, -+#endif -+ .config_aneg = genphy_config_aneg, -+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) ) -+ .aneg_done = yt8614_aneg_done, -+#endif -+ .config_init = yt8614_config_init, -+ .read_status = yt8614_read_status, -+ .suspend = yt8614_suspend, -+ .resume = yt8614_resume, -+ }, -+}; -+ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) -+static int ytphy_drivers_register(struct phy_driver* phy_drvs, int size) -+{ -+ int i, j; -+ int ret; -+ -+ for (i = 0; i < size; i++) { -+ ret = phy_driver_register(&phy_drvs[i]); -+ if (ret) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ for (j = 0; j < i; j++) -+ phy_driver_unregister(&phy_drvs[j]); -+ -+ return ret; -+} -+ -+static void ytphy_drivers_unregister(struct phy_driver* phy_drvs, int size) -+{ -+ int i; -+ -+ for (i = 0; i < size; i++) { -+ phy_driver_unregister(&phy_drvs[i]); -+ } -+} -+ -+static int __init ytphy_init(void) -+{ -+ printk("motorcomm phy register\n"); -+ return ytphy_drivers_register(ytphy_drvs, ARRAY_SIZE(ytphy_drvs)); -+} -+ -+static void __exit ytphy_exit(void) -+{ -+ printk("motorcomm phy unregister\n"); -+ ytphy_drivers_unregister(ytphy_drvs, ARRAY_SIZE(ytphy_drvs)); -+} -+ -+module_init(ytphy_init); -+module_exit(ytphy_exit); -+#else -+/* for linux 4.x */ -+module_phy_driver(ytphy_drvs); -+#endif -+ -+MODULE_DESCRIPTION("Motorcomm PHY driver"); -+MODULE_AUTHOR("Leilei Zhao"); -+MODULE_LICENSE("GPL"); -+ -+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { -+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, -+ { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK }, -+ { PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK }, -+ { PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK }, -+ { PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); -+ -+ -diff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h -new file mode 100644 -index 000000000..56a398338 ---- /dev/null -+++ b/drivers/net/phy/yt8614-phy.h -@@ -0,0 +1,491 @@ -+#ifndef _PHY_H_ -+#define _PHY_H_ -+ -+ -+/* configuration for driver */ -+ -+#define YT8614_MAX_LPORT_ID 3 -+ -+#define YT8614_PHY_MODE_FIBER 1 //fiber mode only -+#define YT8614_PHY_MODE_UTP 2 //utp mode only -+#define YT8614_PHY_MODE_POLL 3 //fiber and utp, poll mode -+ -+/* please make choice according to system design -+ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1 -+ * for UTP only system, please define YT8614_PHY_MODE_CURR 2 -+ * for combo system, please define YT8614_PHY_MODE_CURR 3 -+ */ -+#define YT8614_PHY_MODE_CURR 3 -+ -+ -+ -+/* pls dont modify below lines */ -+ -+#define PHY_ID_YT8614 0x4F51E899 //serdes -+#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff -+ -+#ifndef BOOL -+#define BOOL unsigned int -+#endif -+ -+#ifndef FALSE -+#define FALSE 0 -+#endif -+ -+#ifndef TRUE -+#define TRUE 1 -+#endif -+ -+#ifndef SPEED_1000M -+#define SPEED_1000M 2 -+#endif -+#ifndef SPEED_100M -+#define SPEED_100M 1 -+#endif -+#ifndef SPEED_10M -+#define SPEED_10M 0 -+#endif -+ -+#ifndef SPEED_UNKNOWN -+#define SPEED_UNKNOWN 0xffff -+#endif -+ -+#ifndef DUPLEX_FULL -+#define DUPLEX_FULL 1 -+#endif -+#ifndef DUPLEX_HALF -+#define DUPLEX_HALF 0 -+#endif -+ -+#ifndef BIT -+#define BIT(n) (0x1<<(n)) -+#endif -+#ifndef s32 -+typedef int s32; -+typedef unsigned int u32; -+typedef unsigned short u16; -+typedef unsigned char u8; -+#endif -+ -+#ifndef REG_PHY_SPEC_STATUS -+#define REG_PHY_SPEC_STATUS 0x11 -+#define REG_DEBUG_ADDR_OFFSET 0x1e -+#define REG_DEBUG_DATA 0x1f -+#endif -+ -+/**********YT8614************************************************/ -+ -+#define YT8614_SMI_SEL_PHY 0x0 -+#define YT8614_SMI_SEL_SDS_QSGMII 0x02 -+#define YT8614_SMI_SEL_SDS_SGMII 0x03 -+ -+/* yt8614 register type */ -+#define YT8614_TYPE_COMMON 0x01 -+#define YT8614_TYPE_UTP_MII 0x02 -+#define YT8614_TYPE_UTP_EXT 0x03 -+#define YT8614_TYPE_LDS_MII 0x04 -+#define YT8614_TYPE_UTP_MMD 0x05 -+#define YT8614_TYPE_SDS_QSGMII_MII 0x06 -+#define YT8614_TYPE_SDS_SGMII_MII 0x07 -+#define YT8614_TYPE_SDS_QSGMII_EXT 0x08 -+#define YT8614_TYPE_SDS_SGMII_EXT 0x09 -+ -+/* YT8614 extended common register */ -+#define YT8614_REG_COM_SMI_MUX 0xA000 -+#define YT8614_REG_COM_SLED_CFG0 0xA001 -+#define YT8614_REG_COM_PHY_ID 0xA002 -+#define YT8614_REG_COM_CHIP_VER 0xA003 -+#define YT8614_REG_COM_SLED_CFG 0xA004 -+#define YT8614_REG_COM_MODE_CHG_RESET 0xA005 -+#define YT8614_REG_COM_SYNCE0_CFG 0xA006 -+#define YT8614_REG_COM_CHIP_MODE 0xA007 -+ -+#define YT8614_REG_COM_HIDE_SPEED 0xA009 -+ -+#define YT8614_REG_COM_SYNCE1_CFG 0xA00E -+ -+#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019 -+ -+ -+#define YT8614_REG_COM_HIDE_SEL1 0xA054 -+#define YT8614_REG_COM_HIDE_LED_CFG2 0xB8 -+#define YT8614_REG_COM_HIDE_LED_CFG3 0xB9 -+#define YT8614_REG_COM_HIDE_LED_CFG5 0xBB -+ -+#define YT8614_REG_COM_HIDE_LED_CFG4 0xBA //not used currently -+ -+#if 0 -+#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently -+#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061 -+#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062 -+#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063 -+#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064 -+#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065 -+#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066 -+#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067 -+#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068 -+#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069 -+#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A -+#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B -+#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C -+#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D -+#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E -+#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F -+#endif -+ -+#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070 -+#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071 -+#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072 -+#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073 -+#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074 -+#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075 -+#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076 -+#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077 -+ -+#define YT8614_REG_COM_PKG_CFG0 0xA0A0 -+#define YT8614_REG_COM_PKG_CFG1 0xA0A1 -+#define YT8614_REG_COM_PKG_CFG2 0xA0A2 -+#define YT8614_REG_COM_PKG_RX_VALID0 0xA0A3 -+#define YT8614_REG_COM_PKG_RX_VALID1 0xA0A4 -+#define YT8614_REG_COM_PKG_RX_OS0 0xA0A5 -+#define YT8614_REG_COM_PKG_RX_OS1 0xA0A6 -+#define YT8614_REG_COM_PKG_RX_US0 0xA0A7 -+#define YT8614_REG_COM_PKG_RX_US1 0xA0A8 -+#define YT8614_REG_COM_PKG_RX_ERR 0xA0A9 -+#define YT8614_REG_COM_PKG_RX_OS_BAD 0xA0AA -+#define YT8614_REG_COM_PKG_RX_FRAG 0xA0AB -+#define YT8614_REG_COM_PKG_RX_NOSFD 0xA0AC -+#define YT8614_REG_COM_PKG_TX_VALID0 0xA0AD -+#define YT8614_REG_COM_PKG_TX_VALID1 0xA0AE -+#define YT8614_REG_COM_PKG_TX_OS0 0xA0AF -+ -+#define YT8614_REG_COM_PKG_TX_OS1 0xA0B0 -+#define YT8614_REG_COM_PKG_TX_US0 0xA0B1 -+#define YT8614_REG_COM_PKG_TX_US1 0xA0B2 -+#define YT8614_REG_COM_PKG_TX_ERR 0xA0B3 -+#define YT8614_REG_COM_PKG_TX_OS_BAD 0xA0B4 -+#define YT8614_REG_COM_PKG_TX_FRAG 0xA0B5 -+#define YT8614_REG_COM_PKG_TX_NOSFD 0xA0B6 -+#define YT8614_REG_COM_PKG_CFG3 0xA0B7 -+#define YT8614_REG_COM_PKG_AZ_CFG 0xA0B8 -+#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9 -+ -+#define YT8614_REG_COM_MANU_HW_RESET 0xA0C0 -+ -+/* YT8614 UTP MII register: same as generic phy register definitions */ -+#define REG_MII_BMCR 0x00 /* Basic mode control register */ -+#define REG_MII_BMSR 0x01 /* Basic mode status register */ -+#define REG_MII_PHYSID1 0x02 /* PHYS ID 1 */ -+#define REG_MII_PHYSID2 0x03 /* PHYS ID 2 */ -+#define REG_MII_ADVERTISE 0x04 /* Advertisement control reg */ -+#define REG_MII_LPA 0x05 /* Link partner ability reg */ -+#define REG_MII_EXPANSION 0x06 /* Expansion register */ -+#define REG_MII_NEXT_PAGE 0x07 /* Next page register */ -+#define REG_MII_LPR_NEXT_PAGE 0x08 /* LPR next page register */ -+#define REG_MII_CTRL1000 0x09 /* 1000BASE-T control */ -+#define REG_MII_STAT1000 0x0A /* 1000BASE-T status */ -+ -+#define REG_MII_MMD_CTRL 0x0D /* MMD access control register */ -+#define REG_MII_MMD_DATA 0x0E /* MMD access data register */ -+ -+#define REG_MII_ESTATUS 0x0F /* Extended Status */ -+#define REG_MII_SPEC_CTRL 0x10 /* PHY specific func control */ -+#define REG_MII_SPEC_STATUS 0x11 /* PHY specific status */ -+#define REG_MII_INT_MASK 0x12 /* Interrupt mask register */ -+#define REG_MII_INT_STATUS 0x13 /* Interrupt status register */ -+#define REG_MII_DOWNG_CTRL 0x14 /* Speed auto downgrade control*/ -+#define REG_MII_RERRCOUNTER 0x15 /* Receive error counter */ -+ -+#define REG_MII_EXT_ADDR 0x1E /* Extended reg's address */ -+#define REG_MII_EXT_DATA 0x1F /* Extended reg's date */ -+ -+#ifndef MII_BMSR -+#define MII_BMSR REG_MII_BMSR -+#endif -+ -+#ifndef YT8614_SPEED_MODE_BIT -+#define YT8614_SPEED_MODE 0xc000 -+#define YT8614_DUPLEX 0x2000 -+#define YT8614_SPEED_MODE_BIT 14 -+#define YT8614_DUPLEX_BIT 13 -+#define YT8614_LINK_STATUS_BIT 10 -+ -+#endif -+ -+#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI 0x2000 -+ -+/* YT8614 UTP MMD register */ -+#define YT8614_REG_UTP_MMD_CTRL1 0x00 /* PCS control 1 register */ -+#define YT8614_REG_UTP_MMD_STATUS1 0x01 /* PCS status 1 register */ -+#define YT8614_REG_UTP_MMD_EEE_CTRL 0x14 /* EEE control and capability */ -+#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT 0x16 /* EEE wake error counter */ -+#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI 0x3C /* local device EEE ability */ -+#define YT8614_REG_UTP_MMD_EEE_LP_ABI 0x3D /* link partner EEE ability */ -+#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000 /* autoneg result of EEE */ -+ -+/* YT8614 UTP EXT register */ -+#define YT8614_REG_UTP_EXT_LPBK 0x0A -+#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27 -+#define YT8614_REG_UTP_EXT_DEBUG_MON1 0x5A -+#define YT8614_REG_UTP_EXT_DEBUG_MON2 0x5B -+#define YT8614_REG_UTP_EXT_DEBUG_MON3 0x5C -+#define YT8614_REG_UTP_EXT_DEBUG_MON4 0x5D -+ -+/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */ -+#define REG_SDS_BMCR 0x00 /* Basic mode control register */ -+#define REG_SDS_BMSR 0x01 /* Basic mode status register */ -+#define REG_SDS_PHYSID1 0x02 /* PHYS ID 1 */ -+#define REG_SDS_PHYSID2 0x03 /* PHYS ID 2 */ -+#define REG_SDS_ADVERTISE 0x04 /* Advertisement control reg */ -+#define REG_SDS_LPA 0x05 /* Link partner ability reg */ -+#define REG_SDS_EXPANSION 0x06 /* Expansion register */ -+#define REG_SDS_NEXT_PAGE 0x07 /* Next page register */ -+#define REG_SDS_LPR_NEXT_PAGE 0x08 /* LPR next page register */ -+ -+#define REG_SDS_ESTATUS 0x0F /* Extended Status */ -+#define REG_SDS_SPEC_STATUS 0x11 /* SDS specific status */ -+ -+#define REG_SDS_100FX_CFG 0x14 /* 100fx cfg */ -+#define REG_SDS_RERRCOUNTER 0x15 /* Receive error counter */ -+#define REG_SDS_LINT_FAIL_CNT 0x16 /* Lint fail counter mon */ -+ -+/* YT8614 SDS(5G) EXT register */ -+#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02 /* sds analog digital interface cfg */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06 /* sds prbs cfg2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07 /* sds prbs cfg2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ -+#define YT8614_REG_QSGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ -+#define YT8614_REG_QSGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ -+ -+/* YT8614 SDS(1.25G) EXT register */ -+#define YT8614_REG_SGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ -+#define YT8614_REG_SGMII_EXT_PRBS_CFG2 0x06 /* sds prbs cfg2 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ -+#define YT8614_REG_SGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ -+#define YT8614_REG_SGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ -+#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5 /* Fiber auto sensing */ -+ -+//////////////////////////////////////////////////////////////////// -+#define YT8614_MMD_DEV_ADDR1 0x1 -+#define YT8614_MMD_DEV_ADDR3 0x3 -+#define YT8614_MMD_DEV_ADDR7 0x7 -+#define YT8614_MMD_DEV_ADDR_NONE 0xFF -+ -+/**********YT8521S************************************************/ -+/* Basic mode control register(0x00) */ -+#define BMCR_RESV 0x003f /* Unused... */ -+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ -+#define BMCR_CTST 0x0080 /* Collision test */ -+#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -+#define BMCR_RESET 0x8000 /* Reset the DP83840 */ -+ -+/* Basic mode status register(0x01) */ -+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -+#define BMSR_JCD 0x0002 /* Jabber detected */ -+#define BMSR_LSTATUS 0x0004 /* Link status */ -+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -+#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -+#define BMSR_RESV 0x00c0 /* Unused... */ -+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -+#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ -+#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ -+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ -+ -+/* Advertisement control register(0x04) */ -+#define ADVERTISE_SLCT 0x001f /* Selector bits */ -+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ -+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ -+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ -+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ -+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ -+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ -+#define ADVERTISE_RESV 0x1000 /* Unused... */ -+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ -+ -+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) -+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ -+ ADVERTISE_100HALF | ADVERTISE_100FULL) -+ -+/* Link partner ability register(0x05) */ -+#define LPA_SLCT 0x001f /* Same as advertise selector */ -+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ -+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ -+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ -+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */ -+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -+#define LPA_PAUSE_CAP 0x0400 /* Can pause */ -+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ -+#define LPA_RESV 0x1000 /* Unused... */ -+#define LPA_RFAULT 0x2000 /* Link partner faulted */ -+#define LPA_LPACK 0x4000 /* Link partner acked us */ -+#define LPA_NPAGE 0x8000 /* Next page bit */ -+ -+/* 1000BASE-T Control register(0x09) */ -+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ -+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ -+#define CTL1000_AS_MASTER 0x0800 -+#define CTL1000_ENABLE_MASTER 0x1000 -+ -+/* 1000BASE-T Status register(0x0A) */ -+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ -+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ -+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ -+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ -+ -+/**********YT8614************************************************/ -+/* Basic mode control register(0x00) */ -+#define FIBER_BMCR_RESV 0x001f /* b[4:0] Unused... */ -+#define FIBER_BMCR_EN_UNIDIR 0x0020 /* b[5] Valid when bit 0.12 is zero and bit 0.8 is one */ -+#define FIBER_BMCR_SPEED1000 0x0040 /* b[6] MSB of Speed (1000) */ -+#define FIBER_BMCR_CTST 0x0080 /* b[7] Collision test */ -+#define FIBER_BMCR_DUPLEX_MODE 0x0100 /* b[8] Duplex mode */ -+#define FIBER_BMCR_ANRESTART 0x0200 /* b[9] Auto negotiation restart */ -+#define FIBER_BMCR_ISOLATE 0x0400 /* b[10] Isolate phy from RGMII/SGMII/FIBER */ -+#define FIBER_BMCR_PDOWN 0x0800 /* b[11] 1: Power down */ -+#define FIBER_BMCR_ANENABLE 0x1000 /* b[12] Enable auto negotiation */ -+#define FIBER_BMCR_SPEED100 0x2000 /* b[13] LSB of Speed (100) */ -+#define FIBER_BMCR_LOOPBACK 0x4000 /* b[14] Internal loopback control */ -+#define FIBER_BMCR_RESET 0x8000 /* b[15] PHY Software Reset(self-clear) */ -+ -+/* Sds specific status register(0x11) */ -+#define FIBER_SSR_ERCAP 0x0001 /* b[0] realtime syncstatus */ -+#define FIBER_SSR_XMIT 0x000E /* b[3:1] realtime transmit statemachine. -+ 001: Xmit Idle; -+ 010: Xmit Config; -+ 100: Xmit Data. */ -+#define FIBER_SSR_SER_MODE_CFG 0x0030 /* b[5:4] realtime serdes working mode. -+ 00: SG_MAC; -+ 01: SG_PHY; -+ 10: FIB_1000; -+ 11: FIB_100. */ -+#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040 /* b[6] realtime en_flowctrl_tx */ -+#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080 /* b[7] realtime en_flowctrl_rx */ -+#define FIBER_SSR_DUPLEX_ERROR 0x0100 /* b[8] realtime deplex error */ -+#define FIBER_SSR_RX_LPI_ACTIVE 0x0200 /* b[9] rx lpi is active */ -+#define FIBER_SSR_LSTATUS 0x0400 /* b[10] Link status real-time */ -+#define FIBER_SSR_PAUSE 0x1800 /* b[12:11] Pause to mac */ -+#define FIBER_SSR_DUPLEX 0x2000 /* b[13] This status bit is valid only when bit10 is 1. -+ 1: full duplex -+ 0: half duplex */ -+#define FIBER_SSR_SPEED_MODE 0xC000 /* b[15:14] These status bits are valid only when bit10 is 1. -+ 10---1000M -+ 01---100M */ -+ -+/* SLED cfg0 (ext 0xA001) */ -+#define FIBER_SLED_CFG0_EN_CTRL 0x00FF /* b[7:0] Control to enable the eight ports' SLED */ -+#define FIBER_SLED_CFG0_BIT_MASK 0x0700 /* b[10:8] 1: enable the pin output */ -+#define FIBER_SLED_CFG0_ACT_LOW 0x0800 /* b[11] control SLED's polarity. 1: active low; 0: active high */ -+#define FIBER_SLED_CFG0_MANU_ST 0x7000 /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */ -+#define FIBER_SLED_CFG0_MANU_EN 0x8000 /* b[15] to control serial LEDs status manually */ -+ -+/**********YT8614************************************************/ -+/* Fiber auto sensing(sgmii ext 0xA5) */ -+#define FIBER_AUTO_SEN_ENABLE 0x8000 /* b[15] Enable fiber auto sensing */ -+ -+/* Fiber force speed(common ext 0xA009) */ -+#define FIBER_FORCE_1000M 0x0001 /* b[0] 1:1000BX 0:100FX */ -+ -+#ifndef NULL -+#define NULL 0 -+#endif -+ -+/* errno */ -+enum ytphy_8614_errno_e -+{ -+ SYS_E_NONE, -+ SYS_E_PARAM, -+ SYS_E_MAX -+}; -+ -+/* errno */ -+enum ytphy_8614_combo_speed_e -+{ -+ YT8614_COMBO_FIBER_1000M, -+ YT8614_COMBO_FIBER_100M, -+ YT8614_COMBO_UTP_ONLY, -+ YT8614_COMBO_SPEED_MAX -+}; -+ -+/* definition for porting */ -+/* phy registers access */ -+typedef struct -+{ -+ u16 reg; /* the offset of the phy internal address */ -+ u16 val; /* the value of the register */ -+ u8 regType; /* register type */ -+} phy_data_s; -+ -+/* for porting use. -+ * pls over-write member function read/write for mdio access -+ */ -+typedef struct phy_info_str -+{ -+#if 0 -+ struct phy_device *phydev; -+ int mdio_base; -+#endif -+ unsigned int lport; -+ unsigned int bus_id; -+ unsigned int phy_addr; -+ -+ s32 (*read)(struct phy_info_str *info, phy_data_s *param); -+ s32 (*write)(struct phy_info_str *info, phy_data_s *param); -+}phy_info_s; -+ -+/* get phy access method */ -+s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param); -+s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param); -+s32 yt8614_phy_soft_reset(u32 lport); -+s32 yt8614_phy_init(u32 lport); -+s32 yt8614_fiber_enable(u32 lport, BOOL enable); -+s32 yt8614_utp_enable(u32 lport, BOOL enable); -+s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable); -+s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable); -+s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed); -+s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii); -+int yt8614_combo_media_priority_set (u32 lport, int fiber); -+int yt8614_combo_media_priority_get (u32 lport, int *fiber); -+s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable); -+s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable); -+s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask); -+s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask); -+s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full); -+s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full); -+s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed); -+s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed); -+int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg); -+int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media); -+ -+#endif -diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h -new file mode 100644 -index 000000000..9e01fc205 ---- /dev/null -+++ b/include/linux/motorcomm_phy.h -@@ -0,0 +1,119 @@ -+/* -+ * include/linux/motorcomm_phy.h -+ * -+ * Motorcomm PHY IDs -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef _MOTORCOMM_PHY_H -+#define _MOTORCOMM_PHY_H -+ -+#define MOTORCOMM_PHY_ID_MASK 0x00000fff -+#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff -+#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff -+ -+#define PHY_ID_YT8010 0x00000309 -+#define PHY_ID_YT8510 0x00000109 -+#define PHY_ID_YT8511 0x0000010a -+#define PHY_ID_YT8512 0x00000118 -+#define PHY_ID_YT8512B 0x00000128 -+#define PHY_ID_YT8521 0x0000011a -+#define PHY_ID_YT8531S 0x4f51e91a -+#define PHY_ID_YT8531 0x4f51e91b -+//#define PHY_ID_YT8614 0x0000e899 -+#define PHY_ID_YT8618 0x0000e889 -+ -+#define REG_PHY_SPEC_STATUS 0x11 -+#define REG_DEBUG_ADDR_OFFSET 0x1e -+#define REG_DEBUG_DATA 0x1f -+ -+#define YT8512_EXTREG_AFE_PLL 0x50 -+#define YT8512_EXTREG_EXTEND_COMBO 0x4000 -+#define YT8512_EXTREG_LED0 0x40c0 -+#define YT8512_EXTREG_LED1 0x40c3 -+ -+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 -+ -+#define YT_SOFTWARE_RESET 0x8000 -+ -+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 -+#define YT8512_CONTROL1_RMII_EN 0x0001 -+#define YT8512_LED0_ACT_BLK_IND 0x1000 -+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 -+#define YT8512_LED0_BT_BLK_EN 0x0002 -+#define YT8512_LED0_HT_BLK_EN 0x0004 -+#define YT8512_LED0_COL_BLK_EN 0x0008 -+#define YT8512_LED0_BT_ON_EN 0x0010 -+#define YT8512_LED1_BT_ON_EN 0x0010 -+#define YT8512_LED1_TXACT_BLK_EN 0x0100 -+#define YT8512_LED1_RXACT_BLK_EN 0x0200 -+#define YT8512_SPEED_MODE 0xc000 -+#define YT8512_DUPLEX 0x2000 -+ -+#define YT8512_SPEED_MODE_BIT 14 -+#define YT8512_DUPLEX_BIT 13 -+#define YT8512_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 -+#define YT8521_EN_SLEEP_SW_BIT 15 -+ -+#define YT8521_SPEED_MODE 0xc000 -+#define YT8521_DUPLEX 0x2000 -+#define YT8521_SPEED_MODE_BIT 14 -+#define YT8521_DUPLEX_BIT 13 -+#define YT8521_LINK_STATUS_BIT 10 -+ -+/* based on yt8521 wol config register */ -+#define YTPHY_UTP_INTR_REG 0x12 -+/* WOL Event Interrupt Enable */ -+#define YTPHY_WOL_INTR BIT(6) -+ -+/* Magic Packet MAC address registers */ -+#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007 -+#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008 -+#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009 -+ -+#define YTPHY_WOL_CFG_REG 0xa00a -+#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */ -+#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */ -+#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */ -+#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */ -+#define YTPHY_WOL_CFG_WIDTH2 BIT(2) -+ -+#define YTPHY_REG_SPACE_UTP 0 -+#define YTPHY_REG_SPACE_FIBER 2 -+ -+enum ytphy_wol_type_e -+{ -+ YTPHY_WOL_TYPE_LEVEL, -+ YTPHY_WOL_TYPE_PULSE, -+ YTPHY_WOL_TYPE_MAX -+}; -+typedef enum ytphy_wol_type_e ytphy_wol_type_t; -+ -+enum ytphy_wol_width_e -+{ -+ YTPHY_WOL_WIDTH_84MS, -+ YTPHY_WOL_WIDTH_168MS, -+ YTPHY_WOL_WIDTH_336MS, -+ YTPHY_WOL_WIDTH_672MS, -+ YTPHY_WOL_WIDTH_MAX -+}; -+typedef enum ytphy_wol_width_e ytphy_wol_width_t; -+ -+struct ytphy_wol_cfg_s -+{ -+ int enable; -+ int type; -+ int width; -+}; -+typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t; -+ -+#endif /* _MOTORCOMM_PHY_H */ -+ -+ --- -2.25.1 - diff --git a/patch/kernel/media-current b/patch/kernel/media-current deleted file mode 120000 index f492a3f25..000000000 --- a/patch/kernel/media-current +++ /dev/null @@ -1 +0,0 @@ -archive/media-5.19 \ No newline at end of file diff --git a/patch/kernel/archive/media-6.0/00100-v91-i2s-mclk.patch b/patch/kernel/media-current/00100-v91-i2s-mclk.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00100-v91-i2s-mclk.patch rename to patch/kernel/media-current/00100-v91-i2s-mclk.patch diff --git a/patch/kernel/archive/media-6.0/00110-v91-irq-gic-v3-its.patch b/patch/kernel/media-current/00110-v91-irq-gic-v3-its.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00110-v91-irq-gic-v3-its.patch rename to patch/kernel/media-current/00110-v91-irq-gic-v3-its.patch diff --git a/patch/kernel/archive/media-6.0/00130-rk356x-dtsi.patch b/patch/kernel/media-current/00120-rk356x-dtsi.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00130-rk356x-dtsi.patch rename to patch/kernel/media-current/00120-rk356x-dtsi.patch diff --git a/patch/kernel/archive/media-6.0/00150-v95-make.patch b/patch/kernel/media-current/00130-v95-make.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00150-v95-make.patch rename to patch/kernel/media-current/00130-v95-make.patch diff --git a/patch/kernel/archive/media-6.0/00160-v95-rk3566-firefly-roc-pc.patch b/patch/kernel/media-current/00140-v95-rk3566-firefly-roc-pc.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00160-v95-rk3566-firefly-roc-pc.patch rename to patch/kernel/media-current/00140-v95-rk3566-firefly-roc-pc.patch diff --git a/patch/kernel/archive/media-6.0/00170-v95-rk3568-bpi-r2pro.patch b/patch/kernel/media-current/00150-v95-rk3568-bpi-r2pro.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00170-v95-rk3568-bpi-r2pro.patch rename to patch/kernel/media-current/00150-v95-rk3568-bpi-r2pro.patch diff --git a/patch/kernel/archive/media-6.0/00180-v95-rk3568-firefly-roc-pc.patch b/patch/kernel/media-current/00160-v95-rk3568-firefly-roc-pc.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00180-v95-rk3568-firefly-roc-pc.patch rename to patch/kernel/media-current/00160-v95-rk3568-firefly-roc-pc.patch diff --git a/patch/kernel/media-current/00170-linux-0001-rockchip-from-6.1.patch b/patch/kernel/media-current/00170-linux-0001-rockchip-from-6.1.patch new file mode 100644 index 000000000..386bf174d --- /dev/null +++ b/patch/kernel/media-current/00170-linux-0001-rockchip-from-6.1.patch @@ -0,0 +1,5829 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Thu, 21 Jul 2022 10:33:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add analog audio output on quartz64-b + +This adds the necessary device tree changes to enable analog +audio output on the PINE64 Quartz64 Model B with its RK809 +codec. + +The headphone detection pin is left out for now because I couldn't +get it to work and am not sure if it even matters, but for future +reference: It's pin GPIO4 RK_PC4, named HP_DET_L_GPIO4_C4 in the +schematic. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220721083301.3711-1-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 32 ++++++++++++++++++- + 1 file changed, 31 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +index 528bb4e8ac77..c8315d703ad0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +@@ -42,6 +42,21 @@ led-user { + }; + }; + ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; +@@ -420,6 +440,16 @@ &i2c5 { + status = "disabled"; + }; + ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add vcc_cam regulator to rock-3a + +The Radxa ROCK3 Model A features a voltage regulator that provides +a 3V3 supply to the MIPI CSI connector. Add this regulator to the +device tree of the board. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-1-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index b2e040dffb59..169d4b1d0a34 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -131,6 +131,22 @@ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; ++ ++ vcc_cam: vcc-cam { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_cam_en>; ++ regulator-name = "vcc_cam"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; + }; + + &combphy0 { +@@ -462,6 +478,12 @@ rgmii_phy1: ethernet-phy@0 { + }; + + &pinctrl { ++ cam { ++ vcc_cam_en: vcc_cam_en { ++ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:03 +0200 +Subject: [PATCH] arm64: dts: rockchip: add vcc_mipi regulator to rock-3a + +The Radxa ROCK3 Model A features a voltage regulator that provides +a 3V3 supply to the MIPI DSI connector. Add this regulator to the +device tree of the board. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-2-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 169d4b1d0a34..f0f96c72ec51 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -147,6 +147,22 @@ regulator-state-mem { + regulator-off-in-suspend; + }; + }; ++ ++ vcc_mipi: vcc-mipi { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_mipi_en>; ++ regulator-name = "vcc_mipi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; + }; + + &combphy0 { +@@ -484,6 +500,12 @@ vcc_cam_en: vcc_cam_en { + }; + }; + ++ display { ++ vcc_mipi_en: vcc_mipi_en { ++ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:04 +0200 +Subject: [PATCH] arm64: dts: rockchip: specify pinctrl for i2c adapters on + rock-3a + +On the Radxa ROCK3 Model A the I2C adapters related to the MIPI DSI +connector and the M.2/NGFF connector use the non-default pins. +Specify the correct pinctrl but leave the adapters disabled (as +they are supposed to be activated by overlays that describe the +external hardware). + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-3-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index f0f96c72ec51..52a437f48301 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -472,6 +472,18 @@ codec { + }; + }; + ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3m1_xfer>; ++ status = "disabled"; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "disabled"; ++}; ++ + &i2s0_8ch { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:35 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rk3568 + +Add nodes to rk356x devicetree to support PCIe v3. + +Signed-off-by: Peter Geis +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index 2bdf8c7e9765..ba67b58f05b7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { + reg = <0x0 0xfe190200 0x0 0x20>; + }; + ++ pcie30_phy_grf: syscon@fdcb8000 { ++ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; ++ reg = <0x0 0xfdcb8000 0x0 0x10000>; ++ }; ++ ++ pcie30phy: phy@fe8c0000 { ++ compatible = "rockchip,rk3568-pcie3-phy"; ++ reg = <0x0 0xfe8c0000 0x0 0x20000>; ++ #phy-cells = <0>; ++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, ++ <&cru PCLK_PCIE30PHY>; ++ clock-names = "refclk_m", "refclk_n", "pclk"; ++ resets = <&cru SRST_PCIE30PHY>; ++ reset-names = "phy"; ++ rockchip,phy-grf = <&pcie30_phy_grf>; ++ status = "disabled"; ++ }; ++ ++ pcie3x1: pcie@fe270000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, ++ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, ++ <&cru CLK_PCIE30X1_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, ++ <0 0 0 2 &pcie3x1_intc 1>, ++ <0 0 0 3 &pcie3x1_intc 2>, ++ <0 0 0 4 &pcie3x1_intc 3>; ++ linux,pci-domain = <1>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x1000 0x1000>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0400000 0x0 0x00400000>, ++ <0x0 0xfe270000 0x0 0x00010000>, ++ <0x3 0x7f000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X1_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane1 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x1_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie3x2: pcie@fe280000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, ++ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, ++ <&cru CLK_PCIE30X2_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, ++ <0 0 0 2 &pcie3x2_intc 1>, ++ <0 0 0 3 &pcie3x2_intc 2>, ++ <0 0 0 4 &pcie3x2_intc 3>; ++ linux,pci-domain = <2>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x2000 0x1000>; ++ num-lanes = <2>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0800000 0x0 0x00400000>, ++ <0x0 0xfe280000 0x0 0x00010000>, ++ <0x3 0xbf000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X2_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane0 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:36 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro + +Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and +set PCIe related regulators to always on. + +Suggested-by: Peter Geis +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220825193836.54262-6-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 ++++++++++++++++++ + 1 file changed, 117 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +index 93d383b8be87..bc34061a421e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys { + vin-supply = <&dc_12v>; + }; + ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ /* pi6c pcie clock generator feeds both ports */ ++ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ ++ vcc3v3_minipcie: vcc3v3-minipcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_minipcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_enable_h>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc3v3_pi6c_05>; ++ }; ++ ++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ ++ vcc3v3_ngff: vcc3v3-ngff-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_ngff"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ngffpcie_enable_h>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc3v3_pi6c_05>; ++ }; ++ + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; +@@ -513,6 +573,32 @@ rgmii_phy1: ethernet-phy@0 { + }; + }; + ++&pcie30phy { ++ data-lanes = <1 2>; ++ phy-supply = <&vcc3v3_pi6c_05>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ /* M.2 slot */ ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ngffpcie_reset_h>; ++ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_ngff>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ /* mPCIe slot */ ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_reset_h>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_minipcie>; ++ status = "okay"; ++}; ++ + &pinctrl { + leds { + blue_led_pin: blue-led-pin { +@@ -529,6 +615,24 @@ hym8563_int: hym8563-int { + }; + }; + ++ pcie { ++ minipcie_enable_h: minipcie-enable-h { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ ngffpcie_enable_h: ngffpcie-enable-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ minipcie_reset_h: minipcie-reset-h { ++ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ ngffpcie_reset_h: ngffpcie-reset-h { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = +@@ -708,6 +812,19 @@ &usb2phy0_otg { + status = "okay"; + }; + ++&usb2phy1 { ++ /* USB for PCIe/M2 */ ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ + &vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Wed, 20 Jul 2022 11:15:27 +0200 +Subject: [PATCH] arm64: dts: rockchip: add csi dphy node to rk356x + +Add the MIPI CSI DPHY node to the RK356x device tree. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220720091527.1270365-4-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 319981c3e9f7..c66b60302803 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1594,6 +1594,18 @@ combphy2: phy@fe840000 { + status = "disabled"; + }; + ++ csi_dphy: phy@fe870000 { ++ compatible = "rockchip,rk3568-csi-dphy"; ++ reg = <0x0 0xfe870000 0x0 0x10000>; ++ clocks = <&cru PCLK_MIPICSIPHY>; ++ clock-names = "pclk"; ++ #phy-cells = <0>; ++ resets = <&cru SRST_P_MIPICSIPHY>; ++ reset-names = "apb"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ + usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:29:42 +0800 +Subject: [PATCH] dt-bindings: vendor-prefixes: Add OPEN AI LAB + +Add vendor prefixes for OPEN AI LAB. + +Signed-off-by: Andy Yan +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20220709102942.2753939-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 2f0151e9f6be..dfaff2487b04 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -925,6 +925,8 @@ patternProperties: + description: On Tat Industrial Company + "^opalkelly,.*": + description: Opal Kelly Incorporated ++ "^openailab,.*": ++ description: openailab.com + "^opencores,.*": + description: OpenCores.org + "^openembed,.*": + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:30:01 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: Add EAIDK-610 + +EAIDK-610 is a rk3399 based board from OPEN AI LAB +and popularly used by university students. + +Specification: +- Rockchip RK3399 +- LPDDR3 4GB +- TF sd scard slot +- eMMC +- AP6255 for WiFi + BT +- Gigabit ethernet +- HDMI out +- 40 pin header +- USB 2.0 x 2 +- USB 3.0 x 1 +- USB 3.0 Type-C x 1 +- 12V DC Power supply + +Signed-off-by: Andy Yan +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20220709103001.2753992-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7811ba64149c..adc06522d219 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -470,6 +470,11 @@ properties: + - const: netxeon,r89 + - const: rockchip,rk3288 + ++ - description: OPEN AI LAB EAIDK-610 ++ items: ++ - const: openailab,eaidk-610 ++ - const: rockchip,rk3399 ++ + - description: Orange Pi RK3399 board + items: + - const: rockchip,rk3399-orangepi + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:30:16 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add dts for a rk3399 based board + EAIDK-610 + +EAIDK-610 is from OPEN AI LAB and popularly used by university +students. + +Specification: +- Rockchip RK3399 +- LPDDR3 4GB +- TF sd scard slot +- eMMC +- AP6255 for WiFi + BT +- Gigabit ethernet +- HDMI out +- 40 pin header +- USB 2.0 x 2 +- USB 3.0 x 1 +- USB 3.0 Type-C x 1 +- 12V DC Power supply + +This patch is test on Armbain and Glodroid with +HDMI/GPU/USB HOST/Type-C ADB/WIFI/BT. + +Signed-off-by: Andy Yan +Link: https://lore.kernel.org/r/20220709103016.2754044-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-eaidk-610.dts | 939 ++++++++++++++++++ + 2 files changed, 940 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index ef79a672804a..4ed7d483c864 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts +new file mode 100644 +index 000000000000..d1f343345f67 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts +@@ -0,0 +1,939 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "OPEN AI LAB EAIDK-610"; ++ compatible = "openailab,eaidk-610", "rockchip,rk3399"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm0 0 25000 0>; ++ brightness-levels = < ++ 0 1 2 3 4 5 6 7 ++ 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 ++ 24 25 26 27 28 29 30 31 ++ 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 ++ 48 49 50 51 52 53 54 55 ++ 56 57 58 59 60 61 62 63 ++ 64 65 66 67 68 69 70 71 ++ 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 ++ 88 89 90 91 92 93 94 95 ++ 96 97 98 99 100 101 102 103 ++ 104 105 106 107 108 109 110 111 ++ 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 ++ 128 129 130 131 132 133 134 135 ++ 136 137 138 139 140 141 142 143 ++ 144 145 146 147 148 149 150 151 ++ 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 ++ 168 169 170 171 172 173 174 175 ++ 176 177 178 179 180 181 182 183 ++ 184 185 186 187 188 189 190 191 ++ 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 ++ 208 209 210 211 212 213 214 215 ++ 216 217 218 219 220 221 222 223 ++ 224 225 226 227 228 229 230 231 ++ 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 ++ 248 249 250 251 252 253 254 255>; ++ default-brightness-level = <200>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn>; ++ ++ key-power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "GPIO Key Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&work_led_pin>, <&user_led_pin>, ++ <&heartbeat_led_pin>, <&wlan_active_led_pin>, ++ <&bt_active_led_pin>; ++ ++ work_led: led-0 { ++ label = "blue:work"; ++ default-state = "on"; ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user_led: led-1 { ++ label = "read:user"; ++ default-state = "off"; ++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ heartbeat_led: led-2 { ++ label = "green:heartbeat"; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wlan_active_led: led-3 { ++ label = "yellow:wlan"; ++ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "phy0tx"; ++ default-state = "off"; ++ }; ++ ++ bt_active_led: led-4 { ++ label = "blue:bt"; ++ gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "hci0-power"; ++ default-state = "off"; ++ }; ++ }; ++ ++ rt5651-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "realtek,rt5651-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "Mic Jack", "MICBIAS1", ++ "IN1P", "Mic Jack", ++ "Headphone Jack", "HPOL", ++ "Headphone Jack", "HPOR"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rt5651>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ /* For USB3.0 Port1/2 */ ++ vcc5v0_host1: vcc5v0-host1-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host1_en>; ++ regulator-name = "vcc5v0_host1"; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ /* For USB2.0 Port1/2 */ ++ vcc5v0_host3: vcc5v0-host3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host3_en>; ++ regulator-name = "vcc5v0_host3"; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_typec_en>; ++ regulator-name = "vcc5v0_typec"; ++ regulator-always-on; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_3v0>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG2 { ++ regulator-name = "vcc2v8_dvp"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-name = "vcc_sdio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: vcc_lan: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_pin>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_pin>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++ ++ rt5651: audio-codec@1a { ++ compatible = "rockchip,rt5651"; ++ reg = <0x1a>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; ++ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ #sound-dai-cells = <0>; ++ }; ++ ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ i2c-scl-rising-time-ns = <600>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ vbus-supply = <&vcc5v0_typec>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_role_sw: endpoint@0 { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ }; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USB-C"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc_hs: endpoint { ++ remote-endpoint = <&u2phy0_typec_hs>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc_ss: endpoint { ++ remote-endpoint = <&tcphy0_typec_ss>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2s1 { ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ audio-supply = <&vcca1v8_codec>; ++ bt656-supply = <&vcc_3v0>; ++ gpio1830-supply = <&vcc_3v0>; ++ sdmmc-supply = <&vcc_sdio>; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ ++ pmu1830-supply = <&vcc_3v0>; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb302x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ lcd-panel { ++ lcd_panel_reset: lcd-panel-reset { ++ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ leds { ++ work_led_pin: work-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ user_led_pin: user-led-pin { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ heartbeat_led_pin: heartbeat-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_active_led_pin: wlan-led-pin { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_active_led_pin: bt-led-pin { ++ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_pin: vsel1-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_pin: vsel2-pin { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ rt5651 { ++ rt5651_hpcon: rt5640-hpcon { ++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb-typec { ++ vcc5v0_typec_en: vcc5v0_typec_en { ++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host3_en: vcc5v0-host3-en { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_host1_en: vcc5v0-host1-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_host_wake_l: wifi-host-wake-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ /* WiFi & BT combo module AMPAK AP6255 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ clock-frequency = <50000000>; ++ cap-sdio-irq; ++ cap-sd-highspeed; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy0_usb3 { ++ orientation-switch; ++ port { ++ tcphy0_typec_ss: endpoint { ++ remote-endpoint = <&usbc_ss>; ++ }; ++ }; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host3>; ++ status = "okay"; ++ }; ++ ++ port { ++ u2phy0_typec_hs: endpoint { ++ remote-endpoint = <&usbc_hs>; ++ }; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host3>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk808 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ usb-role-switch; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dwc3_0_role_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tom Fitzhenry +Date: Mon, 15 Aug 2022 22:30:03 +1000 +Subject: [PATCH] dt-bindings: arm: rockchip: Add PinePhone Pro bindings + +Document board compatible names for Pine64 PinePhonePro. + +https://wiki.pine64.org/wiki/PinePhone_Pro + +Signed-off-by: Tom Fitzhenry +Reviewed-by: Caleb Connolly +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220815123004.252014-2-tom@tom-fitzhenry.me.uk +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index adc06522d219..7295eecc6de7 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -499,6 +499,11 @@ properties: + - const: pine64,pinenote + - const: rockchip,rk3566 + ++ - description: Pine64 PinePhonePro ++ items: ++ - const: pine64,pinephone-pro ++ - const: rockchip,rk3399 ++ + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Martijn Braam +Date: Mon, 29 Aug 2022 15:00:40 +1000 +Subject: [PATCH] arm64: dts: rockchip: Add initial support for Pine64 + PinePhone Pro +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is a basic DT containing regulators and UART, intended to be a +base that myself and others can add additional nodes in future patches. + +Tested to work: booting from eMMC/SD, output over UART. + +https://wiki.pine64.org/wiki/PinePhone_Pro + +This is derived from the community pine64-org repo[0] with fixes from +https://megous.com/git/linux. + +0. https://gitlab.com/pine64-org/linux/-/commit/261d3b5f8ac503f97da810986d1d6422430c8531 + +Signed-off-by: Martijn Braam +Co-developed-by: Kamil Trzciński +[no SoB, but Kamil is happy for this patch to be submitted] +Co-developed-by: Ondrej Jirman +Signed-off-by: Ondrej Jirman +Co-developed-by: Tom Fitzhenry +Signed-off-by: Tom Fitzhenry +Reviewed-by: Caleb Connolly +Reviewed-by: Nícolas F. R. A. Prado +Tested-by: Nícolas F. R. A. Prado +Link: https://lore.kernel.org/r/20220829050040.17330-2-tom@tom-fitzhenry.me.uk +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3399-pinephone-pro.dts | 398 ++++++++++++++++++ + 2 files changed, 399 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 4ed7d483c864..236e8ae52c70 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +new file mode 100644 +index 000000000000..f00c80361377 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +@@ -0,0 +1,398 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Martijn Braam ++ * Copyright (c) 2021 Kamil Trzciński ++ */ ++ ++/* ++ * PinePhone Pro datasheet: ++ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf ++ */ ++ ++/dts-v1/; ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "Pine64 PinePhonePro"; ++ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; ++ chassis-type = "handset"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn_pin>; ++ ++ key-power { ++ debounce-interval = <20>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcca1v8_s3: vcc1v8-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_s3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc1v8_codec: vcc1v8-codec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc1v8_codec_en>; ++ regulator-name = "vcc1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk818: pmic@1c { ++ compatible = "rockchip,rk818"; ++ reg = <0x1c>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_cpu_l: DCDC_REG1 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_center: DCDC_REG2 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG1 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-name = "vcc3v0_touch"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ ++ vcca1v8_codec: LDO_REG3 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ rk818_pwr_on: LDO_REG4 { ++ regulator-name = "rk818_pwr_on"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG5 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG7 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ vcc3v3_s3: LDO_REG8 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG9 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1710000>; ++ regulator-max-microvolt = <3150000>; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_pin>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_pin>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&cluster0_opp { ++ opp04 { ++ status = "disabled"; ++ }; ++ ++ opp05 { ++ status = "disabled"; ++ }; ++}; ++ ++&cluster1_opp { ++ opp06 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1100000 1100000 1150000>; ++ }; ++ ++ opp07 { ++ status = "disabled"; ++ }; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc1v8_dvp>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vccio_sd>; ++ gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn_pin: pwrbtn-pin { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_pin: vsel1-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_pin: vsel2-pin { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sound { ++ vcc1v8_codec_en: vcc1v8-codec-en { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:55 +0530 +Subject: [PATCH] dt-bindings: arm: rockchip: Document Radxa ROCK 4C+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Document the dt-bindings for Radxa ROCK 4C+ SBC. + +Key differences of 4C+ compared to previous ROCK Pi 4. +- Rockchip RK3399-T SoC +- DP from 4C replaced with micro HDMI 2K@60fps +- 4-lane MIPI DSI with 1920*1080 +- RK817 Audio codec + +Also, an official naming convention from Radxa mention to remove +Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not +Radxa ROCK Pi 4C+. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-1-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7295eecc6de7..5c1b9f0e4cc1 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -547,6 +547,11 @@ properties: + - const: radxa,rockpi4 + - const: rockchip,rk3399 + ++ - description: Radxa ROCK 4C+ ++ items: ++ - const: radxa,rock-4c-plus ++ - const: rockchip,rk3399 ++ + - description: Radxa ROCK Pi E + items: + - const: radxa,rockpi-e + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:56 +0530 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399-T OPP table + +RK3399-T is down-clocked version of RK3399 SoC operated at 1.5GHz. + +Add CPU operating points table for it. + +Signed-off-by: FUKAUMI Naoki +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-2-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + .../arm64/boot/dts/rockchip/rk3399-t-opp.dtsi | 114 ++++++++++++++++++ + 1 file changed, 114 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi +new file mode 100644 +index 000000000000..1ababadda9df +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi +@@ -0,0 +1,114 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2022 Radxa Limited ++ */ ++ ++/ { ++ cluster0_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <900000 900000 1250000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <975000 975000 1250000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table-1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000 925000 1250000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000 1000000 1250000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1075000 1075000 1250000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1150000 1150000 1250000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table-2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <975000 975000 1150000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:57 +0530 +Subject: [PATCH] arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for Radxa ROCK 4C+ SBC. + +Key differences of 4C+ compared to previous ROCK Pi 4. +- Rockchip RK3399-T SoC +- DP from 4C replaced with micro HDMI 2K@60fps +- 4-lane MIPI DSI with 1920*1080 +- RK817 Audio codec + +Also, an official naming convention from Radxa mention to remove +Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not +Radxa ROCK Pi 4C+. + +Signed-off-by: Stephen Chen +Signed-off-by: Manoj Sai +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-3-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 646 ++++++++++++++++++ + 2 files changed, 647 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 236e8ae52c70..cdd1f211496d 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +new file mode 100644 +index 000000000000..a1c4727acfcd +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -0,0 +1,646 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2022 Amarula Solutions(India) ++ */ ++ ++/dts-v1/; ++#include "rk3399.dtsi" ++#include "rk3399-t-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK 4C+"; ++ compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; ++ ++ aliases { ++ mmc0 = &sdmmc; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_host1: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host1"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_host0_s0>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_typec0_en>; ++ regulator-name = "vcc5v0_typec"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_lan: vcc3v3-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_lan"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x2a>; ++ rx_delay = <0x21>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ i2c-scl-falling-time-ns = <30>; ++ i2c-scl-rising-time-ns = <180>; ++ clock-frequency = <400000>; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc_buck5>; ++ vcc6-supply = <&vcc_buck5>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_log"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_cpu_l"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_ddr"; ++ regulator-initial-mode = <0x2>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sys: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc3v3_sys"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_buck5: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_buck5"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_0v9: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcca_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc0v9_soc: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcc0v9_soc"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_mipi: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_mipi"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc_1v5"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_3v0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_cam: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_cam"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc5v0_host0_s0: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc5v0_host0_s0"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ lcd_3v3: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "lcd_3v3"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-compatible = "fan53555-reg"; ++ pinctrl-0 = <&vsel1_gpio>; ++ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-compatible = "fan53555-reg"; ++ pinctrl-0 = <&vsel2_gpio>; ++ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc_3v0>; ++ gpio1830-supply = <&vcc_3v0>; ++ sdmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sdmmc { ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, ++ <4 9 1 &pcfg_pull_up_8ma>, ++ <4 10 1 &pcfg_pull_up_8ma>, ++ <4 11 1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; ++ }; ++ }; ++ ++ usb-typec { ++ vcc5v0_typec0_en: vcc5v0-typec-en { ++ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ wifi { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_host_wake_l: wifi-host-wake-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vcc_1v8>; ++}; ++ ++&sdhci { ++ max-frequency = <150000000>; ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ non-removable; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ clock-frequency = <50000000>; ++ cap-sdio-irq; ++ cap-sd-highspeed; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ card-detect-delay = <800>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host1>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host1>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk809 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ extcon = <&u2phy0>; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 5 Sep 2022 01:36:47 +0200 +Subject: [PATCH] arm64: dts: rockchip: Fix SD card controller probe on + Pinephone Pro + +Voltage constraints on vccio_sd are invalid. They don't match the voltages +that LDO9 can generate, and this causes rk808-regulator driver to fail +to probe with -EINVAL when it tries to apply the constraints during boot. + +Fix the constraints to something that LDO9 can be actually configured for. + +Fixes: 78a21c7d5952 ("arm64: dts: rockchip: Add initial support for Pine64 PinePhone Pro") +Signed-off-by: Ondrej Jirman +Reviewed-by: Caleb Connolly +Reviewed-by: Tom Fitzhenry +Tested-by: Tom Fitzhenry +Link: https://lore.kernel.org/r/20220904233652.3197885-1-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +index f00c80361377..2e058c315025 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +@@ -253,8 +253,8 @@ regulator-state-mem { + + vccio_sd: LDO_REG9 { + regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <3150000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; + }; + + vcc3v3_s0: SWITCH_REG { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Fri, 26 Aug 2022 21:16:23 -0500 +Subject: [PATCH] arm64: dts: rockchip: add rk817 chg to Odroid Go Advance + +Add the new rk817 charger driver to the Odroid Go Advance. Create a +monitored battery node as well for the charger to use. All values +from monitored battery are gathered from the BSP kernel for the +Odroid Go Advance provided by HardKernel. + +Signed-off-by: Chris Morgan +Signed-off-by: Maya Matuszczyk +Link: https://lore.kernel.org/r/20220827021623.23829-5-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +index 415aa9ff8bd4..72899a714310 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +@@ -52,6 +52,25 @@ backlight: backlight { + pwms = <&pwm1 0 25000 0>; + }; + ++ battery: battery { ++ compatible = "simple-battery"; ++ charge-full-design-microamp-hours = <3000000>; ++ charge-term-current-microamp = <300000>; ++ constant-charge-current-max-microamp = <2000000>; ++ constant-charge-voltage-max-microvolt = <4200000>; ++ factory-internal-resistance-micro-ohms = <180000>; ++ voltage-max-design-microvolt = <4100000>; ++ voltage-min-design-microvolt = <3500000>; ++ ++ ocv-capacity-celsius = <20>; ++ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, ++ <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, ++ <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, ++ <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, ++ <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, ++ <3574170 0>; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +@@ -472,6 +491,13 @@ usb_midu: BOOST { + }; + }; + ++ rk817_charger: charger { ++ monitored-battery = <&battery>; ++ rockchip,resistor-sense-micro-ohms = <10000>; ++ rockchip,sleep-enter-current-microamp = <300000>; ++ rockchip,sleep-filter-current-microamp = <100000>; ++ }; ++ + rk817_codec: codec { + rockchip,mic-in-differential; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 8 Sep 2022 03:17:25 +0000 +Subject: [PATCH] arm64: dts: rockchip: add LED for ROCK Pi 4A/B/C/A+/B+ + +only user_led2 (blue) is supported. + +user_led1 (green) is not connected to any gpio so it cannot be +controlled. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20220908031726.1307105-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index 401e1ae9d944..6464a6729729 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -6,6 +6,7 @@ + + /dts-v1/; + #include ++#include + #include + #include "rk3399.dtsi" + #include "rk3399-opp.dtsi" +@@ -27,6 +28,20 @@ clkin_gmac: external-gmac-clock { + #clock-cells = <0>; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ ++ /* USER_LED2 */ ++ led-0 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; +@@ -553,6 +568,12 @@ hp_int: hp-int { + }; + }; + ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 8 Sep 2022 03:17:26 +0000 +Subject: [PATCH] arm64: dts: rockchip: add LEDs for ROCK 4C+ + +add support for user LEDs on Radxa ROCK 4C+ board. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20220908031726.1307105-2-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +index a1c4727acfcd..3f01772c66ad 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -6,6 +6,7 @@ + */ + + /dts-v1/; ++#include + #include "rk3399.dtsi" + #include "rk3399-t-opp.dtsi" + +@@ -38,6 +39,28 @@ clkin_gmac: external-gmac-clock { + #clock-cells = <0>; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led1 &user_led2>; ++ ++ /* USER_LED1 */ ++ led-0 { ++ function = LED_FUNCTION_POWER; ++ color = ; ++ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ /* USER_LED2 */ ++ led-1 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -424,6 +447,16 @@ bt_wake_l: bt-wake-l { + }; + }; + ++ leds { ++ user_led1: user-led1 { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ user_led2: user-led2 { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 6 Sep 2022 18:42:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add regulator suffix to BPI-R2-Pro + +Add -regulator suffix to regulator names on Banana Pi R2 Pro board as +discussed on Mailinglist + +Signed-off-by: Frank Wunderlich +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906164212.84835-1-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +index bc34061a421e..c282f6e79960 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -46,7 +46,7 @@ green_led: led-1 { + }; + }; + +- dc_12v: dc-12v { ++ dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; +@@ -66,7 +66,7 @@ hdmi_con_in: endpoint { + }; + }; + +- vcc3v3_sys: vcc3v3-sys { ++ vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; +@@ -76,7 +76,7 @@ vcc3v3_sys: vcc3v3-sys { + vin-supply = <&dc_12v>; + }; + +- vcc5v0_sys: vcc5v0-sys { ++ vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; +@@ -146,7 +146,7 @@ vcc3v3_ngff: vcc3v3-ngff-regulator { + vin-supply = <&vcc3v3_pi6c_05>; + }; + +- vcc5v0_usb: vcc5v0_usb { ++ vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; +@@ -156,7 +156,7 @@ vcc5v0_usb: vcc5v0_usb { + vin-supply = <&dc_12v>; + }; + +- vcc5v0_usb_host: vcc5v0-usb-host { ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +@@ -168,7 +168,7 @@ vcc5v0_usb_host: vcc5v0-usb-host { + vin-supply = <&vcc5v0_usb>; + }; + +- vcc5v0_usb_otg: vcc5v0-usb-otg { ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:22 -0500 +Subject: [PATCH] dt-bindings: vendor-prefixes: add Anbernic + +Anbernic designs and manufactures portable gaming systems. +https://anbernic.com/ + +Signed-off-by: Chris Morgan +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906210324.28986-2-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index dfaff2487b04..e370ffde0692 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -105,6 +105,8 @@ patternProperties: + description: AMS-Taos Inc. + "^analogix,.*": + description: Analogix Semiconductor, Inc. ++ "^anbernic,.*": ++ description: Anbernic + "^andestech,.*": + description: Andes Technology Corporation + "^anvo,.*": + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:23 -0500 +Subject: [PATCH] dt-bindings: arm: rockchip: Add Anbernic RG353P and RG503 + +Add entry for the Anbernic RG353P and RG503 handheld devices. + +Signed-off-by: Chris Morgan +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906210324.28986-3-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 5c1b9f0e4cc1..ae7fe15a3b89 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -30,6 +30,16 @@ properties: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + ++ - description: Anbernic RG353P ++ items: ++ - const: anbernic,rg353p ++ - const: rockchip,rk3566 ++ ++ - description: Anbernic RG503 ++ items: ++ - const: anbernic,rg503 ++ - const: rockchip,rk3566 ++ + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:24 -0500 +Subject: [PATCH] arm64: dts: rockchip: add Anbernic RG353P and RG503 + +Anbernic RG353P and RG503 are both RK3566 based handheld gaming devices +from Anbernic. + +Both devices have: + - 2 SDMMC slots. + - A Realtek rtl8821cs WiFi/Bluetooth adapter. + - A mini HDMI port. + - A USB C host port and a USB C otg port (currently only working as + device). + - Multiple GPIO buttons and a single ADC button. + - Dual analog joysticks controlled via a GPIO mux. + - A headphone jack with amplified stereo speakers via a SGM4865 amp. + - A PWM based vibrator for force feedback. + +The RG353P has: + - 2GB LPDDR4 RAM. + - A 32GB eMMC. + - A 3.5 inch 640x480 4-lane DSI panel of unknown origin with an i2c + controlled touchscreen (touchscreen is a Hynitron CST340). + +The RG503 has: + - 1GB LPDDR4 RAM. + - A 5 inch 960x544 AMOLED 2-lane DSI/DBI panel manufactured by Samsung + with part number ams495qa04. Data for this panel is provided via the + DSI interface, however commands are sent via a 9-bit 3-wire SPI + interface. The MISO pin of SPI3 of the SOC is wired to the input of + the panel, so it must be bitbanged. + +This devicetree enables the following hardware: + - HDMI (plus audio). + - Analog audio, including speakers. + - All buttons. + - All SDMMC/eMMC/SDIO controllers. + - The ADC joysticks (note a pending patch is required to use them). + - WiFi/Bluetooth (note out of tree drivers are required). + - The PWM based vibrator motor. + +The following hardware is not enabled: + - The display panels (drivers are being written and there are issues + with the upstream DSI and VOP2 subsystems). + - Battery (driver pending). + - Touchscreen on the RG353P (note the i2c2 bus is enabled for it). + +Signed-off-by: Chris Morgan +Link: https://lore.kernel.org/r/20220906210324.28986-4-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 2 + + .../dts/rockchip/rk3566-anbernic-rg353p.dts | 94 ++ + .../dts/rockchip/rk3566-anbernic-rg503.dts | 87 ++ + .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 831 ++++++++++++++++++ + 4 files changed, 1014 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index cdd1f211496d..94639380ec1e 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -60,6 +60,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +new file mode 100644 +index 000000000000..7a20e2d6876a +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +@@ -0,0 +1,94 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3566-anbernic-rgxx3.dtsi" ++ ++/ { ++ model = "RG353P"; ++ compatible = "anbernic,rg353p", "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc1; ++ mmc3 = &sdmmc2; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ power-supply = <&vcc_sys>; ++ pwms = <&pwm4 0 25000 0>; ++ }; ++}; ++ ++&gpio_keys_control { ++ button-a { ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; ++ label = "EAST"; ++ linux,code = ; ++ }; ++ ++ button-left { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-LEFT"; ++ linux,code = ; ++ }; ++ ++ button-r1 { ++ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; ++ label = "TR"; ++ linux,code = ; ++ }; ++ ++ button-r2 { ++ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; ++ label = "TR2"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-y { ++ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; ++ label = "WEST"; ++ linux,code = ; ++ }; ++}; ++ ++&i2c0 { ++ /* This hardware is physically present but unused. */ ++ power-monitor@62 { ++ compatible = "cellwise,cw2015"; ++ reg = <0x62>; ++ status = "disabled"; ++ }; ++}; ++ ++&i2c2 { ++ pintctrl-names = "default"; ++ pinctrl-0 = <&i2c2m1_xfer>; ++ status = "okay"; ++}; ++ ++&pwm4 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; ++ pinctrl-names = "default"; ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +new file mode 100644 +index 000000000000..3dc01549a5b4 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +@@ -0,0 +1,87 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3566-anbernic-rgxx3.dtsi" ++ ++/ { ++ model = "RG503"; ++ compatible = "anbernic,rg503", "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdmmc1; ++ mmc2 = &sdmmc2; ++ }; ++ ++ gpio_spi: spi { ++ compatible = "spi-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sck-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; ++ mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <0>; ++ }; ++}; ++ ++&gpio_keys_control { ++ button-a { ++ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; ++ label = "EAST"; ++ linux,code = ; ++ }; ++ ++ button-left { ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "DPAD-LEFT"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-r1 { ++ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; ++ label = "TR"; ++ linux,code = ; ++ }; ++ ++ button-r2 { ++ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; ++ label = "TR2"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-y { ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; ++ label = "WEST"; ++ linux,code = ; ++ }; ++}; ++ ++&pinctrl { ++ gpio-spi { ++ spi_pins: spi-pins { ++ rockchip,pins = ++ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +new file mode 100644 +index 000000000000..2b455143b86d +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +@@ -0,0 +1,831 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ adc-joystick { ++ compatible = "adc-joystick"; ++ io-channels = <&adc_mux 0>, ++ <&adc_mux 1>, ++ <&adc_mux 2>, ++ <&adc_mux 3>; ++ pinctrl-0 = <&joy_mux_en>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ axis@0 { ++ reg = <0>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <1023 15>; ++ linux,code = ; ++ }; ++ ++ axis@1 { ++ reg = <1>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <15 1023>; ++ linux,code = ; ++ }; ++ ++ axis@2 { ++ reg = <2>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <15 1023>; ++ linux,code = ; ++ }; ++ ++ axis@3 { ++ reg = <3>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <1023 15>; ++ linux,code = ; ++ }; ++ }; ++ ++ adc_keys: adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <60>; ++ ++ /* ++ * Button is mapped to F key in BSP kernel, but ++ * according to input guidelines it should be mode. ++ */ ++ button-mode { ++ label = "MODE"; ++ linux,code = ; ++ press-threshold-microvolt = <1750>; ++ }; ++ }; ++ ++ adc_mux: adc-mux { ++ compatible = "io-channel-mux"; ++ channels = "left_x", "right_x", "left_y", "right_y"; ++ #io-channel-cells = <1>; ++ io-channels = <&saradc 3>; ++ io-channel-names = "parent"; ++ mux-controls = <&gpio_mux>; ++ settle-time-us = <100>; ++ }; ++ ++ gpio_keys_control: gpio-keys-control { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&btn_pins_ctrl>; ++ pinctrl-names = "default"; ++ ++ button-b { ++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; ++ label = "SOUTH"; ++ linux,code = ; ++ }; ++ ++ button-down { ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; ++ label = "DPAD-DOWN"; ++ linux,code = ; ++ }; ++ ++ button-l1 { ++ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; ++ label = "TL"; ++ linux,code = ; ++ }; ++ ++ button-l2 { ++ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; ++ label = "TL2"; ++ linux,code = ; ++ }; ++ ++ button-select { ++ gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; ++ label = "SELECT"; ++ linux,code = ; ++ }; ++ ++ button-start { ++ gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; ++ label = "START"; ++ linux,code = ; ++ }; ++ ++ button-thumbl { ++ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; ++ label = "THUMBL"; ++ linux,code = ; ++ }; ++ ++ button-thumbr { ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; ++ label = "THUMBR"; ++ linux,code = ; ++ }; ++ ++ button-up { ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; ++ label = "DPAD-UP"; ++ linux,code = ; ++ }; ++ ++ button-x { ++ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ label = "NORTH"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio_keys_vol: gpio-keys-vol { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-0 = <&btn_pins_vol>; ++ pinctrl-names = "default"; ++ ++ button-vol-down { ++ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ label = "VOLUMEDOWN"; ++ linux,code = ; ++ }; ++ ++ button-vol-up { ++ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; ++ label = "VOLUMEUP"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio_mux: mux-controller { ++ compatible = "gpio-mux"; ++ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, ++ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ #mux-control-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ ddc-i2c-bus = <&i2c5>; ++ type = "c"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&led_pins>; ++ pinctrl-names = "default"; ++ ++ green_led: led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ amber_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_CHARGING; ++ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ retain-state-suspended; ++ }; ++ ++ red_led: led-2 { ++ color = ; ++ default-state = "off"; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ /* Channels reversed for both headphones and speakers. */ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "anbernic_rk817"; ++ simple-audio-card,aux-devs = <&spk_amp>; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphones", ++ "Speaker", "Internal Speakers"; ++ simple-audio-card,routing = ++ "MICL", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "Internal Speakers", "Speaker Amp OUTL", ++ "Internal Speakers", "Speaker Amp OUTR", ++ "Speaker Amp INL", "HPOL", ++ "Speaker Amp INR", "HPOR"; ++ simple-audio-card,pin-switches = "Internal Speakers"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk817>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk817 1>; ++ clock-names = "ext_clock"; ++ pinctrl-0 = <&wifi_enable_h>; ++ pinctrl-names = "default"; ++ post-power-on-delay-ms = <200>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ spk_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&spk_amp_enable_h>; ++ pinctrl-names = "default"; ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ pinctrl-0 = <&vcc_lcd_h>; ++ pinctrl-names = "default"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_lcd0_n"; ++ vin-supply = <&vcc_3v3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_sys: regulator-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3800000>; ++ regulator-max-microvolt = <3800000>; ++ regulator-name = "vcc_sys"; ++ }; ++ ++ vcc_wifi: regulator-vcc-wifi { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&vcc_wifi_h>; ++ pinctrl-names = "default"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_wifi"; ++ }; ++ ++ vibrator: pwm-vibrator { ++ compatible = "pwm-vibrator"; ++ pwm-names = "enable"; ++ pwms = <&pwm5 0 1000000000 0>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c5>; ++ pinctrl-0 = <&hdmitxm0_cec>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk817: pmic@20 { ++ compatible = "rockchip,rk817"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&dcdc_boost>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_logic"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_gpu"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_ddr"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_3v3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_acodec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_1v8: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc1v8_dvp"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc2v8_dvp"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ dcdc_boost: BOOST { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4700000>; ++ regulator-max-microvolt = <5400000>; ++ regulator-name = "boost"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ otg_switch: OTG_SWITCH { ++ regulator-name = "otg_switch"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu: regulator@40 { ++ compatible = "fcs,fan53555"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-init-microvolt = <900000>; ++ regulator-name = "vdd_cpu"; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ /* Unknown/unused device at 0x3c */ ++ status = "disabled"; ++}; ++ ++&i2c5 { ++ pinctrl-0 = <&i2c5m1_xfer>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ pinctrl-names = "default"; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ audio-amplifier { ++ spk_amp_enable_h: spk-amp-enable-h { ++ rockchip,pins = ++ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpio-btns { ++ btn_pins_ctrl: btn-pins-ctrl { ++ rockchip,pins = ++ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ btn_pins_vol: btn-pins-vol { ++ rockchip,pins = ++ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-led { ++ led_pins: led-pins { ++ rockchip,pins = ++ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ joy-mux { ++ joy_mux_en: joy-mux-en { ++ rockchip,pins = ++ <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = ++ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ vcc3v3-lcd { ++ vcc_lcd_h: vcc-lcd-h { ++ rockchip,pins = ++ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ vcc-wifi { ++ vcc_wifi_h: vcc-wifi-h { ++ rockchip,pins = ++ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc1v8_dvp>; ++ vccio7-supply = <&vcc_3v3>; ++}; ++ ++&pwm5 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc1v8_dvp>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vcc_wifi>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "realtek,rtl8821cs-bt"; ++ device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; ++ enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; ++ host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++/* ++ * Lack the schematics to verify, but port works as a peripheral ++ * (and not a host or OTG port). ++ */ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ phy-names = "usb2-phy", "usb3-phy"; ++ phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>; ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Mon, 18 Jul 2022 05:31:45 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b + +This adds the regulator node to the quartz64-b device tree, +and enables the PCIe 2 controller and combphy for it. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220718033145.792657-1-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +index c8315d703ad0..0f623198970f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +@@ -69,6 +69,18 @@ sdio_pwrseq: sdio-pwrseq { + power-off-delay-us = <5000000>; + }; + ++ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pcie_p"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3>; ++ }; ++ + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; +@@ -128,6 +140,10 @@ &combphy1 { + status = "okay"; + }; + ++&combphy2 { ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; +@@ -457,6 +473,14 @@ rgmii_phy1: ethernet-phy@1 { + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie_p>; ++ status = "okay"; ++}; ++ + &pinctrl { + bt { + bt_enable_h: bt-enable-h { +@@ -478,6 +502,16 @@ user_led_enable_h: user-led-enable-h { + }; + }; + ++ pcie { ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 26 Jul 2022 10:30:46 +0800 +Subject: [PATCH] arm64: dts: rockchip: add rtc to rock3a + +Add devicetree node for hym8563 rtc to +Radxa ROCK3 Model A board. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20220726023046.5876-1-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 52a437f48301..28a1db4958c7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -484,6 +484,23 @@ &i2c4 { + status = "disabled"; + }; + ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ + &i2s0_8ch { + status = "okay"; + }; +@@ -524,6 +541,12 @@ eth_phy_rst: eth_phy_rst { + }; + }; + ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 26 Jul 2022 10:35:16 +0800 +Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on rock3a + +Add the nodes to enable the PCIe controller on the +Radxa ROCK3 Model A board. Run test with the MT7921 +pcie wireless card. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20220726023516.6487-1-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 28a1db4958c7..fb87a168fe96 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -67,6 +67,18 @@ vcc12v_dcin: vcc12v-dcin { + regulator-boot-on; + }; + ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -173,6 +185,10 @@ &combphy1 { + status = "okay"; + }; + ++&combphy2 { ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; +@@ -522,6 +538,14 @@ rgmii_phy1: ethernet-phy@0 { + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ + &pinctrl { + cam { + vcc_cam_en: vcc_cam_en { +@@ -553,6 +577,16 @@ led_user_en: led_user_en { + }; + }; + ++ pcie { ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Oniszczuk +Date: Mon, 14 Feb 2022 22:29:54 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add VPU support for RK3568/RK3566 + +RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 +video formats. + +This patch enables RK356x video decoder in RK356x device-tree +include. + +Tested on [1] with FFmpeg v4l2_request code taken from [2] +with MPEG2, H.642 and VP8 samples with results [3]. + +[1] https://github.com/warpme/minimyth2 +[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch +[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt + +Signed-off-by: Piotr Oniszczuk +Reviewed-by: Ezequiel Garcia +Link: https://lore.kernel.org/r/20220214212955.1178947-2-piotr.oniszczuk@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index c66b60302803..351797102a19 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -592,6 +592,26 @@ gpu: gpu@fde60000 { + status = "disabled"; + }; + ++ vpu: video-codec@fdea0400 { ++ compatible = "rockchip,rk3568-vpu"; ++ reg = <0x0 0xfdea0000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vdpu_mmu>; ++ power-domains = <&power RK3568_PD_VPU>; ++ }; ++ ++ vdpu_mmu: iommu@fdea0800 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdea0800 0x0 0x40>; ++ interrupts = ; ++ clock-names = "aclk", "iface"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ power-domains = <&power RK3568_PD_VPU>; ++ #iommu-cells = <0>; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Sun, 12 Jun 2022 17:53:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add Hantro encoder node to rk356x + +The RK3566 and RK3568 come with a dedicated Hantro instance solely for +encoding. This patch adds a node for this to the device tree, along with +a node for its MMU. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220612155346.16288-4-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 351797102a19..fd903e697aa2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -612,6 +612,26 @@ vdpu_mmu: iommu@fdea0800 { + #iommu-cells = <0>; + }; + ++ vepu: video-codec@fdee0000 { ++ compatible = "rockchip,rk3568-vepu"; ++ reg = <0x0 0xfdee0000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu_mmu>; ++ power-domains = <&power RK3568_PD_RGA>; ++ }; ++ ++ vepu_mmu: iommu@fdee0800 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdee0800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3568_PD_RGA>; ++ #iommu-cells = <0>; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Judy Hsiao +Date: Fri, 8 Jul 2022 08:07:26 +0000 +Subject: [PATCH] arm64: dts: rockchip: use BCLK to GPIO switch on rk3399 + +We discoverd that the state of BCLK on, LRCLK off and SD_MODE on +may cause the speaker melting issue. Removing LRCLK while BCLK +is present can cause unexpected output behavior including a large +DC output voltage as described in the Max98357a datasheet. + +In order to: + 1. prevent BCLK from turning on by other component. + 2. keep BCLK and LRCLK being present at the same time + +This patch adjusts the device tree to allow BCLK to switch +to GPIO func before LRCLK output, and switch back during +LRCLK is output. + +Signed-off-by: Judy Hsiao +Reviewed-by: Brian Norris +Link: https://lore.kernel.org/r/20220708080726.4170711-1-judyhsiao@chromium.org +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 10 ++++++++ + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++- + 2 files changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +index 40d4053fba80..ed3348b558f8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +@@ -768,6 +768,16 @@ &i2s0_8ch_bus { + <4 RK_PA0 1 &pcfg_pull_none_6ma>; + }; + ++&i2s0_8ch_bus_bclk_off { ++ rockchip,pins = ++ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, ++ <3 RK_PD1 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD2 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD3 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD7 1 &pcfg_pull_none_6ma>, ++ <4 RK_PA0 1 &pcfg_pull_none_6ma>; ++}; ++ + /* there is no external pull up, so need to set this pin pull up */ + &sdmmc_cd_pin { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 9d5b0e8c9cca..f4fbd5bece0e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1664,8 +1664,9 @@ i2s0: i2s@ff880000 { + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; +- pinctrl-names = "default"; ++ pinctrl-names = "bclk_on", "bclk_off"; + pinctrl-0 = <&i2s0_8ch_bus>; ++ pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; +@@ -2409,6 +2410,19 @@ i2s0_8ch_bus: i2s0-8ch-bus { + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; ++ ++ i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { ++ rockchip,pins = ++ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ <3 RK_PD6 1 &pcfg_pull_none>, ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ <4 RK_PA0 1 &pcfg_pull_none>; ++ }; + }; + + i2s1 { +@@ -2420,6 +2434,15 @@ i2s1_2ch_bus: i2s1-2ch-bus { + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; ++ ++ i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { ++ rockchip,pins = ++ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PA4 1 &pcfg_pull_none>, ++ <4 RK_PA5 1 &pcfg_pull_none>, ++ <4 RK_PA6 1 &pcfg_pull_none>, ++ <4 RK_PA7 1 &pcfg_pull_none>; ++ }; + }; + + sdio0 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Furkan Kardame +Date: Mon, 27 Jun 2022 23:22:08 +0300 +Subject: [PATCH] arm64: dts: rockchip: Enable video output on rk3566-roc-pc + +Add the device tree nodes to enable video output on the Station M2. +Enable the GPU and HDMI nodes and fix the GPU regulator range. + +Signed-off-by: Furkan Kardame +Link: https://lore.kernel.org/r/20220627202208.45770-1-f.kardame@manjaro.org +Signed-off-by: Heiko Stuebner +--- + .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 52 +++++++++++++++++++ + 1 file changed, 52 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +index 57759b66d44d..dba648c2f57e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3566.dtsi" + + / { +@@ -27,6 +28,17 @@ gmac1_clkin: external-gmac1-clock { + #clock-cells = <0>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -149,6 +161,29 @@ &gmac1m0_clkinout + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -577,3 +612,20 @@ &usb_host0_ehci { + &usb_host0_ohci { + status = "okay"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:43 +0100 +Subject: [PATCH] arm64: dts: rockchip: enable gamma control on RK3399 + +Define the memory region on RK3399 VOPs containing the gamma LUT at +base+0x2000. + +Signed-off-by: Hugh Cole-Baker +Tested-by: Linus Heckemann +Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index f4fbd5bece0e..92c2207e686c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1702,7 +1702,7 @@ i2s2: i2s@ff8a0000 { + + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; +- reg = <0x0 0xff8f0000 0x0 0x3efc>; ++ reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; + interrupts = ; + assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <400000000>, <100000000>; +@@ -1758,7 +1758,7 @@ vopl_mmu: iommu@ff8f3f00 { + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; +- reg = <0x0 0xff900000 0x0 0x3efc>; ++ reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <400000000>, <100000000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Wed, 17 Aug 2022 12:33:55 -0700 +Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants + +The Gru-Scarlet family includes a variety of SKU identifiers, using +parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few +different manufacturer names) also use the Innolux display. + +For reference, the original vendor tree source: + +CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 + +CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc + +Signed-off-by: Brian Norris +Link: https://lore.kernel.org/r/20220817123350.1.Ibb15bab32dbfa0d89f86321c4eae7adbc8d7ad4a@changeid +Signed-off-by: Heiko Stuebner +--- + .../devicetree/bindings/arm/rockchip.yaml | 27 ++++++++++++++++++- + 1 file changed, 26 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index ae7fe15a3b89..58fc4b677321 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -373,30 +373,55 @@ properties: + - const: google,gru + - const: rockchip,rk3399 + +- - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) ++ - description: | ++ Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) + items: ++ - const: google,scarlet-rev15-sku2 ++ - const: google,scarlet-rev15-sku4 + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 ++ - const: google,scarlet-rev14-sku2 ++ - const: google,scarlet-rev14-sku4 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 ++ - const: google,scarlet-rev13-sku2 ++ - const: google,scarlet-rev13-sku4 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 ++ - const: google,scarlet-rev12-sku2 ++ - const: google,scarlet-rev12-sku4 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 ++ - const: google,scarlet-rev11-sku2 ++ - const: google,scarlet-rev11-sku4 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 ++ - const: google,scarlet-rev10-sku2 ++ - const: google,scarlet-rev10-sku4 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 ++ - const: google,scarlet-rev9-sku2 ++ - const: google,scarlet-rev9-sku4 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 ++ - const: google,scarlet-rev8-sku2 ++ - const: google,scarlet-rev8-sku4 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 ++ - const: google,scarlet-rev7-sku2 ++ - const: google,scarlet-rev7-sku4 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 ++ - const: google,scarlet-rev6-sku2 ++ - const: google,scarlet-rev6-sku4 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 ++ - const: google,scarlet-rev5-sku2 ++ - const: google,scarlet-rev5-sku4 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 ++ - const: google,scarlet-rev4-sku2 ++ - const: google,scarlet-rev4-sku4 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Wed, 17 Aug 2022 12:33:56 -0700 +Subject: [PATCH] arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants + +The Gru-Scarlet family includes a variety of SKU identifiers, using +parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few +different manufacturer names) also use the Innolux display. + +Without this, a SKU2 device may non-deterministically (depending on the +matching order of DTBs and bootloader behavior) select either one of the +INX DTBs (rk3399-gru-scarlet-dumo.dtb or rk3399-gru-scarlet-inx.dtb) or +the KingDisplay DTB (rk3399-gru-scarlet-kd.dtb), to ill effect. + +For reference, the original vendor tree source: + +CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 + +CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc + +Signed-off-by: Brian Norris +Link: https://lore.kernel.org/r/20220817123350.2.I5f4fd0808a927b08e267c189712fb4a85931fd3b@changeid +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts +index 2d721a974790..5d1879033e7c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts +@@ -11,17 +11,29 @@ + + / { + model = "Google Scarlet"; +- compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", ++ compatible = "google,scarlet-rev15-sku2", "google,scarlet-rev15-sku4", ++ "google,scarlet-rev15-sku6", "google,scarlet-rev15", ++ "google,scarlet-rev14-sku2", "google,scarlet-rev14-sku4", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", ++ "google,scarlet-rev13-sku2", "google,scarlet-rev13-sku4", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", ++ "google,scarlet-rev12-sku2", "google,scarlet-rev12-sku4", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", ++ "google,scarlet-rev11-sku2", "google,scarlet-rev11-sku4", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", ++ "google,scarlet-rev10-sku2", "google,scarlet-rev10-sku4", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", ++ "google,scarlet-rev9-sku2", "google,scarlet-rev9-sku4", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", ++ "google,scarlet-rev8-sku2", "google,scarlet-rev8-sku4", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", ++ "google,scarlet-rev7-sku2", "google,scarlet-rev7-sku4", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", ++ "google,scarlet-rev6-sku2", "google,scarlet-rev6-sku4", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", ++ "google,scarlet-rev5-sku2", "google,scarlet-rev5-sku4", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", ++ "google,scarlet-rev4-sku2", "google,scarlet-rev4-sku4", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Markus Reichl +Date: Thu, 15 Sep 2022 13:11:36 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc + +Add avdd-0v9-supply and avdd-1v8-supply to hdmi node for +rk3399-roc-pc to silence dmesg warning and match the name +of the 1v8 supply to the circuit sheet. + +Signed-off-by: Markus Reichl +Link: https://lore.kernel.org/r/20220915111138.1108-1-m.reichl@fivetechno.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +index acb174d3a8c5..2f4b1b2e3ac7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -271,6 +271,8 @@ &gpu { + }; + + &hdmi { ++ avdd-0v9-supply = <&vcca0v9_hdmi>; ++ avdd-1v8-supply = <&vcca1v8_hdmi>; + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; +@@ -369,8 +371,8 @@ regulator-state-mem { + }; + }; + +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Quentin Schulz +Date: Fri, 16 Sep 2022 11:17:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to + px30 + +The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are +2-channel I2S/PCM controllers handled by the same controller driver, and +i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller +driver. + +This adds the device tree node required to enable I2S0 on PX30. + +This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX +(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board. + +Signed-off-by: Quentin Schulz +Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 214f94fea3dc..bfa3580429d1 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -365,6 +365,28 @@ uart0: serial@ff030000 { + status = "disabled"; + }; + ++ i2s0_8ch: i2s@ff060000 { ++ compatible = "rockchip,px30-i2s-tdm"; ++ reg = <0x0 0xff060000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac 16>, <&dmac 17>; ++ dma-names = "tx", "rx"; ++ rockchip,grf = <&grf>; ++ resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; ++ reset-names = "tx-m", "rx-m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx ++ &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx ++ &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 ++ &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 ++ &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 ++ &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s1_2ch: i2s@ff070000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff070000 0x0 0x1000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 15 Sep 2022 10:25:10 +0800 +Subject: [PATCH] dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise + Edition + +Add devicetree binding documentation for the FriendlyARM NanoPi R4S +Enterprise Edition. + +Signed-off-by: Tianling Shen +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220915022511.4267-1-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 58fc4b677321..4c64d9ff089c 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -161,6 +161,7 @@ properties: + - friendlyarm,nanopi-m4b + - friendlyarm,nanopi-neo4 + - friendlyarm,nanopi-r4s ++ - friendlyarm,nanopi-r4s-enterprise + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 15 Sep 2022 10:25:11 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise + Edition + +The only diffrence against the standrard edition is that the enterprise +one has a built-in EEPROM chip which stores a globally unique MAC address. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3399-nanopi-r4s-enterprise.dts | 29 +++++++++++++++++++ + 2 files changed, 30 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 94639380ec1e..8c15593c0ca4 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +new file mode 100644 +index 000000000000..a23d11ca0eb6 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include "rk3399-nanopi-r4s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S Enterprise Edition"; ++ compatible = "friendlyarm,nanopi-r4s-enterprise", "rockchip,rk3399"; ++}; ++ ++&gmac { ++ nvmem-cells = <&mac_address>; ++ nvmem-cell-names = "mac-address"; ++}; ++ ++&i2c2 { ++ eeprom@51 { ++ compatible = "microchip,24c02", "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ size = <256>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ mac_address: mac-address@fa { ++ reg = <0xfa 0x06>; ++ }; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 12:48:21 -0500 +Subject: [PATCH] drm/rockchip: dsi: add rk3568 support + +Add the compatible and GRF definitions for the RK3568 soc. + +Signed-off-by: Chris Morgan +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20220906174823.28561-4-macroalpha82@gmail.com +--- + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 ++++++++++++++++++- + 1 file changed, 49 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +index 110e83aad9bb..bf6948125b84 100644 +--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +@@ -179,6 +179,23 @@ + #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) + #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) + ++#define RK3568_GRF_VO_CON2 0x0368 ++#define RK3568_DSI0_SKEWCALHS (0x1f << 11) ++#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) ++#define RK3568_DSI0_TURNDISABLE BIT(2) ++#define RK3568_DSI0_FORCERXMODE BIT(0) ++ ++/* ++ * Note these registers do not appear in the datasheet, they are ++ * however present in the BSP driver which is where these values ++ * come from. Name GRF_VO_CON3 is assumed. ++ */ ++#define RK3568_GRF_VO_CON3 0x36c ++#define RK3568_DSI1_SKEWCALHS (0x1f << 11) ++#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) ++#define RK3568_DSI1_TURNDISABLE BIT(2) ++#define RK3568_DSI1_FORCERXMODE BIT(0) ++ + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + + enum { +@@ -735,8 +752,9 @@ static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) + static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, + int mux) + { +- regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, +- mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); ++ if (dsi->cdata->lcdsel_grf_reg < 0) ++ regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, ++ mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); + } + + static int +@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, + DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); + goto out_pll_clk; + } ++ rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, ++ dev->of_node, 0, 0); + + ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); + if (ret) { +@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { + { /* sentinel */ } + }; + ++static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { ++ { ++ .reg = 0xfe060000, ++ .lcdsel_grf_reg = -1, ++ .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, ++ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | ++ RK3568_DSI0_FORCETXSTOPMODE | ++ RK3568_DSI0_TURNDISABLE | ++ RK3568_DSI0_FORCERXMODE), ++ .max_data_lanes = 4, ++ }, ++ { ++ .reg = 0xfe070000, ++ .lcdsel_grf_reg = -1, ++ .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, ++ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | ++ RK3568_DSI1_FORCETXSTOPMODE | ++ RK3568_DSI1_TURNDISABLE | ++ RK3568_DSI1_FORCERXMODE), ++ .max_data_lanes = 4, ++ }, ++ { /* sentinel */ } ++}; ++ + static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { + { + .compatible = "rockchip,px30-mipi-dsi", +@@ -1622,6 +1666,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { + }, { + .compatible = "rockchip,rk3399-mipi-dsi", + .data = &rk3399_chip_data, ++ }, { ++ .compatible = "rockchip,rk3568-mipi-dsi", ++ .data = &rk3568_chip_data, + }, + { /* sentinel */ } + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:41 +0100 +Subject: [PATCH] drm/rockchip: define gamma registers for RK3399 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The VOP on RK3399 has a different approach from previous versions for +setting a gamma lookup table, using an update_gamma_lut register. As +this differs from RK3288, give RK3399 its own set of "common" register +definitions. + +Signed-off-by: Hugh Cole-Baker +Tested-by: "Milan P. Stanić" +Tested-by: Linus Heckemann +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-2-sigmaris@gmail.com +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++-- + drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + + 3 files changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +index ba88addc1a75..8502849833d9 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +@@ -113,6 +113,8 @@ struct vop_common { + struct vop_reg dither_down_en; + struct vop_reg dither_up; + struct vop_reg dsp_lut_en; ++ struct vop_reg update_gamma_lut; ++ struct vop_reg lut_buffer_index; + struct vop_reg gate_en; + struct vop_reg mmu_en; + struct vop_reg out_mode; +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index d03dd0402923..014f99e8928e 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -875,6 +875,24 @@ static const struct vop_output rk3399_output = { + .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), + }; + ++static const struct vop_common rk3399_common = { ++ .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), ++ .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), ++ .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), ++ .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), ++ .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), ++ .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), ++ .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), ++ .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), ++ .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), ++ .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), ++ .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), ++ .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), ++ .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), ++ .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), ++ .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), ++}; ++ + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { + .y2r_coefficients = { + VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), +@@ -957,7 +975,7 @@ static const struct vop_data rk3399_vop_big = { + .version = VOP_VERSION(3, 5), + .feature = VOP_FEATURE_OUTPUT_RGB10, + .intr = &rk3366_vop_intr, +- .common = &rk3288_common, ++ .common = &rk3399_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .afbc = &rk3399_vop_afbc, +@@ -965,6 +983,7 @@ static const struct vop_data rk3399_vop_big = { + .win = rk3399_vop_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_win_data), + .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, ++ .lut_size = 1024, + }; + + static const struct vop_win_data rk3399_vop_lit_win_data[] = { +@@ -983,13 +1002,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { + static const struct vop_data rk3399_vop_lit = { + .version = VOP_VERSION(3, 6), + .intr = &rk3366_vop_intr, +- .common = &rk3288_common, ++ .common = &rk3399_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3368_misc, + .win = rk3399_vop_lit_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), + .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, ++ .lut_size = 256, + }; + + static const struct vop_win_data rk3228_vop_win_data[] = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +index 0b3cd65ba5c1..406e981c75bd 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +@@ -628,6 +628,7 @@ + #define RK3399_YUV2YUV_WIN 0x02c0 + #define RK3399_YUV2YUV_POST 0x02c4 + #define RK3399_AUTO_GATING_EN 0x02cc ++#define RK3399_DBG_POST_REG1 0x036c + #define RK3399_WIN0_CSC_COE 0x03a0 + #define RK3399_WIN1_CSC_COE 0x03c0 + #define RK3399_WIN2_CSC_COE 0x03e0 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:42 +0100 +Subject: [PATCH] drm/rockchip: support gamma control on RK3399 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its +"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP. +Compared to the RK3288, it no longer requires disabling gamma while +updating the LUT. On the RK3399, the LUT can be updated at any time as +the hardware has two LUT buffers, one can be written while the other is +in use. A swap of the buffers is triggered by writing 1 to the +update_gamma_lut register. + +Signed-off-by: Hugh Cole-Baker +Tested-by: "Milan P. Stanić" +Tested-by: Linus Heckemann +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-3-sigmaris@gmail.com +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++------- + 1 file changed, 71 insertions(+), 34 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index ad3958b6f8bf..d32117633efe 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -68,6 +69,9 @@ + #define VOP_REG_SET(vop, group, name, v) \ + vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) + ++#define VOP_HAS_REG(vop, group, name) \ ++ (!!(vop->data->group->name.mask)) ++ + #define VOP_INTR_SET_TYPE(vop, name, type, v) \ + do { \ + int i, reg = 0, mask = 0; \ +@@ -1224,17 +1228,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop) + return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); + } + ++static u32 vop_lut_buffer_index(struct vop *vop) ++{ ++ return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); ++} ++ + static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) + { + struct drm_color_lut *lut = crtc->state->gamma_lut->data; +- unsigned int i; ++ unsigned int i, bpc = ilog2(vop->data->lut_size); + + for (i = 0; i < crtc->gamma_size; i++) { + u32 word; + +- word = (drm_color_lut_extract(lut[i].red, 10) << 20) | +- (drm_color_lut_extract(lut[i].green, 10) << 10) | +- drm_color_lut_extract(lut[i].blue, 10); ++ word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | ++ (drm_color_lut_extract(lut[i].green, bpc) << bpc) | ++ drm_color_lut_extract(lut[i].blue, bpc); + writel(word, vop->lut_regs + i * 4); + } + } +@@ -1244,38 +1253,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, + { + struct drm_crtc_state *state = crtc->state; + unsigned int idle; ++ u32 lut_idx, old_idx; + int ret; + + if (!vop->lut_regs) + return; +- /* +- * To disable gamma (gamma_lut is null) or to write +- * an update to the LUT, clear dsp_lut_en. +- */ +- spin_lock(&vop->reg_lock); +- VOP_REG_SET(vop, common, dsp_lut_en, 0); +- vop_cfg_done(vop); +- spin_unlock(&vop->reg_lock); + +- /* +- * In order to write the LUT to the internal memory, +- * we need to first make sure the dsp_lut_en bit is cleared. +- */ +- ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, +- idle, !idle, 5, 30 * 1000); +- if (ret) { +- DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); +- return; +- } ++ if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { ++ /* ++ * To disable gamma (gamma_lut is null) or to write ++ * an update to the LUT, clear dsp_lut_en. ++ */ ++ spin_lock(&vop->reg_lock); ++ VOP_REG_SET(vop, common, dsp_lut_en, 0); ++ vop_cfg_done(vop); ++ spin_unlock(&vop->reg_lock); + +- if (!state->gamma_lut) +- return; ++ /* ++ * In order to write the LUT to the internal memory, ++ * we need to first make sure the dsp_lut_en bit is cleared. ++ */ ++ ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, ++ idle, !idle, 5, 30 * 1000); ++ if (ret) { ++ DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); ++ return; ++ } ++ ++ if (!state->gamma_lut) ++ return; ++ } else { ++ /* ++ * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, ++ * by setting update_gamma_lut then waiting for lut_buffer_index change ++ */ ++ old_idx = vop_lut_buffer_index(vop); ++ } + + spin_lock(&vop->reg_lock); + vop_crtc_write_gamma_lut(vop, crtc); + VOP_REG_SET(vop, common, dsp_lut_en, 1); ++ VOP_REG_SET(vop, common, update_gamma_lut, 1); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); ++ ++ if (VOP_HAS_REG(vop, common, update_gamma_lut)) { ++ ret = readx_poll_timeout(vop_lut_buffer_index, vop, ++ lut_idx, lut_idx != old_idx, 5, 30 * 1000); ++ if (ret) { ++ DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); ++ return; ++ } ++ ++ /* ++ * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit ++ * in our backup of the regs. ++ */ ++ spin_lock(&vop->reg_lock); ++ VOP_REG_SET(vop, common, update_gamma_lut, 0); ++ spin_unlock(&vop->reg_lock); ++ } + } + + static void vop_crtc_atomic_begin(struct drm_crtc *crtc, +@@ -1325,14 +1362,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + return; + } + +- /* +- * If we have a GAMMA LUT in the state, then let's make sure +- * it's updated. We might be coming out of suspend, +- * which means the LUT internal memory needs to be re-written. +- */ +- if (crtc->state->gamma_lut) +- vop_crtc_gamma_set(vop, crtc, old_state); +- + mutex_lock(&vop->vop_lock); + + WARN_ON(vop->event); +@@ -1423,6 +1452,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + + VOP_REG_SET(vop, common, standby, 0); + mutex_unlock(&vop->vop_lock); ++ ++ /* ++ * If we have a GAMMA LUT in the state, then let's make sure ++ * it's updated. We might be coming out of suspend, ++ * which means the LUT internal memory needs to be re-written. ++ */ ++ if (crtc->state->gamma_lut) ++ vop_crtc_gamma_set(vop, crtc, old_state); + } + + static bool vop_fs_irq_is_pending(struct vop *vop) +@@ -2148,8 +2185,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data) + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { +- if (!vop_data->lut_size) { +- DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); ++ if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { ++ DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); + return -EINVAL; + } + vop->lut_regs = devm_ioremap_resource(dev, res); diff --git a/patch/kernel/archive/media-5.19/00110-linux-0002-rockchip-from-list.patch b/patch/kernel/media-current/00180-linux-0002-rockchip-from-list.patch similarity index 99% rename from patch/kernel/archive/media-5.19/00110-linux-0002-rockchip-from-list.patch rename to patch/kernel/media-current/00180-linux-0002-rockchip-from-list.patch index 5afb775c2..21da17d29 100644 --- a/patch/kernel/archive/media-5.19/00110-linux-0002-rockchip-from-list.patch +++ b/patch/kernel/media-current/00180-linux-0002-rockchip-from-list.patch @@ -270,10 +270,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index 4b70cbfc6d5d..5329f983db15 100644 +index ef53a2578824..d4c53074154a 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1356,6 +1356,14 @@ void mmc_power_off(struct mmc_host *host) +@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host) if (host->ios.power_mode == MMC_POWER_OFF) return; diff --git a/patch/kernel/archive/media-5.19/00120-linux-0011-v4l2-from-list.patch b/patch/kernel/media-current/00190-linux-0011-v4l2-from-list.patch similarity index 94% rename from patch/kernel/archive/media-5.19/00120-linux-0011-v4l2-from-list.patch rename to patch/kernel/media-current/00190-linux-0011-v4l2-from-list.patch index 363d3ef7f..7c4afd72e 100644 --- a/patch/kernel/archive/media-5.19/00120-linux-0011-v4l2-from-list.patch +++ b/patch/kernel/media-current/00190-linux-0011-v4l2-from-list.patch @@ -17,10 +17,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index df34b2a283bc..287488016ff2 100644 +index e0fbe6ba4b6c..cb2f1acab7cf 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -336,6 +336,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf +@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf return info->block_h[plane]; } @@ -54,7 +54,7 @@ index df34b2a283bc..287488016ff2 100644 void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, const struct v4l2_frmsize_stepwise *frmsize) { -@@ -371,37 +398,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, +@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, if (info->mem_planes == 1) { plane = &pixfmt->plane_fmt[0]; @@ -99,7 +99,7 @@ index df34b2a283bc..287488016ff2 100644 } } return 0; -@@ -425,22 +434,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, +@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, pixfmt->width = width; pixfmt->height = height; pixfmt->pixelformat = pixelformat; @@ -154,12 +154,12 @@ Signed-off-by: Jonas Karlman 3 files changed, 8 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 287488016ff2..01f8a50586eb 100644 +index cb2f1acab7cf..8446a1deffd8 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, +@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, + { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, + { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, @@ -168,25 +168,25 @@ index 287488016ff2..01f8a50586eb 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 21470de62d72..cb7496c084f6 100644 +index e6fd355a2e92..24771edaa4f2 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1306,6 +1306,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; +@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; + case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break; + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break; + case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break; case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break; case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break; case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 343b95107fce..3a5d6290a379 100644 +index 01e630f2ec78..cea44992aea3 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -603,6 +603,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +@@ -628,6 +628,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ +#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ @@ -212,10 +212,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 2992fb87cf72..54fc3a6d0902 100644 +index 4fc167b42cf0..a8635105e387 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -915,9 +915,9 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, dma_addr_t rlc_addr; dma_addr_t refer_addr; u32 rlc_len; @@ -228,7 +228,7 @@ index 2992fb87cf72..54fc3a6d0902 100644 u32 yuv_virstride = 0; u32 offset; dma_addr_t dst_addr; -@@ -928,8 +928,8 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx, f = &ctx->decoded_fmt; dst_fmt = &f->fmt.pix_mp; @@ -487,10 +487,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 54fc3a6d0902..af530b05a789 100644 +index a8635105e387..0069d3d198db 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1044,19 +1044,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, +@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, { unsigned int width, height; @@ -514,7 +514,7 @@ index 54fc3a6d0902..af530b05a789 100644 return -EINVAL; width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1077,6 +1072,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, +@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, return 0; } @@ -540,7 +540,7 @@ index 54fc3a6d0902..af530b05a789 100644 static int rkvdec_h264_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1198,6 +1212,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { .adjust_fmt = rkvdec_h264_adjust_fmt, @@ -624,7 +624,7 @@ Signed-off-by: Alex Bee 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index af530b05a789..f31b7c021d82 100644 +index 0069d3d198db..2c27acaba85e 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, diff --git a/patch/kernel/archive/media-5.19/00130-linux-0020-drm-from-list.patch b/patch/kernel/media-current/00200-linux-0020-drm-from-list.patch similarity index 93% rename from patch/kernel/archive/media-5.19/00130-linux-0020-drm-from-list.patch rename to patch/kernel/media-current/00200-linux-0020-drm-from-list.patch index 4b796a94e..2c8088f90 100644 --- a/patch/kernel/archive/media-5.19/00130-linux-0020-drm-from-list.patch +++ b/patch/kernel/media-current/00200-linux-0020-drm-from-list.patch @@ -43,7 +43,7 @@ index 07741b678798..5ec38456dc5d 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index f1972154a594..b972d0adfa2e 100644 +index 0206f812c569..fa49ee98f275 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -285,6 +285,8 @@ extern "C" { @@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 74562d40f639..9560f82ce880 100644 +index d32117633efe..9e71263ac770 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -274,6 +274,18 @@ static bool has_uv_swapped(uint32_t format) +@@ -280,6 +280,18 @@ static bool has_uv_swapped(uint32_t format) } } @@ -98,7 +98,7 @@ index 74562d40f639..9560f82ce880 100644 static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { -@@ -289,12 +301,15 @@ static enum vop_data_format vop_convert_format(uint32_t format) +@@ -295,12 +307,15 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: @@ -114,7 +114,7 @@ index 74562d40f639..9560f82ce880 100644 case DRM_FORMAT_NV42: return VOP_FMT_YUV444SP; default: -@@ -948,7 +963,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -954,7 +969,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); @@ -128,7 +128,7 @@ index 74562d40f639..9560f82ce880 100644 offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; -@@ -974,6 +994,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -980,6 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); @@ -136,7 +136,7 @@ index 74562d40f639..9560f82ce880 100644 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); -@@ -990,7 +1011,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -996,7 +1017,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); @@ -150,10 +150,10 @@ index 74562d40f639..9560f82ce880 100644 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index ba88addc1a75..567f226930b2 100644 +index 8502849833d9..b6eea31109d5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -179,6 +179,7 @@ struct vop_win_phy { +@@ -181,6 +181,7 @@ struct vop_win_phy { struct vop_reg enable; struct vop_reg gate; struct vop_reg format; @@ -162,7 +162,7 @@ index ba88addc1a75..567f226930b2 100644 struct vop_reg uv_swap; struct vop_reg act_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index d03dd0402923..3b39b5a5f100 100644 +index 014f99e8928e..16e6aa01e400 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] = { @@ -219,7 +219,7 @@ index d03dd0402923..3b39b5a5f100 100644 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), -@@ -906,11 +925,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -924,11 +943,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, diff --git a/patch/kernel/archive/media-5.19/00140-linux-1000-drm-rockchip.patch b/patch/kernel/media-current/00210-linux-1000-drm-rockchip.patch similarity index 84% rename from patch/kernel/archive/media-5.19/00140-linux-1000-drm-rockchip.patch rename to patch/kernel/media-current/00210-linux-1000-drm-rockchip.patch index 0e9ec6c13..5bbdaabb7 100644 --- a/patch/kernel/archive/media-5.19/00140-linux-1000-drm-rockchip.patch +++ b/patch/kernel/media-current/00210-linux-1000-drm-rockchip.patch @@ -13,12 +13,12 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 9560f82ce880..c3fea637974f 100644 +index 9e71263ac770..dbe4d411b30f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1595,7 +1595,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) - { - struct rockchip_crtc_state *rockchip_state; +@@ -1637,7 +1637,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) + if (WARN_ON(!crtc->state)) + return NULL; - rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); + if (WARN_ON(!crtc->state)) @@ -42,15 +42,16 @@ from the requested pixel clock. This filter is only applied to tmds only connector and/or encoders. Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c3fea637974f..e736c735ec38 100644 +index dbe4d411b30f..fac23d370ee0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1200,6 +1200,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) +@@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -70,10 +71,10 @@ index c3fea637974f..e736c735ec38 100644 + } + + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) -+ if (encoder->encoder_type != DRM_MODE_ENCODER_TMDS) -+ return false; ++ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) ++ return true; + -+ return true; ++ return false; +} + +/* @@ -110,7 +111,7 @@ index c3fea637974f..e736c735ec38 100644 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -1578,6 +1631,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, +@@ -1617,6 +1670,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { @@ -133,10 +134,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index e736c735ec38..2b765ec02a6e 100644 +index fac23d370ee0..9f7326c5b1f5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1238,6 +1238,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (!vop_crtc_is_tmds(crtc)) return MODE_OK; @@ -160,10 +161,10 @@ Signed-off-by: Jonas Karlman 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 567f226930b2..8db9ea4055f6 100644 +index b6eea31109d5..ca4e2b7415fe 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -212,6 +212,11 @@ struct vop_win_data { +@@ -214,6 +214,11 @@ struct vop_win_data { enum drm_plane_type type; }; @@ -175,7 +176,7 @@ index 567f226930b2..8db9ea4055f6 100644 struct vop_data { uint32_t version; const struct vop_intr *intr; -@@ -224,6 +229,7 @@ struct vop_data { +@@ -226,6 +231,7 @@ struct vop_data { const struct vop_win_data *win; unsigned int win_size; unsigned int lut_size; @@ -200,7 +201,7 @@ index c727093a06d6..f1234a151130 100644 VOP2_SCALE_UP_NRST_NBOR, VOP2_SCALE_UP_BIL, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 3b39b5a5f100..0a9b64a62483 100644 +index 16e6aa01e400..9b25b8ffd0ce 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -743,6 +743,7 @@ static const struct vop_intr rk3288_vop_intr = { @@ -227,23 +228,23 @@ index 3b39b5a5f100..0a9b64a62483 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -976,6 +979,7 @@ static const struct vop_afbc rk3399_vop_afbc = { +@@ -994,6 +997,7 @@ static const struct vop_afbc rk3399_vop_afbc = { static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, + .max_output = { 4096, 2160 }, .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, -@@ -1002,6 +1006,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { +@@ -1021,6 +1025,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), + .max_output = { 2560, 1600 }, .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, -@@ -1022,6 +1027,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { +@@ -1042,6 +1047,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { static const struct vop_data rk3228_vop = { .version = VOP_VERSION(3, 7), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -251,7 +252,7 @@ index 3b39b5a5f100..0a9b64a62483 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1093,6 +1099,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { +@@ -1113,6 +1119,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_data rk3328_vop = { .version = VOP_VERSION(3, 8), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -268,49 +269,85 @@ Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported Filter any mode with a resolution not supported by the VOP. Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------ + 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 2b765ec02a6e..92caec48ccd8 100644 +index 9f7326c5b1f5..30e252ba7184 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1232,6 +1232,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - const struct drm_display_mode *mode) - { - struct vop *vop = to_vop(crtc); +@@ -1228,6 +1228,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc) + return false; + } + ++static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode) ++{ ++ struct vop *vop = to_vop(crtc); + const struct vop_rect *max_output = &vop->data->max_output; ++ ++ if (max_output->width && max_output->height) { ++ /* only the size of the resulting rect matters */ ++ if(drm_mode_validate_size(mode, max_output->width, ++ max_output->height) != MODE_OK) { ++ return drm_mode_validate_size(mode, max_output->height, ++ max_output->width); ++ } ++ } ++ ++ return MODE_OK; ++} ++ + /* + * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. + * The CVT spec reuses that tolerance in its examples. +@@ -1241,25 +1259,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, long rounded_rate; long lowest, highest; -@@ -1253,6 +1254,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - if (rounded_rate > highest) - return MODE_CLOCK_HIGH; +- if (!vop_crtc_is_tmds(crtc)) +- return MODE_OK; +- + if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- return MODE_NO_INTERLACE; ++ return MODE_NO_INTERLACE; -+ if (max_output->width && max_output->height) -+ return drm_mode_validate_size(mode, max_output->width, -+ max_output->height); -+ - return MODE_OK; +- rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); +- if (rounded_rate < 0) +- return MODE_NOCLOCK; ++ if (vop_crtc_is_tmds(crtc)) { ++ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); ++ if (rounded_rate < 0) ++ return MODE_NOCLOCK; + +- lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate < lowest) +- return MODE_CLOCK_LOW; ++ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate < lowest) ++ return MODE_CLOCK_LOW; + +- highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate > highest) +- return MODE_CLOCK_HIGH; ++ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate > highest) ++ return MODE_CLOCK_HIGH; ++ } + +- return MODE_OK; ++ return vop_crtc_size_valid(crtc, mode); } -@@ -1261,8 +1266,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - struct drm_display_mode *adjusted_mode) - { + static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1269,6 +1286,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct vop *vop = to_vop(crtc); -+ const struct vop_rect *max_output = &vop->data->max_output; unsigned long rate; -+ if (max_output->width && max_output->height) { -+ enum drm_mode_status status; -+ -+ status = drm_mode_validate_size(adjusted_mode, -+ max_output->width, -+ max_output->height); -+ if (status != MODE_OK) -+ return false; -+ } ++ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK) ++ return false; + /* * Clock craziness. @@ -673,30 +710,6 @@ index 0370bb247fcb..55c0b8dddad5 100644 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 3 May 2020 22:36:23 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: limit resolution to 3840x2160 - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 55c0b8dddad5..dadd2f6ef39a 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -246,7 +246,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - (info->max_tmds_clock && mode->clock > info->max_tmds_clock)) - return MODE_CLOCK_HIGH; - -- return MODE_OK; -+ return drm_mode_validate_size(mode, 3840, 2160); - } - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 8 Jan 2020 21:07:49 +0000 @@ -710,7 +723,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index dadd2f6ef39a..62fbeaecbc92 100644 +index 55c0b8dddad5..15ecb257b902 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -327,6 +327,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, @@ -738,7 +751,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 62fbeaecbc92..a4583fa1643e 100644 +index 15ecb257b902..38dded2baaf7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -417,9 +417,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { @@ -773,7 +786,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a4583fa1643e..1bac3c741ee2 100644 +index 38dded2baaf7..9e460b7e14a4 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -558,7 +558,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, @@ -843,7 +856,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 0a9b64a62483..6446f2158d30 100644 +index 9b25b8ffd0ce..a2b281e290e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = { @@ -875,7 +888,7 @@ index 0a9b64a62483..6446f2158d30 100644 static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, -@@ -1122,8 +1135,10 @@ static const struct of_device_id vop_driver_dt_match[] = { +@@ -1142,8 +1155,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3066_vop }, { .compatible = "rockchip,rk3188-vop", .data = &rk3188_vop }, @@ -936,10 +949,10 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3e1be9894ed1..170d291448df 100644 +index 40d8ca37f5bc..22af42a08980 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -137,7 +137,8 @@ struct dw_hdmi_phy_data { +@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { bool has_svsret; int (*configure)(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, @@ -949,7 +962,7 @@ index 3e1be9894ed1..170d291448df 100644 }; struct dw_hdmi { -@@ -1584,7 +1585,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) +@@ -1585,7 +1586,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) */ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, @@ -959,7 +972,7 @@ index 3e1be9894ed1..170d291448df 100644 { const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; -@@ -1659,9 +1661,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, +@@ -1660,9 +1662,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, /* Write to the PHY as configured by the platform */ if (pdata->configure_phy) @@ -1013,10 +1026,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 170d291448df..507b7bf4c7fd 100644 +index 22af42a08980..7fd45a7006b1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1591,6 +1591,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; @@ -1024,7 +1037,7 @@ index 170d291448df..507b7bf4c7fd 100644 /* TOFIX Will need 420 specific PHY configuration tables */ -@@ -1600,11 +1601,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1601,11 +1602,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, break; for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) @@ -1038,7 +1051,7 @@ index 170d291448df..507b7bf4c7fd 100644 break; if (mpll_config->mpixelclock == ~0UL || -@@ -1612,11 +1613,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1613,11 +1614,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, phy_config->mpixelclock == ~0UL) return -EINVAL; @@ -1072,10 +1085,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 507b7bf4c7fd..2eb0f3cf1516 100644 +index 7fd45a7006b1..a2d101ebf7a7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1593,7 +1593,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; int depth; @@ -1110,7 +1123,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1bac3c741ee2..1bf68ddc124c 100644 +index 9e460b7e14a4..d42ac9fa3246 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -242,8 +242,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -1130,7 +1143,7 @@ index 1bac3c741ee2..1bf68ddc124c 100644 + (info->max_tmds_clock && clock > info->max_tmds_clock)) return MODE_CLOCK_HIGH; - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; @@ -531,6 +538,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return -ENOMEM; @@ -1151,7 +1164,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1bf68ddc124c..454c7bba0969 100644 +index d42ac9fa3246..a37565649c13 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -1222,7 +1235,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 454c7bba0969..cb8b2135ddf0 100644 +index a37565649c13..66fee351f4a7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { @@ -1295,14 +1308,22 @@ atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4. Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 117 +++++++++++++------- - 1 file changed, 80 insertions(+), 37 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------ + 1 file changed, 81 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cb8b2135ddf0..da4a829baded 100644 +index 66fee351f4a7..d6d8f3335813 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -72,6 +72,7 @@ struct rockchip_hdmi_chip_data { +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -72,6 +73,7 @@ struct rockchip_hdmi_chip_data { struct rockchip_hdmi { struct device *dev; struct regmap *regmap; @@ -1310,7 +1331,7 @@ index cb8b2135ddf0..da4a829baded 100644 struct rockchip_encoder encoder; const struct rockchip_hdmi_chip_data *chip_data; struct clk *ref_clk; -@@ -82,11 +83,9 @@ struct rockchip_hdmi { +@@ -82,11 +84,9 @@ struct rockchip_hdmi { struct phy *phy; }; @@ -1324,9 +1345,9 @@ index cb8b2135ddf0..da4a829baded 100644 } static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { -@@ -335,31 +334,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; } - -static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) @@ -1365,7 +1386,7 @@ index cb8b2135ddf0..da4a829baded 100644 u32 val; int ret; -@@ -387,10 +376,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) +@@ -387,10 +377,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) ret ? "LIT" : "BIG"); } @@ -1390,7 +1411,7 @@ index cb8b2135ddf0..da4a829baded 100644 { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -@@ -400,12 +400,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +@@ -400,12 +401,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, return 0; } @@ -1435,7 +1456,7 @@ index cb8b2135ddf0..da4a829baded 100644 }; static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -@@ -602,6 +628,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -602,6 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, struct dw_hdmi_plat_data *plat_data; const struct of_device_id *match; struct drm_device *drm = data; @@ -1443,7 +1464,7 @@ index cb8b2135ddf0..da4a829baded 100644 struct drm_encoder *encoder; struct rockchip_hdmi *hdmi; int ret; -@@ -679,20 +706,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -679,20 +707,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, RK3568_HDMI_SCLIN_MSK)); } @@ -1469,7 +1490,7 @@ index cb8b2135ddf0..da4a829baded 100644 * which would have called the encoder cleanup. Do it manually. */ if (IS_ERR(hdmi->hdmi)) { -@@ -700,8 +728,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -700,8 +729,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, goto err_bind; } @@ -1493,7 +1514,7 @@ index cb8b2135ddf0..da4a829baded 100644 err_bind: drm_encoder_cleanup(encoder); err_disable_clk: -@@ -719,7 +762,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); @@ -1503,78 +1524,6 @@ index cb8b2135ddf0..da4a829baded 100644 regulator_disable(hdmi->avdd_1v8); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 9 Oct 2020 15:24:53 +0000 -Subject: [PATCH] drm/rockchip: vop: create planes in window order - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ - 1 file changed, 4 insertions(+), 32 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 92caec48ccd8..3e2a0ce1a137 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1894,19 +1894,10 @@ static int vop_create_crtc(struct vop *vop) - int ret; - int i; - -- /* -- * Create drm_plane for primary and cursor planes first, since we need -- * to pass them to drm_crtc_init_with_planes, which sets the -- * "possible_crtcs" to the newly initialized crtc. -- */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; - const struct vop_win_data *win_data = vop_win->data; - -- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && -- win_data->type != DRM_PLANE_TYPE_CURSOR) -- continue; -- - ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, - 0, &vop_plane_funcs, - win_data->phy->data_formats, -@@ -1939,32 +1930,13 @@ static int vop_create_crtc(struct vop *vop) - drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); - } - -- /* -- * Create drm_planes for overlay windows with possible_crtcs restricted -- * to the newly created crtc. -- */ -+ /* Set possible_crtcs to the newly created crtc for overlay windows */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; -- const struct vop_win_data *win_data = vop_win->data; -- unsigned long possible_crtcs = drm_crtc_mask(crtc); -- -- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) -- continue; - -- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, -- possible_crtcs, -- &vop_plane_funcs, -- win_data->phy->data_formats, -- win_data->phy->nformats, -- win_data->phy->format_modifiers, -- win_data->type, NULL); -- if (ret) { -- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", -- ret); -- goto err_cleanup_crtc; -- } -- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); -- vop_plane_add_properties(&vop_win->base, win_data); -+ plane = &vop_win->base; -+ if (plane->type == DRM_PLANE_TYPE_OVERLAY) -+ plane->possible_crtcs = drm_crtc_mask(crtc); - } - - port = of_get_child_by_name(dev->of_node, "port"); - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 9 Oct 2020 15:29:27 +0000 @@ -1587,10 +1536,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 0d2cb4f3922b..e46965d16dd0 100644 +index 092bf863110b..e2ee0d6a8d55 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -132,6 +132,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) +@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; @@ -1600,10 +1549,10 @@ index 0d2cb4f3922b..e46965d16dd0 100644 dev->mode_config.helper_private = &rockchip_mode_config_helpers; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 3e2a0ce1a137..3c1c415b039e 100644 +index 30e252ba7184..897f7980ee5d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1871,7 +1871,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1917,7 +1917,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1612,7 +1561,7 @@ index 3e2a0ce1a137..3c1c415b039e 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1881,6 +1881,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1927,6 +1927,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1621,7 +1570,7 @@ index 3e2a0ce1a137..3c1c415b039e 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1912,7 +1914,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1967,7 +1969,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1642,10 +1591,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 3c1c415b039e..1df221b7007d 100644 +index 897f7980ee5d..eadf1b0f1704 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1871,8 +1871,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1917,8 +1917,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1670,7 +1619,7 @@ index 3c1c415b039e..1df221b7007d 100644 { unsigned int flags = 0; -@@ -1883,6 +1898,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1929,6 +1944,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1690,7 +1639,7 @@ index 3c1c415b039e..1df221b7007d 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1914,7 +1942,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1969,7 +1997,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1710,10 +1659,11 @@ MINIARM: set npll be used for hdmi only Signed-off-by: Nickey Yang Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- arch/arm/boot/dts/rk3288.dtsi | 2 ++ - drivers/clk/rockchip/clk-rk3288.c | 4 ++-- - 2 files changed, 4 insertions(+), 2 deletions(-) + drivers/clk/rockchip/clk-rk3288.c | 9 +++++---- + 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index c60eacab8a79..d1ae42757242 100644 @@ -1729,10 +1679,22 @@ index c60eacab8a79..d1ae42757242 100644 vopb_out: port { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index baa5aebd3277..20a3cdbbe909 100644 +index baa5aebd3277..5cfcbaaa154e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -232,7 +232,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; + PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; + + PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; +-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; +-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; ++PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" }; ++PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" }; ++PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" }; + PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; + PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; + +@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1741,12 +1703,12 @@ index baa5aebd3277..20a3cdbbe909 100644 }; static struct clk_div_table div_hclk_cpu_t[] = { -@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { +@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, -+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, ++ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(3), 1, GFLAGS), COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, @@ -1760,43 +1722,60 @@ Subject: [PATCH] HACK: clk: rockchip: rk3288: use npll table to to improve Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3 Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/clk/rockchip/clk-rk3288.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) + drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++- + 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 20a3cdbbe909..47a2527fd238 100644 +index 5cfcbaaa154e..fa1c6e646bdf 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -121,6 +121,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { +@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { { /* sentinel */ }, }; +static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32), ++ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), + RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), + RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), + RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), ++ RK3066_PLL_RATE(348500000, 8, 697, 6), + RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), + RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), + RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), + RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), ++ RK3066_PLL_RATE(241500000, 2, 161, 8), ++ RK3066_PLL_RATE(162000000, 1, 81, 12), ++ RK3066_PLL_RATE(154000000, 6, 539, 14), + RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), + RK3066_PLL_RATE(148352000, 13, 1125, 14), + RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), ++ RK3066_PLL_RATE(121750000, 6, 487, 16), ++ RK3066_PLL_RATE(119000000, 3, 238, 16), + RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), + RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), ++ RK3066_PLL_RATE(101000000, 3, 202, 16), ++ RK3066_PLL_RATE(88750000, 6, 355, 16), + RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), ++ RK3066_PLL_RATE(83500000, 3, 167, 16), ++ RK3066_PLL_RATE(79500000, 1, 53, 16), + RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), + RK3066_PLL_RATE(74176000, 26, 1125, 14), ++ RK3066_PLL_RATE(72000000, 1, 48, 16), ++ RK3066_PLL_RATE(71000000, 3, 142, 16), ++ RK3066_PLL_RATE(68250000, 2, 91, 16), ++ RK3066_PLL_RATE(65000000, 3, 130, 16), ++ RK3066_PLL_RATE(40000000, 3, 80, 16), ++ RK3066_PLL_RATE(33750000, 2, 45, 16), + { /* sentinel */ }, +}; + #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -232,7 +253,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1806,100 +1785,72 @@ index 20a3cdbbe909..47a2527fd238 100644 static struct clk_div_table div_hclk_cpu_t[] = { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 28 Oct 2018 21:43:01 +0100 -Subject: [PATCH] HACK: clk: rockchip: rk3288: add more npll clocks - -Fixes 2560x1440@60Hz, 1600x1200@60Hz, 1920x1200@60Hz, 1680x1050@60Hz and 1440x900@60Hz modes on my monitor - -Signed-off-by: Jonas Karlman ---- - drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 47a2527fd238..233890555616 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -127,18 +127,34 @@ static struct rockchip_pll_rate_table rk3288_npll_rates[] = { - RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), - RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), - RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), -+ RK3066_PLL_RATE(348500000, 8, 697, 6), - RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), - RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), - RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), - RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), -+ RK3066_PLL_RATE(241500000, 2, 161, 8), -+ RK3066_PLL_RATE(162000000, 1, 81, 12), -+ RK3066_PLL_RATE(154000000, 6, 539, 14), - RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), - RK3066_PLL_RATE(148352000, 13, 1125, 14), - RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), -+ RK3066_PLL_RATE(121750000, 6, 487, 16), -+ RK3066_PLL_RATE(119000000, 3, 238, 16), - RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), - RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), -+ RK3066_PLL_RATE(101000000, 3, 202, 16), -+ RK3066_PLL_RATE(88750000, 6, 355, 16), - RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), -+ RK3066_PLL_RATE(83500000, 3, 167, 16), -+ RK3066_PLL_RATE(79500000, 1, 53, 16), - RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), - RK3066_PLL_RATE(74176000, 26, 1125, 14), -+ RK3066_PLL_RATE(72000000, 1, 48, 16), -+ RK3066_PLL_RATE(71000000, 3, 142, 16), -+ RK3066_PLL_RATE(68250000, 2, 91, 16), -+ RK3066_PLL_RATE(65000000, 3, 130, 16), -+ RK3066_PLL_RATE(40000000, 3, 80, 16), -+ RK3066_PLL_RATE(33750000, 2, 45, 16), - { /* sentinel */ }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 25 May 2020 20:36:45 +0000 Subject: [PATCH] HACK: clk: rockchip: rk3399: dedicate vpll for vopb and hdmi use +Rockchip PLLs are kown provide the least jitter for +vco rates between 800 MHz and 2 GHz. I added the +rates for VPLL which are used for VOPs dclk and there- +fore HDMI phy in that manner and used the rates which +require the lowest frac divs. +Additionally I added some rates which are useful to +provide additional VESA and non-VESA rates for HDMI +output. + Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/clk/rockchip/clk-rk3399.c | 32 +++++++++++++++++++++++++------ - 1 file changed, 26 insertions(+), 6 deletions(-) + drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++----- + 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 306910a3a0d3..1db62a3a4c67 100644 +index 306910a3a0d3..436d2789611c 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -105,6 +105,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { +@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { { /* sentinel */ }, }; +static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -+ RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */ -+ RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */ -+ RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */ -+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */ -+ RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */ -+ RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */ -+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */ -+ RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */ -+ RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */ ++ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ ++ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ ++ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ ++ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ ++ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ ++ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ ++ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ ++ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ ++ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ ++ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ ++ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ ++ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ ++ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ ++ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ ++ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ ++ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ ++ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ ++ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ ++ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ ++ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ ++ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ ++ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ ++ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ ++ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ ++ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ ++ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ ++ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ ++ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ + { /* sentinel */ }, +}; + /* CRU parents */ PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -@@ -123,7 +142,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", +@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1908,11 +1859,14 @@ index 306910a3a0d3..1db62a3a4c67 100644 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" }; PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", -@@ -150,9 +169,10 @@ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", +@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", + PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; - PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; +-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; -PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", ++PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" }; ++PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" }; + +PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll", "npll" }; @@ -1921,7 +1875,7 @@ index 306910a3a0d3..1db62a3a4c67 100644 "xin24m" }; PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", -@@ -229,7 +249,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { +@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), @@ -1930,7 +1884,7 @@ index 306910a3a0d3..1db62a3a4c67 100644 }; static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { -@@ -279,7 +299,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = +@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = @@ -1939,12 +1893,12 @@ index 306910a3a0d3..1db62a3a4c67 100644 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1162,7 +1182,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { +@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(28), 0, GFLAGS), - COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, -+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), @@ -1987,10 +1941,10 @@ index d1ae42757242..7b2cde230b87 100644 }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index fbd0346624e6..b0620c45820c 100644 +index 92c2207e686c..980b12cb0a49 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1725,11 +1725,6 @@ vopl_out_edp: endpoint@1 { +@@ -1728,11 +1728,6 @@ vopl_out_edp: endpoint@1 { remote-endpoint = <&edp_in_vopl>; }; @@ -2002,7 +1956,7 @@ index fbd0346624e6..b0620c45820c 100644 vopl_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopl>; -@@ -1923,10 +1918,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1926,10 +1921,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -2025,10 +1979,10 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 2eb0f3cf1516..3b0ce3f22d3e 100644 +index a2d101ebf7a7..7f6ffbc3e7b2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2002,6 +2002,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, +@@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); } @@ -2050,7 +2004,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 static void hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display, const struct drm_display_mode *mode) -@@ -2013,29 +2028,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, +@@ -2014,29 +2029,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, unsigned int vdisplay, hdisplay; vmode->mpixelclock = mode->clock * 1000; @@ -2083,7 +2037,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); /* Set up HDMI_FC_INVIDCONF */ -@@ -2662,8 +2659,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2663,8 +2660,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) * - MEDIA_BUS_FMT_RGB888_1X24, */ @@ -2107,7 +2061,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, -@@ -2675,8 +2685,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2676,8 +2686,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_display_info *info = &conn->display_info; struct drm_display_mode *mode = &crtc_state->mode; u8 max_bpc = conn_state->max_requested_bpc; @@ -2116,7 +2070,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 u32 *output_fmts; unsigned int i = 0; -@@ -2700,29 +2708,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2701,29 +2709,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, * If the current mode enforces 4:2:0, force the output but format * to 4:2:0 and do not add the YUV422/444/RGB formats */ @@ -2158,7 +2112,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 } /* -@@ -2731,40 +2743,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, */ if (max_bpc >= 16 && info->bpc == 16) { @@ -2221,7 +2175,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 *num_output_fmts = i; -@@ -2945,11 +2968,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, +@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; enum drm_mode_status mode_status = MODE_OK; @@ -2254,10 +2208,10 @@ Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index da4a829baded..66e463d58a0b 100644 +index d6d8f3335813..89424c5bc24a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -83,6 +83,8 @@ struct rockchip_hdmi { +@@ -84,6 +84,8 @@ struct rockchip_hdmi { struct phy *phy; }; @@ -2266,7 +2220,7 @@ index da4a829baded..66e463d58a0b 100644 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) { return container_of(bridge, struct rockchip_hdmi, bridge); -@@ -340,6 +342,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, +@@ -341,6 +343,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *adjusted_mode) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); @@ -2278,7 +2232,7 @@ index da4a829baded..66e463d58a0b 100644 clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); } -@@ -380,6 +387,17 @@ static bool is_rgb(u32 format) +@@ -381,6 +388,17 @@ static bool is_rgb(u32 format) { switch (format) { case MEDIA_BUS_FMT_RGB888_1X24: @@ -2296,7 +2250,7 @@ index da4a829baded..66e463d58a0b 100644 return true; default: return false; -@@ -393,9 +411,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -394,9 +412,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); @@ -2321,7 +2275,7 @@ index da4a829baded..66e463d58a0b 100644 return 0; } -@@ -407,10 +440,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -408,10 +441,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, u32 output_fmt, unsigned int *num_input_fmts) { @@ -2365,10 +2319,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3b0ce3f22d3e..cd806742c010 100644 +index 7f6ffbc3e7b2..ae4c49e84470 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1789,6 +1789,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode) { @@ -2376,7 +2330,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 struct hdmi_avi_infoframe frame; u8 val; -@@ -1846,6 +1847,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1847,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; } @@ -2385,7 +2339,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 /* * The Designware IP uses a different byte format from standard * AVI info frames, though generally the bits are in the correct -@@ -2550,7 +2553,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, +@@ -2551,7 +2554,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (!crtc) return 0; @@ -2395,7 +2349,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); -@@ -2618,6 +2622,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2619,6 +2623,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) drm_connector_attach_max_bpc_property(connector, 8, 16); @@ -2414,14 +2368,14 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 +++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 14 ++++++++++ - 4 files changed, 77 insertions(+), 1 deletion(-) + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++ + 4 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 66e463d58a0b..4fad844a18af 100644 +index 89424c5bc24a..05de2052d95d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -67,6 +67,7 @@ struct rockchip_hdmi_chip_data { +@@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data { int lcdsel_grf_reg; u32 lcdsel_big; u32 lcdsel_lit; @@ -2429,7 +2383,7 @@ index 66e463d58a0b..4fad844a18af 100644 }; struct rockchip_hdmi { -@@ -394,10 +395,22 @@ static bool is_rgb(u32 format) +@@ -395,10 +396,22 @@ static bool is_rgb(u32 format) } } @@ -2452,7 +2406,7 @@ index 66e463d58a0b..4fad844a18af 100644 return true; default: return false; -@@ -414,12 +427,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -415,12 +428,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_atomic_state *state = bridge_state->base.state; struct drm_crtc_state *old_crtc_state; struct rockchip_crtc_state *old_state; @@ -2475,7 +2429,7 @@ index 66e463d58a0b..4fad844a18af 100644 s->bus_width = is_10bit(format) ? 10 : 8; old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -@@ -453,7 +476,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -454,7 +477,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (!has_10bit && is_10bit(output_fmt)) return NULL; @@ -2487,7 +2441,7 @@ index 66e463d58a0b..4fad844a18af 100644 return NULL; input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -@@ -603,6 +629,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { +@@ -604,6 +630,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3328_chip_data = { .lcdsel_grf_reg = -1, @@ -2496,10 +2450,10 @@ index 66e463d58a0b..4fad844a18af 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 1df221b7007d..ac3802c3be21 100644 +index eadf1b0f1704..0e4eca0d5121 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -341,6 +341,17 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format) return -EINVAL; } @@ -2517,7 +2471,7 @@ index 1df221b7007d..ac3802c3be21 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1412,6 +1423,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1455,6 +1466,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2525,7 +2479,7 @@ index 1df221b7007d..ac3802c3be21 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1485,6 +1497,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1520,6 +1532,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2534,7 +2488,7 @@ index 1df221b7007d..ac3802c3be21 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1500,6 +1514,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1535,6 +1549,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2557,10 +2511,10 @@ index 1df221b7007d..ac3802c3be21 100644 val = hact_st << 16; val |= hact_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 8db9ea4055f6..e9f256bd8d5a 100644 +index ca4e2b7415fe..47ad74ef1afb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -117,10 +117,16 @@ struct vop_common { +@@ -119,10 +119,16 @@ struct vop_common { struct vop_reg mmu_en; struct vop_reg out_mode; struct vop_reg standby; @@ -2578,7 +2532,7 @@ index 8db9ea4055f6..e9f256bd8d5a 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 6446f2158d30..7c4c3e299760 100644 +index a2b281e290e0..b16a4c42773c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { @@ -2593,7 +2547,19 @@ index 6446f2158d30..7c4c3e299760 100644 }; /* -@@ -1076,6 +1081,10 @@ static const struct vop_output rk3328_output = { +@@ -926,6 +931,11 @@ static const struct vop_common rk3399_common = { + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), ++ ++ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16), ++ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12), ++ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), ++ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), + }; + + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { +@@ -1096,6 +1106,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2604,7 +2570,7 @@ index 6446f2158d30..7c4c3e299760 100644 }; static const struct vop_common rk3328_common = { -@@ -1088,6 +1097,11 @@ static const struct vop_common rk3328_common = { +@@ -1108,6 +1122,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2624,16 +2590,16 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 18 ++++++++++++++++- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++++++---- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ - 4 files changed, 47 insertions(+), 5 deletions(-) + 4 files changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 4fad844a18af..d57e953ce585 100644 +index 05de2052d95d..cb201612199f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -406,9 +406,21 @@ static bool is_yuv444(u32 format) +@@ -407,9 +407,21 @@ static bool is_yuv444(u32 format) } } @@ -2655,7 +2621,7 @@ index 4fad844a18af..d57e953ce585 100644 case MEDIA_BUS_FMT_RGB101010_1X30: case MEDIA_BUS_FMT_YUV10_1X30: return true; -@@ -445,6 +457,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -446,6 +458,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, s->bus_width = is_10bit(format) ? 10 : 8; @@ -2667,7 +2633,7 @@ index 4fad844a18af..d57e953ce585 100644 old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); if (old_crtc_state && !crtc_state->mode_changed) { old_state = to_rockchip_crtc_state(old_crtc_state); -@@ -465,6 +482,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -466,6 +483,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -2675,7 +2641,7 @@ index 4fad844a18af..d57e953ce585 100644 u32 *input_fmt; bool has_10bit = true; -@@ -479,6 +497,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -480,6 +498,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (is_yuv444(output_fmt)) { if (!hdmi->chip_data->ycbcr_444_allowed) return NULL; @@ -2685,7 +2651,7 @@ index 4fad844a18af..d57e953ce585 100644 } else if (!is_rgb(output_fmt)) return NULL; -@@ -639,6 +660,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { +@@ -640,6 +661,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, .use_drm_infoframe = true, @@ -2694,10 +2660,18 @@ index 4fad844a18af..d57e953ce585 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index ac3802c3be21..04a135730b12 100644 +index 0e4eca0d5121..e50f71ad3ceb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -342,6 +342,19 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -348,6 +349,19 @@ static int vop_convert_afbc_format(uint32_t format) } static bool is_yuv_output(uint32_t bus_format) @@ -2717,7 +2691,7 @@ index ac3802c3be21..04a135730b12 100644 { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1497,7 +1510,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1532,7 +1546,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2726,7 +2700,7 @@ index ac3802c3be21..04a135730b12 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1514,6 +1527,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1549,6 +1563,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2737,10 +2711,10 @@ index ac3802c3be21..04a135730b12 100644 VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index e9f256bd8d5a..c5c8d3887081 100644 +index 47ad74ef1afb..94a615dca672 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -119,6 +119,7 @@ struct vop_common { +@@ -121,6 +121,7 @@ struct vop_common { struct vop_reg standby; struct vop_reg overlay_mode; @@ -2748,7 +2722,7 @@ index e9f256bd8d5a..c5c8d3887081 100644 struct vop_reg dsp_data_swap; struct vop_reg dsp_out_yuv; struct vop_reg dsp_background; -@@ -284,11 +285,12 @@ struct vop_data { +@@ -286,11 +287,12 @@ struct vop_data { /* * display output interface supported by rockchip lcdc */ @@ -2766,7 +2740,7 @@ index e9f256bd8d5a..c5c8d3887081 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 7c4c3e299760..1aecdcf63da9 100644 +index b16a4c42773c..5463b04240f7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { @@ -2777,7 +2751,7 @@ index 7c4c3e299760..1aecdcf63da9 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1099,6 +1100,7 @@ static const struct vop_common rk3328_common = { +@@ -1124,6 +1125,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2797,10 +2771,10 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index d57e953ce585..42457f7d9bc9 100644 +index cb201612199f..8627f6826bfe 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -615,6 +615,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { +@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3228_chip_data = { .lcdsel_grf_reg = -1, @@ -2808,7 +2782,7 @@ index d57e953ce585..42457f7d9bc9 100644 }; static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { -@@ -623,6 +624,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { +@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, @@ -2828,21 +2802,20 @@ this will allow modes >= 2160p@50Hz on RK3288/RK3399 (RGB444) Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 42457f7d9bc9..90cc3b33e2a0 100644 +index 8627f6826bfe..e259362f6414 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -325,16 +325,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -326,16 +326,29 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_mode *mode) { struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; + const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; -+ int clock = mode->clock; -+ int i = 0; ++ unsigned int i = 0; if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && - (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) @@ -2865,91 +2838,10 @@ index 42457f7d9bc9..90cc3b33e2a0 100644 + return MODE_CLOCK_HIGH; + } + - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; } static void -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 15 Aug 2020 21:11:08 +0200 -Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit - formats - ---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 1aecdcf63da9..870e388c2345 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -794,8 +794,8 @@ static const struct vop_intr rk3368_vop_intr = { - - static const struct vop_win_phy rk3368_win01_data = { - .scl = &rk3288_win_full_scl, -- .data_formats = formats_win_full_10, -- .nformats = ARRAY_SIZE(formats_win_full_10), -+ .data_formats = formats_win_full, -+ .nformats = ARRAY_SIZE(formats_win_full), - .format_modifiers = format_modifiers_win_full, - .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), - .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 16:42:05 +0100 -Subject: [PATCH] drm/rockchip: split rk3328 vop for 10-bit support - -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 30 ++++++++++++++++++--- - 1 file changed, 27 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 870e388c2345..4ba8f79582db 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1116,12 +1116,36 @@ static const struct vop_intr rk3328_vop_intr = { - .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), - }; - -+static const struct vop_win_phy rk3328_win01_data = { -+ .scl = &rk3288_win_full_scl, -+ .data_formats = formats_win_full_10, -+ .nformats = ARRAY_SIZE(formats_win_full_10), -+ .format_modifiers = format_modifiers_win_full, -+ .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), -+ .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), -+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), -+ .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), -+ .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), -+ .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), -+ .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0), -+ .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0), -+ .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0), -+ .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0), -+ .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0), -+ .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0), -+ .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16), -+ .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0), -+ .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0), -+ .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0), -+}; -+ -+ - static const struct vop_win_data rk3328_vop_win_data[] = { -- { .base = 0xd0, .phy = &rk3368_win01_data, -+ { .base = 0xd0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_PRIMARY }, -- { .base = 0x1d0, .phy = &rk3368_win01_data, -+ { .base = 0x1d0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_OVERLAY }, -- { .base = 0x2d0, .phy = &rk3368_win01_data, -+ { .base = 0x2d0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_CURSOR }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 18 Nov 2017 11:09:39 +0100 @@ -2960,10 +2852,10 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 04a135730b12..96a301501584 100644 +index e50f71ad3ceb..ef0a078c22f4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -958,6 +958,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -965,6 +965,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, int format; int is_yuv = fb->format->is_yuv; int i; @@ -2971,7 +2863,7 @@ index 04a135730b12..96a301501584 100644 /* * can't update plane when vop is disabled. -@@ -976,8 +977,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -983,8 +984,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, obj = fb->obj[0]; rk_obj = to_rockchip_obj(obj); @@ -2987,7 +2879,7 @@ index 04a135730b12..96a301501584 100644 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -1019,7 +1026,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); @@ -2996,7 +2888,7 @@ index 04a135730b12..96a301501584 100644 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); VOP_WIN_SET(vop, win, y_mir_en, -@@ -1043,7 +1050,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1050,7 +1057,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; @@ -3035,36 +2927,6 @@ index d7e44d174d7b..5519347232f6 100644 <100000000>, <100000000>, <50000000>, <50000000>, -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 1 Mar 2021 20:31:15 +0100 -Subject: [PATCH] clk: rockchip: rk3288: use common PLL setting for 594 MHz in - NPLL table - -The settings in the NPLL table (which were obviously copied from RK3368) don't -provide a stable signal for 594 MHz, what leads to random short-term black -screen periods (@2160p@60Hz) on some sensetive HDMI sinks when using this PLL -as the source for VOPs dclk. -Using the PLL settings from the common PLL table for this frequency fixes -this. ---- - drivers/clk/rockchip/clk-rk3288.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 233890555616..676e7c3c6f2b 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { - }; - - static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -- RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32), -+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), - RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), - RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), - RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 10 Apr 2021 16:54:26 +0200 @@ -3091,10 +2953,10 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index cd806742c010..772cc629c35d 100644 +index ae4c49e84470..92e621f2714f 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -81,15 +81,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { +@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { }; static const u16 csc_coeff_rgb_in_eitu601[3][4] = { @@ -3117,79 +2979,6 @@ index cd806742c010..772cc629c35d 100644 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 20 Mar 2021 11:12:07 +0100 -Subject: [PATCH] clk: rockchip: RK3399: adapt VPLL rates - -Rockchip PLLs are kown provide the least jitter for -vco rates between 800 MHz and 2 GHz. I converted the -rates for VPLL which are used for VOPs dclk and there- -fore HDMI phy in that manner and used the rates which -require the lowest frac divs. -Additionally I added some rates which are useful to -provide additional VESA and non-VESA rates for HDMI -output. - -Signed-off-by: Alex Bee ---- - drivers/clk/rockchip/clk-rk3399.c | 42 ++++++++++++++++++++----------- - 1 file changed, 28 insertions(+), 14 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 1db62a3a4c67..b4f559e2b86c 100644 ---- a/drivers/clk/rockchip/clk-rk3399.c -+++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -107,20 +107,34 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { - - static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { - /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -- RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */ -- RK3036_PLL_RATE( 593406592, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */ -- RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */ -- RK3036_PLL_RATE( 296703296, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */ -- RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */ -- RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */ -- RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */ -- RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */ -- RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */ -- RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */ -- RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */ -- RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */ -- RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */ -- RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */ -+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ -+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ -+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ -+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ -+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ -+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ -+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ -+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ -+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ -+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ -+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ -+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ -+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ -+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ -+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ -+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ -+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ -+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ -+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ -+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ -+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ -+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ -+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ - { /* sentinel */ }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 23 Mar 2021 19:45:07 +0100 @@ -3428,42 +3217,6 @@ index 2f01259823ea..1889e78e18ea 100644 }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Algea Cao -Date: Wed, 6 Jun 2018 15:47:12 +0800 -Subject: [PATCH] drm/bridge: synopsys: dw-hdmi: Select formula1 for csc - decimation - -Formula3 and Formula2 for csc decimation will cause hdmi yuv422 -display err. - -Formula3: -The pixel color of left 0-14 columns and right 0-12 columns is -err. - -Formula2: -The pixel color of left 0-2 columns is err. - -Change-Id: I94fdd5fd962a24fde02dde1fe3ac10437ad117ad -Signed-off-by: Algea Cao ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 772cc629c35d..428e057dd415 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1178,7 +1178,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) - if (is_color_space_interpolation(hdmi)) - interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; - else if (is_color_space_decimation(hdmi)) -- decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; -+ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1; - - switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { - case 8: - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 1 Jun 2021 19:24:37 +0200 @@ -3476,28 +3229,14 @@ vop_crtc_mode_valid anyways. Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- - 2 files changed, 3 insertions(+), 3 deletions(-) + 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 90cc3b33e2a0..3c0796c5743d 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -349,7 +349,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - return MODE_CLOCK_HIGH; - } - -- return drm_mode_validate_size(mode, 3840, 2160); -+ return MODE_OK; - } - static void - dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 96a301501584..a89f96ab3974 100644 +index ef0a078c22f4..49619f794061 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -417,8 +417,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, +@@ -424,8 +424,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, if (info->is_yuv) is_yuv = true; @@ -3568,10 +3307,10 @@ Signed-off-by: Jonas Karlman 4 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c -index 8bf91b5a7d0e..ad8a2e5a31ac 100644 +index 41a79293ee02..542ab1425339 100644 --- a/drivers/media/cec/core/cec-adap.c +++ b/drivers/media/cec/core/cec-adap.c -@@ -1671,8 +1671,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) +@@ -1674,8 +1674,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) if (IS_ERR_OR_NULL(adap)) return; @@ -3679,20 +3418,14 @@ depending on sink's implementation. Signed-off-by: Alex Bee --- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 428e057dd415..9f13f2aa87d1 100644 +index 92e621f2714f..7551e3ab77d6 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3172,18 +3172,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) - * ask the source to re-read the EDID. - */ - if (intr_stat & -- (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { -+ (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) - dw_hdmi_setup_rx_sense(hdmi, +@@ -3179,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) phy_stat & HDMI_PHY_HPD, phy_stat & HDMI_PHY_RX_SENSE); @@ -3701,12 +3434,11 @@ index 428e057dd415..9f13f2aa87d1 100644 - cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); - mutex_unlock(&hdmi->cec_notifier_mutex); - } -- } - - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { - enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD - ? connector_status_connected -@@ -3197,6 +3190,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + if (phy_stat & HDMI_PHY_HPD) + status = connector_status_connected; + +@@ -3201,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) drm_helper_hpd_irq_event(hdmi->bridge.dev); drm_bridge_hpd_notify(&hdmi->bridge, status); } @@ -3721,3 +3453,75 @@ index 428e057dd415..9f13f2aa87d1 100644 } hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 9 Oct 2020 15:24:53 +0000 +Subject: [PATCH] drm/rockchip: vop: create planes in window order + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ + 1 file changed, 4 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 49619f794061..9915bf124374 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -2023,19 +2023,10 @@ static int vop_create_crtc(struct vop *vop) + int ret; + int i; + +- /* +- * Create drm_plane for primary and cursor planes first, since we need +- * to pass them to drm_crtc_init_with_planes, which sets the +- * "possible_crtcs" to the newly initialized crtc. +- */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; + const struct vop_win_data *win_data = vop_win->data; + +- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && +- win_data->type != DRM_PLANE_TYPE_CURSOR) +- continue; +- + ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, + 0, &vop_plane_funcs, + win_data->phy->data_formats, +@@ -2068,32 +2059,13 @@ static int vop_create_crtc(struct vop *vop) + drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + } + +- /* +- * Create drm_planes for overlay windows with possible_crtcs restricted +- * to the newly created crtc. +- */ ++ /* Set possible_crtcs to the newly created crtc for overlay windows */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; +- const struct vop_win_data *win_data = vop_win->data; +- unsigned long possible_crtcs = drm_crtc_mask(crtc); +- +- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) +- continue; + +- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, +- possible_crtcs, +- &vop_plane_funcs, +- win_data->phy->data_formats, +- win_data->phy->nformats, +- win_data->phy->format_modifiers, +- win_data->type, NULL); +- if (ret) { +- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", +- ret); +- goto err_cleanup_crtc; +- } +- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); +- vop_plane_add_properties(&vop_win->base, win_data); ++ plane = &vop_win->base; ++ if (plane->type == DRM_PLANE_TYPE_OVERLAY) ++ plane->possible_crtcs = drm_crtc_mask(crtc); + } + + port = of_get_child_by_name(dev->of_node, "port"); diff --git a/patch/kernel/archive/media-5.19/00150-linux-1001-v4l2-rockchip.patch b/patch/kernel/media-current/00220-linux-1001-v4l2-rockchip.patch similarity index 80% rename from patch/kernel/archive/media-5.19/00150-linux-1001-v4l2-rockchip.patch rename to patch/kernel/media-current/00220-linux-1001-v4l2-rockchip.patch index ecc91ff0d..e489f58c8 100644 --- a/patch/kernel/archive/media-5.19/00150-linux-1001-v4l2-rockchip.patch +++ b/patch/kernel/media-current/00220-linux-1001-v4l2-rockchip.patch @@ -1,39 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:18:16 +0000 -Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding - finish - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4f5436c89e08..06c23512e1a7 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1016,7 +1016,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - state = (status & RKVDEC_RDY_STA) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - -- writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -@@ -1037,7 +1038,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -- writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); - } - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 10:16:01 +0000 @@ -46,10 +10,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 06c23512e1a7..630ef09ab70b 100644 +index 4f5436c89e08..eaf2f133a264 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1127,9 +1127,9 @@ static int rkvdec_remove(struct platform_device *pdev) +@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev) { struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); @@ -235,7 +199,7 @@ index 15b9bee92016..3acc914888f6 100644 #define RKVDEC_REG_SYSCTRL 0x008 #define RKVDEC_IN_ENDIAN BIT(0) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 630ef09ab70b..b6d5b26a93c2 100644 +index eaf2f133a264..f55abb7c377f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -10,12 +10,15 @@ @@ -300,7 +264,7 @@ index 630ef09ab70b..b6d5b26a93c2 100644 ret = pm_runtime_resume_and_get(rkvdec->dev); if (ret < 0) { -@@ -1021,6 +1056,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; @@ -312,15 +276,15 @@ index 630ef09ab70b..b6d5b26a93c2 100644 ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); rkvdec_job_finish(ctx, state); } -@@ -1038,6 +1078,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); + rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, - rkvdec->regs + RKVDEC_REG_INTERRUPT); + writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); -@@ -1107,6 +1148,18 @@ static int rkvdec_probe(struct platform_device *pdev) + rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); +@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } @@ -389,7 +353,7 @@ Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index b0620c45820c..e797271ef6b4 100644 +index 980b12cb0a49..6e3149e587c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1062,7 +1062,10 @@ power-domain@RK3399_PD_VCODEC { @@ -428,7 +392,7 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index e797271ef6b4..748eb7368e6a 100644 +index 6e3149e587c5..093ebe070775 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1341,7 +1341,7 @@ vpu_mmu: iommu@ff650800 { @@ -454,7 +418,7 @@ Signed-off-by: Alex Bee 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index fc96501f3bc8..f31550c21172 100644 +index 8de6fd2e8eef..002b1a600f93 100644 --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c @@ -15,7 +15,8 @@ @@ -467,7 +431,7 @@ index fc96501f3bc8..f31550c21172 100644 /* * Supported formats. -@@ -273,13 +274,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) +@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) return 0; } @@ -489,7 +453,7 @@ index fc96501f3bc8..f31550c21172 100644 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; -@@ -507,7 +515,7 @@ const struct hantro_variant rk3288_vpu_variant = { +@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = { .codec_ops = rk3288_vpu_codec_ops, .irqs = rockchip_vpu1_irqs, .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), @@ -499,29 +463,6 @@ index fc96501f3bc8..f31550c21172 100644 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 3 Apr 2022 13:45:57 +0200 -Subject: [PATCH] media: hantro: rockchip: Enable H.264 codec for RK3399 - ---- - drivers/staging/media/hantro/rockchip_vpu_hw.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index f31550c21172..304d7b359295 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -544,7 +544,7 @@ const struct hantro_variant rk3399_vpu_variant = { - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | -- HANTRO_VP8_DECODER, -+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 4 Jul 2021 15:19:44 +0200 @@ -548,7 +489,7 @@ index 3acc914888f6..265f5234f4eb 100644 #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -index 311a12656072..ea270262bbed 100644 +index d8c1c0db15c7..a289bc968e91 100644 --- a/drivers/staging/media/rkvdec/rkvdec-vp9.c +++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c @@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) @@ -574,31 +515,6 @@ index 311a12656072..ea270262bbed 100644 writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 16 Jun 2022 13:15:09 +0200 -Subject: [PATCH] arm64: dts: use correct PLL for vdec core - -vdec core should use codec pll for proper operation, by default -it uses general pll (GPLL) - as all other clocks would ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 748eb7368e6a..658ec3b00445 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1346,6 +1346,8 @@ vdec: video-codec@ff660000 { - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, - <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_VDU>; -+ assigned-clock-parents = <&cru PLL_CPLL>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; - resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 16 Jun 2022 13:18:22 +0200 diff --git a/patch/kernel/archive/media-5.19/00160-linux-1002-for-libreelec.patch b/patch/kernel/media-current/00230-linux-1002-for-libreelec.patch similarity index 86% rename from patch/kernel/archive/media-5.19/00160-linux-1002-for-libreelec.patch rename to patch/kernel/media-current/00230-linux-1002-for-libreelec.patch index 3e70d40a6..40e7e1471 100644 --- a/patch/kernel/archive/media-5.19/00160-linux-1002-for-libreelec.patch +++ b/patch/kernel/media-current/00230-linux-1002-for-libreelec.patch @@ -6,16 +6,48 @@ Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and Note: since the regulator that supplies the GPU usually also supplies other SoC components, we have to make sure voltage is never lower then -1050 mV - also disable 500 MHz for now, since it will crash if rkvdec +1075 mV - also disable 500 MHz for now, since it will crash if rkvdec is running at the same time (voltage to high) Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 ++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) + .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 +++ + .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++ + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++ + 3 files changed, 43 insertions(+) +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index aa22a0c22265..51c7723d6762 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -166,6 +166,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index f69a38f42d2d..c198a8a7f95a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -162,6 +162,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 431c4ec198be..e4977669b16a 100644 +index 431c4ec198be..eec03adf0902 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -300,6 +300,11 @@ power: power-controller { @@ -57,15 +89,15 @@ index 431c4ec198be..e4977669b16a 100644 + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; @@ -137,10 +169,10 @@ Signed-off-by: Alex Bee 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi -index 9c1e38c54eae..ee332fc9cf1f 100644 +index 09618bb7d872..db9106a3dd22 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi -@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq { +@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq { sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -150,10 +182,10 @@ index 9c1e38c54eae..ee332fc9cf1f 100644 simple-audio-card,codec { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 658ec3b00445..925d320dea86 100644 +index 093ebe070775..a10fe60b7680 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1892,7 +1892,7 @@ hdmi_sound: hdmi-sound { +@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <256>; @@ -174,10 +206,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index eb0c2d041f13..9256eadb8a3e 100644 +index ad068865ba20..9deb8d1d291d 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c -@@ -1053,7 +1053,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, +@@ -1038,7 +1038,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, ret = obj->funcs->mmap(obj, vma); if (ret) goto err_drm_gem_object_put; @@ -197,7 +229,7 @@ Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation 1 file changed, 52 insertions(+), 61 deletions(-) diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index b773466619b2..e53950e85631 100644 +index 5679102de91f..f0cd183f7873 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c @@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { @@ -395,7 +427,7 @@ Signed-off-by: Alex Bee 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index aa22a0c22265..a78fbddd21df 100644 +index 51c7723d6762..cf321302daec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { @@ -412,7 +444,7 @@ index aa22a0c22265..a78fbddd21df 100644 leds { compatible = "gpio-leds"; -@@ -308,6 +315,13 @@ &io_domains { +@@ -312,6 +319,13 @@ &io_domains { }; &pinctrl { @@ -553,10 +585,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 925d320dea86..037732441f92 100644 +index a10fe60b7680..dbe6a9cb98a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1478,7 +1478,7 @@ cru: clock-controller@ff760000 { +@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 { <1000000000>, <150000000>, <75000000>, <37500000>, @@ -609,7 +641,7 @@ Signed-off-by: Alex Bee 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index f50b47ac11a8..d9b3c8c29e6f 100644 +index a2f0860b20bb..8961f9c7885d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) @@ -634,3 +666,47 @@ index f50b47ac11a8..d9b3c8c29e6f 100644 .audio_startup = dw_hdmi_i2s_audio_startup, .audio_shutdown = dw_hdmi_i2s_audio_shutdown, .get_eld = dw_hdmi_i2s_get_eld, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 18 Sep 2022 10:35:52 +0200 +Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc + +As it will lead to an unbootable device in case one if those ports +is used to power up the device. +See https://lkml.org/lkml/2022/6/20/413 +--- + arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +index 2f4b1b2e3ac7..7217ead94d39 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -215,7 +215,7 @@ vdd_log: vdd-log { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <450000>; ++ regulator-min-microvolt = <430000>; + regulator-max-microvolt = <1400000>; + pwm-supply = <&vcc3v3_sys>; + }; +@@ -536,7 +536,7 @@ fusb1: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; +- status = "okay"; ++ status = "disabled"; + }; + }; + +@@ -553,7 +553,7 @@ fusb0: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; +- status = "okay"; ++ status = "disabled"; + }; + + mp8859: regulator@66 { diff --git a/patch/kernel/archive/media-5.19/00170-linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/media-current/00240-linux-2000-v4l2-wip-rkvdec-hevc.patch similarity index 92% rename from patch/kernel/archive/media-5.19/00170-linux-2000-v4l2-wip-rkvdec-hevc.patch rename to patch/kernel/media-current/00240-linux-2000-v4l2-wip-rkvdec-hevc.patch index 5d85089dd..34c37c4ff 100644 --- a/patch/kernel/archive/media-5.19/00170-linux-2000-v4l2-wip-rkvdec-hevc.patch +++ b/patch/kernel/media-current/00240-linux-2000-v4l2-wip-rkvdec-hevc.patch @@ -1,102 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:03:46 +0000 -Subject: [PATCH] WIP: media: uapi: hevc: add fields needed for rkvdec - -NOTE: these fields are used by rkvdec hevc backend - -Signed-off-by: Jonas Karlman ---- - include/media/hevc-ctrls.h | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 01ccda48d8c5..a536dab3f8a7 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { - /* The controls are not stable at the moment and will likely be reworked. */ - struct v4l2_ctrl_hevc_sps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u8 video_parameter_set_id; -+ __u8 seq_parameter_set_id; - __u16 pic_width_in_luma_samples; - __u16 pic_height_in_luma_samples; - __u8 bit_depth_luma_minus8; -@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -+ __u8 padding[6]; -+ - __u64 flags; - }; - -@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { - - struct v4l2_ctrl_hevc_pps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 pic_parameter_set_id; - __u8 num_extra_slice_header_bits; - __u8 num_ref_idx_l0_default_active_minus1; - __u8 num_ref_idx_l1_default_active_minus1; -@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { - __s8 pps_tc_offset_div2; - __u8 log2_parallel_merge_level_minus2; - -- __u8 padding[4]; -+ __u8 padding; - __u64 flags; - }; - -@@ -200,7 +205,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding; -+ __u16 short_term_ref_pic_set_size; -+ __u16 long_term_ref_pic_set_size; -+ -+ __u8 padding[4]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:07:15 +0000 -Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices - ---- - include/media/hevc-ctrls.h | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index a536dab3f8a7..c8618dc68fc7 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -- __u8 padding[6]; -+ __u8 num_slices; -+ __u8 padding[5]; - - __u64 flags; - }; -@@ -208,7 +209,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u16 short_term_ref_pic_set_size; - __u16 long_term_ref_pic_set_size; - -- __u8 padding[4]; -+ __u32 num_entry_point_offsets; -+ __u32 entry_point_offset_minus1[256]; -+ __u8 padding[8]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 15:17:45 +0000 @@ -106,13 +7,14 @@ NOTE: cabac table and scailing list code is copied 1:1 from mpp TODO: fix lowdelay flag and rework the scaling list part Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++ + drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 67 + + drivers/staging/media/rkvdec/rkvdec.c | 73 +- drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2592 insertions(+), 1 deletion(-) + 5 files changed, 2647 insertions(+), 2 deletions(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -126,10 +28,10 @@ index cb86b429cfaa..a77122641d14 100644 +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 -index 000000000000..c3cceba837c2 +index 000000000000..7a375a23eaf1 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,2522 @@ +@@ -0,0 +1,2572 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder HEVC backend @@ -248,6 +150,7 @@ index 000000000000..c3cceba837c2 +struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; @@ -2179,7 +2082,7 @@ index 000000000000..c3cceba837c2 + /* write sps */ + WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(1, CHROMA_FORMAT_IDC); ++ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); + WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); + WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); @@ -2225,8 +2128,6 @@ index 000000000000..c3cceba837c2 + SPS_TEMPORAL_MVP_ENABLED_FLAG); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), + STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ //WRITE_PPS(0, PS_FIELD(100, 7)); -+ //WRITE_PPS(0x1fffff, PS_FIELD(107, 21)); + + /* write pps */ + WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); @@ -2284,11 +2185,8 @@ index 000000000000..c3cceba837c2 + WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), + SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ //WRITE_PPS(0, PS_FIELD(209, 3)); + WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); + WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ //WRITE_PPS(0x2, PS_FIELD(222, 2)); -+ //WRITE_PPS(0xffffffff, PS_FIELD(224, 32)); + + if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { + for (i = 0; i <= pps->num_tile_columns_minus1; i++) @@ -2296,27 +2194,28 @@ index 000000000000..c3cceba837c2 + for (i = 0; i <= pps->num_tile_rows_minus1; i++) + WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); + } else { -+ WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1, ++ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, + COLUMN_WIDTH(0)); -+ WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1, ++ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, + ROW_HEIGHT(0)); + } + + scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); + scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; + WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+ //WRITE_PPS(0xffff, PS_FIELD(624, 16)); +} + +static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) +{ ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_rps_packet *hw_ps; + int i, j; ++ unsigned int lowdelay; + +#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) + @@ -2326,47 +2225,49 @@ index 000000000000..c3cceba837c2 +#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) + +#define LOWDELAY PS_FIELD(182, 1) -+#define SHORT_TERM_REF_PIC_SET_SIZE PS_FIELD(183, 10) -+#define LONG_TERM_REF_PIC_SET_SIZE PS_FIELD(193, 9) ++#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) ++#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) +#define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { + sl_params = &run->slices_params[j]; -+ dpb = sl_params->dpb; ++ dpb = decode_params->dpb; ++ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + + for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); ++ ++ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ + } + + for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); ++ ++ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; + } + -+ //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); ++ WRITE_RPS(lowdelay, LOWDELAY); + -+ // TODO: lowdelay -+ WRITE_RPS(0, LOWDELAY); -+ -+ // NOTE: these two differs from mpp ++ WRITE_RPS(sl_params->long_term_ref_pic_set_size + ++ sl_params->short_term_ref_pic_set_size, ++ LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_REF_PIC_SET_SIZE); -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_REF_PIC_SET_SIZE); ++ SHORT_TERM_RPS_BIT_OFFSET); + -+ WRITE_RPS(sl_params->num_rps_poc_st_curr_before + -+ sl_params->num_rps_poc_st_curr_after + -+ sl_params->num_rps_poc_lt_curr, ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, + NUM_RPS_POC); -+ -+ //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); -+ //WRITE_RPS(0xffffffff, PS_FIELD(224, 32)); + } +} + @@ -2412,31 +2313,31 @@ index 000000000000..c3cceba837c2 + unsigned int dpb_idx) +{ + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx = -1; ++ struct vb2_buffer *vb2_buf = NULL; + -+ if (dpb_idx < sl_params->num_active_dpb_entries) -+ buf_idx = vb2_find_timestamp(cap_q, -+ dpb[dpb_idx].timestamp, 0); ++ if (dpb_idx < decode_params->num_active_dpb_entries) ++ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); + + /* + * If a DPB entry is unused or invalid, address of current destination + * buffer is returned. + */ -+ if (buf_idx < 0) ++ if (!vb2_buf) + return &run->base.bufs.dst->vb2_buf; + -+ return vb2_get_buffer(cap_q, buf_idx); ++ return vb2_buf; +} + +static void config_registers(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) +{ + struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; @@ -2498,8 +2399,8 @@ index 000000000000..c3cceba837c2 + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + -+ if (i < 4 && sl_params->num_active_dpb_entries) { -+ reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else + reg = 0; @@ -2508,7 +2409,7 @@ index 000000000000..c3cceba837c2 + writel_relaxed(refer_addr | reg, + rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + -+ reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); + writel_relaxed(reg, + rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } @@ -2547,17 +2448,58 @@ index 000000000000..c3cceba837c2 + return 0; +} + ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; ++ ++ if (sps->bit_depth_luma_minus8 == 2) ++ return V4L2_PIX_FMT_NV15; ++ else ++ return V4L2_PIX_FMT_NV12; ++} ++ +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_priv_tbl *priv_tbl; + struct rkvdec_hevc_ctx *hevc_ctx; ++ struct v4l2_ctrl *ctrl; + int ret; + ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ if (ret) ++ return ret; ++ + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); + if (!hevc_ctx) + return -ENOMEM; + ++ + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), + &hevc_ctx->priv_tbl.dma, GFP_KERNEL); + if (!priv_tbl) { @@ -2593,24 +2535,24 @@ index 000000000000..c3cceba837c2 + struct rkvdec_hevc_run *run) +{ + struct v4l2_ctrl *ctrl; -+ + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); ++ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; ++ run->num_slices = ctrl->new_elems; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ V4L2_CID_STATELESS_HEVC_SPS); + run->sps = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_PPS); ++ V4L2_CID_STATELESS_HEVC_PPS); + run->pps = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); ++ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; + + rkvdec_run_preamble(ctx, &run->base); -+ -+ // HACK: we need num slices from somewhere -+ run->num_slices = run->sps->num_slices; +} + +static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) @@ -2646,11 +2588,21 @@ index 000000000000..c3cceba837c2 + return 0; +} + ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ +const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { + .adjust_fmt = rkvdec_hevc_adjust_fmt, + .start = rkvdec_hevc_start, + .stop = rkvdec_hevc_stop, + .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .valid_fmt = rkvdec_hevc_valid_fmt, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h index 265f5234f4eb..4319ee3ccbbc 100644 @@ -2665,40 +2617,53 @@ index 265f5234f4eb..4319ee3ccbbc 100644 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b6d5b26a93c2..7e8674e7d501 100644 +index f55abb7c377f..00a9bf583596 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -134,6 +134,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { +@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) + { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + +- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { ++ if (!ctx->valid_fmt) { + ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); + if (ctx->valid_fmt) { + struct v4l2_pix_format_mplane *pix_mp; +@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, -+ // HACK: match ffmpeg v4l2 request api hwaccel size, -+ // we should support variable length up to 600 slices -+ .cfg.dims = { 32 }, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, ++ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, ++ .cfg.dims = { 600 }, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, ++ .cfg.ops = &rkvdec_ctrl_ops, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, ++ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, ++ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, @@ -2727,7 +2692,7 @@ index b6d5b26a93c2..7e8674e7d501 100644 static const struct rkvdec_ctrls rkvdec_h264_ctrls = { .ctrls = rkvdec_h264_ctrl_descs, .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -187,6 +239,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .decoded_fmts = rkvdec_h264_decoded_fmts, .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, }, @@ -2762,391 +2727,6 @@ index f02f79c405f0..d6222a2588be 100644 #endif /* RKVDEC_H_ */ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 16:01:43 +0200 -Subject: [PATCH] media: rkvdec: hevc: adapt for 5.14 uAPI - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 29 +++++++++++++--------- - drivers/staging/media/rkvdec/rkvdec.c | 3 +++ - 2 files changed, 20 insertions(+), 12 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index c3cceba837c2..5c341b5fa534 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -116,6 +116,7 @@ struct rkvdec_hevc_priv_tbl { - struct rkvdec_hevc_run { - struct rkvdec_run base; - const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; - const struct v4l2_ctrl_hevc_sps *sps; - const struct v4l2_ctrl_hevc_pps *pps; - const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -@@ -2179,6 +2180,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; - const struct v4l2_ctrl_hevc_slice_params *sl_params; - const struct v4l2_hevc_dpb_entry *dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -@@ -2200,7 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - for (j = 0; j < run->num_slices; j++) { - sl_params = &run->slices_params[j]; -- dpb = sl_params->dpb; -+ dpb = decode_params->dpb; - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2228,9 +2230,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - WRITE_RPS(sl_params->long_term_ref_pic_set_size, - LONG_TERM_REF_PIC_SET_SIZE); - -- WRITE_RPS(sl_params->num_rps_poc_st_curr_before + -- sl_params->num_rps_poc_st_curr_after + -- sl_params->num_rps_poc_lt_curr, -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, - NUM_RPS_POC); - - //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); -@@ -2280,12 +2282,12 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, - unsigned int dpb_idx) - { - struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -- const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; - int buf_idx = -1; - -- if (dpb_idx < sl_params->num_active_dpb_entries) -+ if (dpb_idx < decode_params->num_active_dpb_entries) - buf_idx = vb2_find_timestamp(cap_q, - dpb[dpb_idx].timestamp, 0); - -@@ -2303,8 +2305,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; - const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; - dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; - const struct v4l2_pix_format_mplane *dst_fmt; -@@ -2366,8 +2369,8 @@ static void config_registers(struct rkvdec_ctx *ctx, - for (i = 0; i < 15; i++) { - struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); - -- if (i < 4 && sl_params->num_active_dpb_entries) { -- reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); - reg = (reg >> (i * 4)) & 0xf; - } else - reg = 0; -@@ -2376,7 +2379,7 @@ static void config_registers(struct rkvdec_ctx *ctx, - writel_relaxed(refer_addr | reg, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); - -- reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); - writel_relaxed(reg, - rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); - } -@@ -2461,7 +2464,9 @@ static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - struct v4l2_ctrl *ctrl; -- -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; - ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, - V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); - run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7e8674e7d501..0f877acfba27 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -150,6 +150,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, - }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, -+ }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, - .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 1 Aug 2020 12:24:58 +0000 -Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation - ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 55 +++++++++++++++++++++- - drivers/staging/media/rkvdec/rkvdec.c | 3 +- - 2 files changed, 55 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 5c341b5fa534..ac06039140bc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2208,13 +2208,13 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - memset(hw_ps, 0, sizeof(*hw_ps)); - - for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -- WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); - } - - for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -- WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); - } -@@ -2418,17 +2418,58 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, - return 0; - } - -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ - static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_hevc_priv_tbl *priv_tbl; - struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; - int ret; - -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ - hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); - if (!hevc_ctx) - return -ENOMEM; - -+ - priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), - &hevc_ctx->priv_tbl.dma, GFP_KERNEL); - if (!priv_tbl) { -@@ -2519,9 +2560,19 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - return 0; - } - -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ - const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { - .adjust_fmt = rkvdec_hevc_adjust_fmt, - .start = rkvdec_hevc_start, - .stop = rkvdec_hevc_stop, - .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, - }; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 0f877acfba27..9f6a619499ab 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - -- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ if (!ctx->valid_fmt) { - ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); - if (ctx->valid_fmt) { - struct v4l2_pix_format_mplane *pix_mp; -@@ -143,6 +143,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { - }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, - }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Apr 2021 18:01:21 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: Fix column width / row height - calculation for no-tiled case - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index ac06039140bc..99bfb937facc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - for (i = 0; i <= pps->num_tile_rows_minus1; i++) - WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); - } else { -- WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1, -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, - COLUMN_WIDTH(0)); -- WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1, -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, - ROW_HEIGHT(0)); - } - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Apr 2021 17:26:43 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: fix long ref decoding - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 99bfb937facc..b5bb4c083dbc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - #define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) - - #define LOWDELAY PS_FIELD(182, 1) --#define SHORT_TERM_REF_PIC_SET_SIZE PS_FIELD(183, 10) --#define LONG_TERM_REF_PIC_SET_SIZE PS_FIELD(193, 9) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) - #define NUM_RPS_POC PS_FIELD(202, 4) - - for (j = 0; j < run->num_slices; j++) { -@@ -2224,11 +2224,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - // TODO: lowdelay - WRITE_RPS(0, LOWDELAY); - -- // NOTE: these two differs from mpp -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size + -+ sl_params->short_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->short_term_ref_pic_set_size, -- SHORT_TERM_REF_PIC_SET_SIZE); -- WRITE_RPS(sl_params->long_term_ref_pic_set_size, -- LONG_TERM_REF_PIC_SET_SIZE); -+ SHORT_TERM_RPS_BIT_OFFSET); - - WRITE_RPS(decode_params->num_poc_st_curr_before + - decode_params->num_poc_st_curr_after + - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 15 Apr 2021 20:22:54 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index b5bb4c083dbc..8467084165df 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; - struct rkvdec_rps_packet *hw_ps; - int i, j; -+ unsigned int lowdelay; - - #define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) - -@@ -2203,6 +2204,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - for (j = 0; j < run->num_slices; j++) { - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -+ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2211,18 +2213,24 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ - } - - for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; - } - - //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); - -- // TODO: lowdelay -- WRITE_RPS(0, LOWDELAY); -+ WRITE_RPS(lowdelay, LOWDELAY); - - WRITE_RPS(sl_params->long_term_ref_pic_set_size + - sl_params->short_term_ref_pic_set_size, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 30 Jan 2021 18:16:39 +0100 @@ -3169,7 +2749,7 @@ Signed-off-by: Alex Bee 2 files changed, 85 insertions(+), 30 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 9f6a619499ab..2d1a388e20fe 100644 +index 00a9bf583596..955c53afe20f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -14,6 +14,7 @@ @@ -3344,7 +2924,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 } ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1157,8 +1185,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) } } @@ -3363,7 +2943,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1170,6 +1207,7 @@ static const char * const rkvdec_clk_names[] = { +@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = { static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; @@ -3371,7 +2951,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 unsigned int i; int ret, irq; -@@ -1195,6 +1233,13 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) return ret; @@ -3442,10 +3022,10 @@ Signed-off-by: Alex Bee 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 2d1a388e20fe..c2de6fcb6419 100644 +index 955c53afe20f..4e228cd82f21 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1191,11 +1191,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { +@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { RKVDEC_CAPABILITY_VP9 }; @@ -3517,25 +3097,130 @@ index 7b2cde230b87..59fba3ac6aae 100644 gpu: gpu@ffa30000 { From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 3 Apr 2022 14:39:14 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: Use chroma_format_idc from - v4l2_ctrl_hevc_sps +From: Nicolas Dufresne +Date: Tue, 10 May 2022 14:37:29 -0400 +Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets +The offsets from the uAPI need to be extended to include some bits +that can be calculated from the parameters. This has been compared +to match with the vendor bit sizes (which simply parse again the +data to calcualte it). + +Fixed by this change: +- LTRPSPS_A_Qualcomm_1 +- RPS_C_ericsson_5 +- RPS_D_ericsson_6 +- RPS_E_qualcomm_5 + +Signed-off-by: Nicolas Dufresne --- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 8467084165df..a7dc8262f6d7 100644 +index 7a375a23eaf1..580073d49b6a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2048,7 +2048,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - /* write sps */ - WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); - WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(1, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); - WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); - WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); +@@ -10,6 +10,7 @@ + */ + + #include ++#include + + #include "rkvdec.h" + #include "rkvdec-regs.h" +@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; +@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + #define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { ++ uint st_bit_offset = 0; ++ + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; ++ ++ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { ++ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; ++ ++ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) ++ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; ++ ++ lowdelay = 1; ++ } else { ++ lowdelay = 0; ++ } + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); +@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + WRITE_RPS(lowdelay, LOWDELAY); + +- WRITE_RPS(sl_params->long_term_ref_pic_set_size + +- sl_params->short_term_ref_pic_set_size, ++ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { ++ if (sl_params->short_term_ref_pic_set_size) ++ st_bit_offset = sl_params->short_term_ref_pic_set_size; ++ else if (sps->num_short_term_ref_pic_sets > 1) ++ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); ++ } ++ ++ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, + LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, + SHORT_TERM_RPS_BIT_OFFSET); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Dufresne +Date: Tue, 10 May 2022 15:12:03 -0400 +Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS + +The numbers from the bitstream are values between 1 - 16 (as they are +the number - 1). The difference between 0 and 1 needs to be determined +base on the slice type. I frames have no reference, P frames only have +L0 reference, and B frames have both. + +Signed-off-by: Nicolas Dufresne +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index 580073d49b6a..ce15028918b2 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + for (j = 0; j < run->num_slices; j++) { + uint st_bit_offset = 0; ++ uint num_l0_refs = 0; ++ uint num_l1_refs = 0; + + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + +- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { ++ for (i = 0; i < num_l0_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); +@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + } + +- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { ++ for (i = 0; i < num_l1_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); diff --git a/patch/kernel/archive/media-5.19/00180-linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/media-current/00250-linux-2001-v4l2-wip-iep-driver.patch similarity index 99% rename from patch/kernel/archive/media-5.19/00180-linux-2001-v4l2-wip-iep-driver.patch rename to patch/kernel/media-current/00250-linux-2001-v4l2-wip-iep-driver.patch index 6ed5f6332..058b6fc22 100644 --- a/patch/kernel/archive/media-5.19/00180-linux-2001-v4l2-wip-iep-driver.patch +++ b/patch/kernel/media-current/00250-linux-2001-v4l2-wip-iep-driver.patch @@ -1687,7 +1687,7 @@ Signed-off-by: Alex Bee 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index e4977669b16a..6c0cbc9cea61 100644 +index eec03adf0902..5455a46c9a6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 { @@ -1731,10 +1731,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 037732441f92..d90c90406a49 100644 +index dbe6a9cb98a5..f0629b7a81c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1367,14 +1367,25 @@ vdec_mmu: iommu@ff660480 { +@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 { #iommu-cells = <0>; }; diff --git a/patch/kernel/archive/media-5.19/00190-linux-90100-add-clock.patch b/patch/kernel/media-current/00260-linux-90100-add-clock.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00190-linux-90100-add-clock.patch rename to patch/kernel/media-current/00260-linux-90100-add-clock.patch diff --git a/patch/kernel/archive/media-5.19/00200-linux-90101-add-rt5651-konf.patch b/patch/kernel/media-current/00270-linux-90101-add-rt5651-konf.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00200-linux-90101-add-rt5651-konf.patch rename to patch/kernel/media-current/00270-linux-90101-add-rt5651-konf.patch diff --git a/patch/kernel/archive/media-5.19/00210-linux-90102-rt5651.patch b/patch/kernel/media-current/00280-linux-90102-rt5651.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00210-linux-90102-rt5651.patch rename to patch/kernel/media-current/00280-linux-90102-rt5651.patch diff --git a/patch/kernel/archive/media-5.19/00220-linux-90103-nanopc-t4-5651.patch b/patch/kernel/media-current/00290-linux-90103-nanopc-t4-5651.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00220-linux-90103-nanopc-t4-5651.patch rename to patch/kernel/media-current/00290-linux-90103-nanopc-t4-5651.patch diff --git a/patch/kernel/archive/media-5.19/00240-linux-90104-all-codec.patch b/patch/kernel/media-current/00300-linux-90104-all-codec.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00240-linux-90104-all-codec.patch rename to patch/kernel/media-current/00300-linux-90104-all-codec.patch diff --git a/patch/kernel/archive/media-5.19/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch b/patch/kernel/media-current/00310-linux-90117-add-rk3399-roc-pc-plus-sound.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch rename to patch/kernel/media-current/00310-linux-90117-add-rk3399-roc-pc-plus-sound.patch diff --git a/patch/kernel/archive/media-5.19/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch b/patch/kernel/media-current/00320-linux-90200-rk3328-roc-pc-wifi-fix.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch rename to patch/kernel/media-current/00320-linux-90200-rk3328-roc-pc-wifi-fix.patch diff --git a/patch/kernel/archive/media-5.19/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/patch/kernel/media-current/00330-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch rename to patch/kernel/media-current/00330-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch diff --git a/patch/kernel/archive/media-5.19/00280-add-fusb30x-driver.patch b/patch/kernel/media-current/00340-add-fusb30x-driver.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00280-add-fusb30x-driver.patch rename to patch/kernel/media-current/00340-add-fusb30x-driver.patch diff --git a/patch/kernel/archive/media-5.19/00290-add-rk3328-usb3-phy-driver.patch b/patch/kernel/media-current/00350-add-rk3328-usb3-phy-driver.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00290-add-rk3328-usb3-phy-driver.patch rename to patch/kernel/media-current/00350-add-rk3328-usb3-phy-driver.patch diff --git a/patch/kernel/archive/media-5.19/00300-board-roc-rk3399-pc-fix-fusb302-compatible.patch b/patch/kernel/media-current/00360-board-roc-rk3399-pc-fix-fusb302-compatible.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00300-board-roc-rk3399-pc-fix-fusb302-compatible.patch rename to patch/kernel/media-current/00360-board-roc-rk3399-pc-fix-fusb302-compatible.patch diff --git a/patch/kernel/archive/media-5.19/00310-general-add-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/media-current/00370-general-add-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00310-general-add-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/media-current/00370-general-add-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-5.19/00320-general-add-miniDP-dt-doc.patch b/patch/kernel/media-current/00380-general-add-miniDP-dt-doc.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00320-general-add-miniDP-dt-doc.patch rename to patch/kernel/media-current/00380-general-add-miniDP-dt-doc.patch diff --git a/patch/kernel/archive/media-5.19/00340-general-add-miniDP-virtual-extcon.patch b/patch/kernel/media-current/00390-general-add-miniDP-virtual-extcon.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00340-general-add-miniDP-virtual-extcon.patch rename to patch/kernel/media-current/00390-general-add-miniDP-virtual-extcon.patch diff --git a/patch/kernel/archive/media-5.19/00350-general-add-overlay-compilation-support.patch b/patch/kernel/media-current/00400-general-add-overlay-compilation-support.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00350-general-add-overlay-compilation-support.patch rename to patch/kernel/media-current/00400-general-add-overlay-compilation-support.patch diff --git a/patch/kernel/archive/media-5.19/00360-general-add-overlay-configfs.patch b/patch/kernel/media-current/00410-general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00360-general-add-overlay-configfs.patch rename to patch/kernel/media-current/00410-general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/media-5.19/00370-general-bluetooth-02-add-support-for-RTL8723CS.patch b/patch/kernel/media-current/00420-general-bluetooth-02-add-support-for-RTL8723CS.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00370-general-bluetooth-02-add-support-for-RTL8723CS.patch rename to patch/kernel/media-current/00420-general-bluetooth-02-add-support-for-RTL8723CS.patch diff --git a/patch/kernel/archive/media-5.19/00380-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch b/patch/kernel/media-current/00430-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00380-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch rename to patch/kernel/media-current/00430-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch diff --git a/patch/kernel/archive/media-5.19/00390-general-bluetooth-04-add-rtl8703bs.patch b/patch/kernel/media-current/00440-general-bluetooth-04-add-rtl8703bs.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00390-general-bluetooth-04-add-rtl8703bs.patch rename to patch/kernel/media-current/00440-general-bluetooth-04-add-rtl8703bs.patch diff --git a/patch/kernel/archive/media-5.19/00400-general-bluetooth-add-new-quirk.patch b/patch/kernel/media-current/00450-general-bluetooth-add-new-quirk.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00400-general-bluetooth-add-new-quirk.patch rename to patch/kernel/media-current/00450-general-bluetooth-add-new-quirk.patch diff --git a/patch/kernel/archive/media-5.19/00420-general-fix-es8316-kernel-panic.patch b/patch/kernel/media-current/00460-general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00420-general-fix-es8316-kernel-panic.patch rename to patch/kernel/media-current/00460-general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/archive/media-5.19/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/media-current/00470-general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/media-current/00470-general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/archive/media-5.19/00450-general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/media-current/00480-general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00450-general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/media-current/00480-general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/media-5.19/00460-general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/media-current/00490-general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00460-general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/media-current/00490-general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/media-5.19/00470-general-workaround-broadcom-bt-serdev.patch b/patch/kernel/media-current/00500-general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00470-general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/media-current/00500-general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/media-5.19/00480-rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/media-current/00510-rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00480-rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/media-current/00510-rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/media-5.19/00490-rk3328-roc-pc-bt.patch b/patch/kernel/media-current/00520-rk3328-roc-pc-bt.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00490-rk3328-roc-pc-bt.patch rename to patch/kernel/media-current/00520-rk3328-roc-pc-bt.patch diff --git a/patch/kernel/archive/media-5.19/00500-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/media-current/00530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00500-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/media-current/00530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-5.19/00510-rk3399-nanopc-t4-emmc.patch b/patch/kernel/media-current/00540-rk3399-nanopc-t4-emmc.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00510-rk3399-nanopc-t4-emmc.patch rename to patch/kernel/media-current/00540-rk3399-nanopc-t4-emmc.patch diff --git a/patch/kernel/archive/media-5.19/00520-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch b/patch/kernel/media-current/00550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00520-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch rename to patch/kernel/media-current/00550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch diff --git a/patch/kernel/archive/media-5.19/00530-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/media-current/00560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00530-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/media-current/00560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch diff --git a/patch/kernel/archive/media-5.19/00540-rk3399-sd-drive-level-8ma.patch b/patch/kernel/media-current/00570-rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00540-rk3399-sd-drive-level-8ma.patch rename to patch/kernel/media-current/00570-rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/media-5.19/00550-rk3399-unlock-temperature.patch b/patch/kernel/media-current/00580-rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00550-rk3399-unlock-temperature.patch rename to patch/kernel/media-current/00580-rk3399-unlock-temperature.patch diff --git a/patch/kernel/media-current/00590-add-driver-for-Motorcomm-YT85xx+PHYs.patch b/patch/kernel/media-current/00590-add-driver-for-Motorcomm-YT85xx+PHYs.patch new file mode 100644 index 000000000..46c1e2cd2 --- /dev/null +++ b/patch/kernel/media-current/00590-add-driver-for-Motorcomm-YT85xx+PHYs.patch @@ -0,0 +1,656 @@ +From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001 +From: baiywt +Date: Fri, 18 Feb 2022 16:38:43 +0800 +Subject: [PATCH] Add yt8531c support. +Adapted from orangepi-xunlong/openwrt - 600-Add-yt8531c-support.patch by schwar3kat +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/motorcomm.c | 1540 +++++++++++++++++++++++++++++++++ + drivers/net/phy/yt8614-phy.h | 491 +++++++++++ + include/linux/motorcomm_phy.h | 119 +++ + 5 files changed, 2156 insertions(+) + create mode 100644 drivers/net/phy/motorcomm.c + create mode 100644 drivers/net/phy/yt8614-phy.h + create mode 100644 include/linux/motorcomm_phy.h + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index ce030fcb1..ff4861847 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -297,6 +297,11 @@ config MICROSEMI_PHY + help + Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs + ++config MOTORCOMM_PHY ++ tristate "Motorcomm PHYs" ++ help ++ Supports the YT8010, YT8510, YT8511, YT8512 YT8521 YT8531 PHYs. ++ + config NATIONAL_PHY + tristate "National Semiconductor PHYs" + help +diff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h +new file mode 100644 +index 000000000..56a398338 +--- /dev/null ++++ b/drivers/net/phy/yt8614-phy.h +@@ -0,0 +1,491 @@ ++#ifndef _PHY_H_ ++#define _PHY_H_ ++ ++ ++/* configuration for driver */ ++ ++#define YT8614_MAX_LPORT_ID 3 ++ ++#define YT8614_PHY_MODE_FIBER 1 //fiber mode only ++#define YT8614_PHY_MODE_UTP 2 //utp mode only ++#define YT8614_PHY_MODE_POLL 3 //fiber and utp, poll mode ++ ++/* please make choice according to system design ++ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1 ++ * for UTP only system, please define YT8614_PHY_MODE_CURR 2 ++ * for combo system, please define YT8614_PHY_MODE_CURR 3 ++ */ ++#define YT8614_PHY_MODE_CURR 3 ++ ++ ++ ++/* pls dont modify below lines */ ++ ++#define PHY_ID_YT8614 0x4F51E899 //serdes ++#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff ++ ++#ifndef BOOL ++#define BOOL unsigned int ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef SPEED_1000M ++#define SPEED_1000M 2 ++#endif ++#ifndef SPEED_100M ++#define SPEED_100M 1 ++#endif ++#ifndef SPEED_10M ++#define SPEED_10M 0 ++#endif ++ ++#ifndef SPEED_UNKNOWN ++#define SPEED_UNKNOWN 0xffff ++#endif ++ ++#ifndef DUPLEX_FULL ++#define DUPLEX_FULL 1 ++#endif ++#ifndef DUPLEX_HALF ++#define DUPLEX_HALF 0 ++#endif ++ ++#ifndef BIT ++#define BIT(n) (0x1<<(n)) ++#endif ++#ifndef s32 ++typedef int s32; ++typedef unsigned int u32; ++typedef unsigned short u16; ++typedef unsigned char u8; ++#endif ++ ++#ifndef REG_PHY_SPEC_STATUS ++#define REG_PHY_SPEC_STATUS 0x11 ++#define REG_DEBUG_ADDR_OFFSET 0x1e ++#define REG_DEBUG_DATA 0x1f ++#endif ++ ++/**********YT8614************************************************/ ++ ++#define YT8614_SMI_SEL_PHY 0x0 ++#define YT8614_SMI_SEL_SDS_QSGMII 0x02 ++#define YT8614_SMI_SEL_SDS_SGMII 0x03 ++ ++/* yt8614 register type */ ++#define YT8614_TYPE_COMMON 0x01 ++#define YT8614_TYPE_UTP_MII 0x02 ++#define YT8614_TYPE_UTP_EXT 0x03 ++#define YT8614_TYPE_LDS_MII 0x04 ++#define YT8614_TYPE_UTP_MMD 0x05 ++#define YT8614_TYPE_SDS_QSGMII_MII 0x06 ++#define YT8614_TYPE_SDS_SGMII_MII 0x07 ++#define YT8614_TYPE_SDS_QSGMII_EXT 0x08 ++#define YT8614_TYPE_SDS_SGMII_EXT 0x09 ++ ++/* YT8614 extended common register */ ++#define YT8614_REG_COM_SMI_MUX 0xA000 ++#define YT8614_REG_COM_SLED_CFG0 0xA001 ++#define YT8614_REG_COM_PHY_ID 0xA002 ++#define YT8614_REG_COM_CHIP_VER 0xA003 ++#define YT8614_REG_COM_SLED_CFG 0xA004 ++#define YT8614_REG_COM_MODE_CHG_RESET 0xA005 ++#define YT8614_REG_COM_SYNCE0_CFG 0xA006 ++#define YT8614_REG_COM_CHIP_MODE 0xA007 ++ ++#define YT8614_REG_COM_HIDE_SPEED 0xA009 ++ ++#define YT8614_REG_COM_SYNCE1_CFG 0xA00E ++ ++#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019 ++ ++ ++#define YT8614_REG_COM_HIDE_SEL1 0xA054 ++#define YT8614_REG_COM_HIDE_LED_CFG2 0xB8 ++#define YT8614_REG_COM_HIDE_LED_CFG3 0xB9 ++#define YT8614_REG_COM_HIDE_LED_CFG5 0xBB ++ ++#define YT8614_REG_COM_HIDE_LED_CFG4 0xBA //not used currently ++ ++#if 0 ++#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently ++#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061 ++#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062 ++#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063 ++#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064 ++#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065 ++#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066 ++#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067 ++#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068 ++#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069 ++#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A ++#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B ++#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C ++#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D ++#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E ++#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F ++#endif ++ ++#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070 ++#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071 ++#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072 ++#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073 ++#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074 ++#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075 ++#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076 ++#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077 ++ ++#define YT8614_REG_COM_PKG_CFG0 0xA0A0 ++#define YT8614_REG_COM_PKG_CFG1 0xA0A1 ++#define YT8614_REG_COM_PKG_CFG2 0xA0A2 ++#define YT8614_REG_COM_PKG_RX_VALID0 0xA0A3 ++#define YT8614_REG_COM_PKG_RX_VALID1 0xA0A4 ++#define YT8614_REG_COM_PKG_RX_OS0 0xA0A5 ++#define YT8614_REG_COM_PKG_RX_OS1 0xA0A6 ++#define YT8614_REG_COM_PKG_RX_US0 0xA0A7 ++#define YT8614_REG_COM_PKG_RX_US1 0xA0A8 ++#define YT8614_REG_COM_PKG_RX_ERR 0xA0A9 ++#define YT8614_REG_COM_PKG_RX_OS_BAD 0xA0AA ++#define YT8614_REG_COM_PKG_RX_FRAG 0xA0AB ++#define YT8614_REG_COM_PKG_RX_NOSFD 0xA0AC ++#define YT8614_REG_COM_PKG_TX_VALID0 0xA0AD ++#define YT8614_REG_COM_PKG_TX_VALID1 0xA0AE ++#define YT8614_REG_COM_PKG_TX_OS0 0xA0AF ++ ++#define YT8614_REG_COM_PKG_TX_OS1 0xA0B0 ++#define YT8614_REG_COM_PKG_TX_US0 0xA0B1 ++#define YT8614_REG_COM_PKG_TX_US1 0xA0B2 ++#define YT8614_REG_COM_PKG_TX_ERR 0xA0B3 ++#define YT8614_REG_COM_PKG_TX_OS_BAD 0xA0B4 ++#define YT8614_REG_COM_PKG_TX_FRAG 0xA0B5 ++#define YT8614_REG_COM_PKG_TX_NOSFD 0xA0B6 ++#define YT8614_REG_COM_PKG_CFG3 0xA0B7 ++#define YT8614_REG_COM_PKG_AZ_CFG 0xA0B8 ++#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9 ++ ++#define YT8614_REG_COM_MANU_HW_RESET 0xA0C0 ++ ++/* YT8614 UTP MII register: same as generic phy register definitions */ ++#define REG_MII_BMCR 0x00 /* Basic mode control register */ ++#define REG_MII_BMSR 0x01 /* Basic mode status register */ ++#define REG_MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define REG_MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define REG_MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define REG_MII_LPA 0x05 /* Link partner ability reg */ ++#define REG_MII_EXPANSION 0x06 /* Expansion register */ ++#define REG_MII_NEXT_PAGE 0x07 /* Next page register */ ++#define REG_MII_LPR_NEXT_PAGE 0x08 /* LPR next page register */ ++#define REG_MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define REG_MII_STAT1000 0x0A /* 1000BASE-T status */ ++ ++#define REG_MII_MMD_CTRL 0x0D /* MMD access control register */ ++#define REG_MII_MMD_DATA 0x0E /* MMD access data register */ ++ ++#define REG_MII_ESTATUS 0x0F /* Extended Status */ ++#define REG_MII_SPEC_CTRL 0x10 /* PHY specific func control */ ++#define REG_MII_SPEC_STATUS 0x11 /* PHY specific status */ ++#define REG_MII_INT_MASK 0x12 /* Interrupt mask register */ ++#define REG_MII_INT_STATUS 0x13 /* Interrupt status register */ ++#define REG_MII_DOWNG_CTRL 0x14 /* Speed auto downgrade control*/ ++#define REG_MII_RERRCOUNTER 0x15 /* Receive error counter */ ++ ++#define REG_MII_EXT_ADDR 0x1E /* Extended reg's address */ ++#define REG_MII_EXT_DATA 0x1F /* Extended reg's date */ ++ ++#ifndef MII_BMSR ++#define MII_BMSR REG_MII_BMSR ++#endif ++ ++#ifndef YT8614_SPEED_MODE_BIT ++#define YT8614_SPEED_MODE 0xc000 ++#define YT8614_DUPLEX 0x2000 ++#define YT8614_SPEED_MODE_BIT 14 ++#define YT8614_DUPLEX_BIT 13 ++#define YT8614_LINK_STATUS_BIT 10 ++ ++#endif ++ ++#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI 0x2000 ++ ++/* YT8614 UTP MMD register */ ++#define YT8614_REG_UTP_MMD_CTRL1 0x00 /* PCS control 1 register */ ++#define YT8614_REG_UTP_MMD_STATUS1 0x01 /* PCS status 1 register */ ++#define YT8614_REG_UTP_MMD_EEE_CTRL 0x14 /* EEE control and capability */ ++#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT 0x16 /* EEE wake error counter */ ++#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI 0x3C /* local device EEE ability */ ++#define YT8614_REG_UTP_MMD_EEE_LP_ABI 0x3D /* link partner EEE ability */ ++#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000 /* autoneg result of EEE */ ++ ++/* YT8614 UTP EXT register */ ++#define YT8614_REG_UTP_EXT_LPBK 0x0A ++#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27 ++#define YT8614_REG_UTP_EXT_DEBUG_MON1 0x5A ++#define YT8614_REG_UTP_EXT_DEBUG_MON2 0x5B ++#define YT8614_REG_UTP_EXT_DEBUG_MON3 0x5C ++#define YT8614_REG_UTP_EXT_DEBUG_MON4 0x5D ++ ++/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */ ++#define REG_SDS_BMCR 0x00 /* Basic mode control register */ ++#define REG_SDS_BMSR 0x01 /* Basic mode status register */ ++#define REG_SDS_PHYSID1 0x02 /* PHYS ID 1 */ ++#define REG_SDS_PHYSID2 0x03 /* PHYS ID 2 */ ++#define REG_SDS_ADVERTISE 0x04 /* Advertisement control reg */ ++#define REG_SDS_LPA 0x05 /* Link partner ability reg */ ++#define REG_SDS_EXPANSION 0x06 /* Expansion register */ ++#define REG_SDS_NEXT_PAGE 0x07 /* Next page register */ ++#define REG_SDS_LPR_NEXT_PAGE 0x08 /* LPR next page register */ ++ ++#define REG_SDS_ESTATUS 0x0F /* Extended Status */ ++#define REG_SDS_SPEC_STATUS 0x11 /* SDS specific status */ ++ ++#define REG_SDS_100FX_CFG 0x14 /* 100fx cfg */ ++#define REG_SDS_RERRCOUNTER 0x15 /* Receive error counter */ ++#define REG_SDS_LINT_FAIL_CNT 0x16 /* Lint fail counter mon */ ++ ++/* YT8614 SDS(5G) EXT register */ ++#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02 /* sds analog digital interface cfg */ ++#define YT8614_REG_QSGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06 /* sds prbs cfg2 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07 /* sds prbs cfg2 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ ++#define YT8614_REG_QSGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ ++#define YT8614_REG_QSGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ ++ ++/* YT8614 SDS(1.25G) EXT register */ ++#define YT8614_REG_SGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */ ++#define YT8614_REG_SGMII_EXT_PRBS_CFG2 0x06 /* sds prbs cfg2 */ ++#define YT8614_REG_SGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */ ++#define YT8614_REG_SGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */ ++#define YT8614_REG_SGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */ ++#define YT8614_REG_SGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */ ++#define YT8614_REG_SGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */ ++#define YT8614_REG_SGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */ ++#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5 /* Fiber auto sensing */ ++ ++//////////////////////////////////////////////////////////////////// ++#define YT8614_MMD_DEV_ADDR1 0x1 ++#define YT8614_MMD_DEV_ADDR3 0x3 ++#define YT8614_MMD_DEV_ADDR7 0x7 ++#define YT8614_MMD_DEV_ADDR_NONE 0xFF ++ ++/**********YT8521S************************************************/ ++/* Basic mode control register(0x00) */ ++#define BMCR_RESV 0x003f /* Unused... */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++#define BMCR_CTST 0x0080 /* Collision test */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ ++#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ ++#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ ++#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ ++#define BMCR_RESET 0x8000 /* Reset the DP83840 */ ++ ++/* Basic mode status register(0x01) */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_JCD 0x0002 /* Jabber detected */ ++#define BMSR_LSTATUS 0x0004 /* Link status */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_RFAULT 0x0010 /* Remote fault detected */ ++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ ++#define BMSR_RESV 0x00c0 /* Unused... */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ ++#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ ++ ++/* Advertisement control register(0x04) */ ++#define ADVERTISE_SLCT 0x001f /* Selector bits */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ ++#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ ++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ ++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ ++#define ADVERTISE_RESV 0x1000 /* Unused... */ ++#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ ++#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ ++#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ ++ ++#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++ ++/* Link partner ability register(0x05) */ ++#define LPA_SLCT 0x001f /* Same as advertise selector */ ++#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ ++#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ ++#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ ++#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ ++#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ ++#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ ++#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ ++#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */ ++#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ ++#define LPA_PAUSE_CAP 0x0400 /* Can pause */ ++#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ ++#define LPA_RESV 0x1000 /* Unused... */ ++#define LPA_RFAULT 0x2000 /* Link partner faulted */ ++#define LPA_LPACK 0x4000 /* Link partner acked us */ ++#define LPA_NPAGE 0x8000 /* Next page bit */ ++ ++/* 1000BASE-T Control register(0x09) */ ++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ ++#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ ++#define CTL1000_AS_MASTER 0x0800 ++#define CTL1000_ENABLE_MASTER 0x1000 ++ ++/* 1000BASE-T Status register(0x0A) */ ++#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ ++#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ ++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ ++#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ ++ ++/**********YT8614************************************************/ ++/* Basic mode control register(0x00) */ ++#define FIBER_BMCR_RESV 0x001f /* b[4:0] Unused... */ ++#define FIBER_BMCR_EN_UNIDIR 0x0020 /* b[5] Valid when bit 0.12 is zero and bit 0.8 is one */ ++#define FIBER_BMCR_SPEED1000 0x0040 /* b[6] MSB of Speed (1000) */ ++#define FIBER_BMCR_CTST 0x0080 /* b[7] Collision test */ ++#define FIBER_BMCR_DUPLEX_MODE 0x0100 /* b[8] Duplex mode */ ++#define FIBER_BMCR_ANRESTART 0x0200 /* b[9] Auto negotiation restart */ ++#define FIBER_BMCR_ISOLATE 0x0400 /* b[10] Isolate phy from RGMII/SGMII/FIBER */ ++#define FIBER_BMCR_PDOWN 0x0800 /* b[11] 1: Power down */ ++#define FIBER_BMCR_ANENABLE 0x1000 /* b[12] Enable auto negotiation */ ++#define FIBER_BMCR_SPEED100 0x2000 /* b[13] LSB of Speed (100) */ ++#define FIBER_BMCR_LOOPBACK 0x4000 /* b[14] Internal loopback control */ ++#define FIBER_BMCR_RESET 0x8000 /* b[15] PHY Software Reset(self-clear) */ ++ ++/* Sds specific status register(0x11) */ ++#define FIBER_SSR_ERCAP 0x0001 /* b[0] realtime syncstatus */ ++#define FIBER_SSR_XMIT 0x000E /* b[3:1] realtime transmit statemachine. ++ 001: Xmit Idle; ++ 010: Xmit Config; ++ 100: Xmit Data. */ ++#define FIBER_SSR_SER_MODE_CFG 0x0030 /* b[5:4] realtime serdes working mode. ++ 00: SG_MAC; ++ 01: SG_PHY; ++ 10: FIB_1000; ++ 11: FIB_100. */ ++#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040 /* b[6] realtime en_flowctrl_tx */ ++#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080 /* b[7] realtime en_flowctrl_rx */ ++#define FIBER_SSR_DUPLEX_ERROR 0x0100 /* b[8] realtime deplex error */ ++#define FIBER_SSR_RX_LPI_ACTIVE 0x0200 /* b[9] rx lpi is active */ ++#define FIBER_SSR_LSTATUS 0x0400 /* b[10] Link status real-time */ ++#define FIBER_SSR_PAUSE 0x1800 /* b[12:11] Pause to mac */ ++#define FIBER_SSR_DUPLEX 0x2000 /* b[13] This status bit is valid only when bit10 is 1. ++ 1: full duplex ++ 0: half duplex */ ++#define FIBER_SSR_SPEED_MODE 0xC000 /* b[15:14] These status bits are valid only when bit10 is 1. ++ 10---1000M ++ 01---100M */ ++ ++/* SLED cfg0 (ext 0xA001) */ ++#define FIBER_SLED_CFG0_EN_CTRL 0x00FF /* b[7:0] Control to enable the eight ports' SLED */ ++#define FIBER_SLED_CFG0_BIT_MASK 0x0700 /* b[10:8] 1: enable the pin output */ ++#define FIBER_SLED_CFG0_ACT_LOW 0x0800 /* b[11] control SLED's polarity. 1: active low; 0: active high */ ++#define FIBER_SLED_CFG0_MANU_ST 0x7000 /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */ ++#define FIBER_SLED_CFG0_MANU_EN 0x8000 /* b[15] to control serial LEDs status manually */ ++ ++/**********YT8614************************************************/ ++/* Fiber auto sensing(sgmii ext 0xA5) */ ++#define FIBER_AUTO_SEN_ENABLE 0x8000 /* b[15] Enable fiber auto sensing */ ++ ++/* Fiber force speed(common ext 0xA009) */ ++#define FIBER_FORCE_1000M 0x0001 /* b[0] 1:1000BX 0:100FX */ ++ ++#ifndef NULL ++#define NULL 0 ++#endif ++ ++/* errno */ ++enum ytphy_8614_errno_e ++{ ++ SYS_E_NONE, ++ SYS_E_PARAM, ++ SYS_E_MAX ++}; ++ ++/* errno */ ++enum ytphy_8614_combo_speed_e ++{ ++ YT8614_COMBO_FIBER_1000M, ++ YT8614_COMBO_FIBER_100M, ++ YT8614_COMBO_UTP_ONLY, ++ YT8614_COMBO_SPEED_MAX ++}; ++ ++/* definition for porting */ ++/* phy registers access */ ++typedef struct ++{ ++ u16 reg; /* the offset of the phy internal address */ ++ u16 val; /* the value of the register */ ++ u8 regType; /* register type */ ++} phy_data_s; ++ ++/* for porting use. ++ * pls over-write member function read/write for mdio access ++ */ ++typedef struct phy_info_str ++{ ++#if 0 ++ struct phy_device *phydev; ++ int mdio_base; ++#endif ++ unsigned int lport; ++ unsigned int bus_id; ++ unsigned int phy_addr; ++ ++ s32 (*read)(struct phy_info_str *info, phy_data_s *param); ++ s32 (*write)(struct phy_info_str *info, phy_data_s *param); ++}phy_info_s; ++ ++/* get phy access method */ ++s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param); ++s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param); ++s32 yt8614_phy_soft_reset(u32 lport); ++s32 yt8614_phy_init(u32 lport); ++s32 yt8614_fiber_enable(u32 lport, BOOL enable); ++s32 yt8614_utp_enable(u32 lport, BOOL enable); ++s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable); ++s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable); ++s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed); ++s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable); ++s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable); ++s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii); ++int yt8614_combo_media_priority_set (u32 lport, int fiber); ++int yt8614_combo_media_priority_get (u32 lport, int *fiber); ++s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable); ++s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable); ++s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask); ++s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask); ++s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full); ++s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full); ++s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed); ++s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed); ++int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg); ++int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media); ++ ++#endif +diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h +new file mode 100644 +index 000000000..9e01fc205 +--- /dev/null ++++ b/include/linux/motorcomm_phy.h +@@ -0,0 +1,119 @@ ++/* ++ * include/linux/motorcomm_phy.h ++ * ++ * Motorcomm PHY IDs ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef _MOTORCOMM_PHY_H ++#define _MOTORCOMM_PHY_H ++ ++#define MOTORCOMM_PHY_ID_MASK 0x00000fff ++#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff ++#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff ++ ++#define PHY_ID_YT8010 0x00000309 ++#define PHY_ID_YT8510 0x00000109 ++#define PHY_ID_YT8511 0x0000010a ++#define PHY_ID_YT8512 0x00000118 ++#define PHY_ID_YT8512B 0x00000128 ++#define PHY_ID_YT8521 0x0000011a ++#define PHY_ID_YT8531S 0x4f51e91a ++#define PHY_ID_YT8531 0x4f51e91b ++//#define PHY_ID_YT8614 0x0000e899 ++#define PHY_ID_YT8618 0x0000e889 ++ ++#define REG_PHY_SPEC_STATUS 0x11 ++#define REG_DEBUG_ADDR_OFFSET 0x1e ++#define REG_DEBUG_DATA 0x1f ++ ++#define YT8512_EXTREG_AFE_PLL 0x50 ++#define YT8512_EXTREG_EXTEND_COMBO 0x4000 ++#define YT8512_EXTREG_LED0 0x40c0 ++#define YT8512_EXTREG_LED1 0x40c3 ++ ++#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 ++ ++#define YT_SOFTWARE_RESET 0x8000 ++ ++#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 ++#define YT8512_CONTROL1_RMII_EN 0x0001 ++#define YT8512_LED0_ACT_BLK_IND 0x1000 ++#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 ++#define YT8512_LED0_BT_BLK_EN 0x0002 ++#define YT8512_LED0_HT_BLK_EN 0x0004 ++#define YT8512_LED0_COL_BLK_EN 0x0008 ++#define YT8512_LED0_BT_ON_EN 0x0010 ++#define YT8512_LED1_BT_ON_EN 0x0010 ++#define YT8512_LED1_TXACT_BLK_EN 0x0100 ++#define YT8512_LED1_RXACT_BLK_EN 0x0200 ++#define YT8512_SPEED_MODE 0xc000 ++#define YT8512_DUPLEX 0x2000 ++ ++#define YT8512_SPEED_MODE_BIT 14 ++#define YT8512_DUPLEX_BIT 13 ++#define YT8512_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 ++#define YT8521_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_SPEED_MODE 0xc000 ++#define YT8521_DUPLEX 0x2000 ++#define YT8521_SPEED_MODE_BIT 14 ++#define YT8521_DUPLEX_BIT 13 ++#define YT8521_LINK_STATUS_BIT 10 ++ ++/* based on yt8521 wol config register */ ++#define YTPHY_UTP_INTR_REG 0x12 ++/* WOL Event Interrupt Enable */ ++#define YTPHY_WOL_INTR BIT(6) ++ ++/* Magic Packet MAC address registers */ ++#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007 ++#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008 ++#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009 ++ ++#define YTPHY_WOL_CFG_REG 0xa00a ++#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */ ++#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */ ++#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */ ++#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */ ++#define YTPHY_WOL_CFG_WIDTH2 BIT(2) ++ ++#define YTPHY_REG_SPACE_UTP 0 ++#define YTPHY_REG_SPACE_FIBER 2 ++ ++enum ytphy_wol_type_e ++{ ++ YTPHY_WOL_TYPE_LEVEL, ++ YTPHY_WOL_TYPE_PULSE, ++ YTPHY_WOL_TYPE_MAX ++}; ++typedef enum ytphy_wol_type_e ytphy_wol_type_t; ++ ++enum ytphy_wol_width_e ++{ ++ YTPHY_WOL_WIDTH_84MS, ++ YTPHY_WOL_WIDTH_168MS, ++ YTPHY_WOL_WIDTH_336MS, ++ YTPHY_WOL_WIDTH_672MS, ++ YTPHY_WOL_WIDTH_MAX ++}; ++typedef enum ytphy_wol_width_e ytphy_wol_width_t; ++ ++struct ytphy_wol_cfg_s ++{ ++ int enable; ++ int type; ++ int width; ++}; ++typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t; ++ ++#endif /* _MOTORCOMM_PHY_H */ ++ ++ +-- +2.25.1 + diff --git a/patch/kernel/archive/media-5.19/00630-board-pbp-fix-wonky-wifi-bt.patch b/patch/kernel/media-current/00600-board-pbp-fix-wonky-wifi-bt.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00630-board-pbp-fix-wonky-wifi-bt.patch rename to patch/kernel/media-current/00600-board-pbp-fix-wonky-wifi-bt.patch diff --git a/patch/kernel/archive/media-5.19/00100-board-firefly-rk3399-dts.patch b/patch/kernel/media-current/00610-board-firefly-rk3399-dts.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00100-board-firefly-rk3399-dts.patch rename to patch/kernel/media-current/00610-board-firefly-rk3399-dts.patch diff --git a/patch/kernel/archive/media-5.10/00980-builddeb.patch b/patch/kernel/media-current/00980-builddeb.patch similarity index 97% rename from patch/kernel/archive/media-5.10/00980-builddeb.patch rename to patch/kernel/media-current/00980-builddeb.patch index fef0dc388..e21b34cb5 100644 --- a/patch/kernel/archive/media-5.10/00980-builddeb.patch +++ b/patch/kernel/media-current/00980-builddeb.patch @@ -71,7 +71,7 @@ cat >> $tmpdir/DEBIAN/postinst <<- EOT ln -sf $(basename $installed_image_path) /boot/$image_name 2> /dev/null || cp /$installed_image_path /boot/$image_name + cd /boot -+ ln -sfT linux-image-$version dtb 2> /dev/null || mv linux-image-$version dtb ++ ln -sfT linux-image-$version dtb 2> /dev/null || cp linux-image-$version dtb touch /boot/.next exit 0 EOT diff --git a/patch/kernel/archive/media-5.10/00981-mkdebian.patch b/patch/kernel/media-current/00981-mkdebian.patch similarity index 100% rename from patch/kernel/archive/media-5.10/00981-mkdebian.patch rename to patch/kernel/media-current/00981-mkdebian.patch diff --git a/patch/kernel/media-edge b/patch/kernel/media-edge deleted file mode 120000 index 2879dd064..000000000 --- a/patch/kernel/media-edge +++ /dev/null @@ -1 +0,0 @@ -archive/media-6.0 \ No newline at end of file diff --git a/patch/kernel/media-edge/00100-v91-i2s-mclk.patch b/patch/kernel/media-edge/00100-v91-i2s-mclk.patch new file mode 100644 index 000000000..ac0b9c0bc --- /dev/null +++ b/patch/kernel/media-edge/00100-v91-i2s-mclk.patch @@ -0,0 +1,84 @@ +diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c +index 606ae6cd918b..ee8924ac0093 100644 +--- a/drivers/clk/rockchip/clk-rk3568.c ++++ b/drivers/clk/rockchip/clk-rk3568.c +@@ -13,6 +13,8 @@ + #include + #include "clk.h" + ++#define RK3568_GRF_SOC_CON1 0x504 ++#define RK3568_GRF_SOC_CON2 0x508 + #define RK3568_GRF_SOC_STATUS0 0x580 + + enum rk3568_pmu_plls { +@@ -247,13 +249,13 @@ PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; + PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; + PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; + PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; +-PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +-PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +-PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +-PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +-PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +-PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +-PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; ++PNAME(i2s0_mclkout_tx_p) = { "mclk_i2s0_8ch_tx", "xin_osc0_half" }; ++PNAME(i2s0_mclkout_rx_p) = { "mclk_i2s0_8ch_rx", "xin_osc0_half" }; ++PNAME(i2s1_mclkout_tx_p) = { "mclk_i2s1_8ch_tx", "xin_osc0_half" }; ++PNAME(i2s1_mclkout_rx_p) = { "mclk_i2s1_8ch_rx", "xin_osc0_half" }; ++PNAME(i2s2_mclkout_p) = { "mclk_i2s2_2ch", "xin_osc0_half" }; ++PNAME(i2s3_mclkout_tx_p) = { "mclk_i2s3_2ch_tx", "xin_osc0_half" }; ++PNAME(i2s3_mclkout_rx_p) = { "mclk_i2s3_2ch_rx", "xin_osc0_half" }; + PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; + PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; + PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; +@@ -307,6 +309,12 @@ PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; + PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; + PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; + PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; ++PNAME(i2s1_mclkout_p) = { "i2s1_mclkout_rx", "i2s1_mclkout_tx" }; ++PNAME(i2s3_mclkout_p) = { "i2s3_mclkout_rx", "i2s3_mclkout_tx" }; ++PNAME(i2s1_mclk_rx_ioe_p) = { "i2s1_mclkin_rx", "i2s1_mclkout_rx" }; ++PNAME(i2s1_mclk_tx_ioe_p) = { "i2s1_mclkin_tx", "i2s1_mclkout_tx" }; ++PNAME(i2s2_mclk_ioe_p) = { "i2s2_mclkin", "i2s2_mclkout" }; ++PNAME(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" }; + + static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { + [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, +@@ -704,6 +712,19 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { + RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 11, GFLAGS), + ++ MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3568_GRF_SOC_CON1, 5, 1, MFLAGS), ++ MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3568_GRF_SOC_CON2, 15, 1, MFLAGS), ++ MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0, ++ RK3568_GRF_SOC_CON2, 0, 1, MFLAGS), ++ MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0, ++ RK3568_GRF_SOC_CON2, 1, 1, MFLAGS), ++ MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0, ++ RK3568_GRF_SOC_CON2, 2, 1, MFLAGS), ++ MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0, ++ RK3568_GRF_SOC_CON2, 3, 1, MFLAGS), ++ + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, +diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h +index d29890865150..251445cf7632 100644 +--- a/include/dt-bindings/clock/rk3568-cru.h ++++ b/include/dt-bindings/clock/rk3568-cru.h +@@ -479,6 +479,12 @@ + #define CPLL_25M 416 + #define CPLL_100M 417 + #define SCLK_DDRCLK 418 ++#define I2S1_MCLKOUT 419 ++#define I2S3_MCLKOUT 420 ++#define I2S1_MCLK_RX_IOE 421 ++#define I2S1_MCLK_TX_IOE 422 ++#define I2S2_MCLK_IOE 423 ++#define I2S3_MCLK_IOE 424 + + #define PCLK_CORE_PVTM 450 + diff --git a/patch/kernel/media-edge/00110-v91-irq-gic-v3-its.patch b/patch/kernel/media-edge/00110-v91-irq-gic-v3-its.patch new file mode 100644 index 000000000..ae70f9986 --- /dev/null +++ b/patch/kernel/media-edge/00110-v91-irq-gic-v3-its.patch @@ -0,0 +1,192 @@ +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -45,6 +45,7 @@ + + #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) + #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) ++#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE (1 << 2) + + #define RD_LOCAL_LPI_ENABLED BIT(0) + #define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1) +@@ -2176,6 +2177,11 @@ + { + struct page *prop_page; + ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ pr_err("ITS ALLOCATE PROP WORKAROUND\n"); ++ gfp_flags |= GFP_DMA; ++ } ++ + prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); + if (!prop_page) + return NULL; +@@ -2299,6 +2305,7 @@ + u32 alloc_pages, psz; + struct page *page; + void *base; ++ gfp_t gfp_flags; + + psz = baser->psz; + alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); +@@ -2310,7 +2317,10 @@ + order = get_order(GITS_BASER_PAGES_MAX * psz); + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ gfp_flags |= GFP_DMA; ++ page = alloc_pages_node(its->numa_node, gfp_flags, order); + if (!page) + return -ENOMEM; + +@@ -2356,6 +2366,13 @@ + + its_write_baser(its, baser, val); + tmp = baser->val; ++ ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ if (tmp & GITS_BASER_SHAREABILITY_MASK) ++ tmp &= ~GITS_BASER_SHAREABILITY_MASK; ++ else ++ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); ++ } + + if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { + /* +@@ -2939,6 +2956,10 @@ + { + struct page *pend_page; + ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ gfp_flags |= GFP_DMA; ++ } ++ + pend_page = alloc_pages(gfp_flags | __GFP_ZERO, + get_order(LPI_PENDBASE_SZ)); + if (!pend_page) +@@ -3083,6 +3104,9 @@ + + gicr_write_propbaser(val, rbase + GICR_PROPBASER); + tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); ++ ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; + + if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { + if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { +@@ -3108,6 +3132,9 @@ + gicr_write_pendbaser(val, rbase + GICR_PENDBASER); + tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); + ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; ++ + if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { + /* + * The HW reports non-shareable, we must remove the +@@ -3271,7 +3298,12 @@ + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) { ++ gfp_flags |= GFP_DMA; ++ } ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(baser->psz)); + if (!page) + return false; +@@ -3360,6 +3392,7 @@ + int nr_lpis; + int nr_ites; + int sz; ++ gfp_t gfp_flags; + + if (!its_alloc_device_table(its, dev_id)) + return NULL; +@@ -3367,7 +3400,11 @@ + if (WARN_ON(!is_power_of_2(nvecs))) + nvecs = roundup_pow_of_two(nvecs); + +- dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ gfp_flags = GFP_KERNEL; ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ gfp_flags |= GFP_DMA; ++ ++ dev = kzalloc(sizeof(*dev), gfp_flags); + /* + * Even if the device wants a single LPI, the ITT must be + * sized as a power of two (and you need at least one bit...). +@@ -3375,7 +3412,8 @@ + nr_ites = max(2, nvecs); + sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); + sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; +- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); ++ ++ itt = kzalloc_node(sz, gfp_flags, its->numa_node); + if (alloc_lpis) { + lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); + if (lpi_map) +@@ -4695,6 +4733,13 @@ + * page. Trick it into doing the right thing... + */ + its->vlpi_redist_offset = SZ_128K; ++ return true; ++} ++ ++static bool __maybe_unused its_enable_quirk_rk3568(void *data) ++{ ++ gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE; ++ + return true; + } + +@@ -4745,6 +4790,13 @@ + }, + #endif + { ++ .desc = "ITS: Rockchip RK3568 force no_local_cache", ++ .iidr = 0x0201743b, ++ .mask = 0xffffffff, ++ .init = its_enable_quirk_rk3568, ++ }, ++ ++ { + } + }; + +@@ -4999,6 +5051,7 @@ + struct page *page; + u32 ctlr; + int err; ++ gfp_t gfp_flags; + + its_base = its_map_one(res, &err); + if (!its_base) +@@ -5052,7 +5105,11 @@ + + its->numa_node = numa_node; + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA; ++// if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++// gfp_flags |= GFP_DMA; ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(ITS_CMD_QUEUE_SZ)); + if (!page) { + err = -ENOMEM; +@@ -5082,6 +5139,9 @@ + + gits_write_cbaser(baser, its->base + GITS_CBASER); + tmp = gits_read_cbaser(its->base + GITS_CBASER); ++ ++ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) ++ tmp &= ~GITS_CBASER_SHAREABILITY_MASK; + + if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { + diff --git a/patch/kernel/media-edge/00120-rk356x-dtsi.patch b/patch/kernel/media-edge/00120-rk356x-dtsi.patch new file mode 100644 index 000000000..210d1e567 --- /dev/null +++ b/patch/kernel/media-edge/00120-rk356x-dtsi.patch @@ -0,0 +1,38 @@ +--- v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -287,7 +287,7 @@ + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; +- dr_mode = "otg"; ++ dr_mode = "host"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; +@@ -1031,6 +1031,25 @@ + status = "disabled"; + }; + ++ i2s2_2ch: i2s@fe420000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe420000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 4>, <&dmac1 5>; ++ dma-names = "tx", "rx"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ pinctrl-0 = <&i2s2m0_sclktx ++ &i2s2m0_lrcktx ++ &i2s2m0_sdi ++ &i2s2m0_sdo>; ++ pinctrl-names = "default"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + diff --git a/patch/kernel/archive/media-6.0/00140-board-firefly-rk3399-dts.patch b/patch/kernel/media-edge/00130-board-firefly-rk3399-dts.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00140-board-firefly-rk3399-dts.patch rename to patch/kernel/media-edge/00130-board-firefly-rk3399-dts.patch diff --git a/patch/kernel/media-edge/00140-v95-make.patch b/patch/kernel/media-edge/00140-v95-make.patch new file mode 100644 index 000000000..af74a5865 --- /dev/null +++ b/patch/kernel/media-edge/00140-v95-make.patch @@ -0,0 +1,9 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -1,4 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-firefly-roc-pc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-firefly-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb diff --git a/patch/kernel/media-edge/00150-v95-rk3566-firefly-roc-pc.patch b/patch/kernel/media-edge/00150-v95-rk3566-firefly-roc-pc.patch new file mode 100644 index 000000000..f8d64ff90 --- /dev/null +++ b/patch/kernel/media-edge/00150-v95-rk3566-firefly-roc-pc.patch @@ -0,0 +1,779 @@ +new file mode 100644 +index 000000000..fac2db500 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts +@@ -0,0 +1,773 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ model = "Firefly rk3566-roc-pc"; ++ compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ mmc2 = &sdmmc1; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ vcc5v0_in: vcc5v0_in { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_in"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ gmac1_clkin: external-gmac1-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac1_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0_sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_in>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_otg: vcc5v0-otg-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_otg"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_otg_en>; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pcie_p"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3>; ++ }; ++ ++ firefly_leds: leds { ++ compatible = "gpio-leds"; ++ power_led: power { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power>; ++ }; ++ ++ user_led: user { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ status = "okay"; ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ rk_headset: rk-headset { ++ compatible = "rockchip_headset"; ++ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det>; ++ io-channels = <&saradc 2>; //HP_HOOK pin ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_hot: cpu_hot { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_3v3>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m0_miim ++ &gmac1m0_tx_bus2 ++ &gmac1m0_rx_bus2 ++ &gmac1m0_rgmii_clk ++ &gmac1m0_clkinout ++ &gmac1m0_rgmii_bus>; ++ snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ tx_delay = <0x4e>; ++ rx_delay = <0x2c>; ++ phy-handle = <&rgmii_phy1>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint@0 { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; ++ assigned-clock-rates = <12288000>; ++ assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; ++ #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT>; ++ pinctrl-names = "default", "pmic-sleep", ++ "pmic-power-off", "pmic-reset"; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; ++ ++ rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ //fb-inner-reg-idxs = <2>; ++ /* 1: rst regs (default in codes), 0: rst the pmic */ ++ pmic-reset-func = <0>; ++ /* not save the PMIC_POWER_EN register in uboot */ ++ not-save-power-en = <1>; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd_gpu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ codec { ++ mic-in-differential; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie_p>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_otg_en: vcc5v0-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_power: led-power { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ led_user: led-user { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ headphone { ++ hp_det: hp-det { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ disable-wp; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ bus-width = <4>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart0 { ++// pinctrl-names = "default"; ++// pinctrl-0 = <&uart0_xfer>; ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; ++ status = "okay"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ clocks = <&rk809 1>; ++ clock-names = "lpo"; ++ device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcca1v8_pmu>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ vbus-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ compatible = "rockchip,rk3568-vop"; ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + diff --git a/patch/kernel/media-edge/00160-v95-rk3568-bpi-r2pro.patch b/patch/kernel/media-edge/00160-v95-rk3568-bpi-r2pro.patch new file mode 100644 index 000000000..bc0a10085 --- /dev/null +++ b/patch/kernel/media-edge/00160-v95-rk3568-bpi-r2pro.patch @@ -0,0 +1,190 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -6,6 +6,7 @@ + + /dts-v1/; + #include ++#include + #include + #include + #include +@@ -53,6 +54,14 @@ + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; ++ }; ++ ++ fan: gpio_fan { ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ #cooling-cells = <2>; + }; + + hdmi-con { +@@ -119,6 +128,28 @@ + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ rk_headset: rk-headset { ++ compatible = "rockchip_headset"; ++ headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det>; ++ io-channels = <&saradc 2>; //HP_HOOK pin ++ }; + }; + + &combphy0 { +@@ -134,6 +165,39 @@ + &combphy2 { + /* used for SATA */ + status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_hot: cpu_hot { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + &gmac0 { +@@ -216,15 +280,49 @@ + &i2c0 { + status = "okay"; + ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; ++ assigned-clock-rates = <12288000>; ++ assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + #clock-cells = <1>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT>; ++ pinctrl-names = "default", "pmic-sleep", ++ "pmic-power-off", "pmic-reset"; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; ++ + rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ //fb-inner-reg-idxs = <2>; ++ /* 1: rst regs (default in codes), 0: rst the pmic */ ++ pmic-reset-func = <0>; ++ /* not save the PMIC_POWER_EN register in uboot */ ++ not-save-power-en = <1>; ++ + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; +@@ -427,6 +525,10 @@ + regulator-off-in-suspend; + }; + }; ++ }; ++ ++ codec { ++ mic-in-differential; + }; + }; + }; +@@ -458,6 +560,18 @@ + status = "okay"; + }; + ++&i2s1_8ch { ++ /* headphone */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++ + &mdio0 { + #address-cells = <1>; + #size-cells = <0>; +@@ -543,6 +657,12 @@ + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ headphone { ++ hp_det: hp-det { ++ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + diff --git a/patch/kernel/media-edge/00170-v95-rk3568-firefly-roc-pc.patch b/patch/kernel/media-edge/00170-v95-rk3568-firefly-roc-pc.patch new file mode 100644 index 000000000..6f5f39b7c --- /dev/null +++ b/patch/kernel/media-edge/00170-v95-rk3568-firefly-roc-pc.patch @@ -0,0 +1,1050 @@ +new file mode 100644 +index 000000000..fac2db500 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts +@@ -0,0 +1,1044 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Firefly rk3568-roc-pc"; ++ compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ mmc2 = &sdmmc1; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ fan: gpio_fan { ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ #cooling-cells = <2>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ vcc2v5_sys: vcc2v5-ddr { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc2v5-sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_vga: vcc3v3-vga { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_vga"; ++ regulator-always-on; ++ regulator-boot-on; ++ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_3v3: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "pcie30_3v3"; ++ regulator-min-microvolt = <100000>; ++ regulator-max-microvolt = <3300000>; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0x1>; ++ states = <100000 0x0 ++ 3300000 0x1>; ++ }; ++ ++ vcc3v3_bu: vcc3v3-bu { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_bu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_sys: vcc5v0_sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc3v3_lcd0_n: vcc3v3-lcd0-n { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_lcd0_n"; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_lcd1_n: vcc3v3-lcd1-n { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_lcd1_n"; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ }; ++ ++ vcc5v0_otg: vcc5v0-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_otg_en>; ++ regulator-name = "vcc5v0_otg"; ++ }; ++ ++ vcc3v3_lcd0_n: vcc3v3-lcd0-n { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_lcd0_n"; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_lcd1_n: vcc3v3-lcd1-n { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_lcd1_n"; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_hub_power: vcc-hub-power-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_hub_power_en>; ++ regulator-name = "vcc_hub_power_en"; ++ regulator-always-on; ++ }; ++ ++ vcc_hub_reset: vcc-hub-reset-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_hub_reset_en>; ++ regulator-name = "vcc_hub_reset_en"; ++ regulator-always-on; ++ }; ++ ++ pcie_pi6c_oe: pcie-pi6c-oe-regulator { ++ compatible = "regulator-fixed"; ++ //enable-active-high; ++ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pi6c_oe_en>; ++ regulator-name = "pcie_pi6c_oe_en"; ++ regulator-always-on; ++ }; ++ ++ vcc_4g_power: vcc-4g-power-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_4g_power_en>; ++ regulator-name = "vcc_4g_power_en"; ++ regulator-always-on; ++ }; ++ ++ firefly_leds: leds { ++ compatible = "gpio-leds"; ++ power_led: power { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power>; ++ }; ++ ++ user_led: user { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ status = "okay"; ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wireless_wlan: wireless-wlan { ++ compatible = "wlan-platdata"; ++ rockchip,grf = <&grf>; ++ wifi_chip_type = "ap6398s"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_irq>; ++ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ wireless_bluetooth: wireless-bluetooth { ++ compatible = "bluetooth-platdata"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ //wifi-bt-power-toggle; ++ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default", "rts_gpio"; ++ pinctrl-0 = <&uart8m0_rtsn>; ++ pinctrl-1 = <&uart8_gpios>; ++ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; ++ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; ++ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ flash_led: flash-led { ++ compatible = "led,rgb13h"; ++ label = "pwm-flash-led"; ++ led-max-microamp = <20000>; ++ flash-max-microamp = <20000>; ++ flash-max-timeout-us = <1000000>; ++ pwms = <&pwm11 0 25000 0>; ++ rockchip,camera-module-index = <1>; ++ rockchip,camera-module-facing = "front"; ++ status = "disabled"; ++ }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ rk_headset: rk-headset { ++ compatible = "rockchip_headset"; ++ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det>; ++ io-channels = <&saradc 2>; //HP_HOOK pin ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_hot: cpu_hot { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus>; ++ tx_delay = <0x4f>; ++ rx_delay = <0x26>; ++ snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint@0 { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ fusb0: fusb30x@22 { ++ compatible = "fairchild,fusb302"; ++ reg = <0x22>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; ++ fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; ++ vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; ++ assigned-clock-rates = <12288000>; ++ assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; ++ #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT>; ++ pinctrl-names = "default", "pmic-sleep", ++ "pmic-power-off", "pmic-reset"; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; ++ ++ rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ //fb-inner-reg-idxs = <2>; ++ /* 1: rst regs (default in codes), 0: rst the pmic */ ++ pmic-reset-func = <0>; ++ /* not save the PMIC_POWER_EN register in uboot */ ++ not-save-power-en = <1>; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd_gpu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ codec { ++ mic-in-differential; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++}; ++ ++&i2c5 { ++ status = "okay"; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&pcie30_3v3>; ++ ++ status = "okay"; ++}; ++ ++&gic { ++ status = "okay"; ++}; ++ ++&sata2 { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wireless-wlan { ++ wifi_host_wake_irq: wifi-host-wake-irq { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ wireless-bluetooth { ++ uart8_gpios: uart8-gpios { ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_otg_en: vcc5v0-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc_hub_power_en: vcc-hub-power-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc_hub_reset_en: vcc-hub-reset-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pi6c_oe_en: pcie-pi6c-oe-en { ++ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ 4g { ++ vcc_4g_power_en: vcc-4g-power-en { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_power: led-power { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ led_user: led-user { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ headphone { ++ hp_det: hp-det { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ supports-emmc; ++ non-removable; ++ max-frequency = <200000000>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ max-frequency = <150000000>; ++ supports-sd; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ max-frequency = <150000000>; ++// max-frequency = <100000000>; ++ supports-sdio; ++ bus-width = <4>; ++ disable-wp; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; ++ sd-uhs-sdr104; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdio_pwrseq { ++ status = "okay"; ++ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <100>; ++}; ++ ++&wireless_wlan { ++ wifi_chip_type = "ap6275s"; ++ status = "okay"; ++}; ++ ++&wireless_bluetooth { ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart3 { ++// status = "disabled"; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4m1_xfer>; ++ status = "okay"; ++}; ++ ++&uart8 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ vbus-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++//&usbdrd30 { ++// status = "okay"; ++//}; ++ ++//&usbhost30 { ++// status = "okay"; ++//}; ++ ++&rk809 { ++ rtc { ++ status = "disabled"; ++ }; ++}; ++ ++&pwm4 { ++ status = "okay"; ++}; ++ ++&pwm5 { ++ status = "okay"; ++}; ++ ++&pwm7 { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + diff --git a/patch/kernel/archive/media-6.0/00190-linux-0002-rockchip-from-list.patch b/patch/kernel/media-edge/00180-linux-0002-rockchip-from-list.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00190-linux-0002-rockchip-from-list.patch rename to patch/kernel/media-edge/00180-linux-0002-rockchip-from-list.patch diff --git a/patch/kernel/archive/media-6.0/00200-linux-90100-add-clock.patch b/patch/kernel/media-edge/00190-linux-90100-add-clock.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00200-linux-90100-add-clock.patch rename to patch/kernel/media-edge/00190-linux-90100-add-clock.patch diff --git a/patch/kernel/archive/media-6.0/00210-linux-90101-add-rt5651-konf.patch b/patch/kernel/media-edge/00200-linux-90101-add-rt5651-konf.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00210-linux-90101-add-rt5651-konf.patch rename to patch/kernel/media-edge/00200-linux-90101-add-rt5651-konf.patch diff --git a/patch/kernel/archive/media-6.0/00220-linux-90102-rt5651.patch b/patch/kernel/media-edge/00210-linux-90102-rt5651.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00220-linux-90102-rt5651.patch rename to patch/kernel/media-edge/00210-linux-90102-rt5651.patch diff --git a/patch/kernel/archive/media-6.0/00230-linux-90103-nanopc-t4-5651.patch b/patch/kernel/media-edge/00220-linux-90103-nanopc-t4-5651.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00230-linux-90103-nanopc-t4-5651.patch rename to patch/kernel/media-edge/00220-linux-90103-nanopc-t4-5651.patch diff --git a/patch/kernel/archive/media-6.0/00240-linux-90104-all-codec.patch b/patch/kernel/media-edge/00230-linux-90104-all-codec.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00240-linux-90104-all-codec.patch rename to patch/kernel/media-edge/00230-linux-90104-all-codec.patch diff --git a/patch/kernel/archive/media-6.0/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch b/patch/kernel/media-edge/00240-linux-90117-add-rk3399-roc-pc-plus-sound.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00250-linux-90117-add-rk3399-roc-pc-plus-sound.patch rename to patch/kernel/media-edge/00240-linux-90117-add-rk3399-roc-pc-plus-sound.patch diff --git a/patch/kernel/archive/media-6.0/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch b/patch/kernel/media-edge/00250-linux-90200-rk3328-roc-pc-wifi-fix.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00260-linux-90200-rk3328-roc-pc-wifi-fix.patch rename to patch/kernel/media-edge/00250-linux-90200-rk3328-roc-pc-wifi-fix.patch diff --git a/patch/kernel/archive/media-6.0/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/patch/kernel/media-edge/00260-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00270-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch rename to patch/kernel/media-edge/00260-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch diff --git a/patch/kernel/archive/media-6.0/00290-rk3328-usb3-phy-driver.patch b/patch/kernel/media-edge/00270-add-rk3328-usb3-phy-driver.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00290-rk3328-usb3-phy-driver.patch rename to patch/kernel/media-edge/00270-add-rk3328-usb3-phy-driver.patch diff --git a/patch/kernel/archive/media-6.0/00300-add-rockchip-iep-driver.patch b/patch/kernel/media-edge/00280-add-rockchip-iep-driver.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00300-add-rockchip-iep-driver.patch rename to patch/kernel/media-edge/00280-add-rockchip-iep-driver.patch diff --git a/patch/kernel/archive/media-6.0/00310-board-roc-rk3399-pc-fix-fusb302-compatible.patch b/patch/kernel/media-edge/00290-board-roc-rk3399-pc-fix-fusb302-compatible.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00310-board-roc-rk3399-pc-fix-fusb302-compatible.patch rename to patch/kernel/media-edge/00290-board-roc-rk3399-pc-fix-fusb302-compatible.patch diff --git a/patch/kernel/archive/media-6.0/00320-general-add-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/media-edge/00300-general-add-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00320-general-add-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/media-edge/00300-general-add-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-6.0/00330-general-add-miniDP-dt-doc.patch b/patch/kernel/media-edge/00310-general-add-miniDP-dt-doc.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00330-general-add-miniDP-dt-doc.patch rename to patch/kernel/media-edge/00310-general-add-miniDP-dt-doc.patch diff --git a/patch/kernel/archive/media-6.0/00340-general-add-miniDP-virtual-extcon.patch b/patch/kernel/media-edge/00320-general-add-miniDP-virtual-extcon.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00340-general-add-miniDP-virtual-extcon.patch rename to patch/kernel/media-edge/00320-general-add-miniDP-virtual-extcon.patch diff --git a/patch/kernel/archive/media-6.0/00350-general-add-overlay-compilation-support.patch b/patch/kernel/media-edge/00330-general-add-overlay-compilation-support.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00350-general-add-overlay-compilation-support.patch rename to patch/kernel/media-edge/00330-general-add-overlay-compilation-support.patch diff --git a/patch/kernel/archive/media-6.0/00360-general-add-overlay-configfs.patch b/patch/kernel/media-edge/00340-general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00360-general-add-overlay-configfs.patch rename to patch/kernel/media-edge/00340-general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/media-6.0/00370-general-add-pll-hdmi-timings.patch b/patch/kernel/media-edge/00350-general-add-pll-hdmi-timings.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00370-general-add-pll-hdmi-timings.patch rename to patch/kernel/media-edge/00350-general-add-pll-hdmi-timings.patch diff --git a/patch/kernel/archive/media-6.0/00380-general-bluetooth-02-add-support-for-RTL8723CS.patch b/patch/kernel/media-edge/00360-general-bluetooth-02-add-support-for-RTL8723CS.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00380-general-bluetooth-02-add-support-for-RTL8723CS.patch rename to patch/kernel/media-edge/00360-general-bluetooth-02-add-support-for-RTL8723CS.patch diff --git a/patch/kernel/archive/media-6.0/00390-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch b/patch/kernel/media-edge/00370-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00390-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch rename to patch/kernel/media-edge/00370-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch diff --git a/patch/kernel/archive/media-6.0/00400-general-bluetooth-04-add-rtl8703bs.patch b/patch/kernel/media-edge/00380-general-bluetooth-04-add-rtl8703bs.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00400-general-bluetooth-04-add-rtl8703bs.patch rename to patch/kernel/media-edge/00380-general-bluetooth-04-add-rtl8703bs.patch diff --git a/patch/kernel/archive/media-6.0/00410-general-bluetooth-add-new-quirk.patch b/patch/kernel/media-edge/00390-general-bluetooth-add-new-quirk.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00410-general-bluetooth-add-new-quirk.patch rename to patch/kernel/media-edge/00390-general-bluetooth-add-new-quirk.patch diff --git a/patch/kernel/archive/media-6.0/00420-general-fix-es8316-kernel-panic.patch b/patch/kernel/media-edge/00400-general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00420-general-fix-es8316-kernel-panic.patch rename to patch/kernel/media-edge/00400-general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/archive/media-6.0/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/media-edge/00410-general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00430-general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/media-edge/00410-general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/archive/media-6.0/00440-general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/media-edge/00420-general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00440-general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/media-edge/00420-general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/media-6.0/00450-general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/media-edge/00430-general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00450-general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/media-edge/00430-general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/media-6.0/00460-general-workaround-broadcom-bt-serdev.patch b/patch/kernel/media-edge/00440-general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00460-general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/media-edge/00440-general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/media-6.0/00470-rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/media-edge/00450-rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00470-rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/media-edge/00450-rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/media-6.0/00480-rk3328-roc-pc-bt.patch b/patch/kernel/media-edge/00460-rk3328-roc-pc-bt.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00480-rk3328-roc-pc-bt.patch rename to patch/kernel/media-edge/00460-rk3328-roc-pc-bt.patch diff --git a/patch/kernel/archive/media-6.0/00490-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/media-edge/00470-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00490-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/media-edge/00470-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-6.0/00500-rk3399-nanopc-t4-emmc.patch b/patch/kernel/media-edge/00480-rk3399-nanopc-t4-emmc.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00500-rk3399-nanopc-t4-emmc.patch rename to patch/kernel/media-edge/00480-rk3399-nanopc-t4-emmc.patch diff --git a/patch/kernel/archive/media-6.0/00510-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch b/patch/kernel/media-edge/00490-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00510-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch rename to patch/kernel/media-edge/00490-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch diff --git a/patch/kernel/archive/media-6.0/00520-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/media-edge/00500-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00520-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/media-edge/00500-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch diff --git a/patch/kernel/archive/media-6.0/00530-rk3399-sd-drive-level-8ma.patch b/patch/kernel/media-edge/00510-rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00530-rk3399-sd-drive-level-8ma.patch rename to patch/kernel/media-edge/00510-rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/media-6.0/00540-rk3399-unlock-temperature.patch b/patch/kernel/media-edge/00520-rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00540-rk3399-unlock-temperature.patch rename to patch/kernel/media-edge/00520-rk3399-unlock-temperature.patch diff --git a/patch/kernel/archive/media-6.0/00560-board-pbp-fix-wonky-wifi-bt.patch b/patch/kernel/media-edge/00530-board-pbp-fix-wonky-wifi-bt.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00560-board-pbp-fix-wonky-wifi-bt.patch rename to patch/kernel/media-edge/00530-board-pbp-fix-wonky-wifi-bt.patch diff --git a/patch/kernel/archive/media-5.19/00980-builddeb.patch b/patch/kernel/media-edge/09980-builddeb.patch similarity index 97% rename from patch/kernel/archive/media-5.19/00980-builddeb.patch rename to patch/kernel/media-edge/09980-builddeb.patch index fef0dc388..e21b34cb5 100644 --- a/patch/kernel/archive/media-5.19/00980-builddeb.patch +++ b/patch/kernel/media-edge/09980-builddeb.patch @@ -71,7 +71,7 @@ cat >> $tmpdir/DEBIAN/postinst <<- EOT ln -sf $(basename $installed_image_path) /boot/$image_name 2> /dev/null || cp /$installed_image_path /boot/$image_name + cd /boot -+ ln -sfT linux-image-$version dtb 2> /dev/null || mv linux-image-$version dtb ++ ln -sfT linux-image-$version dtb 2> /dev/null || cp linux-image-$version dtb touch /boot/.next exit 0 EOT diff --git a/patch/kernel/archive/media-5.19/00981-mkdebian.patch b/patch/kernel/media-edge/09981-mkdebian.patch similarity index 100% rename from patch/kernel/archive/media-5.19/00981-mkdebian.patch rename to patch/kernel/media-edge/09981-mkdebian.patch diff --git a/patch/kernel/media-legacy b/patch/kernel/media-legacy deleted file mode 120000 index 9ee13198d..000000000 --- a/patch/kernel/media-legacy +++ /dev/null @@ -1 +0,0 @@ -archive/media-5.10 \ No newline at end of file diff --git a/patch/kernel/archive/media-6.0/00980-builddeb.patch b/patch/kernel/media-legacy/00980-builddeb.patch similarity index 97% rename from patch/kernel/archive/media-6.0/00980-builddeb.patch rename to patch/kernel/media-legacy/00980-builddeb.patch index fef0dc388..e21b34cb5 100644 --- a/patch/kernel/archive/media-6.0/00980-builddeb.patch +++ b/patch/kernel/media-legacy/00980-builddeb.patch @@ -71,7 +71,7 @@ cat >> $tmpdir/DEBIAN/postinst <<- EOT ln -sf $(basename $installed_image_path) /boot/$image_name 2> /dev/null || cp /$installed_image_path /boot/$image_name + cd /boot -+ ln -sfT linux-image-$version dtb 2> /dev/null || mv linux-image-$version dtb ++ ln -sfT linux-image-$version dtb 2> /dev/null || cp linux-image-$version dtb touch /boot/.next exit 0 EOT diff --git a/patch/kernel/archive/media-6.0/00981-mkdebian.patch b/patch/kernel/media-legacy/00981-mkdebian.patch similarity index 100% rename from patch/kernel/archive/media-6.0/00981-mkdebian.patch rename to patch/kernel/media-legacy/00981-mkdebian.patch diff --git a/patch/kernel/station-p2-current b/patch/kernel/station-p2-current deleted file mode 120000 index 01b2ae6d6..000000000 --- a/patch/kernel/station-p2-current +++ /dev/null @@ -1 +0,0 @@ -archive/station-p2-5.19 \ No newline at end of file