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add community support for MediaTek Filogic device (BananaPi R4 Router)

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This commit is contained in:
Hsun Lai
2025-07-21 15:10:40 +08:00
committed by Igor
parent f7b1a70dbb
commit 2576cd1d8e
51 changed files with 18029 additions and 0 deletions
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18
config/boards/bananapir4.csc Normal file
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# Mediatek MT7988a quad core Cortex-A73 4/8GB RAM 8GB EMMC mPci USB3.0 4xGBE
BOARD_NAME="Banana Pi R4"
BOARDFAMILY="filogic"
BOARD_MAINTAINER=""
KERNEL_TARGET="current"
KERNEL_TEST_TARGET="current"
BOOTCONFIG="mt7988a_bananapi_bpi-r4-sdmmc_defconfig"
BOOT_FDT_FILE="mediatek/mt7988a-bananapi-bpi-r4-sd.dtb"
SRC_EXTLINUX="yes"
SRC_CMDLINE="console=ttyS0,115200n1 earlyprintk loglevel=8 initcall_debug=0 swiotlb=512 cgroup_enable cgroup_memory=1 init=/sbin/init"
function post_family_tweaks__bpi-r4() {
display_alert "Applying eth blobs"
mkdir -p "$SDCARD/lib/firmware/mediatek/mt7988"
cp -v "$SRC/packages/blobs/filogic/firmware/mediatek/mt7988/mt7988_wo_0.bin" "$SDCARD/lib/firmware/mediatek/mt7988/mt7988_wo_0.bin"
cp -v "$SRC/packages/blobs/filogic/firmware/mediatek/mt7988/mt7988_wo_1.bin" "$SDCARD/lib/firmware/mediatek/mt7988/mt7988_wo_1.bin"
}

642
config/kernel/linux-filogic-current.config Normal file
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@@ -0,0 +1,642 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
# CONFIG_CPU_ISOLATION is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_BPF=y
CONFIG_NAMESPACES=y
# CONFIG_TIME_NS is not set
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_RSEQ is not set
# CONFIG_CACHESTAT_SYSCALL is not set
CONFIG_ARCH_MEDIATEK=y
# CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
# CONFIG_ARM64_ERRATUM_826319 is not set
# CONFIG_ARM64_ERRATUM_827319 is not set
# CONFIG_ARM64_ERRATUM_824069 is not set
# CONFIG_ARM64_ERRATUM_819472 is not set
# CONFIG_ARM64_ERRATUM_832075 is not set
# CONFIG_ARM64_ERRATUM_1024718 is not set
# CONFIG_ARM64_ERRATUM_1165522 is not set
# CONFIG_ARM64_ERRATUM_1319367 is not set
# CONFIG_ARM64_ERRATUM_1530923 is not set
# CONFIG_ARM64_ERRATUM_1463225 is not set
# CONFIG_ARM64_ERRATUM_1508412 is not set
# CONFIG_ARM64_ERRATUM_2051678 is not set
# CONFIG_ARM64_ERRATUM_2077057 is not set
# CONFIG_ARM64_ERRATUM_2658417 is not set
# CONFIG_ARM64_ERRATUM_2054223 is not set
# CONFIG_ARM64_ERRATUM_2067961 is not set
# CONFIG_ARM64_ERRATUM_2645198 is not set
# CONFIG_ARM64_ERRATUM_2966298 is not set
# CONFIG_ARM64_ERRATUM_3117295 is not set
# CONFIG_ARM64_ERRATUM_3194386 is not set
# CONFIG_CAVIUM_ERRATUM_22375 is not set
# CONFIG_CAVIUM_ERRATUM_23154 is not set
# CONFIG_CAVIUM_ERRATUM_27456 is not set
# CONFIG_CAVIUM_ERRATUM_30115 is not set
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
# CONFIG_FUJITSU_ERRATUM_010001 is not set
# CONFIG_HISILICON_ERRATUM_161600802 is not set
# CONFIG_HISILICON_ERRATUM_162100801 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set
# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
CONFIG_NR_CPUS=4
CONFIG_HZ_100=y
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
CONFIG_ARM64_SW_TTBR0_PAN=y
# CONFIG_ARM64_HW_AFDBM is not set
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
# CONFIG_ARM64_RAS_EXTN is not set
# CONFIG_ARM64_PTR_AUTH is not set
# CONFIG_ARM64_AMU_EXTN is not set
# CONFIG_ARM64_TLB_RANGE is not set
# CONFIG_ARM64_BTI is not set
# CONFIG_ARM64_E0PD is not set
# CONFIG_ARM64_MTE is not set
# CONFIG_ARM64_EPAN is not set
# CONFIG_ARM64_POE is not set
# CONFIG_ARM64_SVE is not set
# CONFIG_RELOCATABLE is not set
CONFIG_CMDLINE_OVERRIDE=y
# CONFIG_SUSPEND is not set
CONFIG_PM=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_ARM_MEDIATEK_CPUFREQ=y
# CONFIG_ARM_MEDIATEK_CPUFREQ_HW is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STACKPROTECTOR_STRONG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
# CONFIG_IOSCHED_BFQ is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_ZSWAP=y
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SECRETMEM is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_INET_ESP=m
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
# CONFIG_TCP_CONG_WESTWOOD is not set
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_IPV6_SIT is not set
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_MPTCP=y
CONFIG_NETFILTER=y
CONFIG_BRIDGE_NETFILTER=m
# CONFIG_NETFILTER_EGRESS is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_LABELS=y
# CONFIG_NF_CT_PROTO_DCCP is not set
# CONFIG_NF_CT_PROTO_SCTP is not set
# CONFIG_NF_CT_PROTO_UDPLITE is not set
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_IP_VS=m
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_NFCT=y
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_LOG_IPV4=m
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_RAW=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_BRIDGE=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=y
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_DEFAULT=y
CONFIG_DEFAULT_FQ_CODEL=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_CGROUP_NET_PRIO=y
CONFIG_BT=y
CONFIG_CFG80211=m
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=m
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_RFKILL_FULL=y
CONFIG_RFKILL_GPIO=y
# CONFIG_LWTUNNEL_BPF is not set
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM_PERFORMANCE=y
CONFIG_PCI_DEBUG=y
# CONFIG_VGA_ARB is not set
CONFIG_PCIE_MEDIATEK_GEN3=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
# CONFIG_ARM_SMCCC_SOC_ID is not set
CONFIG_MTD=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_NVMEM=y
CONFIG_OF_OVERLAY=y
CONFIG_ZRAM=y
CONFIG_ZRAM_BACKEND_LZ4=y
CONFIG_ZRAM_BACKEND_LZ4HC=y
CONFIG_ZRAM_BACKEND_ZSTD=y
CONFIG_ZRAM_BACKEND_DEFLATE=y
CONFIG_ZRAM_BACKEND_842=y
CONFIG_ZRAM_BACKEND_LZO=y
CONFIG_ZRAM_DEF_COMP_ZSTD=y
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_NVME=y
CONFIG_EEPROM_AT24=m
CONFIG_BLK_DEV_SD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
# CONFIG_ATA_VERBOSE_ERROR is not set
# CONFIG_ATA_FORCE is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
CONFIG_MACVLAN=m
CONFIG_IPVLAN=m
CONFIG_VXLAN=m
CONFIG_VETH=m
CONFIG_NETKIT=y
CONFIG_NET_DSA_AN8855=y
CONFIG_NET_DSA_MT7530=y
# CONFIG_NET_VENDOR_ASIX is not set
# CONFIG_NET_VENDOR_ENGLEDER is not set
# CONFIG_NET_VENDOR_FUNGIBLE is not set
# CONFIG_NET_VENDOR_LITEX is not set
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_MEDIATEK_SOC=y
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_VERTEXCOM is not set
# CONFIG_NET_VENDOR_WANGXUN is not set
CONFIG_SFP=m
CONFIG_AIROHA_EN8801SC_PHY=y
CONFIG_AIR_AN8855_PHY=y
CONFIG_AQUANTIA_PHY=m
CONFIG_ICPLUS_PHY=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MEDIATEK_2P5GE_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MDIO_AN8855=y
CONFIG_PPP=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
CONFIG_AT76C50X_USB=m
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
CONFIG_MT7601U=m
CONFIG_MT76x0U=m
CONFIG_MT76x2U=m
CONFIG_MT7663U=m
CONFIG_MT7915E=m
CONFIG_MT7921E=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_MT7925E=m
CONFIG_MT7925U=m
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
CONFIG_RTL8XXXU=m
CONFIG_RTW88=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CU=m
CONFIG_RTW89=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
CONFIG_RTW89_8922AE=m
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_SILABS is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
CONFIG_RTL8822BU=m
CONFIG_RTL8821CU=m
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_ISDN=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_LEGACY_TIOCSTI is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
# CONFIG_SERIAL_8250_EXAR is not set
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_8250_MT6577=y
# CONFIG_SERIAL_8250_PERICOM is not set
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set
# CONFIG_DEVMEM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=m
CONFIG_I2C_MUX_PCA954x=m
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_MT65XX=y
CONFIG_SPI=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_SNFI=y
# CONFIG_PTP_1588_CLOCK is not set
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6779 is not set
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
# CONFIG_PINCTRL_MT7622 is not set
# CONFIG_PINCTRL_MT8167 is not set
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
# CONFIG_PINCTRL_MT8186 is not set
# CONFIG_PINCTRL_MT8188 is not set
# CONFIG_PINCTRL_MT8192 is not set
# CONFIG_PINCTRL_MT8195 is not set
# CONFIG_PINCTRL_MT8365 is not set
# CONFIG_PINCTRL_MT8516 is not set
CONFIG_GPIO_SYSFS=y
# CONFIG_GPIO_CDEV_V1 is not set
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_POWER_SUPPLY_HWMON is not set
CONFIG_SENSORS_PWM_FAN=m
CONFIG_THERMAL=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
# CONFIG_CPU_FREQ_THERMAL is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_SOC_THERMAL=y
CONFIG_MTK_LVTS_THERMAL=y
CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_MFD_AIROHA_AN8855=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
CONFIG_REGULATOR_RT5190A=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_USB=m
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_PLATFORM=m
CONFIG_USB_XHCI_MTK=m
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_UAS=m
CONFIG_MMC=y
CONFIG_MMC_MTK=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_MT7622=y
CONFIG_DMADEVICES=y
CONFIG_MTK_HSDMA=y
CONFIG_DMATEST=y
CONFIG_STAGING=y
# CONFIG_SURFACE_PLATFORMS is not set
# CONFIG_COMMON_CLK_MT2712 is not set
# CONFIG_COMMON_CLK_MT6765 is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
# CONFIG_COMMON_CLK_MT8167 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8188 is not set
# CONFIG_COMMON_CLK_MT8192 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
# CONFIG_FSL_ERRATUM_A008585 is not set
# CONFIG_HISILICON_ERRATUM_161010101 is not set
# CONFIG_ARM64_ERRATUM_858921 is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MTK_PMIC_WRAP=y
# CONFIG_MTK_MMSYS is not set
# CONFIG_MTK_SOCINFO is not set
CONFIG_PM_DEVFREQ=y
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_MST_IRQ is not set
CONFIG_RESET_TI_SYSCON=y
CONFIG_PHY_MTK_XFI_TPHY=y
CONFIG_PHY_MTK_TPHY=y
CONFIG_PHY_MTK_XSPHY=y
CONFIG_NVMEM_LAYOUT_ADTRAN=y
CONFIG_NVMEM_AN8855_EFUSE=y
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_XFS_FS=y
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_IOSTAT is not set
# CONFIG_DNOTIFY is not set
CONFIG_FANOTIFY=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_XINO_AUTO=y
CONFIG_ISO9660_FS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_EXFAT_FS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
CONFIG_NTFS_FS=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
# CONFIG_JFFS2_ZLIB is not set
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_EROFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFSD=y
CONFIG_CIFS=y
CONFIG_SMB_SERVER=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEY_DH_OPERATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"
CONFIG_INIT_STACK_NONE=y
CONFIG_LIST_HARDENED=y
CONFIG_CRYPTO_USER=m
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_SHA1_ARM64_CE=m
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=m
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRC_CCITT=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_ARM64 is not set
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_RISCV is not set
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO_DWARF5=y
CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_MAGIC_SYSRQ_SERIAL is not set
CONFIG_DEBUG_FS=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SCHED_DEBUG is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set

63
config/sources/families/filogic.conf Normal file
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@@ -0,0 +1,63 @@
#
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2013-2023 Igor Pecovnik, igor@armbian.com
#
# This file is a part of the Armbian Build Framework
# https://github.com/armbian/build/
#
declare -g ARCH=arm64
declare -g OFFSET=16
declare -g ATFSOURCE='https://github.com/mtk-openwrt/arm-trusted-firmware.git'
declare -g ATF_TARGET_MAP="PLAT=mt7988 BOOT_DEVICE=sdmmc USE_MKIMAGE=1 BOARD_BGA=1 HAVE_DRAM_OBJ_FILE=yes DRAM_USE_COMB=1 all;;build/mt7988/release/bl2.img build/mt7988/release/bl31.bin"
declare -g ATFBRANCH="branch:mtksoc-20250212"
declare -g BOOTDELAY=1
declare -g BOOTPATCHDIR="${BOOTPATCHDIR:-"u-boot-filogic"}"
declare -g BOOTBRANCH="${BOOTBRANCH:-"tag:v2025.04"}"
declare -g BOOTENV_FILE='filogic.txt'
declare -g UBOOT_TARGET_MAP=";;u-boot.bin"
declare -g BOOTSCRIPT='boot-filogic.cmd:boot.cmd'
declare -g IMAGE_PARTITION_TABLE="gpt"
declare -g LINUXFAMILY=filogic
# This build requires xxd
function add_host_dependencies__filogic_add_xxd_hostdep() {
display_alert "Adding xxd dep" "for ${BOARD} bootloader compile" "debug"
declare -g EXTRA_BUILD_DEPS="${EXTRA_BUILD_DEPS} xxd arm-trusted-firmware-tools"
}
# Handling of FIP blobs
function uboot_custom_postprocess() {
run_host_command_logged rm -f "$SRC"/cache/u-boot_sdmmc.fip
run_host_command_logged fiptool create \
--soc-fw "$SRC"/cache/sources/arm-trusted-firmware/mtksoc-20250212/build/mt7988/release/bl31.bin \
--nt-fw "$SRC"/cache/sources/u-boot-worktree/u-boot/v2025.04/u-boot.bin \
"$SRC"/cache/u-boot_sdmmc.fip
}
case $BRANCH in
current)
KERNELSOURCE='https://github.com/chainsx/linux-filogic.git'
KERNELBRANCH="branch:linux-6.12.35"
declare -g KERNEL_MAJOR_MINOR="6.12"
KERNELPATCHDIR="${LINUXFAMILY}-${BRANCH}"
LINUXCONFIG="linux-${LINUXFAMILY}-${BRANCH}"
;;
esac
#KERNELPATCHDIR="archive/filogic-${KERNEL_MAJOR_MINOR}"
write_uboot_platform() {
dd if="$SRC"/cache/sources/arm-trusted-firmware/mtksoc-20250212/build/mt7988/release/bl2.img of=$2 bs=512 seek=34 status=noxfer > /dev/null 2>&1
dd if="$SRC"/cache/u-boot_sdmmc.fip of=$2 bs=512 seek=13312 status=noxfer >/dev/null 2>&1
# backup gpt table
LAST_START=$(parted "$2" unit s print | grep -v "^$" | tail -n 1 | awk '{print $2}' | tr -d 's')
LAST_SIZE=$(parted "$2" unit s print | grep -v "^$" | tail -n 1 | awk '{print $4}' | tr -d 's')
# write mtk gpt table
dd if="${SRC}/packages/blobs/filogic/gpt" of="$2" conv=notrunc
# append armbian rootfs info
echo "${LAST_START},${LAST_SIZE}" | sfdisk --no-reread --append "$2"
}

BIN
packages/blobs/filogic/firmware/mediatek/mt7988/mt7988_wo_0.bin Normal file
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BIN
packages/blobs/filogic/firmware/mediatek/mt7988/mt7988_wo_1.bin Normal file
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packages/blobs/filogic/gpt Normal file
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4024
patch/u-boot/u-boot-filogic/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch Normal file
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175
patch/u-boot/u-boot-filogic/100-03-mtd-mtk-snand-add-support-for-SPL.patch Normal file
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@@ -0,0 +1,175 @@
From a347e374cb338213632c6dde88dd226d64bd8b27 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Mar 2021 08:57:29 +0800
Subject: [PATCH 37/71] mtd: mtk-snand: add support for SPL
Add support to initialize SPI-NAND in SPL.
Add implementation for SPL NAND loader.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/mtk-snand/Kconfig | 6 ++
drivers/mtd/mtk-snand/Makefile | 4 +
drivers/mtd/mtk-snand/mtk-snand-spl.c | 133 ++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-spl.c
--- a/drivers/mtd/mtk-snand/Kconfig
+++ b/drivers/mtd/mtk-snand/Kconfig
@@ -19,3 +19,9 @@ config MTK_SPI_NAND_MTD
help
This option enables access to SPI-NAND flashes through the
MTD interface of MediaTek SPI NAND Flash Controller
+
+config SPL_MTK_SPI_NAND
+ tristate "SPL support for MediaTek SPI NAND flash controller"
+ depends on MTK_SPI_NAND
+ help
+ This option enables access to SPI-NAND flashes in the SPL stage
--- a/drivers/mtd/mtk-snand/Makefile
+++ b/drivers/mtd/mtk-snand/Makefile
@@ -8,4 +8,8 @@
obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_MTK_SPI_NAND) += mtk-snand-spl.o
+endif
+
ccflags-y += -DPRIVATE_MTK_SNAND_HEADER
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <mtd.h>
+#include <watchdog.h>
+
+#include "mtk-snand.h"
+
+static struct mtk_snand *snf;
+static struct mtk_snand_chip_info cinfo;
+static u32 oobavail;
+
+static u8 *page_cache;
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ u32 sizeremain = size, chunksize, leading;
+ uint32_t off = offs, writesize_mask = cinfo.pagesize - 1;
+ uint8_t *ptr = dst;
+ int ret;
+
+ if (!snf)
+ return -ENODEV;
+
+ while (sizeremain) {
+ schedule();
+
+ leading = off & writesize_mask;
+ chunksize = cinfo.pagesize - leading;
+ if (chunksize > sizeremain)
+ chunksize = sizeremain;
+
+ if (chunksize == cinfo.pagesize) {
+ ret = mtk_snand_read_page(snf, off - leading, ptr,
+ NULL, false);
+ if (ret)
+ break;
+ } else {
+ ret = mtk_snand_read_page(snf, off - leading,
+ page_cache, NULL, false);
+ if (ret)
+ break;
+
+ memcpy(ptr, page_cache + leading, chunksize);
+ }
+
+ off += chunksize;
+ ptr += chunksize;
+ sizeremain -= chunksize;
+ }
+
+ return ret;
+}
+
+void nand_init(void)
+{
+ struct mtk_snand_platdata mtk_snand_pdata = {};
+ struct udevice *dev;
+ fdt_addr_t base;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(mtk_snand),
+ &dev);
+ if (ret) {
+ printf("mtk-snand-spl: Device instance not found!\n");
+ return;
+ }
+
+ base = dev_read_addr_name(dev, "nfi");
+ if (base == FDT_ADDR_T_NONE) {
+ printf("mtk-snand-spl: NFI base not set\n");
+ return;
+ }
+ mtk_snand_pdata.nfi_base = map_sysmem(base, 0);
+
+ base = dev_read_addr_name(dev, "ecc");
+ if (base == FDT_ADDR_T_NONE) {
+ printf("mtk-snand-spl: ECC base not set\n");
+ return;
+ }
+ mtk_snand_pdata.ecc_base = map_sysmem(base, 0);
+
+ mtk_snand_pdata.soc = dev_get_driver_data(dev);
+ mtk_snand_pdata.quad_spi = dev_read_bool(dev, "quad-spi");
+
+ ret = mtk_snand_init(NULL, &mtk_snand_pdata, &snf);
+ if (ret) {
+ printf("mtk-snand-spl: failed to initialize SPI-NAND\n");
+ return;
+ }
+
+ mtk_snand_get_chip_info(snf, &cinfo);
+
+ oobavail = cinfo.num_sectors * (cinfo.fdm_size - 1);
+
+ printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
+ (u32)(cinfo.chipsize >> 20));
+
+ page_cache = malloc(cinfo.pagesize + cinfo.sparesize);
+ if (!page_cache) {
+ mtk_snand_cleanup(snf);
+ printf("mtk-snand-spl: failed to allocate page cache\n");
+ }
+}
+
+void nand_deselect(void)
+{
+
+}
+
+static const struct udevice_id mtk_snand_ids[] = {
+ { .compatible = "mediatek,mt7622-snand", .data = SNAND_SOC_MT7622 },
+ { .compatible = "mediatek,mt7629-snand", .data = SNAND_SOC_MT7629 },
+ { .compatible = "mediatek,mt7981-snand", .data = SNAND_SOC_MT7981 },
+ { .compatible = "mediatek,mt7986-snand", .data = SNAND_SOC_MT7986 },
+ { /* sentinel */ },
+};
+
+U_BOOT_DRIVER(mtk_snand) = {
+ .name = "mtk-snand",
+ .id = UCLASS_MTD,
+ .of_match = mtk_snand_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};

390
patch/u-boot/u-boot-filogic/100-04-env-add-support-for-generic-MTD-device.patch Normal file
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@@ -0,0 +1,390 @@
From efc3e6f5d29f87a433b42f15a0b87e04b7cd498d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 3 Mar 2021 10:11:32 +0800
Subject: [PATCH 38/71] env: add support for generic MTD device
Add an env driver for generic MTD device.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/nvedit.c | 3 +-
env/Kconfig | 37 +++++-
env/Makefile | 1 +
env/env.c | 3 +
env/mtd.c | 256 +++++++++++++++++++++++++++++++++++++++++
include/env_internal.h | 1 +
tools/Makefile | 1 +
7 files changed, 299 insertions(+), 3 deletions(-)
create mode 100644 env/mtd.c
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
- !ENV_IS_IN_UBI
+ !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -267,6 +267,27 @@ config ENV_IS_IN_MMC
offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
+config ENV_IS_IN_MTD
+ bool "Environment in a MTD device"
+ depends on !CHAIN_OF_TRUST
+ depends on MTD
+ help
+ Define this if you have a MTD device which you want to use for
+ the environment.
+
+ - CONFIG_ENV_MTD_NAME:
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These three #defines specify the MTD device where the environment
+ is stored, offset and size of the environment area within the MTD
+ device. CONFIG_ENV_OFFSET must be aligned to an erase block boundary.
+
+ - CONFIG_ENV_SIZE_REDUND:
+
+ This #define specify the maximum size allowed for read/write/erase
+ with skipped bad blocks starting from ENV_OFFSET.
+
config ENV_IS_IN_NAND
bool "Environment in a NAND device"
depends on !CHAIN_OF_TRUST
@@ -574,10 +595,16 @@ config ENV_ADDR_REDUND
Offset from the start of the device (or partition) of the redundant
environment location.
+config ENV_MTD_NAME
+ string "Name of the MTD device storing the environment"
+ depends on ENV_IS_IN_MTD
+ help
+ Name of the MTD device that stores the environment
+
config ENV_OFFSET
hex "Environment offset"
depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
- ENV_IS_IN_SPI_FLASH
+ ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
default 0xF0000 if ARCH_SUNXI
@@ -635,6 +662,12 @@ config ENV_SECT_SIZE
help
Size of the sector containing the environment.
+config ENV_SIZE_REDUND
+ hex "Redundant environment size"
+ depends on ENV_IS_IN_MTD
+ help
+ The maximum size allowed for read/write/erase with skipped bad blocks.
+
config ENV_UBI_PART
string "UBI partition name"
depends on ENV_IS_IN_UBI
--- a/env/Makefile
+++ b/env/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_NOWHERE) +=
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) += mmc.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
--- a/env/env.c
+++ b/env/env.c
@@ -46,6 +46,9 @@ static enum env_location env_locations[]
#ifdef CONFIG_ENV_IS_IN_MMC
ENVL_MMC,
#endif
+#ifdef CONFIG_ENV_IS_IN_MTD
+ ENVL_MTD,
+#endif
#ifdef CONFIG_ENV_IS_IN_NAND
ENVL_NAND,
#endif
--- /dev/null
+++ b/env/mtd.c
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <command.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/mtd/mtd.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <mtd.h>
+#include <search.h>
+
+#if CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE
+#undef CONFIG_ENV_SIZE_REDUND
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#endif
+
+#if defined(ENV_IS_EMBEDDED)
+env_t *env_ptr = &environment;
+#else /* ! ENV_IS_EMBEDDED */
+env_t *env_ptr;
+#endif /* ENV_IS_EMBEDDED */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int env_mtd_init(void)
+{
+#if defined(ENV_IS_EMBEDDED)
+ int crc1_ok = 0, crc2_ok = 0;
+ env_t *tmp_env1;
+
+ tmp_env1 = env_ptr;
+ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
+
+ if (!crc1_ok && !crc2_ok) {
+ gd->env_addr = 0;
+ gd->env_valid = ENV_INVALID;
+
+ return 0;
+ } else if (crc1_ok && !crc2_ok) {
+ gd->env_valid = ENV_VALID;
+ }
+
+ if (gd->env_valid == ENV_VALID)
+ env_ptr = tmp_env1;
+
+ gd->env_addr = (ulong)env_ptr->data;
+
+#else /* ENV_IS_EMBEDDED */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = ENV_VALID;
+#endif /* ENV_IS_EMBEDDED */
+
+ return 0;
+}
+
+static struct mtd_info *env_mtd_get_dev(void)
+{
+ struct mtd_info *mtd;
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm(CONFIG_ENV_MTD_NAME);
+ if (IS_ERR(mtd) || !mtd) {
+ printf("MTD device '%s' not found\n", CONFIG_ENV_MTD_NAME);
+ return NULL;
+ }
+
+ return mtd;
+}
+
+static inline bool mtd_addr_is_block_aligned(struct mtd_info *mtd, u64 addr)
+{
+ return (addr & mtd->erasesize_mask) == 0;
+}
+
+static int mtd_io_skip_bad(struct mtd_info *mtd, bool read, loff_t offset,
+ size_t length, size_t redund, u8 *buffer)
+{
+ struct mtd_oob_ops io_op = {};
+ size_t remaining = length;
+ loff_t off, end;
+ int ret;
+
+ io_op.mode = MTD_OPS_PLACE_OOB;
+ io_op.len = mtd->writesize;
+ io_op.datbuf = (void *)buffer;
+
+ /* Search for the first good block after the given offset */
+ off = offset;
+ end = (off + redund) | (mtd->erasesize - 1);
+ while (mtd_block_isbad(mtd, off) && off < end)
+ off += mtd->erasesize;
+
+ /* Reached end position */
+ if (off >= end)
+ return -EIO;
+
+ /* Loop over the pages to do the actual read/write */
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (mtd_addr_is_block_aligned(mtd, off) &&
+ mtd_block_isbad(mtd, off)) {
+ off += mtd->erasesize;
+ continue;
+ }
+
+ if (read)
+ ret = mtd_read_oob(mtd, off, &io_op);
+ else
+ ret = mtd_write_oob(mtd, off, &io_op);
+
+ if (ret) {
+ printf("Failure while %s at offset 0x%llx\n",
+ read ? "reading" : "writing", off);
+ break;
+ }
+
+ off += io_op.retlen;
+ remaining -= io_op.retlen;
+ io_op.datbuf += io_op.retlen;
+ io_op.oobbuf += io_op.oobretlen;
+
+ /* Reached end position */
+ if (off >= end)
+ return -EIO;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+static int mtd_erase_skip_bad(struct mtd_info *mtd, loff_t offset,
+ size_t length, size_t redund)
+{
+ struct erase_info erase_op = {};
+ loff_t end = (offset + redund) | (mtd->erasesize - 1);
+ int ret;
+
+ erase_op.mtd = mtd;
+ erase_op.addr = offset;
+ erase_op.len = length;
+
+ while (erase_op.len) {
+ ret = mtd_erase(mtd, &erase_op);
+
+ /* Abort if its not a bad block error */
+ if (ret != -EIO)
+ return ret;
+
+ printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr);
+
+ /* Skip bad block and continue behind it */
+ erase_op.len -= erase_op.fail_addr - erase_op.addr;
+ erase_op.len -= mtd->erasesize;
+ erase_op.addr = erase_op.fail_addr + mtd->erasesize;
+
+ /* Reached end position */
+ if (erase_op.addr >= end)
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int env_mtd_save(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
+ struct mtd_info *mtd;
+ int ret = 0;
+
+ ret = env_export(env_new);
+ if (ret)
+ return ret;
+
+ mtd = env_mtd_get_dev();
+ if (!mtd)
+ return 1;
+
+ printf("Erasing on MTD device '%s'... ", mtd->name);
+
+ ret = mtd_erase_skip_bad(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ CONFIG_ENV_SIZE_REDUND);
+
+ puts(ret ? "FAILED\n" : "OK\n");
+
+ if (ret) {
+ put_mtd_device(mtd);
+ return 1;
+ }
+
+ printf("Writing to MTD device '%s'... ", mtd->name);
+
+ ret = mtd_io_skip_bad(mtd, false, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ CONFIG_ENV_SIZE_REDUND, (u8 *)env_new);
+
+ puts(ret ? "FAILED\n" : "OK\n");
+
+ put_mtd_device(mtd);
+
+ return !!ret;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+static int readenv(size_t offset, u_char *buf)
+{
+ struct mtd_info *mtd;
+ int ret;
+
+ mtd = env_mtd_get_dev();
+ if (!mtd)
+ return 1;
+
+ ret = mtd_io_skip_bad(mtd, true, offset, CONFIG_ENV_SIZE,
+ CONFIG_ENV_SIZE_REDUND, buf);
+
+ put_mtd_device(mtd);
+
+ return !!ret;
+}
+
+static int env_mtd_load(void)
+{
+#if !defined(ENV_IS_EMBEDDED)
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+ int ret;
+
+ ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);
+ if (ret) {
+ env_set_default("readenv() failed", 0);
+ return -EIO;
+ }
+
+ return env_import(buf, 1, H_EXTERNAL);
+#endif /* ! ENV_IS_EMBEDDED */
+
+ return 0;
+}
+
+U_BOOT_ENV_LOCATION(mtd) = {
+ .location = ENVL_MTD,
+ ENV_NAME("MTD")
+ .load = env_mtd_load,
+#if defined(CONFIG_CMD_SAVEENV)
+ .save = env_save_ptr(env_mtd_save),
+#endif
+ .init = env_mtd_init,
+};
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -108,6 +108,7 @@ enum env_location {
ENVL_FAT,
ENVL_FLASH,
ENVL_MMC,
+ ENVL_MTD,
ENVL_NAND,
ENVL_NVRAM,
ENVL_ONENAND,
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -37,6 +37,7 @@ subdir-$(HOST_TOOLS_ALL) += gdb
ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y
ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y
ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y
ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y

44
patch/u-boot/u-boot-filogic/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch Normal file
View File

@@ -0,0 +1,44 @@
From d26a789c451068caf4bbb4d1ac7bc1f592b5493e Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:58:06 +0800
Subject: [PATCH 39/71] mtd: add a new mtd device type for NMBM
This patch adds a new mtd device type for NMBM so that mtdparts can be
correctly probed. And this also gives us an opportunity to add NMBM support
for filesystems in the future.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/mtdparts.c | 3 +++
include/jffs2/load_kernel.h | 4 +++-
2 files changed, 6 insertions(+), 1 deletion(-)
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1054,6 +1054,9 @@ int mtd_id_parse(const char *id, const c
} else if (strncmp(p, "spi-nand", 8) == 0) {
*dev_type = MTD_DEV_TYPE_SPINAND;
p += 8;
+ } else if (strncmp(p, "nmbm", 4) == 0) {
+ *dev_type = MTD_DEV_TYPE_NMBM;
+ p += 4;
} else {
printf("incorrect device type in %s\n", id);
return 1;
--- a/include/jffs2/load_kernel.h
+++ b/include/jffs2/load_kernel.h
@@ -17,11 +17,13 @@
#define MTD_DEV_TYPE_NAND 0x0002
#define MTD_DEV_TYPE_ONENAND 0x0004
#define MTD_DEV_TYPE_SPINAND 0x0008
+#define MTD_DEV_TYPE_NMBM 0x0010
#define MTD_DEV_TYPE(type) (type == MTD_DEV_TYPE_NAND ? "nand" : \
(type == MTD_DEV_TYPE_NOR ? "nor" : \
(type == MTD_DEV_TYPE_ONENAND ? "onenand" : \
- "spi-nand"))) \
+ (type == MTD_DEV_TYPE_SPINAND ? "spi-nand" : \
+ "nmbm")))) \
struct mtd_device {
struct list_head link;

3533
patch/u-boot/u-boot-filogic/100-06-mtd-add-core-facility-code-of-NMBM.patch Normal file
View File

File diff suppressed because it is too large Load Diff

958
patch/u-boot/u-boot-filogic/100-07-mtd-nmbm-add-support-for-mtd.patch Normal file
View File

@@ -0,0 +1,958 @@
From 0524995f07fcd216a1a7e267fdb5cf2b0ede8489 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:42:12 +0800
Subject: [PATCH 41/71] mtd: nmbm: add support for mtd
Add support to create NMBM based on MTD devices
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nmbm/Kconfig | 5 +
drivers/mtd/nmbm/Makefile | 1 +
drivers/mtd/nmbm/nmbm-mtd.c | 890 ++++++++++++++++++++++++++++++++++++
include/nmbm/nmbm-mtd.h | 27 ++
4 files changed, 923 insertions(+)
create mode 100644 drivers/mtd/nmbm/nmbm-mtd.c
create mode 100644 include/nmbm/nmbm-mtd.h
--- a/drivers/mtd/nmbm/Kconfig
+++ b/drivers/mtd/nmbm/Kconfig
@@ -27,3 +27,8 @@ config NMBM_LOG_LEVEL_NONE
bool "5 - None"
endchoice
+
+config NMBM_MTD
+ bool "Enable MTD based NAND mapping block management"
+ default n
+ depends on NMBM
--- a/drivers/mtd/nmbm/Makefile
+++ b/drivers/mtd/nmbm/Makefile
@@ -3,3 +3,4 @@
# (C) Copyright 2020 MediaTek Inc. All rights reserved.
obj-$(CONFIG_NMBM) += nmbm-core.o
+obj-$(CONFIG_NMBM_MTD) += nmbm-mtd.o
--- /dev/null
+++ b/drivers/mtd/nmbm/nmbm-mtd.c
@@ -0,0 +1,890 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <linux/list.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mtd/mtd.h>
+#include <jffs2/load_kernel.h>
+#include <watchdog.h>
+
+#include "nmbm-debug.h"
+
+#define NMBM_UPPER_MTD_NAME "nmbm"
+
+static uint32_t nmbm_id_cnt;
+static LIST_HEAD(nmbm_devs);
+
+struct nmbm_mtd {
+ struct mtd_info upper;
+ char *name;
+ uint32_t id;
+
+ struct mtd_info *lower;
+
+ struct nmbm_instance *ni;
+ uint8_t *page_cache;
+
+ struct list_head node;
+};
+
+static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob,
+ enum nmbm_oob_mode mode)
+{
+ struct nmbm_mtd *nm = arg;
+ struct mtd_oob_ops ops;
+ int ret;
+
+ memset(&ops, 0, sizeof(ops));
+
+ switch (mode) {
+ case NMBM_MODE_PLACE_OOB:
+ ops.mode = MTD_OPS_PLACE_OOB;
+ break;
+ case NMBM_MODE_AUTO_OOB:
+ ops.mode = MTD_OPS_AUTO_OOB;
+ break;
+ case NMBM_MODE_RAW:
+ ops.mode = MTD_OPS_RAW;
+ break;
+ default:
+ pr_debug("%s: unsupported NMBM mode: %u\n", __func__, mode);
+ return -ENOTSUPP;
+ }
+
+ if (buf) {
+ ops.datbuf = buf;
+ ops.len = nm->lower->writesize;
+ }
+
+ if (oob) {
+ ops.oobbuf = oob;
+ ops.ooblen = mtd_oobavail(nm->lower, &ops);
+ }
+
+ ret = mtd_read_oob(nm->lower, addr, &ops);
+ nm->upper.ecc_stats.corrected = nm->lower->ecc_stats.corrected;
+ nm->upper.ecc_stats.failed = nm->lower->ecc_stats.failed;
+
+ /* Report error on failure (including ecc error) */
+ if (ret < 0 && ret != -EUCLEAN)
+ return ret;
+
+ /*
+ * Since mtd_read_oob() won't report exact bitflips, what we can know
+ * is whether bitflips exceeds the threshold.
+ * We want the -EUCLEAN to be passed to the upper layer, but not the
+ * error value itself. To achieve this, report bitflips above the
+ * threshold.
+ */
+
+ if (ret == -EUCLEAN) {
+ return min_t(u32, nm->lower->bitflip_threshold + 1,
+ nm->lower->ecc_strength);
+ }
+
+ /* For bitflips less than the threshold, return 0 */
+
+ return 0;
+}
+
+static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf,
+ const void *oob, enum nmbm_oob_mode mode)
+{
+ struct nmbm_mtd *nm = arg;
+ struct mtd_oob_ops ops;
+
+ memset(&ops, 0, sizeof(ops));
+
+ switch (mode) {
+ case NMBM_MODE_PLACE_OOB:
+ ops.mode = MTD_OPS_PLACE_OOB;
+ break;
+ case NMBM_MODE_AUTO_OOB:
+ ops.mode = MTD_OPS_AUTO_OOB;
+ break;
+ case NMBM_MODE_RAW:
+ ops.mode = MTD_OPS_RAW;
+ break;
+ default:
+ pr_debug("%s: unsupported NMBM mode: %u\n", __func__, mode);
+ return -ENOTSUPP;
+ }
+
+ if (buf) {
+ ops.datbuf = (uint8_t *)buf;
+ ops.len = nm->lower->writesize;
+ }
+
+ if (oob) {
+ ops.oobbuf = (uint8_t *)oob;
+ ops.ooblen = mtd_oobavail(nm->lower, &ops);
+ }
+
+ return mtd_write_oob(nm->lower, addr, &ops);
+}
+
+static int nmbm_lower_erase_block(void *arg, uint64_t addr)
+{
+ struct nmbm_mtd *nm = arg;
+ struct erase_info ei;
+
+ memset(&ei, 0, sizeof(ei));
+
+ ei.mtd = nm->lower;
+ ei.addr = addr;
+ ei.len = nm->lower->erasesize;
+
+ return mtd_erase(nm->lower, &ei);
+}
+
+static int nmbm_lower_is_bad_block(void *arg, uint64_t addr)
+{
+ struct nmbm_mtd *nm = arg;
+
+ return mtd_block_isbad(nm->lower, addr);
+}
+
+static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr)
+{
+ struct nmbm_mtd *nm = arg;
+
+ return mtd_block_markbad(nm->lower, addr);
+}
+
+static void nmbm_lower_log(void *arg, enum nmbm_log_category level,
+ const char *fmt, va_list ap)
+{
+ vprintf(fmt, ap);
+}
+
+static int nmbm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+
+ /* Do not allow read past end of device */
+ if ((from + len) > mtd->size) {
+ pr_debug("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return nmbm_read_range(nm->ni, from, len, buf, MTD_OPS_PLACE_OOB,
+ retlen);
+}
+
+static int nmbm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+
+ /* Do not allow write past end of device */
+ if ((to + len) > mtd->size) {
+ pr_debug("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return nmbm_write_range(nm->ni, to, len, buf, MTD_OPS_PLACE_OOB,
+ retlen);
+}
+
+static int nmbm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+ int ret;
+
+ instr->state = MTD_ERASING;
+
+ ret = nmbm_erase_block_range(nm->ni, instr->addr, instr->len,
+ &instr->fail_addr);
+ if (ret)
+ instr->state = MTD_ERASE_FAILED;
+ else
+ instr->state = MTD_ERASE_DONE;
+
+ if (!ret)
+ /* FIXME */
+ /* mtd_erase_callback(instr); */
+ return ret;
+ else
+ ret = -EIO;
+
+ return ret;
+}
+
+static int nmbm_mtd_read_data(struct nmbm_mtd *nm, uint64_t addr,
+ struct mtd_oob_ops *ops, enum nmbm_oob_mode mode)
+{
+ size_t len, ooblen, maxooblen, chklen;
+ uint32_t col, ooboffs;
+ uint8_t *datcache, *oobcache;
+ bool has_ecc_err = false;
+ int ret, max_bitflips = 0;
+
+ col = addr & nm->lower->writesize_mask;
+ addr &= ~nm->lower->writesize_mask;
+ maxooblen = mtd_oobavail(nm->lower, ops);
+ ooboffs = ops->ooboffs;
+ ooblen = ops->ooblen;
+ len = ops->len;
+
+ datcache = len ? nm->page_cache : NULL;
+ oobcache = ooblen ? nm->page_cache + nm->lower->writesize : NULL;
+
+ ops->oobretlen = 0;
+ ops->retlen = 0;
+
+ while (len || ooblen) {
+ schedule();
+
+ ret = nmbm_read_single_page(nm->ni, addr, datcache, oobcache,
+ mode);
+ if (ret < 0 && ret != -EBADMSG)
+ return ret;
+
+ /* Continue reading on ecc error */
+ if (ret == -EBADMSG)
+ has_ecc_err = true;
+
+ /* Record the maximum bitflips between pages */
+ if (ret > max_bitflips)
+ max_bitflips = ret;
+
+ if (len) {
+ /* Move data */
+ chklen = nm->lower->writesize - col;
+ if (chklen > len)
+ chklen = len;
+
+ memcpy(ops->datbuf + ops->retlen, datcache + col,
+ chklen);
+ len -= chklen;
+ col = 0; /* (col + chklen) % */
+ ops->retlen += chklen;
+ }
+
+ if (ooblen) {
+ /* Move oob */
+ chklen = maxooblen - ooboffs;
+ if (chklen > ooblen)
+ chklen = ooblen;
+
+ memcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs,
+ chklen);
+ ooblen -= chklen;
+ ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */
+ ops->oobretlen += chklen;
+ }
+
+ addr += nm->lower->writesize;
+ }
+
+ if (has_ecc_err)
+ return -EBADMSG;
+
+ return max_bitflips;
+}
+
+static int nmbm_mtd_read_oob(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+ uint32_t maxooblen;
+ enum nmbm_oob_mode mode;
+
+ if (!ops->oobbuf && !ops->datbuf) {
+ if (ops->ooblen || ops->len)
+ return -EINVAL;
+
+ return 0;
+ }
+
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ mode = NMBM_MODE_PLACE_OOB;
+ break;
+ case MTD_OPS_AUTO_OOB:
+ mode = NMBM_MODE_AUTO_OOB;
+ break;
+ case MTD_OPS_RAW:
+ mode = NMBM_MODE_RAW;
+ break;
+ default:
+ pr_debug("%s: unsupported oob mode: %u\n", __func__, ops->mode);
+ return -ENOTSUPP;
+ }
+
+ maxooblen = mtd_oobavail(mtd, ops);
+
+ /* Do not allow read past end of device */
+ if (ops->datbuf && (from + ops->len) > mtd->size) {
+ pr_debug("%s: attempt to read beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (!ops->oobbuf) {
+ /* Optimized for reading data only */
+ return nmbm_read_range(nm->ni, from, ops->len, ops->datbuf,
+ mode, &ops->retlen);
+ }
+
+ if (unlikely(ops->ooboffs >= maxooblen)) {
+ pr_debug("%s: attempt to start read outside oob\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (unlikely(from >= mtd->size ||
+ ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -
+ (from >> mtd->writesize_shift)) * maxooblen)) {
+ pr_debug("%s: attempt to read beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return nmbm_mtd_read_data(nm, from, ops, mode);
+}
+
+static int nmbm_mtd_write_data(struct nmbm_mtd *nm, uint64_t addr,
+ struct mtd_oob_ops *ops, enum nmbm_oob_mode mode)
+{
+ size_t len, ooblen, maxooblen, chklen;
+ uint32_t col, ooboffs;
+ uint8_t *datcache, *oobcache;
+ int ret;
+
+ col = addr & nm->lower->writesize_mask;
+ addr &= ~nm->lower->writesize_mask;
+ maxooblen = mtd_oobavail(nm->lower, ops);
+ ooboffs = ops->ooboffs;
+ ooblen = ops->ooblen;
+ len = ops->len;
+
+ datcache = len ? nm->page_cache : NULL;
+ oobcache = ooblen ? nm->page_cache + nm->lower->writesize : NULL;
+
+ ops->oobretlen = 0;
+ ops->retlen = 0;
+
+ while (len || ooblen) {
+ schedule();
+
+ if (len) {
+ /* Move data */
+ chklen = nm->lower->writesize - col;
+ if (chklen > len)
+ chklen = len;
+
+ memset(datcache, 0xff, col);
+ memcpy(datcache + col, ops->datbuf + ops->retlen,
+ chklen);
+ memset(datcache + col + chklen, 0xff,
+ nm->lower->writesize - col - chklen);
+ len -= chklen;
+ col = 0; /* (col + chklen) % */
+ ops->retlen += chklen;
+ }
+
+ if (ooblen) {
+ /* Move oob */
+ chklen = maxooblen - ooboffs;
+ if (chklen > ooblen)
+ chklen = ooblen;
+
+ memset(oobcache, 0xff, ooboffs);
+ memcpy(oobcache + ooboffs,
+ ops->oobbuf + ops->oobretlen, chklen);
+ memset(oobcache + ooboffs + chklen, 0xff,
+ nm->lower->oobsize - ooboffs - chklen);
+ ooblen -= chklen;
+ ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */
+ ops->oobretlen += chklen;
+ }
+
+ ret = nmbm_write_single_page(nm->ni, addr, datcache, oobcache,
+ mode);
+ if (ret)
+ return ret;
+
+ addr += nm->lower->writesize;
+ }
+
+ return 0;
+}
+
+static int nmbm_mtd_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+ enum nmbm_oob_mode mode;
+ uint32_t maxooblen;
+
+ if (!ops->oobbuf && !ops->datbuf) {
+ if (ops->ooblen || ops->len)
+ return -EINVAL;
+
+ return 0;
+ }
+
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ mode = NMBM_MODE_PLACE_OOB;
+ break;
+ case MTD_OPS_AUTO_OOB:
+ mode = NMBM_MODE_AUTO_OOB;
+ break;
+ case MTD_OPS_RAW:
+ mode = NMBM_MODE_RAW;
+ break;
+ default:
+ pr_debug("%s: unsupported oob mode: %u\n", __func__,
+ ops->mode);
+ return -ENOTSUPP;
+ }
+
+ maxooblen = mtd_oobavail(mtd, ops);
+
+ /* Do not allow write past end of device */
+ if (ops->datbuf && (to + ops->len) > mtd->size) {
+ pr_debug("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (!ops->oobbuf) {
+ /* Optimized for writing data only */
+ return nmbm_write_range(nm->ni, to, ops->len, ops->datbuf,
+ mode, &ops->retlen);
+ }
+
+ if (unlikely(ops->ooboffs >= maxooblen)) {
+ pr_debug("%s: attempt to start write outside oob\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (unlikely(to >= mtd->size ||
+ ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -
+ (to >> mtd->writesize_shift)) * maxooblen)) {
+ pr_debug("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return nmbm_mtd_write_data(nm, to, ops, mode);
+}
+
+static int nmbm_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+
+ return nmbm_check_bad_block(nm->ni, offs);
+}
+
+static int nmbm_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
+{
+ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper);
+
+ return nmbm_mark_bad_block(nm->ni, offs);
+}
+
+int nmbm_attach_mtd(struct mtd_info *lower, int flags, uint32_t max_ratio,
+ uint32_t max_reserved_blocks, struct mtd_info **upper)
+{
+ struct nmbm_lower_device nld;
+ struct nmbm_instance *ni;
+ struct mtd_info *mtd;
+ struct nmbm_mtd *nm;
+ size_t namelen, alloc_size;
+ int ret;
+
+ if (!lower)
+ return -EINVAL;
+
+ if (lower->type != MTD_NANDFLASH || lower->flags != MTD_CAP_NANDFLASH)
+ return -ENOTSUPP;
+
+ namelen = strlen(NMBM_UPPER_MTD_NAME) + 16;
+
+ nm = calloc(sizeof(*nm) + lower->writesize + lower->oobsize + namelen + 1, 1);
+ if (!nm)
+ return -ENOMEM;
+
+ nm->lower = lower;
+ nm->name = (char *)nm + sizeof(*nm);
+ nm->page_cache = (uint8_t *)nm->name + namelen + 1;
+
+ nm->id = nmbm_id_cnt++;
+ snprintf(nm->name, namelen + 1, "%s%u", NMBM_UPPER_MTD_NAME, nm->id);
+
+ memset(&nld, 0, sizeof(nld));
+
+ nld.flags = flags;
+ nld.max_ratio = max_ratio;
+ nld.max_reserved_blocks = max_reserved_blocks;
+
+ nld.size = lower->size;
+ nld.erasesize = lower->erasesize;
+ nld.writesize = lower->writesize;
+ nld.oobsize = lower->oobsize;
+ nld.oobavail = lower->oobavail;
+
+ nld.arg = nm;
+ nld.read_page = nmbm_lower_read_page;
+ nld.write_page = nmbm_lower_write_page;
+ nld.erase_block = nmbm_lower_erase_block;
+ nld.is_bad_block = nmbm_lower_is_bad_block;
+ nld.mark_bad_block = nmbm_lower_mark_bad_block;
+
+ nld.logprint = nmbm_lower_log;
+
+ alloc_size = nmbm_calc_structure_size(&nld);
+ ni = calloc(alloc_size, 1);
+ if (!ni) {
+ free(nm);
+ return -ENOMEM;
+ }
+
+ ret = nmbm_attach(&nld, ni);
+ if (ret) {
+ free(ni);
+ free(nm);
+ return ret;
+ }
+
+ nm->ni = ni;
+
+ /* Initialize upper mtd */
+ mtd = &nm->upper;
+
+ mtd->name = nm->name;
+ mtd->type = MTD_DEV_TYPE_NMBM;
+ mtd->flags = lower->flags;
+
+ mtd->size = (uint64_t)ni->data_block_count * ni->lower.erasesize;
+ mtd->erasesize = lower->erasesize;
+ mtd->writesize = lower->writesize;
+ mtd->writebufsize = lower->writesize;
+ mtd->oobsize = lower->oobsize;
+ mtd->oobavail = lower->oobavail;
+
+ mtd->erasesize_shift = lower->erasesize_shift;
+ mtd->writesize_shift = lower->writesize_shift;
+ mtd->erasesize_mask = lower->erasesize_mask;
+ mtd->writesize_mask = lower->writesize_mask;
+
+ mtd->bitflip_threshold = lower->bitflip_threshold;
+
+ /* XXX: should this be duplicated? */
+ mtd->ooblayout = lower->ooblayout;
+ mtd->ecclayout = lower->ecclayout;
+
+ mtd->ecc_step_size = lower->ecc_step_size;
+ mtd->ecc_strength = lower->ecc_strength;
+
+ mtd->numeraseregions = lower->numeraseregions;
+ mtd->eraseregions = lower->eraseregions;
+
+ mtd->_read = nmbm_mtd_read;
+ mtd->_write = nmbm_mtd_write;
+ mtd->_erase = nmbm_mtd_erase;
+ mtd->_read_oob = nmbm_mtd_read_oob;
+ mtd->_write_oob = nmbm_mtd_write_oob;
+ mtd->_block_isbad = nmbm_mtd_block_isbad;
+ mtd->_block_markbad = nmbm_mtd_block_markbad;
+
+ *upper = mtd;
+
+ list_add_tail(&nm->node, &nmbm_devs);
+
+ return 0;
+}
+
+int nmbm_free_mtd(struct mtd_info *upper)
+{
+ struct nmbm_mtd *pos;
+
+ if (!upper)
+ return -EINVAL;
+
+ list_for_each_entry(pos, &nmbm_devs, node) {
+ if (&pos->upper == upper) {
+ list_del(&pos->node);
+
+ nmbm_detach(pos->ni);
+ free(pos->ni);
+ free(pos);
+
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+struct mtd_info *nmbm_mtd_get_upper_by_index(uint32_t index)
+{
+ struct nmbm_mtd *nm;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (nm->id == index)
+ return &nm->upper;
+ }
+
+ return NULL;
+}
+
+struct mtd_info *nmbm_mtd_get_upper(struct mtd_info *lower)
+{
+ struct nmbm_mtd *nm;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (nm->lower == lower)
+ return &nm->upper;
+ }
+
+ return NULL;
+}
+
+void nmbm_mtd_list_devices(void)
+{
+ struct nmbm_mtd *nm;
+
+ printf("Index NMBM device Lower device\n");
+ printf("========================================\n");
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ printf("%-8u%-20s%s\n", nm->id, nm->name, nm->lower->name);
+ }
+}
+
+int nmbm_mtd_print_info(const char *name)
+{
+ struct nmbm_mtd *nm;
+ bool found = false;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (!strcmp(nm->name, name)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ printf("Error: NMBM device '%s' not found\n", name);
+ return -ENODEV;
+ }
+
+ printf("%s:\n", name);
+ printf("Total blocks: %u\n", nm->ni->block_count);
+ printf("Data blocks: %u\n", nm->ni->data_block_count);
+ printf("Management start block: %u\n", nm->ni->mgmt_start_ba);
+ printf("Info table size: 0x%x\n", nm->ni->info_table_size);
+
+ if (nm->ni->main_table_ba)
+ printf("Main info table start block: %u\n", nm->ni->main_table_ba);
+ else
+ printf("Main info table start block: Not exist\n");
+
+ if (nm->ni->backup_table_ba)
+ printf("Backup info table start block: %u\n", nm->ni->backup_table_ba);
+ else
+ printf("Backup info table start block: Not exist\n");
+
+ printf("Signature block: %u\n", nm->ni->signature_ba);
+ printf("Mapping blocks top address: %u\n", nm->ni->mapping_blocks_top_ba);
+ printf("Mapping blocks limit address: %u\n", nm->ni->mapping_blocks_ba);
+
+ return 0;
+}
+
+static const char nmbm_block_legends[] = {
+ [NMBM_BLOCK_GOOD_DATA] = '-',
+ [NMBM_BLOCK_GOOD_MGMT] = '+',
+ [NMBM_BLOCK_BAD] = 'B',
+ [NMBM_BLOCK_MAIN_INFO_TABLE] = 'I',
+ [NMBM_BLOCK_BACKUP_INFO_TABLE] = 'i',
+ [NMBM_BLOCK_REMAPPED] = 'M',
+ [NMBM_BLOCK_SIGNATURE] = 'S',
+};
+
+int nmbm_mtd_print_states(const char *name)
+{
+ struct nmbm_mtd *nm;
+ enum nmmb_block_type bt;
+ bool found = false;
+ uint32_t i;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (!strcmp(nm->name, name)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ printf("Error: NMBM device '%s' not found\n", name);
+ return -ENODEV;
+ }
+
+ printf("Physical blocks:\n");
+ printf("\n");
+
+ printf("Legends:\n");
+ printf(" - Good data block\n");
+ printf(" + Good management block\n");
+ printf(" B Bad block\n");
+ printf(" I Main info table\n");
+ printf(" i Backup info table\n");
+ printf(" M Remapped spare block\n");
+ printf(" S Signature block\n");
+ printf("\n");
+
+ for (i = 0; i < nm->ni->block_count; i++) {
+ if (i % 64 == 0)
+ printf(" ");
+
+ bt = nmbm_debug_get_phys_block_type(nm->ni, i);
+ if (bt < __NMBM_BLOCK_TYPE_MAX)
+ putc(nmbm_block_legends[bt]);
+ else
+ putc('?');
+
+ if (i % 64 == 63)
+ printf("\n");
+ }
+
+ printf("\n");
+ printf("Logical blocks:\n");
+ printf("\n");
+
+ printf("Legends:\n");
+ printf(" - Good block\n");
+ printf(" + Initially remapped block\n");
+ printf(" M Remapped block\n");
+ printf(" B Bad/Unmapped block\n");
+ printf("\n");
+
+ for (i = 0; i < nm->ni->data_block_count; i++) {
+ if (i % 64 == 0)
+ printf(" ");
+
+ if (nm->ni->block_mapping[i] < 0)
+ putc('B');
+ else if (nm->ni->block_mapping[i] == i)
+ putc('-');
+ else if (nm->ni->block_mapping[i] < nm->ni->data_block_count)
+ putc('+');
+ else if (nm->ni->block_mapping[i] > nm->ni->mapping_blocks_top_ba &&
+ nm->ni->block_mapping[i] < nm->ni->signature_ba)
+ putc('M');
+ else
+ putc('?');
+
+ if (i % 64 == 63)
+ printf("\n");
+ }
+
+ return 0;
+}
+
+int nmbm_mtd_print_bad_blocks(const char *name)
+{
+ struct nmbm_mtd *nm;
+ bool found = false;
+ uint32_t i;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (!strcmp(nm->name, name)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ printf("Error: NMBM device '%s' not found\n", name);
+ return -ENODEV;
+ }
+
+ printf("Physical blocks:\n");
+
+ for (i = 0; i < nm->ni->block_count; i++) {
+ switch (nmbm_debug_get_block_state(nm->ni, i)) {
+ case BLOCK_ST_BAD:
+ printf("%-12u [0x%08llx] - Bad\n", i,
+ (uint64_t)i << nm->ni->erasesize_shift);
+ break;
+ case BLOCK_ST_NEED_REMAP:
+ printf("%-12u [0x%08llx] - Awaiting remapping\n", i,
+ (uint64_t)i << nm->ni->erasesize_shift);
+ break;
+ }
+ }
+
+ printf("\n");
+ printf("Logical blocks:\n");
+
+ for (i = 0; i < nm->ni->data_block_count; i++) {
+ if (nm->ni->block_mapping[i] < 0) {
+ printf("%-12u [0x%08llx] - Bad\n", i,
+ (uint64_t)i << nm->ni->erasesize_shift);
+ }
+ }
+
+ return 0;
+}
+
+int nmbm_mtd_print_mappings(const char *name, int printall)
+{
+ struct nmbm_mtd *nm;
+ bool found = false;
+ int32_t pb;
+ uint32_t i;
+
+ list_for_each_entry(nm, &nmbm_devs, node) {
+ if (!strcmp(nm->name, name)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ printf("Error: NMBM device '%s' not found\n", name);
+ return -ENODEV;
+ }
+
+ printf("Logical Block Physical Block\n");
+ printf("==================================\n");
+
+ if (!printall) {
+ for (i = 0; i < nm->ni->data_block_count; i++) {
+ pb = nm->ni->block_mapping[i];
+ if (pb < 0)
+ printf("%-20uUnmapped\n", i);
+ else if ((uint32_t)pb > nm->ni->mapping_blocks_top_ba &&
+ (uint32_t)pb < nm->ni->signature_ba)
+ printf("%-20u%u\n", i, pb);
+ }
+
+ return 0;
+ }
+
+ for (i = 0; i < nm->ni->data_block_count; i++) {
+ pb = nm->ni->block_mapping[i];
+
+ if (pb >= 0)
+ printf("%-20u%u\n", i, pb);
+ else
+ printf("%-20uUnmapped\n", i);
+ }
+
+ return 0;
+}
--- a/include/nmbm/nmbm-mtd.h
+++ b/include/nmbm/nmbm-mtd.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _NMBM_MTD_H_
+#define _NMBM_MTD_H_
+
+#include <linux/mtd/mtd.h>
+
+int nmbm_attach_mtd(struct mtd_info *lower, int flags, uint32_t max_ratio,
+ uint32_t max_reserved_blocks, struct mtd_info **upper);
+
+int nmbm_free_mtd(struct mtd_info *upper);
+
+struct mtd_info *nmbm_mtd_get_upper_by_index(uint32_t index);
+struct mtd_info *nmbm_mtd_get_upper(struct mtd_info *lower);
+
+void nmbm_mtd_list_devices(void);
+int nmbm_mtd_print_info(const char *name);
+int nmbm_mtd_print_states(const char *name);
+int nmbm_mtd_print_bad_blocks(const char *name);
+int nmbm_mtd_print_mappings(const char *name, int printall);
+
+#endif /* _NMBM_MTD_H_ */

46
patch/u-boot/u-boot-filogic/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch Normal file
View File

@@ -0,0 +1,46 @@
From dcf24c8deeb43a4406ae18136c8700dc2f867415 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:18:03 +0800
Subject: [PATCH 42/71] common: board_r: add support to initialize NMBM after
nand initialization
This patch add support to initialize NMBM after nand initialized.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/board_r.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -378,6 +378,20 @@ static int initr_nand(void)
}
#endif
+#ifdef CONFIG_NMBM_MTD
+
+__weak int board_nmbm_init(void)
+{
+ return 0;
+}
+
+/* go init the NMBM */
+static int initr_nmbm(void)
+{
+ return board_nmbm_init();
+}
+#endif
+
#if defined(CONFIG_CMD_ONENAND)
/* go init the NAND */
static int initr_onenand(void)
@@ -693,6 +707,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_CMD_ONENAND
initr_onenand,
#endif
+#ifdef CONFIG_NMBM_MTD
+ initr_nmbm,
+#endif
#ifdef CONFIG_MMC
initr_mmc,
#endif

370
patch/u-boot/u-boot-filogic/100-09-cmd-add-nmbm-command.patch Normal file
View File

@@ -0,0 +1,370 @@
From 0af8d0aac77f4df4bc7dadbcdea5d9a16f5f3e45 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:44:57 +0800
Subject: [PATCH 43/71] cmd: add nmbm command
Add nmbm command for debugging, data operations and image-booting support
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/Kconfig | 6 +
cmd/Makefile | 1 +
cmd/nmbm.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 334 insertions(+)
create mode 100644 cmd/nmbm.c
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1525,6 +1525,12 @@ config CMD_NAND_WATCH
endif # CMD_NAND
+config CMD_NMBM
+ depends on NMBM_MTD
+ bool "nmbm"
+ help
+ NAND mapping block management (NMBM) utility
+
config CMD_NVME
bool "nvme"
depends on NVME
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o
endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_CMD_NMBM) += nmbm.o
ifdef CONFIG_NET
obj-$(CONFIG_CMD_NET) += net.o net-common.o
else ifdef CONFIG_NET_LWIP
--- /dev/null
+++ b/cmd/nmbm.c
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <command.h>
+#include <image.h>
+#include <stdbool.h>
+#include <linux/types.h>
+#include <linux/mtd/mtd.h>
+#include <jffs2/load_kernel.h>
+
+#include <nmbm/nmbm-mtd.h>
+
+static int nmbm_parse_offset_size(struct mtd_info *mtd, char *off_str,
+ char *size_str, uint64_t *off,
+ uint64_t *size)
+{
+ char *end;
+
+ *off = simple_strtoull(off_str, &end, 16);
+ if (end == off_str) {
+ printf("Error: offset '%s' is invalid\n", off_str);
+ return -EINVAL;
+ }
+
+ if (*off >= mtd->size) {
+ printf("Error: offset '0x%llx' is beyond the end of device\n",
+ *off);
+ return -EINVAL;
+ }
+
+ *size = simple_strtoull(size_str, &end, 16);
+ if (end == off_str) {
+ printf("Error: size '%s' is invalid\n", off_str);
+ return -EINVAL;
+ }
+
+ if (*off + *size > mtd->size) {
+ printf("Error: size '0x%llx' is too large\n", *size);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int do_nmbm_erase(struct mtd_info *mtd, uint64_t offset, uint64_t size)
+{
+ struct erase_info ei;
+ int ret;
+
+ memset(&ei, 0, sizeof(ei));
+
+ ei.mtd = mtd;
+ ei.addr = offset;
+ ei.len = size;
+
+ printf("Erasing from 0x%llx, size 0x%llx ...\n", offset, size);
+
+ ret = mtd_erase(mtd, &ei);
+
+ if (!ret) {
+ printf("Succeeded\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ printf("Failed at 0x%llx\n", ei.fail_addr);
+
+ return CMD_RET_FAILURE;
+}
+
+static int do_nmbm_rw(int read, struct mtd_info *mtd, uintptr_t addr,
+ uint64_t offset, size_t size)
+{
+ size_t retlen;
+ int ret;
+
+ printf("%s 0x%llx, size 0x%zx\n", read ? "Reading from" : "Writing to",
+ offset, size);
+
+ if (read)
+ ret = mtd_read(mtd, offset, size, &retlen, (void *)addr);
+ else
+ ret = mtd_write(mtd, offset, size, &retlen, (void *)addr);
+
+ if (!ret) {
+ printf("Succeeded\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ printf("Failed at 0x%llx\n", offset + retlen);
+
+ return CMD_RET_FAILURE;
+}
+
+static int do_nmbm_mtd_boot(struct cmd_tbl *cmdtp, struct mtd_info *mtd,
+ int argc, char *const argv[])
+{
+ bool print_image_contents = true;
+ uintptr_t loadaddr = image_load_addr;
+ char *end, *image_name;
+ const char *ep;
+ size_t retlen;
+ uint32_t size;
+ uint64_t off;
+ int ret;
+
+#if defined(CONFIG_CMD_MTDPARTS)
+ struct mtd_device *partdev;
+ struct mtd_info *partmtd;
+ struct part_info *part;
+ u8 pnum;
+#endif
+
+ ep = env_get("autostart");
+
+ if (ep && !strcmp(ep, "yes"))
+ print_image_contents = false;
+
+ if (argc == 2) {
+ loadaddr = simple_strtoul(argv[0], &end, 0);
+ if (*end || end == argv[0]) {
+ printf("'%s' is not a valid address\n", argv[0]);
+ return CMD_RET_FAILURE;
+ }
+
+ argc--;
+ argv++;
+ }
+
+ off = simple_strtoull(argv[0], &end, 0);
+ if (*end || end == argv[0]) {
+#if defined(CONFIG_CMD_MTDPARTS)
+ ret = mtdparts_init();
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ ret = find_dev_and_part(argv[0], &partdev, &pnum, &part);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (partdev->id->type != MTD_DEV_TYPE_NMBM) {
+ printf("'%s' is not a NMBM device partition\n",
+ argv[0]);
+ return CMD_RET_FAILURE;
+ }
+
+ partmtd = nmbm_mtd_get_upper_by_index(partdev->id->num);
+
+ if (partmtd != mtd) {
+ printf("'%s' does not belong to this device\n",
+ argv[0]);
+ return CMD_RET_FAILURE;
+ }
+
+ off = part->offset;
+#else
+ printf("'%s' is not a valid offset\n", argv[0]);
+ return CMD_RET_FAILURE;
+#endif
+ }
+
+ ret = mtd_read(mtd, off, sizeof(struct legacy_img_hdr), &retlen,
+ (void *)loadaddr);
+ if (ret || retlen != sizeof(struct legacy_img_hdr)) {
+ printf("Failed to read NMBM at offset 0x%08llx\n", off);
+ return CMD_RET_FAILURE;
+ }
+
+ switch (genimg_get_format((void *)loadaddr)) {
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
+ case IMAGE_FORMAT_LEGACY:
+ size = image_get_image_size((struct legacy_img_hdr *)loadaddr);
+ image_name = "legacy";
+ break;
+#endif
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ size = fit_get_size((const void *)loadaddr);
+ image_name = "FIT";
+ break;
+#endif
+ default:
+ printf("Error: no Image found at offset 0x%08llx\n", off);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Loading %s image at offset 0x%llx to memory 0x%08lx, size 0x%x ...\n",
+ image_name, off, loadaddr, size);
+
+ ret = mtd_read(mtd, off, size, &retlen, (void *)loadaddr);
+ if (ret || retlen != size) {
+ printf("Error: Failed to load image at offset 0x%08llx\n",
+ off + retlen);
+ return CMD_RET_FAILURE;
+ }
+
+ switch (genimg_get_format((void *)loadaddr)) {
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
+ case IMAGE_FORMAT_LEGACY:
+ if (print_image_contents)
+ image_print_contents((void *)loadaddr);
+ break;
+#endif
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ if (print_image_contents)
+ fit_print_contents((void *)loadaddr);
+ break;
+#endif
+ }
+
+ image_load_addr = loadaddr;
+
+ return bootm_maybe_autostart(cmdtp, "nmbm");
+}
+
+static int do_nmbm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ uint64_t offset, size;
+ char *end;
+ uintptr_t addr;
+ int ret, all = 0;
+
+ if (argc == 1)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[1], "list")) {
+ nmbm_mtd_list_devices();
+ return CMD_RET_SUCCESS;
+ }
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[2], "info"))
+ return !!nmbm_mtd_print_info(argv[1]);
+
+ if (!strcmp(argv[2], "state"))
+ return !!nmbm_mtd_print_states(argv[1]);
+
+ if (!strcmp(argv[2], "bad"))
+ return !!nmbm_mtd_print_bad_blocks(argv[1]);
+
+ if (!strcmp(argv[2], "mapping")) {
+ if (argc >= 4) {
+ if (!strcmp(argv[3], "all"))
+ all = 1;
+ }
+
+ return nmbm_mtd_print_mappings(argv[1], all);
+ }
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_device_nm(argv[1]);
+ if (IS_ERR(mtd)) {
+ printf("Error: NMBM device '%s' not found\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ if (mtd->type != MTD_DEV_TYPE_NMBM) {
+ printf("Error: '%s' is not a NMBM device\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ if (!strcmp(argv[2], "boot"))
+ return do_nmbm_mtd_boot(cmdtp, mtd, argc - 3, argv + 3);
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[2], "erase")) {
+ ret = nmbm_parse_offset_size(mtd, argv[3], argv[4], &offset,
+ &size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return do_nmbm_erase(mtd, offset, size);
+ }
+
+ if (argc < 6)
+ return CMD_RET_USAGE;
+
+ ret = nmbm_parse_offset_size(mtd, argv[4], argv[5], &offset, &size);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (size > SIZE_MAX) {
+ printf("Error: size 0x%llx is too large\n", size);
+ return -EINVAL;
+ }
+
+ addr = simple_strtoul(argv[3], &end, 16);
+ if (end == argv[3]) {
+ printf("Error: addr '%s' is invalid\n", argv[3]);
+ return -EINVAL;
+ }
+
+ if (!strcmp(argv[2], "read"))
+ return do_nmbm_rw(1, mtd, addr, offset, (size_t)size);
+
+ if (!strcmp(argv[2], "write"))
+ return do_nmbm_rw(0, mtd, addr, offset, (size_t)size);
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ nmbm, CONFIG_SYS_MAXARGS, 0, do_nmbm,
+ "NMBM utility commands",
+ "\n"
+ "nmbm list - List NMBM devices\n"
+ "nmbm <name> info - Display NMBM information\n"
+ "nmbm <name> state - Display block states\n"
+ "nmbm <name> bad - Display bad blocks\n"
+ "nmbm <name> boot <part | [loadaddr] offset> - Boot from NMBM\n"
+ "nmbm <name> mapping [all] - Display block mapping\n"
+ "nmbm <name> erase <offset> <size> - Erase blocks\n"
+ "nmbm <name> read <addr> <offset> <size> - Read data\n"
+ "nmbm <name> write <addr> <offset> <size> - Write data\n"
+);

80
patch/u-boot/u-boot-filogic/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch Normal file
View File

@@ -0,0 +1,80 @@
From 6dbbc8affb6ab22f940d13d0e928d5e881127ca4 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:22:57 +0800
Subject: [PATCH 44/71] cmd: mtd: add markbad subcommand for NMBM testing
This patch adds:
* Mark bad block on lower mtd device and erase on upper mtd
device, which will trigger remapping:
$ mtd markbad spi-nand0 0x20000 (mark block1 as bad)
$ mtd erase nmbm0 0x20000 0x20000 (let nmbm detect the bad block and remap it)
* Clear bad block mark through:
$ mtd erase.dontskipbad spi-nand0 0x20000 0x20000
(After cleaning bad block mark, we need to rebuild nmbm manage table.)
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
cmd/mtd.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -728,6 +728,42 @@ out_put_mtd:
return CMD_RET_SUCCESS;
}
+static int do_mtd_markbad(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct mtd_info *mtd;
+ loff_t off;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR(mtd) || !mtd)
+ return CMD_RET_FAILURE;
+
+ if (!mtd_can_have_bb(mtd)) {
+ printf("Only NAND-based devices can have mark blocks\n");
+ goto out_put_mtd;
+ }
+
+ off = simple_strtoull(argv[2], NULL, 0);
+
+ ret = mtd_block_markbad(mtd, off);
+ if (!ret) {
+ printf("MTD device %s block at 0x%08llx marked bad\n",
+ mtd->name, off);
+ } else {
+ printf("MTD device %s block at 0x%08llx mark bad failed\n",
+ mtd->name, off);
+ }
+
+out_put_mtd:
+ put_mtd_device(mtd);
+
+ return CMD_RET_SUCCESS;
+}
+
#ifdef CONFIG_AUTO_COMPLETE
static int mtd_name_complete(int argc, char *const argv[], char last_char,
int maxv, char *cmdv[])
@@ -775,6 +811,7 @@ U_BOOT_LONGHELP(mtd,
"\n"
"Specific functions:\n"
"mtd bad <name>\n"
+ "mtd markbad <name> <off>\n"
#if CONFIG_IS_ENABLED(CMD_MTD_OTP)
"mtd otpread <name> [u|f] <off> <size>\n"
"mtd otpwrite <name> <off> <hex string>\n"
@@ -815,4 +852,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
mtd_name_complete),
U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,
+ mtd_name_complete),
+ U_BOOT_SUBCMD_MKENT_COMPLETE(markbad, 3, 1, do_mtd_markbad,
mtd_name_complete));

260
patch/u-boot/u-boot-filogic/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch Normal file
View File

@@ -0,0 +1,260 @@
From 240d98e6ad0aed3c11236aa40a60bbd6fe01fae5 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:50:46 +0800
Subject: [PATCH 45/71] env: add support for NMBM upper MTD layer
Add an env driver for NMBM upper MTD layer
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
env/Kconfig | 19 ++++-
env/Makefile | 1 +
env/env.c | 3 +
env/nmbm.c | 155 +++++++++++++++++++++++++++++++++++++++++
include/env_internal.h | 1 +
tools/Makefile | 1 +
6 files changed, 178 insertions(+), 2 deletions(-)
create mode 100644 env/nmbm.c
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
- !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+ !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -318,6 +318,21 @@ config ENV_IS_IN_NAND
Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
using CONFIG_ENV_OFFSET_OOB.
+config ENV_IS_IN_NMBM
+ bool "Environment in a NMBM upper MTD layer"
+ depends on !CHAIN_OF_TRUST
+ depends on NMBM_MTD
+ help
+ Define this if you have a NMBM upper MTD which you want to use for
+ the environment.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the environment
+ area within the first NAND device. CONFIG_ENV_OFFSET must be
+ aligned to an erase block boundary.
+
config ENV_RANGE
hex "Length of the region in which the environment can be written"
depends on ENV_IS_IN_NAND
@@ -604,7 +619,7 @@ config ENV_MTD_NAME
config ENV_OFFSET
hex "Environment offset"
depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
- ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
+ ENV_IS_IN_SPI_FLASH || ENV_IS_IN_NMBM || ENV_IS_IN_MTD
default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
default 0xF0000 if ARCH_SUNXI
--- a/env/Makefile
+++ b/env/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) +=
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NMBM) += nmbm.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
--- a/env/env.c
+++ b/env/env.c
@@ -52,6 +52,9 @@ static enum env_location env_locations[]
#ifdef CONFIG_ENV_IS_IN_NAND
ENVL_NAND,
#endif
+#ifdef CONFIG_ENV_IS_IN_NMBM
+ ENVL_NMBM,
+#endif
#ifdef CONFIG_ENV_IS_IN_NVRAM
ENVL_NVRAM,
#endif
--- /dev/null
+++ b/env/nmbm.c
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <command.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <search.h>
+
+#include <nmbm/nmbm-mtd.h>
+
+#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_NMBM_MTD)
+#define CMD_SAVEENV
+#endif
+
+#if defined(ENV_IS_EMBEDDED)
+env_t *env_ptr = &environment;
+#else /* ! ENV_IS_EMBEDDED */
+env_t *env_ptr;
+#endif /* ENV_IS_EMBEDDED */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int env_nmbm_init(void)
+{
+#if defined(ENV_IS_EMBEDDED)
+ int crc1_ok = 0, crc2_ok = 0;
+ env_t *tmp_env1;
+
+ tmp_env1 = env_ptr;
+ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
+
+ if (!crc1_ok && !crc2_ok) {
+ gd->env_addr = 0;
+ gd->env_valid = ENV_INVALID;
+
+ return 0;
+ } else if (crc1_ok && !crc2_ok) {
+ gd->env_valid = ENV_VALID;
+ }
+
+ if (gd->env_valid == ENV_VALID)
+ env_ptr = tmp_env1;
+
+ gd->env_addr = (ulong)env_ptr->data;
+
+#else /* ENV_IS_EMBEDDED */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = ENV_VALID;
+#endif /* ENV_IS_EMBEDDED */
+
+ return 0;
+}
+
+#ifdef CMD_SAVEENV
+static int env_nmbm_save(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
+ struct mtd_info *mtd;
+ struct erase_info ei;
+ int ret = 0;
+
+ ret = env_export(env_new);
+ if (ret)
+ return ret;
+
+ mtd = nmbm_mtd_get_upper_by_index(0);
+ if (!mtd)
+ return 1;
+
+ printf("Erasing on NMBM...\n");
+ memset(&ei, 0, sizeof(ei));
+
+ ei.mtd = mtd;
+ ei.addr = CONFIG_ENV_OFFSET;
+ ei.len = CONFIG_ENV_SIZE;
+
+ if (mtd_erase(mtd, &ei))
+ return 1;
+
+ printf("Writing on NMBM... ");
+ ret = mtd_write(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, NULL,
+ (u_char *)env_new);
+ puts(ret ? "FAILED!\n" : "OK\n");
+
+ return !!ret;
+}
+#endif /* CMD_SAVEENV */
+
+static int readenv(size_t offset, u_char *buf)
+{
+ struct mtd_info *mtd;
+ struct mtd_oob_ops ops;
+ int ret;
+ size_t len = CONFIG_ENV_SIZE;
+
+ mtd = nmbm_mtd_get_upper_by_index(0);
+ if (!mtd)
+ return 1;
+
+ ops.mode = MTD_OPS_AUTO_OOB;
+ ops.ooblen = 0;
+ while(len > 0) {
+ ops.datbuf = buf;
+ ops.len = min(len, (size_t)mtd->writesize);
+ ops.oobbuf = NULL;
+
+ ret = mtd_read_oob(mtd, offset, &ops);
+ if (ret)
+ return 1;
+
+ buf += mtd->writesize;
+ len -= mtd->writesize;
+ offset += mtd->writesize;
+ }
+
+ return 0;
+}
+
+static int env_nmbm_load(void)
+{
+#if !defined(ENV_IS_EMBEDDED)
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+ int ret;
+
+ ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);
+ if (ret) {
+ env_set_default("readenv() failed", 0);
+ return -EIO;
+ }
+
+ return env_import(buf, 1, H_EXTERNAL);
+#endif /* ! ENV_IS_EMBEDDED */
+
+ return 0;
+}
+
+U_BOOT_ENV_LOCATION(nmbm) = {
+ .location = ENVL_NMBM,
+ ENV_NAME("NMBM")
+ .load = env_nmbm_load,
+#if defined(CMD_SAVEENV)
+ .save = env_save_ptr(env_nmbm_save),
+#endif
+ .init = env_nmbm_init,
+};
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -110,6 +110,7 @@ enum env_location {
ENVL_MMC,
ENVL_MTD,
ENVL_NAND,
+ ENVL_NMBM,
ENVL_NVRAM,
ENVL_ONENAND,
ENVL_REMOTE,
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -39,6 +39,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y
ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y
ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_NMBM) = y
ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
BUILD_ENVCRC ?= $(ENVCRC-y)

173
patch/u-boot/u-boot-filogic/100-12-mtd-mtk-snand-add-NMBM-support-for-SPL.patch Normal file
View File

@@ -0,0 +1,173 @@
From 9e8ac4fc7125795ac5e8834aaf454fd45b99c580 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 10:53:03 +0800
Subject: [PATCH 46/71] mtd: mtk-snand: add NMBM support for SPL
Add NMBM support for mtk-snand SPL loader
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/mtk-snand/mtk-snand-spl.c | 127 ++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
--- a/drivers/mtd/mtk-snand/mtk-snand-spl.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
@@ -13,12 +13,134 @@
#include <mtd.h>
#include <watchdog.h>
+#include <nmbm/nmbm.h>
+
#include "mtk-snand.h"
static struct mtk_snand *snf;
static struct mtk_snand_chip_info cinfo;
static u32 oobavail;
+#ifdef CONFIG_ENABLE_NAND_NMBM
+static struct nmbm_instance *ni;
+
+static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob,
+ enum nmbm_oob_mode mode)
+{
+ int ret;
+ bool raw = mode == NMBM_MODE_RAW ? true : false;
+
+ if (mode == NMBM_MODE_AUTO_OOB) {
+ ret = mtk_snand_read_page_auto_oob(snf, addr, buf, oob,
+ oobavail, NULL, false);
+ } else {
+ ret = mtk_snand_read_page(snf, addr, buf, oob, raw);
+ }
+
+ if (ret == -EBADMSG)
+ return 1;
+ else if (ret >= 0)
+ return 0;
+
+ return ret;
+}
+
+static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf,
+ const void *oob, enum nmbm_oob_mode mode)
+{
+ bool raw = mode == NMBM_MODE_RAW ? true : false;
+
+ if (mode == NMBM_MODE_AUTO_OOB) {
+ return mtk_snand_write_page_auto_oob(snf, addr, buf, oob,
+ oobavail, NULL, false);
+ }
+
+ return mtk_snand_write_page(snf, addr, buf, oob, raw);
+}
+
+static int nmbm_lower_erase_block(void *arg, uint64_t addr)
+{
+ return mtk_snand_erase_block(snf, addr);
+}
+
+static int nmbm_lower_is_bad_block(void *arg, uint64_t addr)
+{
+ return mtk_snand_block_isbad(snf, addr);
+}
+
+static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr)
+{
+ return mtk_snand_block_markbad(snf, addr);
+}
+
+static void nmbm_lower_log(void *arg, enum nmbm_log_category level,
+ const char *fmt, va_list ap)
+{
+ vprintf(fmt, ap);
+}
+
+static int nmbm_init(void)
+{
+ struct nmbm_lower_device nld;
+ size_t ni_size;
+ int ret;
+
+ memset(&nld, 0, sizeof(nld));
+
+ nld.flags = NMBM_F_CREATE;
+ nld.max_ratio = CONFIG_NMBM_MAX_RATIO;
+ nld.max_reserved_blocks = CONFIG_NMBM_MAX_BLOCKS;
+
+ nld.size = cinfo.chipsize;
+ nld.erasesize = cinfo.blocksize;
+ nld.writesize = cinfo.pagesize;
+ nld.oobsize = cinfo.sparesize;
+ nld.oobavail = oobavail;
+
+ nld.read_page = nmbm_lower_read_page;
+ nld.write_page = nmbm_lower_write_page;
+ nld.erase_block = nmbm_lower_erase_block;
+ nld.is_bad_block = nmbm_lower_is_bad_block;
+ nld.mark_bad_block = nmbm_lower_mark_bad_block;
+
+ nld.logprint = nmbm_lower_log;
+
+ ni_size = nmbm_calc_structure_size(&nld);
+ ni = malloc(ni_size);
+ if (!ni) {
+ printf("Failed to allocate memory (0x%u) for NMBM instance\n",
+ ni_size);
+ return -ENOMEM;
+ }
+
+ memset(ni, 0, ni_size);
+
+ printf("Initializing NMBM ...\n");
+
+ ret = nmbm_attach(&nld, ni);
+ if (ret) {
+ ni = NULL;
+ return ret;
+ }
+
+ return 0;
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ size_t retlen;
+
+ if (!ni)
+ return -ENODEV;
+
+ nmbm_read_range(ni, offs, size, dst, NMBM_MODE_PLACE_OOB, &retlen);
+ if (retlen != size)
+ return -EIO;
+
+ return 0;
+}
+
+#else
static u8 *page_cache;
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
@@ -60,6 +182,7 @@ int nand_spl_load_image(uint32_t offs, u
return ret;
}
+#endif
void nand_init(void)
{
@@ -105,11 +228,15 @@ void nand_init(void)
printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
(u32)(cinfo.chipsize >> 20));
+#ifdef CONFIG_ENABLE_NAND_NMBM
+ nmbm_init();
+#else
page_cache = malloc(cinfo.pagesize + cinfo.sparesize);
if (!page_cache) {
mtk_snand_cleanup(snf);
printf("mtk-snand-spl: failed to allocate page cache\n");
}
+#endif
}
void nand_deselect(void)

1118
patch/u-boot/u-boot-filogic/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch Normal file
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File diff suppressed because it is too large Load Diff

142
patch/u-boot/u-boot-filogic/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch Normal file
View File

@@ -0,0 +1,142 @@
From c4172a95df8a57a66c70a8b9948b9600a01c4cb7 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:32:08 +0800
Subject: [PATCH 49/71] mtd: spi-nor: add support to read flash unique ID
This patch adds support to read unique ID from spi-nor flashes.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/spi/spi-nor-core.c | 95 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 2 +
2 files changed, 97 insertions(+)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3248,6 +3248,100 @@ static int spi_nor_init_params(struct sp
return 0;
}
+static int spi_nor_read_uuid(struct spi_nor *nor)
+{
+ u8 read_opcode, addr_width, read_dummy;
+ loff_t addr;
+ u8 *uuid;
+ u8 uuid_len;
+ int shift = 0;
+ int ret;
+ int i;
+ struct spi_mem_op op;
+
+ read_opcode = nor->read_opcode;
+ addr_width = nor->addr_width;
+ read_dummy = nor->read_dummy;
+
+ switch (JEDEC_MFR(nor->info)) {
+ case SNOR_MFR_WINBOND:
+ uuid_len = 8;
+ nor->read_opcode = 0x4b;
+ nor->addr_width = 0;
+ addr = 0x0;
+ nor->read_dummy = 4;
+ break;
+ case SNOR_MFR_GIGADEVICE:
+ uuid_len = 16;
+ nor->read_opcode = 0x4b;
+ nor->addr_width = 3;
+ addr = 0x0;
+ nor->read_dummy = 1;
+ break;
+ case CFI_MFR_ST:
+ case SNOR_MFR_MICRON:
+ uuid_len = 17;
+ shift = 3;
+ nor->read_opcode = 0x9f;
+ nor->addr_width = 0;
+ addr = 0x0;
+ nor->read_dummy = 0;
+ break;
+ case SNOR_MFR_EON:
+ uuid_len = 12;
+ nor->read_opcode = 0x5a;
+ nor->addr_width = 3;
+ addr = 0x80;
+ nor->read_dummy = 1;
+ break;
+ /* Automotive only in SPANSION's NOR devices */
+ case SNOR_MFR_SPANSION:
+ uuid_len = 11;
+ shift = 386;
+ nor->read_opcode = 0x9f;
+ nor->addr_width = 0;
+ addr = 0x0;
+ nor->read_dummy = 0;
+ break;
+ default:
+ printf("UUID not supported on this device.\n");
+ return -ENOTSUPP;
+ }
+
+ uuid = kmalloc((uuid_len + shift) * sizeof(*uuid), GFP_KERNEL);
+ if (!uuid) {
+ ret = -ENOMEM;
+ goto read_err;
+ }
+ memset(uuid, 0x0, (uuid_len + shift) * sizeof(*uuid));
+
+ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
+ SPI_MEM_OP_DATA_IN(uuid_len+shift, NULL, 0));
+
+ spi_nor_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_nor_read_write_reg(nor, &op, uuid);
+ if (ret < 0) {
+ dev_dbg(nor->dev, "error %d reading %x\n", ret, nor->read_opcode);
+ goto read_err;
+ }
+
+ printf("UUID: 0x");
+ for(i = 0; i<uuid_len; i++)
+ printf("%02x", uuid[i+shift]);
+ puts("\n");
+
+read_err:
+ nor->read_opcode = read_opcode;
+ nor->addr_width = addr_width;
+ nor->read_dummy = read_dummy;
+ kfree(uuid);
+
+ return ret;
+}
+
static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
{
size_t i;
@@ -4450,6 +4544,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->write = spi_nor_write_data;
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
+ nor->read_uuid = spi_nor_read_uuid;
nor->setup = spi_nor_default_setup;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -32,6 +32,7 @@
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
+#define SNOR_MFR_EON CFI_MFR_EON
#define SNOR_MFR_CYPRESS 0x34
/*
@@ -590,6 +591,7 @@ struct spi_nor {
void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+ int (*read_uuid)(struct spi_nor *nor);
ssize_t (*read)(struct spi_nor *nor, loff_t from,
size_t len, u_char *read_buf);

49
patch/u-boot/u-boot-filogic/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch Normal file
View File

@@ -0,0 +1,49 @@
From e60939acbebd07161f3978d1c6f13123fdd2ebf2 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 11:27:02 +0800
Subject: [PATCH 50/71] cmd: sf: add support to read flash unique ID
This patch adds support to display unique ID from spi-nor flashes
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/sf.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -421,6 +421,14 @@ static int do_spi_protect(int argc, char
return ret == 0 ? 0 : 1;
}
+static int do_spi_flash_read_uuid(void)
+{
+ int ret = 0;
+ ret = flash->read_uuid(flash);
+
+ return ret == 0 ? 0 : 1;
+}
+
enum {
STAGE_ERASE,
STAGE_CHECK,
@@ -615,6 +623,8 @@ static int do_spi_flash(struct cmd_tbl *
ret = do_spi_flash_erase(argc, argv);
else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
+ else if (strcmp(cmd, "uuid") == 0)
+ ret = do_spi_flash_read_uuid();
else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
else
@@ -643,8 +653,9 @@ U_BOOT_LONGHELP(sf,
" at address 'sector'"
#endif
#ifdef CONFIG_CMD_SF_TEST
- "\nsf test offset len - run a very basic destructive test"
+ "\nsf test offset len - run a very basic destructive test"
#endif
+ "\nsf uuid - read uuid from flash"
);
U_BOOT_CMD(

28
patch/u-boot/u-boot-filogic/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch Normal file
View File

@@ -0,0 +1,28 @@
From 7ab891faaaf2b6126694352d4503dc40605a6aec Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 15:10:02 +0800
Subject: [PATCH 52/71] common: spl: spl_nand: enable
CONFIG_SYS_NAND_U_BOOT_OFFS undefined
Enable using spl_nand with CONFIG_SYS_NAND_U_BOOT_OFFS undefined since
mtk-snand does not require raw nand framework.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/spl/spl_nand.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -18,7 +18,11 @@
uint32_t __weak spl_nand_get_uboot_raw_page(void)
{
+#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS
return CONFIG_SYS_NAND_U_BOOT_OFFS;
+#else
+ return 0;
+#endif
}
#if defined(CONFIG_SPL_NAND_RAW_ONLY)

77
patch/u-boot/u-boot-filogic/100-21-mtd-spi-nor-add-more-flash-ids.patch Normal file
View File

@@ -0,0 +1,77 @@
From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:32:17 +0800
Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
Add more spi-nor flash ids
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/spi/spi-nor-core.c | 1 +
drivers/mtd/spi/spi-nor-ids.c | 23 ++++++++++++++++++++++-
2 files changed, 23 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor
case SNOR_MFR_ISSI:
case SNOR_MFR_MACRONIX:
case SNOR_MFR_WINBOND:
+ case SNOR_MFR_EON:
if (need_wren)
write_enable(nor);
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -83,7 +83,9 @@ const struct flash_info spi_nor_ids[] =
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
+ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("en25qx128", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
@@ -149,6 +151,11 @@ const struct flash_info spi_nor_ids[] =
{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
+ INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -520,6 +527,16 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
+ INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -583,6 +600,11 @@ const struct flash_info spi_nor_ids[] =
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ {
+ INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

550
patch/u-boot/u-boot-filogic/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch Normal file
View File

@@ -0,0 +1,550 @@
From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:36:13 +0800
Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
Backport new features from upstream kernel
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nand/spi/Kconfig | 1 +
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 102 ++++++----
drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++
drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++---
drivers/mtd/nand/spi/micron.c | 50 ++---
drivers/mtd/nand/spi/toshiba.c | 66 +++---
drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++---
include/linux/mtd/spinand.h | 87 +++++---
10 files changed, 923 insertions(+), 225 deletions(-)
create mode 100644 drivers/mtd/nand/spi/etron.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
};
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &etron_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/etron.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Etron Technology, Inc.
+ *
+ */
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bug.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ETRON 0xD5
+
+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (14 * section) + 72;
+ region->length = 14;
+
+ return 0;
+}
+
+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 18 * section;
+ region->length = 18;
+ } else {
+ /* section 0 has one byte reserved for bad block mark */
+ region->offset = 2;
+ region->length = 16;
+ }
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops etron_ooblayout = {
+ .ecc = etron_ooblayout_ecc,
+ .rfree = etron_ooblayout_free,
+};
+
+static int etron_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return nand->eccreq.strength >> 1;
+
+ case STATUS_ECC_LIMIT_BITFLIPS:
+ return nand->eccreq.strength;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info etron_spinand_table[] = {
+ /* EM73C 1Gb 3.3V */
+ SPINAND_INFO("EM73C044VCF",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xD 2Gb */
+ SPINAND_INFO("EM73D044VCR",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM73D044VCO",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78D044VCM",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xE 4Gb */
+ SPINAND_INFO("EM73E044VCE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78E044VCD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xF044VCA 8Gb */
+ SPINAND_INFO("EM73F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer etron_spinand_manufacturer = {
+ .id = SPINAND_MFR_ETRON,
+ .name = "Etron",
+ .chips = etron_spinand_table,
+ .nchips = ARRAY_SIZE(etron_spinand_table),
+ .ops = &etron_spinand_manuf_ops,
+};
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+/* Q5 1Gb */
+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+/* Q5 2Gb & 4Gb */
+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
return -EINVAL;
}
+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 6;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
+ .ecc = esmt_1_ooblayout_ecc,
+ .rfree = esmt_1_ooblayout_free,
+ };
+
static const struct spinand_info gigadevice_spinand_table[] = {
+ SPINAND_INFO("F50L1G41LB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
SPINAND_INFO("GD5F1GQ4xA",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxH",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+ NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -18,6 +18,23 @@
#define WINBOND_CFG_BUF_READ BIT(3)
+#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4)
+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4)
+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
+#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4)
+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
+#define W25N01KV_STATUS_ECC_MASK (3 << 4)
+#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
+#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 64;
+ region->length = 16;
+
+ return 0;
+}
+
+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
+ .ecc = w25n02kv_n04kv_ooblayout_ecc,
+ .rfree = w25n02kv_n04kv_ooblayout_free,
+};
+
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
.rfree = w25n02kv_ooblayout_free,
};
+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & W25N01KV_STATUS_ECC_MASK) {
+ case W25N01KV_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
+ return 3;
+
+ case W25N01KV_STATUS_ECC_4_BITFLIPS:
+ return 4;
+
+ case W25N01KV_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
+ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
+ return 3;
+
+ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
+ return 4;
+
+ /* W25N02_N04KV_use internal 8bit ECC algorithm.
+ * But the ECC strength is 4 bit requried.
+ * Return 3 if the bit bit flip count less than 5.
+ * Return 4 if the bit bit flip count more than 5 to 8.
+ */
+
+ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
@@ -163,6 +261,15 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ SPINAND_INFO("W25N01KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
SPINAND_INFO("W25N02KV",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
@@ -172,6 +279,16 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ SPINAND_INFO("W25N04KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
+ w25n02kv_n04kv_ecc_get_status)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -244,6 +244,7 @@ struct spinand_manufacturer {
};
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;

78
patch/u-boot/u-boot-filogic/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch Normal file
View File

@@ -0,0 +1,78 @@
From 793bed29e78cc54d989333d756fef51efaca4e56 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 26 Jul 2022 09:29:18 +0800
Subject: [PATCH 58/71] mmc: mtk-sd: add support to display verbose error log
Add an option to enable debug log, and also display verbose error log for
both command and data.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mmc/Kconfig | 8 ++++++++
drivers/mmc/Makefile | 4 ++++
drivers/mmc/mtk-sd.c | 24 +++++++++++++++---------
3 files changed, 27 insertions(+), 9 deletions(-)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -868,6 +868,14 @@ config MMC_MTK
This is needed if support for any SD/SDIO/MMC devices is required.
If unsure, say N.
+config MMC_MTK_DEBUG
+ bool "Display verbose error log"
+ default n
+ depends on MMC_MTK
+ help
+ Enable this option to allow verbose error log being displayed for
+ debugging.
+
endif
config FSL_SDHC_V2_3
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -85,3 +85,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o
+
+ifdef CONFIG_MMC_MTK_DEBUG
+CFLAGS_mtk-sd.o += -DDEBUG
+endif
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -784,18 +784,24 @@ static int msdc_ops_send_cmd(struct udev
if (cmd_ret &&
!(cmd_ret == -EIO &&
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))) {
+ dev_dbg(dev, "MSDC start command failure with %d, cmd=%d, arg=0x%x\n",
+ cmd_ret, cmd->cmdidx, cmd->cmdarg);
return cmd_ret;
-
- if (data) {
- data_ret = msdc_start_data(host, data);
- if (cmd_ret)
- return cmd_ret;
- else
- return data_ret;
}
- return 0;
+ if (!data)
+ return cmd_ret;
+
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+
+ if (data_ret)
+ dev_dbg(dev, "MSDC start data failure with %d, cmd=%d, arg=0x%x\n",
+ data_ret, cmd->cmdidx, cmd->cmdarg);
+
+ return data_ret;
}
static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)

58
patch/u-boot/u-boot-filogic/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch Normal file
View File

@@ -0,0 +1,58 @@
From dd66fc817f7ab7a4fcab9836a9251a8f64f329df Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 16:58:36 +0800
Subject: [PATCH 59/71] cmd: ubi: make volume find/create/remove APIs public
Export ubi_create_vol/ubi_find_volume/ubi_remove_vol to public so that they
can be used by other programs.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/ubi.c | 8 ++++----
include/ubi_uboot.h | 4 ++++
2 files changed, 8 insertions(+), 4 deletions(-)
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -213,8 +213,8 @@ bad:
return err;
}
-static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id,
- bool skipcheck)
+int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id,
+ bool skipcheck)
{
struct ubi_mkvol_req req;
int err;
@@ -247,7 +247,7 @@ static int ubi_create_vol(char *volume,
return ubi_create_volume(ubi, &req);
}
-static struct ubi_volume *ubi_find_volume(char *volume)
+struct ubi_volume *ubi_find_volume(char *volume)
{
struct ubi_volume *vol;
int i;
@@ -262,7 +262,7 @@ static struct ubi_volume *ubi_find_volum
return NULL;
}
-static int ubi_remove_vol(char *volume)
+int ubi_remove_vol(char *volume)
{
int err, reserved_pebs, i;
struct ubi_volume *vol;
--- a/include/ubi_uboot.h
+++ b/include/ubi_uboot.h
@@ -50,6 +50,10 @@ extern void ubi_exit(void);
extern int ubi_part(char *part_name, const char *vid_header_offset);
extern int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size);
extern int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size);
+extern int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id,
+ bool skipcheck);
+extern struct ubi_volume *ubi_find_volume(char *volume);
+extern int ubi_remove_vol(char *volume);
extern struct ubi_device *ubi_devices[];
int cmd_ubifs_mount(char *vol_name);

27
patch/u-boot/u-boot-filogic/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch Normal file
View File

@@ -0,0 +1,27 @@
From f6a4130959af1e6d13d616203e42ed3c894666ad Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:00:00 +0800
Subject: [PATCH 60/71] cmd: ubi: allow creating volume with all free spaces
Allow creating volume with all free spaces by giving a negative size value.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
cmd/ubi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -226,7 +226,11 @@ int ubi_create_vol(char *volume, int64_t
req.vol_id = vol_id;
req.alignment = 1;
- req.bytes = size;
+
+ if (size < 0)
+ req.bytes = ubi->avail_pebs * ubi->leb_size;
+ else
+ req.bytes = size;
strcpy(req.name, volume);
req.name_len = strlen(volume);

71
patch/u-boot/u-boot-filogic/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch Normal file
View File

@@ -0,0 +1,71 @@
From fc0c70a7c6a088072d0c77e5a59d5e9b7754c6db Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:01:20 +0800
Subject: [PATCH 61/71] env: ubi: add support to create environment volume if
it does not exist
Add an option to allow environment volume being auto created if not exist.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
env/Kconfig | 6 ++++++
env/ubi.c | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+)
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -701,6 +701,12 @@ config ENV_UBI_VOLUME_REDUND
help
Name of the redundant volume that you want to store the environment in.
+config ENV_UBI_VOLUME_CREATE
+ bool "Create UBI volume if not exist"
+ depends on ENV_IS_IN_UBI
+ help
+ Create the UBI volume if it does not exist.
+
config ENV_UBI_VID_OFFSET
int "ubi environment VID offset"
depends on ENV_IS_IN_UBI
--- a/env/ubi.c
+++ b/env/ubi.c
@@ -105,6 +105,18 @@ static int env_ubi_save(void)
#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
#endif /* CONFIG_CMD_SAVEENV */
+int __weak env_ubi_volume_create(const char *volume)
+{
+ struct ubi_volume *vol;
+
+ vol = ubi_find_volume((char *)volume);
+ if (vol)
+ return 0;
+
+ return ubi_create_vol((char *)volume, CONFIG_ENV_SIZE, true,
+ UBI_VOL_NUM_AUTO, false);
+}
+
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
static int env_ubi_load(void)
{
@@ -134,6 +146,10 @@ static int env_ubi_load(void)
return -EIO;
}
+ if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) {
+ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME);
+ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND);
+ }
read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0,
CONFIG_ENV_SIZE);
if (read1_fail)
@@ -171,6 +187,9 @@ static int env_ubi_load(void)
return -EIO;
}
+ if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE))
+ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME);
+
if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, 0, CONFIG_ENV_SIZE)) {
printf("\n** Unable to read env from %s:%s **\n",
CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME);

66
patch/u-boot/u-boot-filogic/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch Normal file
View File

@@ -0,0 +1,66 @@
From 189a2fe96931ef3ea0e187c8e9bfa589c2a0ae10 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Mon, 25 Jul 2022 17:24:56 +0800
Subject: [PATCH 62/71] mtd: ubi: add support for UBI end-of-filesystem marker
used by OpenWrt
Add support for UBI end-of-filesystem marker used by OpenWrt to allow
attaching a new UBI mtd partition just upgraded.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++---
drivers/mtd/ubi/ubi.h | 1 +
2 files changed, 23 insertions(+), 3 deletions(-)
--- a/drivers/mtd/ubi/attach.c
+++ b/drivers/mtd/ubi/attach.c
@@ -803,6 +803,13 @@ out_unlock:
return err;
}
+static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech)
+{
+ return ech->padding1[0] == 'E' &&
+ ech->padding1[1] == 'O' &&
+ ech->padding1[2] == 'F';
+}
+
/**
* scan_peb - scan and process UBI headers of a PEB.
* @ubi: UBI device description object
@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u
return 0;
}
- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
- if (err < 0)
- return err;
+ if (!ai->eof_found) {
+ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+ if (err < 0)
+ return err;
+
+ if (ec_hdr_has_eof(ech)) {
+ pr_notice("UBI: EOF marker found, PEBs from %d will be erased\n",
+ pnum);
+ ai->eof_found = true;
+ }
+ }
+
+ if (ai->eof_found)
+ err = UBI_IO_FF_BITFLIPS;
+
switch (err) {
case 0:
break;
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -746,6 +746,7 @@ struct ubi_attach_info {
int mean_ec;
uint64_t ec_sum;
int ec_count;
+ bool eof_found;
struct kmem_cache *aeb_slab_cache;
};

235
patch/u-boot/u-boot-filogic/100-29-board-mediatek-wire-up-NMBM-support.patch Normal file
View File

@@ -0,0 +1,235 @@
From 6792b57b3ba61ca6d69ea4a13a58bed65fc5da87 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sun, 7 Aug 2022 04:04:46 +0200
Subject: [PATCH] board: mediatek: wire-up NMBM support
---
board/mediatek/mt7622/mt7622_rfb.c | 38 +++++++++++++++++++++
board/mediatek/mt7629/mt7629_rfb.c | 38 +++++++++++++++++++++
board/mediatek/mt7981/mt7981_rfb.c | 52 ++++++++++++++++++++++++++++
board/mediatek/mt7986/mt7986_rfb.c | 54 ++++++++++++++++++++++++++++++
4 files changed, 182 insertions(+)
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -9,9 +9,47 @@
#include <init.h>
#include <asm/global_data.h>
+#include <mtd.h>
+#include <linux/mtd/mtd.h>
+#include <nmbm/nmbm.h>
+#include <nmbm/nmbm-mtd.h>
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
+
+int board_nmbm_init(void)
+{
+#ifdef CONFIG_ENABLE_NAND_NMBM
+ struct mtd_info *lower, *upper;
+ int ret;
+
+ printf("\n");
+ printf("Initializing NMBM ...\n");
+
+ mtd_probe_devices();
+
+ lower = get_mtd_device_nm("spi-nand0");
+ if (IS_ERR(lower) || !lower) {
+ printf("Lower MTD device 'spi-nand0' not found\n");
+ return 0;
+ }
+
+ ret = nmbm_attach_mtd(lower,
+ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK,
+ CONFIG_NMBM_MAX_RATIO,
+ CONFIG_NMBM_MAX_BLOCKS, &upper);
+
+ printf("\n");
+
+ if (ret)
+ return 0;
+
+ add_mtd_device(upper);
+#endif
+
+ return 0;
+}
--- a/board/mediatek/mt7629/mt7629_rfb.c
+++ b/board/mediatek/mt7629/mt7629_rfb.c
@@ -6,6 +6,11 @@
#include <config.h>
#include <asm/global_data.h>
+#include <mtd.h>
+#include <linux/mtd/mtd.h>
+#include <nmbm/nmbm.h>
+#include <nmbm/nmbm-mtd.h>
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -15,3 +20,36 @@ int board_init(void)
return 0;
}
+
+int board_nmbm_init(void)
+{
+#ifdef CONFIG_ENABLE_NAND_NMBM
+ struct mtd_info *lower, *upper;
+ int ret;
+
+ printf("\n");
+ printf("Initializing NMBM ...\n");
+
+ mtd_probe_devices();
+
+ lower = get_mtd_device_nm("spi-nand0");
+ if (IS_ERR(lower) || !lower) {
+ printf("Lower MTD device 'spi-nand0' not found\n");
+ return 0;
+ }
+
+ ret = nmbm_attach_mtd(lower,
+ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK,
+ CONFIG_NMBM_MAX_RATIO,
+ CONFIG_NMBM_MAX_BLOCKS, &upper);
+
+ printf("\n");
+
+ if (ret)
+ return 0;
+
+ add_mtd_device(upper);
+#endif
+
+ return 0;
+}
--- a/board/mediatek/mt7981/mt7981_rfb.c
+++ b/board/mediatek/mt7981/mt7981_rfb.c
@@ -4,7 +4,57 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <mtd.h>
+#include <linux/mtd/mtd.h>
+#include <nmbm/nmbm.h>
+#include <nmbm/nmbm-mtd.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
int board_init(void)
{
return 0;
}
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ env_relocate();
+ return 0;
+}
+
+int board_nmbm_init(void)
+{
+#ifdef CONFIG_ENABLE_NAND_NMBM
+ struct mtd_info *lower, *upper;
+ int ret;
+
+ printf("\n");
+ printf("Initializing NMBM ...\n");
+
+ mtd_probe_devices();
+
+ lower = get_mtd_device_nm("spi-nand0");
+ if (IS_ERR(lower) || !lower) {
+ printf("Lower MTD device 'spi-nand0' not found\n");
+ return 0;
+ }
+
+ ret = nmbm_attach_mtd(lower, NMBM_F_CREATE, CONFIG_NMBM_MAX_RATIO,
+ CONFIG_NMBM_MAX_BLOCKS, &upper);
+
+ printf("\n");
+
+ if (ret)
+ return 0;
+
+ add_mtd_device(upper);
+#endif
+
+ return 0;
+}
--- a/board/mediatek/mt7986/mt7986_rfb.c
+++ b/board/mediatek/mt7986/mt7986_rfb.c
@@ -4,7 +4,59 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <mtd.h>
+#include <linux/mtd/mtd.h>
+#include <nmbm/nmbm.h>
+#include <nmbm/nmbm-mtd.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
int board_init(void)
{
return 0;
}
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ env_relocate();
+ return 0;
+}
+
+int board_nmbm_init(void)
+{
+#ifdef CONFIG_ENABLE_NAND_NMBM
+ struct mtd_info *lower, *upper;
+ int ret;
+
+ printf("\n");
+ printf("Initializing NMBM ...\n");
+
+ mtd_probe_devices();
+
+ lower = get_mtd_device_nm("spi-nand0");
+ if (IS_ERR(lower) || !lower) {
+ printf("Lower MTD device 'spi-nand0' not found\n");
+ return 0;
+ }
+
+ ret = nmbm_attach_mtd(lower,
+ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK,
+ CONFIG_NMBM_MAX_RATIO,
+ CONFIG_NMBM_MAX_BLOCKS, &upper);
+
+ printf("\n");
+
+ if (ret)
+ return 0;
+
+ add_mtd_device(upper);
+#endif
+
+ return 0;
+}

149
patch/u-boot/u-boot-filogic/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch Normal file
View File

@@ -0,0 +1,149 @@
From 49c8e854869d673df8452f24dfa8989cd0f615a8 Mon Sep 17 00:00:00 2001
From: Martin Kurbanov <mmkurbanov@salutedevices.com>
Date: Mon, 2 Oct 2023 17:04:58 +0300
Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA002G
Add support for FORESEE F35SQA002G SPI NAND.
Datasheet:
https://www.longsys.com/uploads/LM-00006FORESEEF35SQA002GDatasheet_1650183701.pdf
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salutedevices.com
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/foresee.c | 95 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/foresee.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -834,6 +834,7 @@ static const struct spinand_manufacturer
&toshiba_spinand_manufacturer,
&winbond_spinand_manufacturer,
&esmt_c8_spinand_manufacturer,
+ &foresee_spinand_manufacturer,
&xtx_spinand_manufacturer,
};
--- /dev/null
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023, SberDevices. All Rights Reserved.
+ *
+ * Author: Martin Kurbanov <mmkurbanov@salutedevices.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_FORESEE 0xCD
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ return -ERANGE;
+}
+
+static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = {
+ .ecc = f35sqa002g_ooblayout_ecc,
+ .rfree = f35sqa002g_ooblayout_free,
+};
+
+static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return 1;
+
+ default:
+ break;
+ }
+
+ /* More than 1-bit error was detected in one or more sectors and
+ * cannot be corrected.
+ */
+ return -EBADMSG;
+}
+
+static const struct spinand_info foresee_spinand_table[] = {
+ SPINAND_INFO("F35SQA002G",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&f35sqa002g_ooblayout,
+ f35sqa002g_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer foresee_spinand_manufacturer = {
+ .id = SPINAND_MFR_FORESEE,
+ .name = "FORESEE",
+ .chips = foresee_spinand_table,
+ .nchips = ARRAY_SIZE(foresee_spinand_table),
+ .ops = &foresee_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -252,6 +252,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
+extern const struct spinand_manufacturer foresee_spinand_manufacturer;
extern const struct spinand_manufacturer xtx_spinand_manufacturer;
/**

38
patch/u-boot/u-boot-filogic/101-02-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch Normal file
View File

@@ -0,0 +1,38 @@
From ae461cde5c559675fc4c0ba351c7c31ace705f56 Mon Sep 17 00:00:00 2001
From: Bohdan Chubuk <chbgdn@gmail.com>
Date: Sun, 10 Nov 2024 22:50:47 +0200
Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA001G
Add support for FORESEE F35SQA001G SPI NAND.
Similar to F35SQA002G, but differs in capacity.
Datasheet:
- https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf
Tested on Xiaomi AX3000T flashed with OpenWRT.
Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/foresee.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/mtd/nand/spi/foresee.c
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -83,6 +83,16 @@ static const struct spinand_info foresee
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&f35sqa002g_ooblayout,
f35sqa002g_ecc_get_status)),
+ SPINAND_INFO("F35SQA001G",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&f35sqa002g_ooblayout,
+ f35sqa002g_ecc_get_status)),
};
static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {

19
patch/u-boot/u-boot-filogic/101-03-mtd-spinand-fix-support-for-FORESEE.patch Normal file
View File

@@ -0,0 +1,19 @@
Force update_cache_variants to use reset for Foresee NAND with bad blocks
Tested on Xiaomi AX3000T + F35SQA001G with bad blocks and without bad blocks
Signed-off-by: Dim Fish <dimfish@gmail.com>
--- a/drivers/mtd/nand/spi/foresee.c
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -22,8 +22,8 @@ static SPINAND_OP_VARIANTS(write_cache_v
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)

33
patch/u-boot/u-boot-filogic/103-04-mt7988-enable-pstore.patch Normal file
View File

@@ -0,0 +1,33 @@
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -63,6 +63,30 @@
#clock-cells = <0>;
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ record-size = <0x1000>;
+ };
+
+ /* 320 KiB reserved for ARM Trusted Firmware (BL31+BL32) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x50000>;
+ no-map;
+ };
+ };
+
hwver: hwver {
compatible = "mediatek,hwver", "syscon";
reg = <0 0x8000000 0 0x1000>;

289
patch/u-boot/u-boot-filogic/105-configs-add-usefull-stuff-to-mt7988-rfb.patch Normal file
View File

@@ -0,0 +1,289 @@
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -5,37 +5,76 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x400000
CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_MT7988=y
CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
@@ -44,28 +83,43 @@ CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_PROT_TCP=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_FIXED=y
CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7988=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_RAM=y
CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
-CONFIG_LZO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
CONFIG_HEXDUMP=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -6,36 +6,76 @@ CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_MT7988=y
CONFIG_SYS_LOAD_ADDR=0x44000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_AUTOBOOT is not set
+CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_UBI_VOLUME="ubootenv"
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
@@ -44,9 +84,13 @@ CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_PROT_TCP=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
@@ -64,20 +108,31 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_FIXED=y
CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7988=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_RAM=y
CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
-CONFIG_LZO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
CONFIG_HEXDUMP=y
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -195,6 +195,23 @@
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@200000 {
+ label = "ubi";
+ reg = <0x200000 0x7e00000>;
+ compatible = "linux,ubi";
+ };
+ };
};
};

11
patch/u-boot/u-boot-filogic/120-use-xz-instead-of-lzma.patch Normal file
View File

@@ -0,0 +1,11 @@
--- a/Makefile
+++ b/Makefile
@@ -1094,7 +1094,7 @@ quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
quiet_cmd_lzma = LZMA $@
-cmd_lzma = lzma -c -z -k -9 $< > $@
+cmd_lzma = xz --format=lzma -c -z -k -9 $< > $@
cfg: u-boot.cfg

24
patch/u-boot/u-boot-filogic/130-fix-mkimage-host-build.patch Normal file
View File

@@ -0,0 +1,24 @@
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -1175,6 +1175,7 @@ static int fit_config_add_verification_d
* 2) get public key (X509_get_pubkey)
* 3) provide der format (d2i_RSAPublicKey)
*/
+#ifdef CONFIG_TOOLS_LIBCRYPTO
static int read_pub_key(const char *keydir, const void *name,
unsigned char **pubkey, int *pubkey_len)
{
@@ -1228,6 +1229,13 @@ err_cert:
fclose(f);
return ret;
}
+#else
+static int read_pub_key(const char *keydir, const void *name,
+ unsigned char **pubkey, int *pubkey_len)
+{
+ return -ENOSYS;
+}
+#endif
int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
{

1929
patch/u-boot/u-boot-filogic/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

261
patch/u-boot/u-boot-filogic/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch Normal file
View File

@@ -0,0 +1,261 @@
From 16fd9af92b7ed93ece62fa8d1bef341455d773cf Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Sat, 24 May 2025 23:23:53 +0200
Subject: [PATCH v2] cmd: bootmenu: permit to select bootmenu entry with a
shortcut
Permit to select a bootmenu entry with a key shortcut. This is
especially useful in production or testing scenario to automate flashing
procedure or testing procedure.
The boot entry are changed to append the shortcut key to it.
Example:
1. Run default boot command.
2. Boot system via TFTP.
3. Boot production system from NAND.
4. Boot recovery system from NAND.
5. Load production system via TFTP then write to NAND.
6. Load recovery system via TFTP then write to NAND.
7. Load BL31+U-Boot FIP via TFTP then write to NAND.
8. Load BL2 preloader via TFTP then write to NAND.
9. Reboot.
a. Reset all settings to factory defaults.
0. Exit
0 is always reserved for Exit to console.
On pressing the keyboard key 2, the bootmenu entry 2 is selected and
executed.
Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9
and a-z.
If a shortcut key not present in the bootmenu list is pressed, it is
simply ignored and eventually the autoboot is interrupted.
Capital A-Z are converted to lower a-z and the related option is
selected.
Suggested-by: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v2:
- Fix spelling mistake
- Fix case with '0'
cmd/bootmenu.c | 41 ++++++++++++++++++++++++++++++++++++++---
common/menu.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
include/cli.h | 2 ++
include/menu.h | 3 +++
4 files changed, 85 insertions(+), 5 deletions(-)
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -114,6 +114,14 @@ static char *bootmenu_choice_entry(void
++menu->active;
/* no menu key selected, regenerate menu */
return NULL;
+ case BKEY_SHORTCUT:
+ /* invalid shortcut, regenerate menu */
+ if (cch->shortcut_key >= menu->count - 1)
+ return NULL;
+ /* shortcut_key value for Exit is is -1 */
+ menu->active = cch->shortcut_key < 0 ? menu->count - 1 :
+ cch->shortcut_key;
+ fallthrough;
case BKEY_SELECT:
iter = menu->first;
for (i = 0; i < menu->active; ++i)
@@ -161,6 +169,21 @@ static void bootmenu_destroy(struct boot
free(menu);
}
+static char bootmenu_entry_shortcut_key(int index)
+{
+ switch (index) {
+ /* 1-9 shortcut key (0 reserved) */
+ case 0 ... 8:
+ return '1' + index;
+ /* a-z shortcut key */
+ case 9 ... 34:
+ return 'a' + index - 9;
+ /* We support shortcut for up to 34 options (0 reserved) */
+ default:
+ return -ENOENT;
+ }
+}
+
/**
* prepare_bootmenu_entry() - generate the bootmenu_xx entries
*
@@ -184,6 +207,8 @@ static int prepare_bootmenu_entry(struct
struct bootmenu_entry *iter = *current;
while ((option = bootmenu_getoption(i))) {
+ char shortcut_key;
+ int len;
/* bootmenu_[num] format is "[title]=[commands]" */
sep = strchr(option, '=');
@@ -196,12 +221,22 @@ static int prepare_bootmenu_entry(struct
if (!entry)
return -ENOMEM;
- entry->title = strndup(option, sep - option);
+ /* Add shotcut key option: %c. %s\0 */
+ len = sep - option + 4;
+
+ entry->title = malloc(len);
if (!entry->title) {
free(entry);
return -ENOMEM;
}
+ shortcut_key = bootmenu_entry_shortcut_key(i);
+ /* Use emtpy space if entry doesn't support shortcut key */
+ snprintf(entry->title, len, "%c%c %s",
+ shortcut_key > 0 ? shortcut_key : ' ',
+ shortcut_key > 0 ? '.' : ' ',
+ option);
+
entry->command = strdup(sep + 1);
if (!entry->command) {
free(entry->title);
@@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_cr
/* Add Quit entry if exiting bootmenu is disabled */
if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
- entry->title = strdup("Exit");
+ entry->title = strdup("0. Exit");
else
- entry->title = strdup("Quit");
+ entry->title = strdup("0. Quit");
if (!entry->title) {
free(entry);
--- a/common/menu.c
+++ b/common/menu.c
@@ -8,6 +8,7 @@
#include <cli.h>
#include <malloc.h>
#include <errno.h>
+#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <watchdog.h>
@@ -436,6 +437,29 @@ int menu_destroy(struct menu *m)
return 1;
}
+static int bootmenu_conv_shortcut_key(struct bootmenu_data *menu, int ichar)
+{
+ int shortcut_key;
+
+ ichar = tolower(ichar);
+ switch (ichar) {
+ /* a-z for bootmenu entry > 9 */
+ case 'a' ... 'z':
+ shortcut_key = ichar - 'a' + 9;
+ break;
+ /* 1-9 for bootmenu entry <= 9 */
+ case '1' ... '9':
+ shortcut_key = ichar - '1';
+ break;
+ /* Reserve 0 for last option (aka Exit) */
+ case '0':
+ default:
+ return -1;
+ }
+
+ return shortcut_key;
+}
+
enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
struct cli_ch_state *cch)
{
@@ -443,12 +467,12 @@ enum bootmenu_key bootmenu_autoboot_loop
int i, c;
while (menu->delay > 0) {
+ int ichar;
+
if (ansi)
printf(ANSI_CURSOR_POSITION, menu->count + 5, 3);
printf("Hit any key to stop autoboot: %d ", menu->delay);
for (i = 0; i < 100; ++i) {
- int ichar;
-
if (!tstc()) {
schedule();
mdelay(10);
@@ -470,6 +494,11 @@ enum bootmenu_key bootmenu_autoboot_loop
case 0x3: /* ^C */
key = BKEY_QUIT;
break;
+ case 'A' ... 'Z':
+ case 'a' ... 'z':
+ case '0' ... '9':
+ key = BKEY_SHORTCUT;
+ break;
default:
key = BKEY_NONE;
break;
@@ -477,6 +506,9 @@ enum bootmenu_key bootmenu_autoboot_loop
break;
}
+ if (key == BKEY_SHORTCUT)
+ cch->shortcut_key = bootmenu_conv_shortcut_key(menu, ichar);
+
if (menu->delay < 0)
break;
@@ -524,6 +556,11 @@ enum bootmenu_key bootmenu_conv_key(int
case ' ':
key = BKEY_SPACE;
break;
+ case 'A' ... 'Z':
+ case 'a' ... 'z':
+ case '0' ... '9':
+ key = BKEY_SHORTCUT;
+ break;
default:
key = BKEY_NONE;
break;
@@ -554,5 +591,8 @@ enum bootmenu_key bootmenu_loop(struct b
key = bootmenu_conv_key(c);
+ if (key == BKEY_SHORTCUT)
+ cch->shortcut_key = bootmenu_conv_shortcut_key(menu, c);
+
return key;
}
--- a/include/cli.h
+++ b/include/cli.h
@@ -17,12 +17,14 @@
* @esc_save: Escape characters collected so far
* @emit_upto: Next index to emit from esc_save
* @emitting: true if emitting from esc_save
+ * @shortcut_key: Selected shortcut option index
*/
struct cli_ch_state {
int esc_len;
char esc_save[8];
int emit_upto;
bool emitting;
+ int shortcut_key;
};
/**
--- a/include/menu.h
+++ b/include/menu.h
@@ -54,6 +54,9 @@ enum bootmenu_key {
BKEY_QUIT,
BKEY_SAVE,
+ /* shortcut key to select menu option directly */
+ BKEY_SHORTCUT,
+
/* 'extra' keys, which are used by menus but not cedit */
BKEY_PLUS,
BKEY_MINUS,

130
patch/u-boot/u-boot-filogic/200-cmd-add-imsz-and-imszb.patch Normal file
View File

@@ -0,0 +1,130 @@
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -260,6 +260,67 @@ U_BOOT_CMD(
/* iminfo - print header info for a requested image */
/*******************************************************************/
#if defined(CONFIG_CMD_IMI)
+#if defined(CONFIG_FIT)
+#define SECTOR_SHIFT 9
+static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[], short int in_blocks)
+{
+ ulong addr;
+ void *fit;
+ int bsize, tsize;
+ char buf[16];
+
+ if (argc >= 2)
+ addr = simple_strtoul(argv[1], NULL, 16);
+ else
+ addr = image_load_addr;
+
+ fit = (void *)map_sysmem(addr, 0);
+ tsize = fit_get_totalsize(fit);
+ unmap_sysmem(fit);
+ if (tsize == 0)
+ return 1;
+
+ bsize = (tsize >> SECTOR_SHIFT) + ((tsize & ((1 << SECTOR_SHIFT) - 1))?1:0);
+
+ if (!in_blocks)
+ snprintf(buf, sizeof(buf), "%x", tsize);
+ else
+ snprintf(buf, sizeof(buf), "%x", bsize);
+
+ if (argc >= 3)
+ return env_set(argv[2], buf);
+ else
+ printf("%s\n", buf);
+
+ return 0;
+}
+
+static int do_imsz(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return image_totalsize(cmdtp, flag, argc, argv, 0);
+}
+
+static int do_imszb(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return image_totalsize(cmdtp, flag, argc, argv, 1);
+}
+
+U_BOOT_CMD(
+ imsz, CONFIG_SYS_MAXARGS, 1, do_imsz,
+ "get image total size (in bytes)",
+ "addr [maxhdrlen] [varname]\n"
+);
+
+U_BOOT_CMD(
+ imszb, CONFIG_SYS_MAXARGS, 1, do_imszb,
+ "get image total size (in blocks)",
+ "addr [maxhdrlen] [varname]\n"
+);
+
+#endif
static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -2054,6 +2054,47 @@ static const char *fit_get_image_type_pr
return "unknown";
}
+size_t fit_get_totalsize(const void *fit)
+{
+ int ret, ndepth, noffset, images_noffset;
+ size_t data_size, hdrsize, img_total, max_size = 0;
+ const void *data;
+
+ ret = fdt_check_header(fit);
+ if (ret) {
+ debug("Wrong FIT format: not a flattened device tree (err=%d)\n",
+ ret);
+ return 0;
+ }
+
+ hdrsize = fdt_totalsize(fit);
+
+ /* take care of simple FIT with internal images */
+ max_size = hdrsize;
+
+ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ if (images_noffset < 0)
+ goto out;
+
+ for (ndepth = 0,
+ noffset = fdt_next_node(fit, images_noffset, &ndepth);
+ (noffset >= 0) && (ndepth > 0);
+ noffset = fdt_next_node(fit, noffset, &ndepth)) {
+ if (ndepth == 1) {
+ ret = fit_image_get_data(fit, noffset, &data, &data_size);
+ if (ret)
+ goto out;
+
+ img_total = data_size + (data - fit);
+
+ max_size = (max_size > img_total) ? max_size : img_total;
+ }
+ }
+
+out:
+ return max_size;
+}
+
int fit_image_load(struct bootm_headers *images, ulong addr,
const char **fit_unamep, const char **fit_uname_configp,
int arch, int ph_type, int bootstage_id,
--- a/include/image.h
+++ b/include/image.h
@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec,
ulong *addr, const char **image_name);
int fit_get_subimage_count(const void *fit, int images_noffset);
+size_t fit_get_totalsize(const void *fit);
void fit_print_contents(const void *fit);
void fit_image_print(const void *fit, int noffset, const char *p);

33
patch/u-boot/u-boot-filogic/211-cmd-bootmenu-custom-title.patch Normal file
View File

@@ -0,0 +1,33 @@
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -482,7 +482,11 @@ static void menu_display_statusline(stru
printf(ANSI_CURSOR_POSITION, 1, 1);
puts(ANSI_CLEAR_LINE);
printf(ANSI_CURSOR_POSITION, 2, 3);
- puts("*** U-Boot Boot Menu ***");
+ if (menu->mtitle)
+ puts(menu->mtitle);
+ else
+ puts(" *** U-Boot Boot Menu ***");
+
puts(ANSI_CLEAR_LINE_TO_END);
printf(ANSI_CURSOR_POSITION, 3, 1);
puts(ANSI_CLEAR_LINE);
@@ -573,6 +577,7 @@ static enum bootmenu_ret bootmenu_show(i
return BOOTMENU_RET_FAIL;
}
+ bootmenu->mtitle = env_get("bootmenu_title");
for (iter = bootmenu->first; iter; iter = iter->next) {
if (menu_item_add(menu, iter->key, iter) != 1)
goto cleanup;
--- a/include/menu.h
+++ b/include/menu.h
@@ -43,6 +43,7 @@ struct bootmenu_data {
int last_active; /* last active menu entry */
int count; /* total count of menu entries */
struct bootmenu_entry *first; /* first menu entry */
+ char *mtitle; /* custom menu title */
};
/** enum bootmenu_key - keys that can be returned by the bootmenu */

116
patch/u-boot/u-boot-filogic/220-cmd-env-readmem.patch Normal file
View File

@@ -0,0 +1,116 @@
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -707,6 +707,12 @@ config CMD_ENV_EXISTS
Check if a variable is defined in the environment for use in
shell scripting.
+config CMD_ENV_READMEM
+ bool "env readmem"
+ default y
+ help
+ Store memory content into environment variable.
+
config CMD_ENV_CALLBACK
bool "env callbacks - print callbacks and their associated variables"
help
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -273,6 +273,60 @@ static int do_env_ask(struct cmd_tbl *cm
}
#endif
+#if defined(CONFIG_CMD_ENV_READMEM)
+int do_env_readmem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ char varstr[CONFIG_SYS_CBSIZE];
+ const void *buf;
+ char *local_args[4];
+ ulong addr, bytes = 6;
+ int hexdump = 0;
+
+ /*
+ * Check the syntax:
+ *
+ * readmem [-b] name address [size]
+ */
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ local_args[0] = argv[0];
+
+ if (!strncmp(argv[1], "-b", 3))
+ hexdump = 1;
+
+ local_args[1] = argv[hexdump + 1];
+ local_args[2] = varstr;
+ local_args[3] = NULL;
+
+ addr = simple_strtoul(argv[hexdump + 2], NULL, 16);
+
+ if (!hexdump)
+ bytes = simple_strtoul(argv[hexdump + 3], NULL, 16);
+
+ if (bytes < 1)
+ return 1;
+
+ if ((hexdump * 3) * bytes >= CONFIG_SYS_CBSIZE)
+ return 1;
+
+ buf = map_sysmem(addr, bytes);
+ if (!buf)
+ return 1;
+
+ if (hexdump) {
+ sprintf(varstr, "%pM", buf);
+ } else {
+ memcpy(varstr, buf, bytes);
+ varstr[bytes] = '\0';
+ }
+ unmap_sysmem(buf);
+
+ /* Continue calling setenv code */
+ return env_do_env_set(flag, 3, local_args, H_INTERACTIVE);
+}
+#endif
+
#if defined(CONFIG_CMD_ENV_CALLBACK)
static int print_static_binding(const char *var_name, const char *callback_name,
void *priv)
@@ -1092,6 +1146,9 @@ static struct cmd_tbl cmd_env_sub[] = {
U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
#endif
U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
+#if defined(CONFIG_CMD_ENV_READMEM)
+ U_BOOT_CMD_MKENT(readmem, CONFIG_SYS_MAXARGS, 3, do_env_readmem, "", ""),
+#endif
#if defined(CONFIG_CMD_RUN)
U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
#endif
@@ -1176,6 +1233,9 @@ U_BOOT_LONGHELP(env,
#if defined(CONFIG_CMD_NVEDIT_EFI)
"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
#endif
+#if defined(CONFIG_CMD_ENV_READMEM)
+ "env readmem [-b] name address size - read variable from memory\n"
+#endif
#if defined(CONFIG_CMD_RUN)
"env run var [...] - run commands in an environment variable\n"
#endif
@@ -1284,6 +1344,17 @@ U_BOOT_CMD(
);
#endif
+#if defined(CONFIG_CMD_ENV_READMEM)
+U_BOOT_CMD_COMPLETE(
+ readmem, CONFIG_SYS_MAXARGS, 3, do_env_readmem,
+ "get environment variable from memory address",
+ "name [-b] address size\n"
+ " - store memory address to env variable\n"
+ " \"-b\": read binary ethaddr",
+ var_complete
+);
+#endif
+
#if defined(CONFIG_CMD_RUN)
U_BOOT_CMD_COMPLETE(
run, CONFIG_SYS_MAXARGS, 1, do_run,

78
patch/u-boot/u-boot-filogic/230-cmd-add-pstore-check.patch Normal file
View File

@@ -0,0 +1,78 @@
--- a/cmd/pstore.c
+++ b/cmd/pstore.c
@@ -208,6 +208,58 @@ static int pstore_set(struct cmd_tbl *cm
}
/**
+ * pstore_check() - Check for pstore records
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Return: 0 if there are records in pstore, 1 otherwise
+ */
+static int pstore_check(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ phys_addr_t ptr;
+ char *buffer;
+ u32 size;
+ int header_len = 0;
+ bool compressed;
+
+ if (pstore_length == 0) {
+ printf("Please set PStore configuration\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (buffer_size == 0)
+ pstore_init_buffer_size();
+
+ buffer = malloc_cache_aligned(buffer_size);
+
+ ptr = pstore_addr;
+ phys_addr_t ptr_end = ptr + pstore_length - pstore_pmsg_size
+ - pstore_ftrace_size - pstore_console_size;
+
+ while (ptr < ptr_end) {
+ size = pstore_get_buffer(PERSISTENT_RAM_SIG, ptr,
+ pstore_record_size, buffer);
+ ptr += pstore_record_size;
+
+ if (size == 0)
+ continue;
+
+ header_len = pstore_read_kmsg_hdr(buffer, &compressed);
+ if (header_len == 0)
+ continue;
+
+ free(buffer);
+ return 0;
+ }
+
+ free(buffer);
+ return 1;
+}
+
+/**
* pstore_print_buffer() - Print buffer
* @type: buffer type
* @buffer: buffer to print
@@ -459,6 +511,7 @@ static int pstore_save(struct cmd_tbl *c
static struct cmd_tbl cmd_pstore_sub[] = {
U_BOOT_CMD_MKENT(set, 8, 0, pstore_set, "", ""),
+ U_BOOT_CMD_MKENT(check, 1, 0, pstore_check, "", ""),
U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""),
U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""),
};
@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
" 'pmsg-size' is the size of the user space logs record.\n"
" 'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n"
" bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n"
+ "pstore check\n"
+ "- Returns true if there are records in pstore.\n"
"pstore display [record-type] [nb]\n"
"- Display existing records in pstore reserved memory. A 'record-type' can\n"
" be given to only display records of this kind. 'record-type' can be one\n"

11
patch/u-boot/u-boot-filogic/250-fix-mmc-erase-timeout.patch Normal file
View File

@@ -0,0 +1,11 @@
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -79,7 +79,7 @@ ulong mmc_berase(struct blk_desc *block_
u32 start_rem, blkcnt_rem, erase_args = 0;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
- int timeout_ms = 1000;
+ int timeout_ms = blkcnt;
if (!mmc)
return -1;

31
patch/u-boot/u-boot-filogic/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch Normal file
View File

@@ -0,0 +1,31 @@
From 5f2d5915f8ea4785bc2b8a26955e176a7898c15b Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Apr 2022 21:00:43 +0100
Subject: [PATCH] image-fdt: save name of FIT configuration in '/chosen' node
It can be useful for the OS (Linux) to know which configuration has
been chosen by U-Boot when launching a FIT image.
Store the name of the FIT configuration node used in a new string
property called 'u-boot,bootconf' in the '/chosen' node in device tree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
boot/image-fdt.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -613,6 +613,12 @@ int image_setup_libfdt(struct bootm_head
images->fit_uname_cfg,
strlen(images->fit_uname_cfg) + 1, 1);
+ /* Store name of configuration node as u-boot,bootconf in /chosen node */
+ if (images->fit_uname_cfg)
+ fdt_find_and_setprop(blob, "/chosen", "u-boot,bootconf",
+ images->fit_uname_cfg,
+ strlen(images->fit_uname_cfg) + 1, 1);
+
/* Update ethernet nodes */
fdt_fixup_ethernet(blob);
#if IS_ENABLED(CONFIG_CMD_PSTORE)

45
patch/u-boot/u-boot-filogic/305-mt7988-generic-reset-button-ignore-env.patch Normal file
View File

@@ -0,0 +1,45 @@
--- a/board/mediatek/mt7988/mt7988_rfb.c
+++ b/board/mediatek/mt7988/mt7988_rfb.c
@@ -4,7 +4,42 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
+#include <config.h>
+#include <dm.h>
+#include <button.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#ifndef CONFIG_RESET_BUTTON_LABEL
+#define CONFIG_RESET_BUTTON_LABEL "reset"
+#endif
+
int board_init(void)
{
return 0;
}
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ struct udevice *dev;
+
+ gd->env_valid = ENV_VALID;
+ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {
+ puts("reset button found\n");
+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY
+ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) {
+ button_get_state(dev);
+ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY);
+ }
+#endif
+ if (button_get_state(dev) == BUTTON_ON) {
+ puts("button pushed, resetting environment\n");
+ gd->env_valid = ENV_INVALID;
+ }
+ }
+ env_relocate();
+ return 0;
+}

67
patch/u-boot/u-boot-filogic/310-mt7988-select-rootdisk.patch Normal file
View File

@@ -0,0 +1,67 @@
--- a/board/mediatek/mt7988/mt7988_rfb.c
+++ b/board/mediatek/mt7988/mt7988_rfb.c
@@ -10,7 +10,9 @@
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <linux/delay.h>
+#include <linux/libfdt.h>
#ifndef CONFIG_RESET_BUTTON_LABEL
#define CONFIG_RESET_BUTTON_LABEL "reset"
@@ -43,3 +45,54 @@ int board_late_init(void)
env_relocate();
return 0;
}
+
+#define MT7988_BOOT_NOR 0
+#define MT7988_BOOT_SPIM_NAND 1
+#define MT7988_BOOT_EMMC 2
+#define MT7988_BOOT_SNFI_NAND 3
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ const u32 *media_handle_p;
+ int chosen, len, ret;
+ const char *media;
+ u32 media_handle;
+
+ switch ((readl(0x1001f6f0) & 0xc00) >> 10) {
+ case MT7988_BOOT_NOR:
+ media = "rootdisk-nor";
+ break
+ ;;
+ case MT7988_BOOT_SPIM_NAND:
+ media = "rootdisk-spim-nand";
+ break
+ ;;
+ case MT7988_BOOT_EMMC:
+ media = "rootdisk-emmc";
+ break
+ ;;
+ case MT7988_BOOT_SNFI_NAND:
+ media = "rootdisk-sd";
+ break
+ ;;
+ }
+
+ chosen = fdt_path_offset(blob, "/chosen");
+ if (chosen <= 0)
+ return 0;
+
+ media_handle_p = fdt_getprop(blob, chosen, media, &len);
+ if (media_handle_p <= 0 || len != 4)
+ return 0;
+
+ media_handle = *media_handle_p;
+ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
+ if (ret) {
+ printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
+ return ret;
+ }
+
+ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
+
+ return 0;
+}

329
patch/u-boot/u-boot-filogic/341-mtd-spinand-Support-dosilicon.patch Normal file
View File

@@ -0,0 +1,329 @@
From cead43cc5781492f2706eeed1157c8986a216bc9 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sun, 17 Oct 2021 09:51:39 +0800
Subject: [PATCH] mtd: spinand: Support dosilicon
DS35X1GA, DS35Q2GA, DS35M1GA, DS35M2GA, DS35Q2GB, DS35M1GB
Change-Id: I5aeb0219f01dbe98d36b398e66b94ab31b07788e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/dosilicon.c | 187 +++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/dosilicon.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs += dosilicon.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
};
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &dosilicon_spinand_manufacturer,
&etron_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/dosilicon.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_DOSILICON 0xE5
+
+#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4)
+#define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
+#define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
+#define DOSICON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static int ds35xxga_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int ds35xxga_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 6;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops ds35xxga_ooblayout = {
+ .ecc = ds35xxga_ooblayout_ecc,
+ .rfree = ds35xxga_ooblayout_free,
+};
+
+static int ds35xxgb_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 64;
+ region->length = 64;
+
+ return 0;
+}
+
+static int ds35xxgb_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 1 bytes for the BBM. */
+ region->offset = 1;
+ region->length = 63;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops ds35xxgb_ooblayout = {
+ .ecc = ds35xxgb_ooblayout_ecc,
+ .rfree = ds35xxgb_ooblayout_free,
+};
+
+static int ds35xxgb_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & DOSICON_STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case DOSICON_STATUS_ECC_1TO3_BITFLIPS:
+ return 3;
+
+ case DOSICON_STATUS_ECC_4TO6_BITFLIPS:
+ return 6;
+
+ case DOSICON_STATUS_ECC_7TO8_BITFLIPS:
+ return 8;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info dosilicon_spinand_table[] = {
+ SPINAND_INFO("DS35X1GA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)),
+ SPINAND_INFO("DS35Q2GA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)),
+ SPINAND_INFO("DS35M1GA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)),
+ SPINAND_INFO("DS35M2GA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)),
+ SPINAND_INFO("DS35Q2GB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35M1GB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q1GB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q4GM",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF4),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q12B",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35M12B",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q1GD-IB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35M4GB-IB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q4GB-IB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB4),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q12C-IB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35M12C-IB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q2GBS",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer dosilicon_spinand_manufacturer = {
+ .id = SPINAND_MFR_DOSILICON,
+ .name = "dosilicon",
+ .chips = dosilicon_spinand_table,
+ .nchips = ARRAY_SIZE(dosilicon_spinand_table),
+ .ops = &dosilicon_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -244,6 +244,7 @@ struct spinand_manufacturer {
};
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;

290
patch/u-boot/u-boot-filogic/342-mtd-spinand-Support-fmsh.patch Normal file
View File

@@ -0,0 +1,290 @@
From 205a24e34751220c3ba04f0ac6ecc734e56ed225 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Sun, 17 Oct 2021 09:59:10 +0800
Subject: [PATCH] mtd: spinand: Support fmsh
FM25S01A, FM25S02A, FM25S01
Change-Id: I7e0ceec39c57dc591d77a4ebde599ad326cf25b7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/fmsh.c | 122 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/fmsh.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
-spinand-objs += dosilicon.o
+spinand-objs += dosilicon.o fmsh.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -828,6 +828,7 @@ static const struct nand_ops spinand_ops
static const struct spinand_manufacturer *spinand_manufacturers[] = {
&dosilicon_spinand_manufacturer,
&etron_spinand_manufacturer,
+ &fmsh_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/fmsh.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ *
+ * Authors:
+ * Dingqiang Lin <jon.lin@rock-chips.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_FMSH 0xA1
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int fm25s01a_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ return -ERANGE;
+}
+
+static int fm25s01a_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25s01a_ooblayout = {
+ .ecc = fm25s01a_ooblayout_ecc,
+ .rfree = fm25s01a_ooblayout_free,
+};
+
+static int fm25s01_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 64;
+ region->length = 64;
+
+ return 0;
+}
+
+static int fm25s01_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25s01_ooblayout = {
+ .ecc = fm25s01_ooblayout_ecc,
+ .rfree = fm25s01_ooblayout_free,
+};
+
+/*
+ * ecc bits: 0xC0[4,6]
+ * [0b000], No bit errors were detected;
+ * [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not
+ * reach Flipping Bits;
+ * [0b101], Bit error count equals the bit flip
+ * detection threshold
+ * [0b010], Multiple bit errors were detected and
+ * not corrected.
+ * others, Reserved.
+ */
+static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
+
+ if (eccsr <= 1 || eccsr == 3)
+ return eccsr;
+ else if (eccsr == 5)
+ return nand->eccreq.strength;
+ else
+ return -EBADMSG;
+}
+
+static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 64;
+ region->length = 64;
+
+ return 0;
+}
+
+static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = {
+ .ecc = fm25g0xd_ooblayout_ecc,
+ .rfree = fm25g0xd_ooblayout_free,
+};
+
+/*
+ * ecc bits: 0xC0[4,6]
+ * [0x0], No bit errors were detected;
+ * [0x001, 0x011], Bit errors were detected and corrected. Not
+ * reach Flipping Bits;
+ * [0x100], Bit error count equals the bit flip
+ * detectionthreshold
+ * [0x101, 0x110], Reserved;
+ * [0x111], Multiple bit errors were detected and
+ * not corrected.
+ */
+static int fm25g0xd_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
+
+ if (eccsr <= 3)
+ return 0;
+ else if (eccsr == 4)
+ return nand->eccreq.strength;
+ else
+ return -EBADMSG;
+}
+
+static const struct spinand_info fmsh_spinand_table[] = {
+ SPINAND_INFO("FM25S01A",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
+ SPINAND_INFO("FM25S02A",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE5),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
+ SPINAND_INFO("FM25S01",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
+ SPINAND_INFO("FM25LS01",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
+ SPINAND_INFO("FM25S01BI3",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
+ SPINAND_INFO("FM25S02BI3-DND-A-G3",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
+ SPINAND_INFO("FM25G02D",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer fmsh_spinand_manufacturer = {
+ .id = SPINAND_MFR_FMSH,
+ .name = "FMSH",
+ .chips = fmsh_spinand_table,
+ .nchips = ARRAY_SIZE(fmsh_spinand_table),
+ .ops = &fmsh_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -246,6 +246,7 @@ struct spinand_manufacturer {
/* SPI NAND manufacturers */
extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
extern const struct spinand_manufacturer etron_spinand_manufacturer;
+extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;

189
patch/u-boot/u-boot-filogic/343-mtd-spinand-gsto-Add-code.patch Normal file
View File

@@ -0,0 +1,189 @@
From 1e5200d59e21c8a8fa63badf415becb2301e78a4 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Thu, 27 Apr 2023 22:00:04 +0800
Subject: [PATCH] mtd: spinand: gsto: Add code
GSS01GSAK1, GSS02GSAK1
Change-Id: I7ee9048d934694803d6d081cb7d0cdc56f114e79
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/gsto.c | 90 +++++++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 1 +
4 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/gsto.c
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
-spinand-objs += dosilicon.o fmsh.o
+spinand-objs += dosilicon.o fmsh.o gsto.o
spinand-objs += toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -830,6 +830,7 @@ static const struct spinand_manufacturer
&etron_spinand_manufacturer,
&fmsh_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
+ &gsto_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
&paragon_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/gsto.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * Authors:
+ * Dingqiang Lin <jon.lin@rock-chips.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_GSTO 0x52
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int gss0xgsak1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 32;
+ region->length = 32;
+
+ return 0;
+}
+
+static int gss0xgsak1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 2;
+ region->length = 30;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
+ .ecc = gss0xgsak1_ooblayout_ecc,
+ .rfree = gss0xgsak1_ooblayout_free,
+};
+
+static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 64;
+ region->length = 64;
+
+ return 0;
+}
+
+static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = {
+ .ecc = gss0xgsax1_ooblayout_ecc,
+ .rfree = gss0xgsax1_ooblayout_free,
+};
+
+static const struct spinand_info gsto_spinand_table[] = {
+ SPINAND_INFO("GSS01GSAK1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 10, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
+ SPINAND_INFO("GSS02GSAK1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x23),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
+ SPINAND_INFO("GSS02GSAX1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x23),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
+ SPINAND_INFO("GSS01GSAX1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x13),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
+};
+
+static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer gsto_spinand_manufacturer = {
+ .id = SPINAND_MFR_GSTO,
+ .name = "GSTO",
+ .chips = gsto_spinand_table,
+ .nchips = ARRAY_SIZE(gsto_spinand_table),
+ .ops = &gsto_spinand_manuf_ops,
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -248,6 +248,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+extern const struct spinand_manufacturer gsto_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;
extern const struct spinand_manufacturer paragon_spinand_manufacturer;

653
patch/u-boot/u-boot-filogic/450-add-bpi-r4.patch Normal file
View File

@@ -0,0 +1,653 @@
--- a/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig
+++ b/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig
@@ -0,0 +1,132 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7988=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+CONFIG_LOGLEVEL=6
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_UFETCH=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- a/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig
+++ b/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig
@@ -0,0 +1,132 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7988=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+CONFIG_LOGLEVEL=6
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_UFETCH=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- a/configs/mt7988a_bananapi_bpi-r4-snand_defconfig
+++ b/configs/mt7988a_bananapi_bpi-r4-snand_defconfig
@@ -0,0 +1,132 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7988=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+CONFIG_LOGLEVEL=6
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_UFETCH=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MTK_AHCI=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
--- a/arch/arm/dts/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "Bananapi BPI-R4";
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x10000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_green: led-green {
+ label = "green:status";
+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_blue: led-blue {
+ label = "blue:status";
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "usxgmii";
+ mediatek,switch = "mt7988";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&pio {
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6", "pwm7";
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ };
+
+ conf-clk {
+ pins = "EMMC_CK";
+ };
+
+ conf-dsl {
+ pins = "EMMC_DSL";
+ };
+
+ conf-rst {
+ pins = "EMMC_RSTB";
+ };
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "flash";
+ groups = "emmc_45";
+ };
+
+ conf-cmd-dat {
+ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
+ "SPI2_CLK", "SPI2_HOLD";
+ input-enable;
+ };
+
+ conf-clk {
+ pins = "SPI2_WP";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <2>;
+ sample_sel = <0>;
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@200000 {
+ label = "ubi";
+ reg = <0x200000 0x7e00000>;
+ compatible = "linux,ubi";
+ };
+ };
+ };
+};
--- a/arch/arm/dts/mt7988a-bananapi-bpi-r4-sd.dts
+++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-sd.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+ max-frequency = <52000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
--- a/arch/arm/dts/mt7988a-bananapi-bpi-r4-emmc.dts
+++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-emmc.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ max-frequency = <52000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ non-removable;
+ status = "okay";
+};

29
patch/u-boot/u-boot-filogic/500-add-distro-boot-support.patch Normal file
View File

@@ -0,0 +1,29 @@
--- a/include/configs/mt7988.h
+++ b/include/configs/mt7988.h
@@ -11,4 +11,26 @@
#define CFG_MAX_MEM_MAPPED 0xC0000000
+#include <linux/sizes.h>
+
+#ifndef BOOT_TARGETS
+#define BOOT_TARGETS "mmc0 nvme usb pxe dhcp spi"
#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x50000000\0" \
+ "script_size_f=0x2000\0" \
+ "kernel_addr_r=0x52000000\0" \
+ "fdt_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x62180000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0" \
+ "bootcmd=sysboot mmc 0:5 any ${scriptaddr} /boot/extlinux/extlinux.conf\0" \
+ "\0"
+
+#endif /* _MT7988_H_ */