mirror of
https://github.com/armbian/build
synced 2025-09-24 19:47:06 +07:00
Merge pull request #4847 from armbian/AR-1543
Update RK35xx legacy kernel to 5.10
This commit is contained in:
Igor Pečovnik
13
config/boards/radxa-e25.wip
Normal file
13
config/boards/radxa-e25.wip
Normal file
@@ -0,0 +1,13 @@
|
||||
# Rockchip RK3568 quad core 1-8GB SoC GBe eMMC USB3
|
||||
BOARD_NAME="Radxa E25"
|
||||
BOARDFAMILY="rk35xx"
|
||||
BOOTCONFIG="radxa-e25-rk3568_defconfig"
|
||||
KERNEL_TARGET="legacy,edge"
|
||||
FULL_DESKTOP="yes"
|
||||
BOOT_LOGO="desktop"
|
||||
BOOT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
|
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BOOT_SCENARIO="spl-blobs"
|
||||
WIREGUARD="no"
|
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BOOT_SUPPORT_SPI="yes"
|
||||
IMAGE_PARTITION_TABLE="gpt"
|
||||
BOOTFS_TYPE="fat"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -11,14 +11,11 @@ case $BRANCH in
|
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UBOOT_COMPILER="aarch64-linux-gnu-"
|
||||
UBOOT_USE_GCC='< 8.0'
|
||||
BOOTDIR='u-boot-rockchip64'
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KERNELSOURCE='https://github.com/radxa/kernel'
|
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export KERNEL_MAJOR_MINOR="4.19" # Major and minor versions of this kernel.
|
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KERNELBRANCH='branch:stable-4.19-rock3'
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KERNELSOURCE='https://gitlab.com/rk3588_linux/rk/kernel.git'
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KERNELBRANCH='tag:linux-5.10-gen-rkr3.6'
|
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export KERNEL_MAJOR_MINOR="5.10" # Major and minor versions of this kernel.
|
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KERNELDIR='linux-rockchip64'
|
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KERNELPATCHDIR='rk35xx-legacy'
|
||||
if [[ $BOARD == rock-3a ]]; then
|
||||
BOOT_FDT_FILE="rockchip/rk3568-rock-3-a.dtb"
|
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fi
|
||||
|
||||
;;
|
||||
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
index f4c886a8a..6639fa6c6 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -135,6 +135,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
|
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
|
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3-a.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
|
||||
333
patch/kernel/archive/rk35xx-5.10/board-dts-add-radxa-e25.patch
Normal file
333
patch/kernel/archive/rk35xx-5.10/board-dts-add-radxa-e25.patch
Normal file
@@ -0,0 +1,333 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
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new file mode 100644
|
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index 000000000..3cd366e6c
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -0,0 +1,327 @@
|
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
||||
+ * Copyright (c) 2021 Radxa Limited.
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||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3568-radxa-rock-3-compute-module-plus.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa E25";
|
||||
+ compatible = "radxa,e25", "rockchip,rk3568";
|
||||
+
|
||||
+ vcc5v0_otg: vcc5v0-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
+ regulator-name = "vcc5v0_otg";
|
||||
+ };
|
||||
+
|
||||
+ pcie30_3v3: pcie30-3v3 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "pcie30_3v3";
|
||||
+ regulator-min-microvolt = <100000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
+ gpios-states = <0x1>;
|
||||
+ states = <100000 0x0
|
||||
+ 3300000 0x1>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_minipcie: vcc3v3-minipcie {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc3v3_minipcie_en>;
|
||||
+ regulator-name = "vcc3v3_minipcie";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ //low:wifi,high:5G
|
||||
+ vcc3v3_minipcie_to_5g_or_wifi: vcc3v3-minipcie-to-5g-or-wifi {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-low;
|
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+ gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
|
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+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc3v3_minipcie_to_5g_or_wifi_en>;
|
||||
+ regulator-name = "vcc3v3_minipcie_to_5g_or_wifi";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie_30x1: vcc3v3-pci-30x1 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc3v3_pcie_30x1_en>;
|
||||
+ regulator-name = "vcc3v3_pci_30x1";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ em05_modem: em05-modem {
|
||||
+ compatible = "lte-em05-modem-platdata";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&em05_power_en &em05_airplane_mode &em05_reset>;
|
||||
+ em05,power-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ em05,reset-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
+ em05,airplane-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ rgb0: rgb0 {
|
||||
+ compatible = "pwm-leds";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rgb0-red {
|
||||
+ pwms = <&pwm1 0 1000000 0>;
|
||||
+ max-brightness = <255>;
|
||||
+ };
|
||||
+
|
||||
+ rgb0-blue {
|
||||
+ pwms = <&pwm12 0 1000000 0>;
|
||||
+ max-brightness = <255>;
|
||||
+ };
|
||||
+
|
||||
+ rgb0-green {
|
||||
+ pwms = <&pwm2 0 1000000 0>;
|
||||
+ max-brightness = <255>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&fiq_debugger {
|
||||
+ rockchip,baudrate = <115200>;
|
||||
+};
|
||||
+
|
||||
+&sdio_pwrseq {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&wireless_wlan {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&wireless_bluetooth {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sdmmc2 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+//sdcard
|
||||
+&sdmmc0 {
|
||||
+ max-frequency = <150000000>;
|
||||
+ supports-sd;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
+ cd-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ vbus-supply = <&vcc5v0_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ phy-supply = <&vcc5v0_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB OTG/USB Host_1 USB 2.0 Comb PHY_0 */
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+ u2phy0_host {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* USB Host_2/USB Host_3 USB 2.0 Comb PHY_1 */
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+ u2phy1_host {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* USB 2.0 Host_2 EHCI controller for high speed */
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 2.0 Host_2 OHCI controller for full/low speed */
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 2.0 Host_3 EHCI controller for high speed */
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 2.0 Host_3 OHCI controller for full/low speed */
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3 {
|
||||
+ extcon=<&usb2phy0>;
|
||||
+ status="okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 3.0 OTG controller */
|
||||
+&usbdrd30 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbhost_dwc3 {
|
||||
+ phys = <&u2phy0_host>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ maximum-speed = "high-speed"; /* set dwc3 controller to high speed */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 3.0 Host_1 controller */
|
||||
+&usbhost30 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+/* USB 3.0 OTG/SATA Combo PHY_0 */
|
||||
+&combphy0_us {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* USB 3.0 Host/SATA/QSGMII Combo PHY_1 */
|
||||
+&combphy1_usq {
|
||||
+ rockchip,dis-u3otg1-port; /* set dwc3 controller to high speed */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sata1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ rockchip,bifurcation;
|
||||
+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+ pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ rockchip,bifurcation;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+ pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2_psq {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+ pinctrl-0 = <&pcie20m2_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "active";
|
||||
+ pinctrl-0 = <&pwm1m0_pins>;
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "active";
|
||||
+ pinctrl-0 = <&pwm2m0_pins>;
|
||||
+};
|
||||
+
|
||||
+&pwm12 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "active";
|
||||
+ pinctrl-0 = <&pwm12m1_pins>;
|
||||
+};
|
||||
+
|
||||
+&user_leds {
|
||||
+ linux,default-trigger = "none";
|
||||
+ default-state = "off";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ usb {
|
||||
+ vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pci-en {
|
||||
+ vcc3v3_minipcie_en: vcc3v3-minipcie-en {
|
||||
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie_30x1_en: vcc3v3-pcie-30x1-en {
|
||||
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_minipcie_to_5g_or_wifi_en: vcc3v3-minipcie-to-5g-or-wifi-en {
|
||||
+ rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ lte-em05-modem {
|
||||
+ em05_airplane_mode: em05-airplane-mode {
|
||||
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ em05_power_en: em05-power-en {
|
||||
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ em05_reset: em05-reset {
|
||||
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
1067
patch/kernel/archive/rk35xx-5.10/board-dts-add-rock3a.patch
Normal file
1067
patch/kernel/archive/rk35xx-5.10/board-dts-add-rock3a.patch
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3-a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3-a.dts
|
||||
new file mode 120000
|
||||
index 000000000..81a81de4d
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3-a.dts
|
||||
@@ -0,0 +1 @@
|
||||
+rk3568-rock-3a.dts
|
||||
\ No newline at end of file
|
||||
@@ -0,0 +1,723 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi
|
||||
new file mode 100644
|
||||
index 000000000..29b978245
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-rock-3-compute-module-plus.dtsi
|
||||
@@ -0,0 +1,717 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
||||
+ * Copyright (c) 2021 Radxa Limited.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pwm/pwm.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/input/rk-input.h>
|
||||
+#include <dt-bindings/display/drm_mipi_dsi.h>
|
||||
+#include <dt-bindings/sensor-dev.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "radxa,rock-3-compute-module-plus", "rockchip,rk3568";
|
||||
+
|
||||
+ fiq_debugger: fiq-debugger {
|
||||
+ compatible = "rockchip,fiq-debugger";
|
||||
+ rockchip,serial-id = <2>;
|
||||
+ rockchip,wake-irq = <0>;
|
||||
+ /* If enable uart uses irq instead of fiq */
|
||||
+ rockchip,irq-mode-enable = <1>;
|
||||
+ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
|
||||
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart2m0_xfer>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ debug: debug@fd904000 {
|
||||
+ compatible = "rockchip,debug";
|
||||
+ reg = <0x0 0xfd904000 0x0 0x1000>,
|
||||
+ <0x0 0xfd905000 0x0 0x1000>,
|
||||
+ <0x0 0xfd906000 0x0 0x1000>,
|
||||
+ <0x0 0xfd907000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ cspmu: cspmu@fd90c000 {
|
||||
+ compatible = "rockchip,cspmu";
|
||||
+ reg = <0x0 0xfd90c000 0x0 0x1000>,
|
||||
+ <0x0 0xfd90d000 0x0 0x1000>,
|
||||
+ <0x0 0xfd90e000 0x0 0x1000>,
|
||||
+ <0x0 0xfd90f000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ rknpu_reserved: rknpu {
|
||||
+ compatible = "shared-dma-pool";
|
||||
+ inactive;
|
||||
+ reusable;
|
||||
+ size = <0x0 0x20000000>;
|
||||
+ alignment = <0x0 0x1000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809_sound: rk809-sound {
|
||||
+ status = "disabled";
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,name = "rockchip,rk809-codec";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s1_8ch>;
|
||||
+ };
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&rk809_codec>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+
|
||||
+ /*
|
||||
+ * On the module itself this is one of these (depending
|
||||
+ * on the actual card populated):
|
||||
+ * - SDIO_RESET_L_WL_REG_ON
|
||||
+ * - PDN (power down when low)
|
||||
+ */
|
||||
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //WIFI_REG_ON_H
|
||||
+ };
|
||||
+
|
||||
+ wireless_wlan: wireless-wlan {
|
||||
+ compatible = "wlan-platdata";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "clk_wifi";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ wifi_chip_type = "ap6256";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
+ WIFI,host_wake_irq = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //WIFI_WAKE_HOST_H
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ bt_uart8: wireless_bluetooth: wireless-bluetooth {
|
||||
+ compatible = "bluetooth-platdata";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ //wifi-bt-power-toggle;
|
||||
+ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default", "rts_gpio";
|
||||
+ pinctrl-0 = <&uart8m0_rtsn>;
|
||||
+ pinctrl-1 = <&uart8_gpios>;
|
||||
+ BT,reset_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //BT_REG_ON_H
|
||||
+ BT,wake_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; //HOST_WAKE_BT_H
|
||||
+ BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; //BT_WAKE_HOST_H
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ gpio_leds: gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ status = "okay";
|
||||
+ user_leds: user-led {
|
||||
+ gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "timer";
|
||||
+ default-state = "on";
|
||||
+ pinctrl-0 = <&user_led>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ status = "okay";
|
||||
+ pmuio2-supply = <&vcc_3v3>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&dfi {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&dmc {
|
||||
+ center-supply = <&vdd_logic>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ clock-names = "gpu", "bus";
|
||||
+ interrupt-names = "gpu", "mmu", "job";
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: tcs4525@1c {
|
||||
+ compatible = "tcs,tcs452x";
|
||||
+ reg = <0x1c>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ regulator-compatible = "fan53555-reg";
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1390000>;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-always-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+
|
||||
+ pinctrl-names = "default", "pmic-sleep",
|
||||
+ "pmic-power-off", "pmic-reset";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
|
||||
+ pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
|
||||
+ pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
|
||||
+
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
+ //fb-inner-reg-idxs = <2>;
|
||||
+ /* 1: rst regs (default in codes), 0: rst the pmic */
|
||||
+ pmic-reset-func = <0>;
|
||||
+ /* not save the PMIC_POWER_EN register in uboot */
|
||||
+ not-save-power-en = <1>;
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ pwrkey {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ pinctrl_rk8xx: pinctrl_rk8xx {
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ rk817_slppin_null: rk817_slppin_null {
|
||||
+ pins = "gpio_slp";
|
||||
+ function = "pin_fun0";
|
||||
+ };
|
||||
+
|
||||
+ rk817_slppin_slp: rk817_slppin_slp {
|
||||
+ pins = "gpio_slp";
|
||||
+ function = "pin_fun1";
|
||||
+ };
|
||||
+
|
||||
+ rk817_slppin_pwrdn: rk817_slppin_pwrdn {
|
||||
+ pins = "gpio_slp";
|
||||
+ function = "pin_fun2";
|
||||
+ };
|
||||
+
|
||||
+ rk817_slppin_rst: rk817_slppin_rst {
|
||||
+ pins = "gpio_slp";
|
||||
+ function = "pin_fun3";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-boot-on;
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ rk809_codec: codec {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
|
||||
+ clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ clock-names = "mclk";
|
||||
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s1m0_mclk>;
|
||||
+ hp-volume = <20>;
|
||||
+ spk-volume = <3>;
|
||||
+ mic-in-differential;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ status = "disabled";
|
||||
+ rockchip,clk-trcm = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s1m0_sclktx
|
||||
+ &i2s1m0_lrcktx
|
||||
+ &i2s1m0_sdi0
|
||||
+ &i2s1m0_sdo0>;
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ phy-mode = "rgmii";
|
||||
+ clock_in_out = "output";
|
||||
+
|
||||
+ snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus>;
|
||||
+
|
||||
+ tx_delay = <0x44>;
|
||||
+ rx_delay = <0x26>;
|
||||
+
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ rgmii_phy1: phy@0 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&iep {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&iep_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&jpegd {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&jpegd_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mpp_srv {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rk_rga {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkvdec {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkvdec_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkvenc {
|
||||
+ venc-supply = <&vdd_logic>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkvenc_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&bus_npu {
|
||||
+ bus-supply = <&vdd_logic>;
|
||||
+ pvtm-supply = <&vdd_cpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rknpu {
|
||||
+ memory-region = <&rknpu_reserved>;
|
||||
+ rknpu-supply = <&vdd_npu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rknpu_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ status = "okay";
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ supports-emmc;
|
||||
+ non-removable;
|
||||
+ max-frequency = <200000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//wifi
|
||||
+&sdmmc2 {
|
||||
+ max-frequency = <150000000>;
|
||||
+ supports-sdio;
|
||||
+ bus-width = <4>;
|
||||
+ disable-wp;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sfc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vdpu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vdpu_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vepu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vepu_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ status = "okay";
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkisp {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rkisp_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//bt
|
||||
+&uart8 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
|
||||
+};
|
||||
+
|
||||
+&reserved_memory {
|
||||
+ ramoops: ramoops@110000 {
|
||||
+ compatible = "ramoops";
|
||||
+ reg = <0x0 0x110000 0x0 0xf0000>;
|
||||
+ record-size = <0x20000>;
|
||||
+ console-size = <0x80000>;
|
||||
+ ftrace-size = <0x00000>;
|
||||
+ pmsg-size = <0x50000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&rng {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&rockchip_suspend {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ soc_slppin_gpio: soc_slppin_gpio {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ soc_slppin_slp: soc_slppin_slp {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA2 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ soc_slppin_rst: soc_slppin_rst {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA2 2 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-bluetooth {
|
||||
+ uart8_gpios: uart8-gpios {
|
||||
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ user_led: user-led {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@@ -0,0 +1,106 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi
|
||||
new file mode 100644
|
||||
index 0000000..b98b78e
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a-display.dtsi
|
||||
@@ -0,0 +1,100 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Radxa Limited.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "radxa,rock-3a", "rockchip,rk3568";
|
||||
+
|
||||
+ vcc_mipi: vcc-mipi {
|
||||
+ status = "disabled";
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_mipi";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ regulator-always-on;
|
||||
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&video_phy1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&dsi1 {
|
||||
+ status = "disabled";
|
||||
+ power-supply = <&vcc_mipi>;
|
||||
+
|
||||
+ dsi1_panel: dsi-panel@0 {
|
||||
+ compatible = "rockpi,tc358762";
|
||||
+ reg = <0x0>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ port@0 {
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ panel_in_dsi1: endpoint {
|
||||
+ remote-endpoint = <&dsi1_out_panel>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ port@1 {
|
||||
+ reg = <1>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ dsi1_out_panel: endpoint@0 {
|
||||
+ reg = <0>;
|
||||
+ remote-endpoint = <&panel_in_dsi1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&dsi1_in_vp0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&dsi1_in_vp1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&route_dsi1 {
|
||||
+ status = "disabled";
|
||||
+ connect = <&vp1_out_dsi1>;
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ status = "disabled";
|
||||
+ pinctrl-0 = <&i2c3m1_xfer>;
|
||||
+
|
||||
+ rockpi_mcu: rockpi-mcu@45 {
|
||||
+ compatible = "rockpi_mcu";
|
||||
+ reg = <0x45>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ rockpi_ft5406: rockpi-ft5406@38 {
|
||||
+ compatible = "rockpi_ft5406";
|
||||
+ reg = <0x38>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
@@ -0,0 +1,158 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi
|
||||
new file mode 100644
|
||||
index 0000000..5ceac78
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3ab-cameras.dtsi
|
||||
@@ -0,0 +1,152 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Radxa Limited.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/ {
|
||||
+ ext_cam_clk: ext-cam-clk {
|
||||
+ status = "disabled";
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <25000000>;
|
||||
+ clock-output-names = "ext_cam_clk";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ext_cam_clk_imx219: ext-cam-clk-imx219 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <24000000>;
|
||||
+ clock-output-names = "ext_cam_clk_imx219";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_camera: vcc-camera {
|
||||
+ status = "disabled";
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_camera";
|
||||
+ gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
+ enable-active-high;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ status = "disabled";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2c5m0_xfer>;
|
||||
+
|
||||
+ ov5647: ov5647@36 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "ovti,ov5647";
|
||||
+ reg = <0x36>;
|
||||
+
|
||||
+ clocks = <&ext_cam_clk>;
|
||||
+ clock-names = "ext_cam_clk";
|
||||
+ pwdn-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ port {
|
||||
+ ov5647_out: endpoint {
|
||||
+ remote-endpoint = <&mipi_in_ucam0>;
|
||||
+ data-lanes = <1 2>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ imx219: imx219@10 {
|
||||
+ status = "disabled";
|
||||
+ compatible = "sony,imx219";
|
||||
+ reg = <0x10>;
|
||||
+
|
||||
+ clocks = <&ext_cam_clk_imx219>;
|
||||
+ clock-names = "ext_cam_clk_imx219";
|
||||
+ pwdn-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+
|
||||
+ rockchip,camera-module-index = <1>;
|
||||
+ rockchip,camera-module-facing = "front";
|
||||
+ rockchip,camera-module-name = "rpi-camera-v2";
|
||||
+ rockchip,camera-module-lens-name = "default";
|
||||
+
|
||||
+ port {
|
||||
+ imx219_out: endpoint {
|
||||
+ remote-endpoint = <&mipi_in_ucam1>;
|
||||
+ data-lanes = <1 2>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&csi2_dphy_hw {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&csi2_dphy0 {
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ port@0 {
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ mipi_in_ucam0: endpoint@1 {
|
||||
+ reg = <1>;
|
||||
+ remote-endpoint = <&ov5647_out>;
|
||||
+ data-lanes = <1 2>;
|
||||
+ };
|
||||
+
|
||||
+ mipi_in_ucam1: endpoint@2 {
|
||||
+ reg = <2>;
|
||||
+ remote-endpoint = <&imx219_out>;
|
||||
+ data-lanes = <1 2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ port@1 {
|
||||
+ reg = <1>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ dphy0_out: endpoint@1 {
|
||||
+ reg = <1>;
|
||||
+ remote-endpoint = <&isp0_in>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&rkisp_vir0 {
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ port {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ isp0_in: endpoint@0 {
|
||||
+ reg = <0>;
|
||||
+ remote-endpoint = <&dphy0_out>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&rkisp {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&rkisp_mmu {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&rkcif_mmu {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&rkcif {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
@@ -1 +1 @@
|
||||
archive/rk35xx-4.19
|
||||
archive/rk35xx-5.10
|
||||
19
patch/u-boot/legacy/board_radxa-e25/fix-vcc3v3.patch
Normal file
19
patch/u-boot/legacy/board_radxa-e25/fix-vcc3v3.patch
Normal file
@@ -0,0 +1,19 @@
|
||||
diff --git a/arch/arm/dts/rk3568-radxa-rock-3-compute-module-plus.dtsi b/arch/arm/dts/rk3568-radxa-rock-3-compute-module-plus.dtsi
|
||||
index e2cdda8a..15d7b41f 100644
|
||||
--- a/arch/arm/dts/rk3568-radxa-rock-3-compute-module-plus.dtsi
|
||||
+++ b/arch/arm/dts/rk3568-radxa-rock-3-compute-module-plus.dtsi
|
||||
@@ -372,6 +372,7 @@
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-state-mem {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
@@ -418,4 +419,4 @@
|
||||
<0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
-};
|
||||
\ No newline at end of file
|
||||
+};
|
||||
Reference in New Issue
Block a user