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https://github.com/LibreELEC/LibreELEC.tv
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112 lines
4.0 KiB
Diff
112 lines
4.0 KiB
Diff
From a8c11ce34a3526c1f1bd528e700ac4ffab28a821 Mon Sep 17 00:00:00 2001
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From: Detlev Casanova <detlev.casanova@collabora.com>
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Date: Mon, 23 Jun 2025 12:07:17 -0400
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Subject: [PATCH 007/113] FROMGIT(6.18): arm64: dts: rockchip: Add the vdpu381
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Video Decoders on RK3588
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Add the vdpu381 Video Decoders to the rk3588-base devicetree.
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The RK3588 based SoCs all embed 2 vdpu381 decoders.
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This also adds the dedicated IOMMU controllers.
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Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
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1 file changed, 74 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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index 70f03e68ba55..c1eaff86d5b7 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 {
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#iommu-cells = <0>;
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};
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+ vdec0: video-codec@fdc38000 {
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+ compatible = "rockchip,rk3588-vdec";
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+ reg = <0x0 0xfdc38100 0x0 0x500>,
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+ <0x0 0xfdc38000 0x0 0x100>,
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+ <0x0 0xfdc38600 0x0 0x100>;
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+ reg-names = "function", "link", "cache";
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
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+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
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+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
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+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
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+ assigned-clock-rates = <800000000>, <600000000>,
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+ <600000000>, <1000000000>;
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+ iommus = <&vdec0_mmu>;
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+ power-domains = <&power RK3588_PD_RKVDEC0>;
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+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
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+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
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+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ sram = <&vdec0_sram>;
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+ };
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+
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+ vdec0_mmu: iommu@fdc38700 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
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+ clock-names = "aclk", "iface";
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+ power-domains = <&power RK3588_PD_RKVDEC0>;
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+ #iommu-cells = <0>;
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+ };
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+
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+ vdec1: video-codec@fdc40000 {
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+ compatible = "rockchip,rk3588-vdec";
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+ reg = <0x0 0xfdc40100 0x0 0x500>,
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+ <0x0 0xfdc40000 0x0 0x100>,
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+ <0x0 0xfdc40600 0x0 0x100>;
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+ reg-names = "function", "link", "cache";
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+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
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+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
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+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
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+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
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+ assigned-clock-rates = <800000000>, <600000000>,
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+ <600000000>, <1000000000>;
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+ iommus = <&vdec1_mmu>;
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+ power-domains = <&power RK3588_PD_RKVDEC1>;
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+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
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+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
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+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ sram = <&vdec1_sram>;
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+ };
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+
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+ vdec1_mmu: iommu@fdc40700 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
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+ clock-names = "aclk", "iface";
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+ power-domains = <&power RK3588_PD_RKVDEC1>;
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+ #iommu-cells = <0>;
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+ };
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+
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av1d: video-codec@fdc70000 {
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compatible = "rockchip,rk3588-av1-vpu";
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reg = <0x0 0xfdc70000 0x0 0x800>;
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@@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 {
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ranges = <0x0 0x0 0xff001000 0xef000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ vdec0_sram: codec-sram@0 {
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+ reg = <0x0 0x78000>;
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+ pool;
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+ };
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+
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+ vdec1_sram: codec-sram@78000 {
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+ reg = <0x78000 0x77000>;
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+ pool;
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+ };
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};
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pinctrl: pinctrl {
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--
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2.34.1
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