91d759d5a2
reference: - https://www.spinics.net/lists/arm-kernel/msg934335.html This series adds a new devfreq driver for the MBUS/DRAM controller in some Allwinner SoCs, and enables it for the A64 and H5. The binding and DTs are updated in patches 1-5. The MBUS nodes already existed, but were not bound to any driver before; they were only used for their dma-ranges property. Finally, the driver is added in patch 6. I am not quite sure the best way to handle DRAM register range in the DT binding -- as a separate reg property, a separate node, or simply enlarging the MBUS register range. While the DRAM controller is a separate IP block, the MBUS hardware has the ability to double-buffer certain DRAM controller registers, and the hardware MDFS process writes to some DRAM controller registers as well. So they are rather tightly integrated. Like the driver commit description says, this driver could support additional SoCs: at least A33, A83T, and H3. I can send follow-up patches adding compatibles for these, but I cannot test A33 or A83T. - https://www.spinics.net/lists/arm-kernel/msg934341.html This driver works by adjusting the divider on the DRAM controller's module clock. Thus there is no fixed set of OPPs, only "full speed" down to "quarter speed" (or whatever the maximum divider is on that variant). It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which takes care of updating registers during the critical section while DRAM is inaccessible. This driver should support several sunxi SoCs, starting with the A33, which have a DesignWare DDR3 controller with merged PHY register space and the matching MBUS register layout (so not A63 or later). However, the driver has only been tested on the A64/H5, so those are the only compatibles enabled for now.
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