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https://github.com/LibreELEC/LibreELEC.tv
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168 lines
5.0 KiB
Diff
168 lines
5.0 KiB
Diff
From 24fc7c42d539648a107ab7096d45cfdab0647707 Mon Sep 17 00:00:00 2001
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From: Quentin Schulz <quentin.schulz@cherry.de>
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Date: Tue, 10 Jun 2025 11:42:50 +0200
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Subject: [PATCH 54/84] rockchip: px30/rk3326: Implement checkboard() to print
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SoC variant
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This implements checkboard() to print the current SoC model used by a
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board, e.g. one of:
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SoC: PX30
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SoC: PX30S
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SoC: PX30K
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SoC: RK3326
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SoC: RK3326S
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when U-Boot proper is running.
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The information is read from the OTP and also the DDR_GRF. There's no
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public information as far as I know about the layout and stored
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information on OTP but this was provided by Rockchip themselves through
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their support channel.
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The OTP stores the information of whether the SoC is PX30K or something
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else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
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to read some undocumented bitfield in a DDR_GRF register as done in
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vendor kernel,
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c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
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I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
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properly.
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Also add the OTP node to the pre-relocation phase of U-Boot proper so
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that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
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This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
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happens after relocation. If both are enabled, then the SoC variant will
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be printed twice in the boot log, e.g.:
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U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200)
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Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
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SoC: PX30 <---- due to DISPLAY_BOARDINFO
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DRAM: 2 GiB
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PMIC: RK809 (on=0x40, off=0x00)
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Core: 293 devices, 27 uclasses, devicetree: separate
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MMC: mmc@ff370000: 1, mmc@ff390000: 0
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Loading Environment from MMC... Reading from MMC(1)... OK
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In: serial@ff030000
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Out: serial@ff030000
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Err: serial@ff030000
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Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
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SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE
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Net: eth0: ethernet@ff360000
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Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
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Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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arch/arm/dts/px30-u-boot.dtsi | 4 ++
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arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++
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2 files changed, 65 insertions(+)
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diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
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index 157d0ea6930..2f726b0aaba 100644
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--- a/arch/arm/dts/px30-u-boot.dtsi
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+++ b/arch/arm/dts/px30-u-boot.dtsi
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@@ -27,6 +27,10 @@
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};
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};
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+&otp {
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+ bootph-some-ram;
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+};
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+
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&uart2 {
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clock-frequency = <24000000>;
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bootph-all;
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diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
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index 8ce9ac561f0..5a5c119328f 100644
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--- a/arch/arm/mach-rockchip/px30/px30.c
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+++ b/arch/arm/mach-rockchip/px30/px30.c
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@@ -2,10 +2,14 @@
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/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*/
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+
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+#define LOG_CATEGORY LOGC_ARCH
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+
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#include <clk.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <init.h>
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+#include <misc.h>
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#include <spl.h>
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#include <asm/armv8/mmu.h>
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#include <asm/arch-rockchip/bootrom.h>
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@@ -15,6 +19,7 @@
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_px30.h>
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#include <dt-bindings/clock/px30-cru.h>
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+#include <linux/bitfield.h>
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
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@@ -442,3 +447,59 @@ void board_debug_uart_init(void)
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#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
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}
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#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
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+
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+#define PX30_OTP_SPECIFICATION_OFFSET 0x06
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+
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+#define DDR_GRF_BASE_ADDR 0xff630000
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+#define DDR_GRF_CON(n) (0 + (n) * 4)
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+
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+int checkboard(void)
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+{
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+ struct udevice *dev;
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+ u8 specification;
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+ u32 base_soc;
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+ int ret;
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+
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+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
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+ return 0;
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_DRIVER_GET(rockchip_otp), &dev);
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+ if (ret) {
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+ log_debug("Could not find otp device, ret=%d\n", ret);
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+ return 0;
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+ }
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+
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+ /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
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+ ret = misc_read(dev, 0, &base_soc, 4);
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+ if (ret < 0) {
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+ log_debug("Could not read specification, ret=%d\n", ret);
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+ return 0;
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+ }
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+
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+ if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
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+ log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
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+ return 0;
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+ }
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+
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+ /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
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+ ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
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+ if (ret < 0) {
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+ log_debug("Could not read specification, ret=%d\n", ret);
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+ return 0;
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+ }
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+
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+ if (specification == 0x2b) {
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+ printf("SoC: PX30K\n");
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+ return 0;
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+ }
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+
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+ /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
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+ specification = FIELD_GET(GENMASK(15, 14),
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+ readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
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+ log_debug("DDR specification is %d\n", specification);
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+ printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
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+ specification == 0x3 ? "S" : "");
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+
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+ return 0;
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+}
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--
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2.34.1
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