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https://github.com/LibreELEC/LibreELEC.tv
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160 lines
3.8 KiB
Diff
160 lines
3.8 KiB
Diff
From 87ec15bbdc953d552dde11a5772b1e3dadc855f4 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Mon, 21 Jul 2025 22:07:13 +0000
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Subject: [PATCH 05/84] phy: rockchip: naneng-combphy: Simplify init ops
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The init ops for Rockchip COMBPHY driver is more complex than it needs
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to be, e.g. declaring multiple init functions that only differ in the
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error message.
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Simplify the init ops based on code from the Linux mainline driver.
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This change also ensure that errors returned from combphy_cfg() and
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reset_deassert_bulk() is propertly propagated to the caller. No other
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runtime change is expected with this simplication.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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.../rockchip/phy-rockchip-naneng-combphy.c | 101 ++++--------------
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1 file changed, 19 insertions(+), 82 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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index a3038d067d3..f246c8db2d6 100644
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--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -98,104 +98,41 @@ static int param_write(struct regmap *base,
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return regmap_write(base, reg->offset, val);
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}
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-static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
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-{
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- int ret = 0;
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-
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- if (priv->cfg->combphy_cfg) {
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- ret = priv->cfg->combphy_cfg(priv);
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- if (ret) {
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- dev_err(priv->dev, "failed to init phy for pcie\n");
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- return ret;
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- }
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- }
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-
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- return ret;
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-}
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-
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-static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
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-{
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- int ret = 0;
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-
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- if (priv->cfg->combphy_cfg) {
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- ret = priv->cfg->combphy_cfg(priv);
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- if (ret) {
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- dev_err(priv->dev, "failed to init phy for usb3\n");
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- return ret;
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- }
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- }
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-
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- return ret;
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-}
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-
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-static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
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-{
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- int ret = 0;
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-
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- if (priv->cfg->combphy_cfg) {
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- ret = priv->cfg->combphy_cfg(priv);
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- if (ret) {
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- dev_err(priv->dev, "failed to init phy for sata\n");
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- return ret;
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- }
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- }
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-
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- return ret;
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-}
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-
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-static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
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+static int rockchip_combphy_init(struct phy *phy)
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{
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- int ret = 0;
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-
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- if (priv->cfg->combphy_cfg) {
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- ret = priv->cfg->combphy_cfg(priv);
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- if (ret) {
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- dev_err(priv->dev, "failed to init phy for sgmii\n");
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- return ret;
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- }
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- }
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+ struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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+ int ret;
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- return ret;
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-}
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+ ret = clk_enable(&priv->ref_clk);
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+ if (ret < 0 && ret != -ENOSYS)
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+ return ret;
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-static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
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-{
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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- rockchip_combphy_pcie_init(priv);
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- break;
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case PHY_TYPE_USB3:
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- rockchip_combphy_usb3_init(priv);
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- break;
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case PHY_TYPE_SATA:
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- rockchip_combphy_sata_init(priv);
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- break;
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case PHY_TYPE_SGMII:
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case PHY_TYPE_QSGMII:
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- return rockchip_combphy_sgmii_init(priv);
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+ if (priv->cfg->combphy_cfg)
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+ ret = priv->cfg->combphy_cfg(priv);
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+ else
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+ ret = 0;
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+ break;
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default:
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dev_err(priv->dev, "incompatible PHY type\n");
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- return -EINVAL;
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+ ret = -EINVAL;
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+ break;
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}
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- return 0;
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-}
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-
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-static int rockchip_combphy_init(struct phy *phy)
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-{
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- struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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- int ret;
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-
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- ret = clk_enable(&priv->ref_clk);
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- if (ret < 0 && ret != -ENOSYS)
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- return ret;
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+ if (ret) {
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+ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode);
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+ goto err_clk;
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+ }
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- ret = rockchip_combphy_set_mode(priv);
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+ ret = reset_deassert_bulk(&priv->phy_rsts);
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if (ret)
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goto err_clk;
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- reset_deassert_bulk(&priv->phy_rsts);
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-
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return 0;
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err_clk:
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@@ -305,7 +242,7 @@ static int rockchip_combphy_probe(struct udevice *udev)
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}
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priv->dev = udev;
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- priv->mode = PHY_TYPE_SATA;
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+ priv->mode = PHY_NONE;
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priv->cfg = phy_cfg;
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return rockchip_combphy_parse_dt(udev, priv);
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--
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2.34.1
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