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38 lines
1.5 KiB
Diff
38 lines
1.5 KiB
Diff
From 78e2b1bdd84264d6a9d84759da26547f887552cd Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue, 16 Dec 2014 08:44:32 +0000
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Subject: [PATCH] drm/i915: Force the CS stall for invalidate flushes
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In order to act as a full command barrier by itself, we need to tell the
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pipecontrol to actually stall the command streamer while the flush runs.
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We require the full command barrier before operations like
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MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
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References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
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Cc: Simon Farnsworth <simon@farnz.org.uk>
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Cc: Daniel Vetter <daniel@ffwll.ch>
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Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Cc: stable@vger.kernel.org
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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---
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drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
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index b02cf69..ae17e77 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
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@@ -369,6 +369,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
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flags |= PIPE_CONTROL_QW_WRITE;
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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+ flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
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+
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/* Workaround: we must issue a pipe_control with CS-stall bit
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* set before a pipe_control command that has the state cache
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* invalidate bit set. */
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