mirror of
https://github.com/LibreELEC/LibreELEC.tv
synced 2025-09-24 19:46:01 +07:00
41 lines
1.6 KiB
Diff
41 lines
1.6 KiB
Diff
From 14b4f30929d8d88f850e012e2abfe07c7b11ff33 Mon Sep 17 00:00:00 2001
|
|
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
|
Date: Tue, 8 Jul 2025 20:12:00 +0300
|
|
Subject: [PATCH 103/110] [WIP-FRL] arm64: dts: rockchip: Assign ACLK_VOP to
|
|
750 MHz on rk3588
|
|
|
|
In preparation to support HDMI 2.1 display modes on RK3588, e.g.
|
|
4K@120Hz, increase ACLK_VOP from the default 500 MHz to 750 MHz.
|
|
|
|
This resolves some VOP2 rendering artifacts and helps get rid of a bunch
|
|
of DRM errors:
|
|
|
|
rockchip-drm display-subsystem: [drm] *ERROR* POST_BUF_EMPTY irq err at vp0
|
|
|
|
TODO: In order to optimize the power consumption, consider the approach
|
|
of dynamically adjusting the clock, i.e. increase rate to 750 MHz when
|
|
operating in FRL mode and decrease it back to 500 MHz for TMDS.
|
|
|
|
Suggested-by: Algea Cao <algea.cao@rock-chips.com>
|
|
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 ++
|
|
1 file changed, 2 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
|
index 3bd1b5e3b101..d4d66e456069 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
|
@@ -1436,6 +1436,8 @@ vop: vop@fdd90000 {
|
|
reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
|
reg-names = "vop", "gamma-lut";
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ assigned-clocks = <&cru ACLK_VOP>;
|
|
+ assigned-clock-rates = <750000000>;
|
|
clocks = <&cru ACLK_VOP>,
|
|
<&cru HCLK_VOP>,
|
|
<&cru DCLK_VOP0>,
|
|
--
|
|
2.34.1
|
|
|