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https://github.com/LibreELEC/LibreELEC.tv
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126 lines
4.4 KiB
Diff
126 lines
4.4 KiB
Diff
From 5bd6f7efb942d73f95ec7d384c6ef6fecdabf226 Mon Sep 17 00:00:00 2001
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From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
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Date: Mon, 21 Jul 2025 11:17:35 +0200
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Subject: [PATCH 017/110] FROMGIT(6.18): arm64: dts: rockchip: Add nodes for
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NPU and its MMU to rk3588-base
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See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
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The IP is divided in three cores, programmed independently. The first
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core though is special, being able to delegate work to the other cores.
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The IOMMU of the first core is also special in that it has two subunits
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(read/write?) that need to be programmed in sync.
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Tested-by: Heiko Stuebner <heiko@sntech.de>
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Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
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---
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arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++
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1 file changed, 91 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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index 3707aa1af785..56bf903eb04f 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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@@ -1140,6 +1140,97 @@ power-domain@RK3588_PD_SDMMC {
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};
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};
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+ rknn_core_0: npu@fdab0000 {
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+ compatible = "rockchip,rk3588-rknn-core";
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+ reg = <0x0 0xfdab0000 0x0 0x1000>,
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+ <0x0 0xfdab1000 0x0 0x1000>,
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+ <0x0 0xfdab3000 0x0 0x1000>;
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+ reg-names = "pc", "cna", "core";
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
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+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
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+ clock-names = "aclk", "hclk", "npu", "pclk";
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+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
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+ assigned-clock-rates = <200000000>;
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+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
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+ reset-names = "srst_a", "srst_h";
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+ power-domains = <&power RK3588_PD_NPUTOP>;
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+ iommus = <&rknn_mmu_0>;
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+ status = "disabled";
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+ };
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+
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+ rknn_mmu_0: iommu@fdab9000 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdab9000 0x0 0x100>,
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+ <0x0 0xfdaba000 0x0 0x100>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
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+ clock-names = "aclk", "iface";
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+ #iommu-cells = <0>;
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+ power-domains = <&power RK3588_PD_NPUTOP>;
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+ status = "disabled";
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+ };
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+
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+ rknn_core_1: npu@fdac0000 {
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+ compatible = "rockchip,rk3588-rknn-core";
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+ reg = <0x0 0xfdac0000 0x0 0x1000>,
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+ <0x0 0xfdac1000 0x0 0x1000>,
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+ <0x0 0xfdac3000 0x0 0x1000>;
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+ reg-names = "pc", "cna", "core";
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+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>,
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+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
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+ clock-names = "aclk", "hclk", "npu", "pclk";
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+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
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+ assigned-clock-rates = <200000000>;
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+ resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>;
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+ reset-names = "srst_a", "srst_h";
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+ power-domains = <&power RK3588_PD_NPU1>;
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+ iommus = <&rknn_mmu_1>;
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+ status = "disabled";
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+ };
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+
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+ rknn_mmu_1: iommu@fdac9000 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdaca000 0x0 0x100>;
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+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
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+ clock-names = "aclk", "iface";
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+ #iommu-cells = <0>;
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+ power-domains = <&power RK3588_PD_NPU1>;
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+ status = "disabled";
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+ };
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+
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+ rknn_core_2: npu@fdad0000 {
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+ compatible = "rockchip,rk3588-rknn-core";
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+ reg = <0x0 0xfdad0000 0x0 0x1000>,
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+ <0x0 0xfdad1000 0x0 0x1000>,
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+ <0x0 0xfdad3000 0x0 0x1000>;
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+ reg-names = "pc", "cna", "core";
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>,
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+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
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+ clock-names = "aclk", "hclk", "npu", "pclk";
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+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
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+ assigned-clock-rates = <200000000>;
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+ resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>;
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+ reset-names = "srst_a", "srst_h";
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+ power-domains = <&power RK3588_PD_NPU2>;
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+ iommus = <&rknn_mmu_2>;
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+ status = "disabled";
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+ };
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+
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+ rknn_mmu_2: iommu@fdad9000 {
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+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfdada000 0x0 0x100>;
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
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+ clock-names = "aclk", "iface";
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+ #iommu-cells = <0>;
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+ power-domains = <&power RK3588_PD_NPU2>;
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+ status = "disabled";
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+ };
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+
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vpu121: video-codec@fdb50000 {
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compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
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reg = <0x0 0xfdb50000 0x0 0x800>;
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--
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2.34.1
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