mirror of
https://github.com/armbian/build
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48 lines
1.5 KiB
Diff
48 lines
1.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Joshua Riek <jjriek@verizon.net>
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Date: Wed, 7 Aug 2024 10:19:47 -0400
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Subject: arm64: dts: rockchip: Split pcie30x1m1 pinctrl
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The PCIe 3.0 PHYs need an external clock and will assert CLKREQ# to
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get it. Some RK3588 boards such as the Turning RK1, Mixtile 3588E,
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and the ArmSoM AIM7 only provide this clock when CLKREQ# is asserted.
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Signed-off-by: Joshua Riek <jjriek@verizon.net>
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---
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arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 16 ++++++++--
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1 file changed, 13 insertions(+), 3 deletions(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
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index 111111111111..222222222222 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
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@@ -1799,12 +1799,22 @@ pcie30x4m0_pins: pcie30x4m0-pins {
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};
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/omit-if-no-ref/
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- pcie30x4m1_pins: pcie30x4m1-pins {
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+ pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
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rockchip,pins =
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/* pcie30x4_clkreqn_m1 */
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- <4 RK_PB4 4 &pcfg_pull_none>,
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+ <4 RK_PB4 4 &pcfg_pull_down>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4_perstn_m1: pcie30x4-perstn-m1 {
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+ rockchip,pins =
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/* pcie30x4_perstn_m1 */
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- <4 RK_PB6 4 &pcfg_pull_none>,
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+ <4 RK_PB6 4 &pcfg_pull_none>;
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+ };
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+
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+ /omit-if-no-ref/
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+ pcie30x4_waken_m1: pcie30x4-waken-m1 {
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+ rockchip,pins =
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/* pcie30x4_waken_m1 */
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<4 RK_PB5 4 &pcfg_pull_none>;
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};
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--
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Armbian
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