mirror of
https://github.com/armbian/build
synced 2025-09-24 19:47:06 +07:00
764 lines
21 KiB
Diff
764 lines
21 KiB
Diff
From de6c467b764ac5cd739a2072c1209029fe615a1d Mon Sep 17 00:00:00 2001
|
|
From: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
|
|
Date: Wed, 10 Jan 2024 13:16:31 +0100
|
|
Subject: [PATCH] arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314
|
|
|
|
This adds support for TQMa8MPQL module on MBa8MP-RAS314 board.
|
|
|
|
Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
|
|
---
|
|
arch/arm64/boot/dts/freescale/Makefile | 1 +
|
|
.../imx8mp-tqma8mpql-mba8mp-ras314.dts | 728 ++++++++++++++++++
|
|
2 files changed, 729 insertions(+)
|
|
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
|
|
|
|
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
|
|
index 89aee6c92576..8ebaf3aa9ad7 100644
|
|
--- a/arch/arm64/boot/dts/freescale/Makefile
|
|
+++ b/arch/arm64/boot/dts/freescale/Makefile
|
|
@@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
|
|
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
|
|
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
|
|
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
|
|
new file mode 100644
|
|
index 000000000000..b7c45d0a3bcd
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
|
|
@@ -0,0 +1,728 @@
|
|
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
+/*
|
|
+ * Copyright 2021-2022 TQ-Systems GmbH
|
|
+ * Author: Alexander Stein <alexander.stein@tq-group.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include <dt-bindings/leds/common.h>
|
|
+#include <dt-bindings/net/ti-dp83867.h>
|
|
+#include <dt-bindings/phy/phy-imx8-pcie.h>
|
|
+#include <dt-bindings/pwm/pwm.h>
|
|
+#include "imx8mp-tqma8mpql.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
|
|
+ compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart4;
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ mmc0 = &usdhc3;
|
|
+ mmc1 = &usdhc2;
|
|
+ mmc2 = &usdhc1;
|
|
+ rtc0 = &pcf85063;
|
|
+ rtc1 = &snvs_rtc;
|
|
+ };
|
|
+
|
|
+ gpio-leds {
|
|
+ compatible = "gpio-leds";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpioled>;
|
|
+
|
|
+ led-1 {
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ led-2 {
|
|
+ color = <LED_COLOR_ID_YELLOW>;
|
|
+ gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reg_usdhc2_vmmc: regulator-usdhc2 {
|
|
+ compatible = "regulator-fixed";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
|
+ regulator-name = "VSD_3V3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
|
+ enable-active-high;
|
|
+ startup-delay-us = <100>;
|
|
+ off-on-delay-us = <12000>;
|
|
+ };
|
|
+
|
|
+ reg_vcc_3v3: regulator-3v3 {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "VCC_3V3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ };
|
|
+
|
|
+ reg_vcc_5v0: regulator-5v0 {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "VCC_5V0";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ ocram: ocram@900000 {
|
|
+ no-map;
|
|
+ reg = <0 0x900000 0 0x70000>;
|
|
+ };
|
|
+
|
|
+ /* global autoconfigured region for contiguous allocations */
|
|
+ linux,cma {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reusable;
|
|
+ size = <0 0x38000000>;
|
|
+ alloc-ranges = <0 0x40000000 0 0xB0000000>;
|
|
+ linux,cma-default;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ compatible = "fsl,imx-audio-tlv320aic32x4";
|
|
+ model = "tq-tlv320aic32x";
|
|
+ audio-cpu = <&sai5>;
|
|
+ audio-codec = <&tlv320aic3x04>;
|
|
+ audio-routing =
|
|
+ "IN3_L", "Mic Jack",
|
|
+ "Mic Jack", "Mic Bias",
|
|
+ "IN1_L", "Line In Jack",
|
|
+ "IN1_R", "Line In Jack",
|
|
+ "Line Out Jack", "LOL",
|
|
+ "Line Out Jack", "LOR";
|
|
+
|
|
+ };
|
|
+
|
|
+ thermal-zones {
|
|
+ soc-thermal {
|
|
+ trips {
|
|
+ soc_active0: trip-active0 {
|
|
+ temperature = <40000>;
|
|
+ hysteresis = <5000>;
|
|
+ type = "active";
|
|
+ };
|
|
+
|
|
+ soc_active1: trip-active1 {
|
|
+ temperature = <48000>;
|
|
+ hysteresis = <3000>;
|
|
+ type = "active";
|
|
+ };
|
|
+
|
|
+ soc_active2: trip-active2 {
|
|
+ temperature = <60000>;
|
|
+ hysteresis = <10000>;
|
|
+ type = "active";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ecspi3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_ecspi3>;
|
|
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
|
|
+ status = "okay";
|
|
+
|
|
+ spidev@0 {
|
|
+ reg = <0>; /* Chip Select 0 */
|
|
+ compatible = "rohm,dh2228fv";
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&eqos {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
|
|
+ phy-mode = "rgmii-id";
|
|
+ phy-handle = <ðphy3>;
|
|
+ status = "okay";
|
|
+
|
|
+ mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ethphy3: ethernet-phy@3 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <3>;
|
|
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
+ ti,dp83867-rxctrl-strap-quirk;
|
|
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
|
+ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
|
+ reset-assert-us = <500000>;
|
|
+ reset-deassert-us = <50000>;
|
|
+ enet-phy-lane-no-swap;
|
|
+ interrupt-parent = <&gpio4>;
|
|
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&fec {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
|
|
+ phy-mode = "rgmii-id";
|
|
+ phy-handle = <ðphy0>;
|
|
+ fsl,magic-packet;
|
|
+ status = "okay";
|
|
+
|
|
+ mdio {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ethphy0: ethernet-phy@0 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <0>;
|
|
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
+ ti,dp83867-rxctrl-strap-quirk;
|
|
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
|
+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
|
|
+ reset-assert-us = <500000>;
|
|
+ reset-deassert-us = <50000>;
|
|
+ enet-phy-lane-no-swap;
|
|
+ interrupt-parent = <&gpio4>;
|
|
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpio1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio1>;
|
|
+
|
|
+ gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "LVDS_BLT_EN",
|
|
+ "", "", "", "LVDS_PWR_EN",
|
|
+ "PMIC_IRQ", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "";
|
|
+};
|
|
+
|
|
+&gpio2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio2>;
|
|
+
|
|
+ gpio-line-names = "", "", "", "",
|
|
+ "", "", "CAM_GPIO1", "CAM_GPIO2",
|
|
+ "", "", "", "",
|
|
+ "USDHC2_CD", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "";
|
|
+};
|
|
+
|
|
+&gpio3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio3>;
|
|
+
|
|
+ gpio-line-names = "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "RTC_EVENT#",
|
|
+ "TEMP_EVENT#", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "";
|
|
+};
|
|
+
|
|
+&gpio4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio4>;
|
|
+
|
|
+ gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "USER_LED1", "USER_LED2",
|
|
+ "HDMI_OC#", "", "", "",
|
|
+ "", "", "GPIO19", "GPIO20",
|
|
+ "", "", "", "";
|
|
+};
|
|
+
|
|
+&gpio5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio5>;
|
|
+
|
|
+ gpio-line-names = "", "GPIO18", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "GPIO21", "CODEC_RST#",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "", "", "",
|
|
+ "", "ECSPI3_SS0", "USB_HUB_RST#", "",
|
|
+ "", "", "", "";
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ clock-frequency = <384000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c2>;
|
|
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
|
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ status = "okay";
|
|
+
|
|
+ /* NXP SE97BTP with temperature sensor + eeprom */
|
|
+ se97_1c: temperature-sensor-eeprom@1c {
|
|
+ compatible = "nxp,se97", "jedec,jc-42.4-temp";
|
|
+ reg = <0x1c>;
|
|
+ };
|
|
+
|
|
+ at24c02_54: eeprom@54 {
|
|
+ compatible = "nxp,se97b", "atmel,24c02";
|
|
+ reg = <0x54>;
|
|
+ pagesize = <16>;
|
|
+ vcc-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c3 {
|
|
+ clock-frequency = <384000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c3>;
|
|
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
|
+ scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ clock-frequency = <384000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c4>;
|
|
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
|
|
+ scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ status = "okay";
|
|
+
|
|
+ tlv320aic3x04: audio-codec@18 {
|
|
+ compatible = "ti,tlv320aic32x4";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_tlv320aic3x04>;
|
|
+ reg = <0x18>;
|
|
+ clock-names = "mclk";
|
|
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
|
|
+ reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
|
+ iov-supply = <®_vcc_3v3>;
|
|
+ ldoin-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c6 {
|
|
+ clock-frequency = <384000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c6>;
|
|
+ pinctrl-1 = <&pinctrl_i2c6_gpio>;
|
|
+ scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcf85063 {
|
|
+ /* RTC_EVENT# is connected on MBa8MP-RAS314 */
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pcf85063>;
|
|
+ interrupt-parent = <&gpio3>;
|
|
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
|
|
+};
|
|
+
|
|
+&pwm3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwm4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm4>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sai5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_sai5>;
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
|
|
+ assigned-clock-rates = <12288000>;
|
|
+ fsl,sai-mclk-direction-output;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&snvs_pwrkey {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart1>;
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart2>;
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_UART2>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart3>;
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ /* console */
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart4>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb3_0 {
|
|
+ fsl,over-current-active-low;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb3_1 {
|
|
+ fsl,disable-port-power-control;
|
|
+ fsl,permanently-attached;
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb3_phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb3_phy1 {
|
|
+ vbus-supply = <®_vcc_5v0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_dwc3_0 {
|
|
+ dr_mode = "device";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_dwc3_1 {
|
|
+ dr_mode = "host";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_usbhub>;
|
|
+ status = "okay";
|
|
+
|
|
+ hub_2_0: hub@1 {
|
|
+ compatible = "usb451,8142";
|
|
+ reg = <1>;
|
|
+ peer-hub = <&hub_3_0>;
|
|
+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
|
+ vdd-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+
|
|
+ hub_3_0: hub@2 {
|
|
+ compatible = "usb451,8140";
|
|
+ reg = <2>;
|
|
+ peer-hub = <&hub_2_0>;
|
|
+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
|
+ vdd-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&usdhc2 {
|
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
|
+ vmmc-supply = <®_usdhc2_vmmc>;
|
|
+ no-mmc;
|
|
+ no-sdio;
|
|
+ disable-wp;
|
|
+ bus-width = <4>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iomuxc {
|
|
+ pinctrl_ecspi3: ecspi3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>,
|
|
+ <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>,
|
|
+ <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
|
|
+ <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_eqos: eqosgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
|
|
+ <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
|
|
+ <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
|
|
+ <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
|
|
+ <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
|
|
+ <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
|
|
+ <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
|
|
+ <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
|
|
+ <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_eqos_phy: eqosphygrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_fec: fecgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_fec_phy: fecphygrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
|
|
+ <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpioled: gpioledgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio1: gpio1grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>,
|
|
+ <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>,
|
|
+ <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio2: gpio2grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x14>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio3: gpio3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio4: gpio4grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>,
|
|
+ <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x180>,
|
|
+ <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x180>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio5: gpio5grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x10>,
|
|
+ <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x10>;
|
|
+ };
|
|
+
|
|
+ pinctrl_hdmi: hdmigrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
|
|
+ <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
|
|
+ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
|
|
+ <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpt1: gpt1grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpt2: gpt2grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpt3: gpt3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c2: i2c2grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c3: i2c3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c4: i2c4grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>;
|
|
+ };
|
|
+
|
|
+
|
|
+ pinctrl_i2c5: i2c5grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c5_gpio: i2c5-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c6: i2c6grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c6_gpio: i2c6-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_pcf85063: pcf85063grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>;
|
|
+ };
|
|
+
|
|
+ /* X1 - PWM3 */
|
|
+ pinctrl_pwm3: pwm3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>;
|
|
+ };
|
|
+
|
|
+ /* X1 - PWM4 */
|
|
+ pinctrl_pwm4: pwm4grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_reg12v0: reg12v0grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>;
|
|
+ };
|
|
+
|
|
+ pinctrl_sai5: sai5grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>,
|
|
+ <MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>,
|
|
+ <MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>,
|
|
+ <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>,
|
|
+ <MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>;
|
|
+ };
|
|
+
|
|
+ pinctrl_tlv320aic3x04: tlv320aic3x04grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>;
|
|
+ };
|
|
+
|
|
+ /* X1 UART1 */
|
|
+ pinctrl_uart1: uart1grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
|
|
+ };
|
|
+
|
|
+ /* Bluetooth UART2 */
|
|
+ pinctrl_uart2: uart2grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x14>,
|
|
+ <MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x14>;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart3: uart3grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart4: uart4grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>,
|
|
+ <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usbhub: usbhubgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2: usdhc2grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
|
|
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
|
|
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc1: usdhc1grp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>,
|
|
+ <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>,
|
|
+ <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
|
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
|
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
|
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
|
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
|
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
|
+ fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
|
|
+ };
|
|
+};
|
|
--
|
|
2.34.1
|
|
|