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build/patch/kernel/genio-1200-bsp/dt/mt8395-radxa-nio-12l.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2023 Radxa Limited.
*/
/dts-v1/;
#include "mt8195-iot-usb.dtsi"
#include "mt6359.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Radxa NIO 12L";
compatible = "radxa,nio-12l", "mediatek,mt8195";
aliases {
ethernet0 = &eth;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
spi5 = &spi5;
};
soc {
gpu: mali@13000000 {
compatible = "mediatek,mt8195-mali", "arm,mali-midgard";
reg = <0 0x13000000 0 0x4000>;
interrupts =
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names =
"GPU",
"MMU",
"JOB";
/*
* Note: the properties below are not part of the
* upstream binding.
*/
clocks =
<&topckgen CLK_TOP_MFG_CK_FAST_REF>,
<&apmixedsys CLK_APMIXED_MFGPLL>,
<&apmixedsys CLK_APMIXED_MFGPLL>,
<&topckgen CLK_TOP_MFG_CORE_TMP>,
<&mfgcfg CLK_MFG_BG3D>;
clock-names =
"clk_mux",
"clk_pll_src",
"clk_main_parent",
"clk_sub_parent",
"subsys_bg3d";
operating-points-v2 = <&gpu_opp_table>;
power-domains =
<&spm MT8195_POWER_DOMAIN_MFG2>,
<&spm MT8195_POWER_DOMAIN_MFG3>,
<&spm MT8195_POWER_DOMAIN_MFG4>,
<&spm MT8195_POWER_DOMAIN_MFG5>,
<&spm MT8195_POWER_DOMAIN_MFG6>;
power-domain-names = "core0",
"core1",
"core2",
"core3",
"core4";
supply-names = "mali","mali_sram";
mali-supply = <&mt6315_7_vbuck1>;
mali_sram-supply = <&mt6359_vsram_others_ldo_reg>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2", "operating-points-v2-mali";
opp-shared;
opp-390000000 {
opp-hz = /bits/ 64 <390000000>;
opp-hz-real = /bits/ 64 <390000000>,
/bits/ 64 <390000000>;
opp-microvolt = <625000>,
<750000>;
};
opp-410000000 {
opp-hz = /bits/ 64 <410000000>;
opp-hz-real = /bits/ 64 <410000000>,
/bits/ 64 <410000000>;
opp-microvolt = <631250>,
<750000>;
};
opp-431000000 {
opp-hz = /bits/ 64 <431000000>;
opp-hz-real = /bits/ 64 <431000000>,
/bits/ 64 <431000000>;
opp-microvolt = <631250>,
<750000>;
};
opp-473000000 {
opp-hz = /bits/ 64 <473000000>;
opp-hz-real = /bits/ 64 <473000000>,
/bits/ 64 <473000000>;
opp-microvolt = <637500>,
<750000>;
};
opp-515000000 {
opp-hz = /bits/ 64 <515000000>;
opp-hz-real = /bits/ 64 <515000000>,
/bits/ 64 <515000000>;
opp-microvolt = <637500>,
<750000>;
};
opp-556000000 {
opp-hz = /bits/ 64 <556000000>;
opp-hz-real = /bits/ 64 <556000000>,
/bits/ 64 <556000000>;
opp-microvolt = <643750>,
<750000>;
};
opp-598000000 {
opp-hz = /bits/ 64 <598000000>;
opp-hz-real = /bits/ 64 <598000000>,
/bits/ 64 <598000000>;
opp-microvolt = <650000>,
<750000>;
};
opp-640000000 {
opp-hz = /bits/ 64 <640000000>;
opp-hz-real = /bits/ 64 <640000000>,
/bits/ 64 <640000000>;
opp-microvolt = <650000>,
<750000>;
};
opp-670000000 {
opp-hz = /bits/ 64 <670000000>;
opp-hz-real = /bits/ 64 <670000000>,
/bits/ 64 <670000000>;
opp-microvolt = <662500>,
<750000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-hz-real = /bits/ 64 <700000000>,
/bits/ 64 <700000000>;
opp-microvolt = <675000>,
<750000>;
};
opp-730000000 {
opp-hz = /bits/ 64 <730000000>;
opp-hz-real = /bits/ 64 <730000000>,
/bits/ 64 <730000000>;
opp-microvolt = <687500>,
<750000>;
};
opp-760000000 {
opp-hz = /bits/ 64 <760000000>;
opp-hz-real = /bits/ 64 <760000000>,
/bits/ 64 <760000000>;
opp-microvolt = <700000>,
<750000>;
};
opp-790000000 {
opp-hz = /bits/ 64 <790000000>;
opp-hz-real = /bits/ 64 <790000000>,
/bits/ 64 <790000000>;
opp-microvolt = <712500>,
<750000>;
};
opp-820000000 {
opp-hz = /bits/ 64 <820000000>;
opp-hz-real = /bits/ 64 <820000000>,
/bits/ 64 <820000000>;
opp-microvolt = <725000>,
<750000>;
};
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-hz-real = /bits/ 64 <850000000>,
/bits/ 64 <850000000>;
opp-microvolt = <737500>,
<750000>;
};
opp-880000000 {
opp-hz = /bits/ 64 <880000000>;
opp-hz-real = /bits/ 64 <880000000>,
/bits/ 64 <880000000>;
opp-microvolt = <750000>,
<750000>;
};
};
apu_conn: syscon@19020000 {
compatible = "mediatek,mt8195-apu_conn", "syscon";
reg = <0 0x19020000 0 0x1000>;
};
apusys_reviser@19021000 {
compatible = "mediatek, rv-reviser";
reg = <0 0x19021000 0 0x1000>, /* apu_sctrl_reviser */
<0 0x1d800000 0 0x400000>, /* VLM */
<0 0x1d000000 0 0x100000>, /* TCM */
<0 0x19001000 0 0x1000>; /* apusys int */
interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
default-dram = <0x1 0x01 0x88000000>;
dma-ranges = <0x0 0x0 0x0 0x40000000 0x1 0x0>;
boundary = <0x0>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_DATA>;
};
apu_conn1: syscon@19024000 {
compatible = "mediatek,mt8195-apu_conn1", "syscon";
reg = <0 0x19024000 0 0x1000>;
};
apu_vcore: syscon@19029000 {
compatible = "mediatek,mt8195-apu_vcore", "syscon";
reg = <0 0x19029000 0 0x1000>;
};
apu0: syscon@19030000 {
compatible = "mediatek,mt8195-apu0", "syscon";
reg = <0 0x19030000 0 0x1000>;
};
vpu_core0: vpu_core0@19030000 {
compatible = "mediatek,mt8195-vpu_core0";
reg = <0 0x19030000 0 0x1000>,
<0 0x1d400000 0 0x40000>,
<0 0x1d440000 0 0x30000>,
<0 0x0d190000 0 0x4000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH 0>;
id = <0>;
reset-vector = <0x7da00000 0x00100000 0x0>;
main-prog = <0x7db00000 0x00300000 0x100000>;
kernel-lib = <0x7de00000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_VPU>;
dma-ranges = <0x0 0x20000000 0x0 0x40000000 0x0 0xe0000000>;
#cooling-cells = <2>;
memory-region = <&vpu_reserve_memory>;
firmware-name = "mediatek/mt8395/cam_vpu1.img",
"mediatek/mt8395/cam_vpu2.img",
"mediatek/mt8395/cam_vpu3.img";
};
apu1: syscon@19031000 {
compatible = "mediatek,mt8195-apu1", "syscon";
reg = <0 0x19031000 0 0x1000>;
};
vpu_core1: vpu_core1@19031000 {
compatible = "mediatek,mt8195-vpu_core1";
reg = <0 0x19031000 0 0x1000>,
<0 0x1d500000 0 0x40000>,
<0 0x1d540000 0 0x30000>,
<0 0x0d194000 0 0x4000>;
interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH 0>;
id = <1>;
reset-vector = <0x7e300000 0x00100000 0x400000>;
main-prog = <0x7e400000 0x00300000 0x500000>;
kernel-lib = <0x7e700000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
dma-ranges = <0x0 0x20000000 0x0 0x40000000 0x0 0xe0000000>;
iommus = <&iommu_apu1 IOMMU_PORT_APU_VPU>;
#cooling-cells = <2>;
memory-region = <&vpu_reserve_memory>;
};
apu_mdla0: syscon@19034000 {
compatible = "mediatek,mt8195-apu_mdla0", "syscon";
reg = <0 0x19034000 0 0x1000>;
};
apu_mdla1: syscon@19038000 {
compatible = "mediatek,mt8195-apu_mdla1", "syscon";
reg = <0 0x19038000 0 0x1000>;
};
mtk_mdla: mtk_mdla {
compatible = "mediatek, mdla-rv";
core_num = <2>;
version = <0x81950200>;
dma-ranges = <0x0 0x0 0x0 0x40000000 0x1 0x0>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_DATA>;
status = "okay";
};
apusys_mnoc@1906e000 {
compatible = "mediatek,apusys_mnoc";
reg = <0 0x1906e000 0 0x6000>, /* mnoc reg */
<0 0x19001000 0 0x1000>, /* apusys int */
<0 0x19020000 0 0x1000>; /* apu_conn_config */
interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
};
apu_pcu: syscon@190f1000 {
compatible = "mediatek,mt8195-apu_pcu", "syscon";
reg = <0 0x190f1000 0 0x1000>;
};
apu_ao_ctrl: syscon@190f2000 {
compatible = "mediatek,mt8195-apu_ao_ctrl", "syscon";
reg = <0 0x190f2000 0 0x1000>;
};
apu_acc: syscon@190f4000 {
compatible = "mediatek,mt8195-apu_acc", "syscon";
reg = <0 0x190f4000 0 0x100>;
};
apu_top_3: apu_top_3 {
compatible = "mt8195,apu_top_3";
clocks = <&apusys_pll CLK_APUSYS_PLL_APUPLL>,
<&apusys_pll CLK_APUSYS_PLL_NPUPLL>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL1>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL2>,
<&topckgen CLK_TOP_DSP>,
<&topckgen CLK_TOP_DSP1>,
<&topckgen CLK_TOP_DSP2>,
<&topckgen CLK_TOP_DSP4>,
<&topckgen CLK_TOP_DSP5>,
<&topckgen CLK_TOP_DSP7>,
<&topckgen CLK_TOP_MAINPLL_D4_D2>,
<&topckgen CLK_TOP_UNIVPLL_D4_D2>,
<&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&infracfg_ao CLK_INFRA_AO_DEBUGSYS>;
clock-names = "clk_apupll_apupll",
"clk_apupll_npupll",
"clk_apupll_apupll1",
"clk_apupll_apupll2",
"clk_top_dsp_sel",
"clk_top_dsp1_sel",
"clk_top_dsp2_sel",
"clk_top_dsp4_sel",
"clk_top_dsp5_sel",
"clk_top_ipu_if_sel",
"clk_top_mainpll_d4_d2",
"clk_top_univpll_d4_d2",
"clk_top_univpll_d6_d2",
"clk_infra_ao_debugsys";
reg = <0 0x10006000 0 0x1000>, // sys_spm
<0 0x19020000 0 0x1000>, // apu_conn
<0 0x19024000 0 0x1000>, // apu_conn1
<0 0x19029000 0 0x1000>, // apu_vcore
<0 0x19000000 0 0x1000>, // apu_md32_mbox
<0 0x190f0000 0 0x1000>, // apu_rpc
<0 0x190f1000 0 0x1000>, // apu_pcu
<0 0x190f2000 0 0x1000>, // apu_ao_ctl
<0 0x190f3000 0 0x1000>, // apu_pll
<0 0x190f4000 0 0x1000>, // apu_acc
<0 0x19030000 0 0x1000>, // apu_vpu0
<0 0x19031000 0 0x1000>, // apu_vpu1
<0 0x19034000 0 0x1000>, // apu_mdla0
<0 0x19038000 0 0x1000>; // apu_mdla1
reg-names =
"sys_spm",
"apu_conn",
"apu_conn1",
"apu_vcore",
"apu_md32_mbox",
"apu_rpc",
"apu_pcu",
"apu_ao_ctl",
"apu_pll",
"apu_acc",
"apu_vpu0",
"apu_vpu1",
"apu_mdla0",
"apu_mdla1";
consumer = <&iommu_apu0>, <&iommu_apu1>;
vapu-supply = <&mt6359_vproc1_buck_reg>;
vmdla-supply = <&mt6359_vproc2_buck_reg>;
vsram-supply = <&mt6359_vsram_md_ldo_reg>;
operating-points-v2 = <&opp_table_apu_conn>,
<&opp_table_apu_rv>,
<&opp_table_vpu>,
<&opp_table_dla>;
status = "okay";
};
mdla_devfreq: mdla_devfreq {
compatible = "mediatek,mt8195-mdla-devfreq";
#cooling-cells = <2>;
dynamic-power-coefficient = <1667>;
power_table = <581>,
<448>,
<320>,
<208>,
<127>,
<96>;
status = "okay";
};
vpu_devfreq: vpu_devfreq {
compatible = "mediatek,mt8195-vpu-devfreq";
#cooling-cells = <2>;
dynamic-power-coefficient = <1667>;
power_table = <493>,
<402>,
<295>,
<200>,
<119>,
<87>;
status = "okay";
};
apusys_sw_logger: apusys_sw_logger {
compatible = "mediatek,apusys_sw_logger";
reg = <0 0x19000000 0 0x1000>;
reg-names = "apu_mbox";
dma-ranges = <0x0 0x0 0x0 0x40000000 0x1 0x0>;
iommus = <&iommu_apu1 IOMMU_PORT_APU_DATA>;
};
apusys_rv: apusys_rv@19001000 {
compatible = "mediatek,mt8195-apusys_rv";
memory-region = <&apu_reserve_memory>;
reg = <0 0x19000000 0 0x1000>,
<0 0x19001000 0 0x1000>,
<0 0x19002000 0 0x10>,
<0 0x19021000 0 0x1000>,
<0 0x190f2000 0 0x1000>,
<0 0x1df00000 0 0x20000>,
<0 0x0d19c000 0 0x10000>;
reg-names = "apu_mbox",
"md32_sysctrl",
"apu_wdt",
"apu_sctrl_reviser",
"apu_ao_ctl",
"md32_tcm",
"md32_debug_apb";
mediatek,apusys_power = <&apu_top_3>;
firmware-name = "mediatek/mt8395/apusys.sig.img";
apu_iommu0 = <&iommu_apu0>;
apu_iommu1 = <&iommu_apu1>;
dma-ranges = <0x0 0x0 0x0 0x40000000 0x1 0x0>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_DATA>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "apu_wdt",
"mbox0_irq";
up_code_buf_sz = <0x100000>;
up_coredump_buf_sz = <0x180000>;
regdump_buf_sz = <0x10000>;
mdla_coredump_buf_sz = <0x0>;
mvpu_coredump_buf_sz = <0x0>;
mvpu_sec_coredump_buf_sz = <0x0>;
status = "okay";
apu_ctrl {
compatible = "mediatek,apu-ctrl-rpmsg";
mtk,rpmsg-name = "apu-ctrl-rpmsg";
};
apu_top_rpmsg {
compatible = "mediatek,aputop-rpmsg";
mtk,rpmsg-name = "apu_top_3_rpmsg";
};
apu_mdw {
compatible = "mediatek,apu-mdw-rpmsg";
mtk,rpmsg-name = "apu-mdw-rpmsg";
};
apu_reviser {
compatible = "mediatek,apu-reviser-rpmsg";
mtk,rpmsg-name = "apu-reviser-rpmsg";
};
apu_edma {
compatible = "mediatek,apu-edma-rpmsg";
mtk,rpmsg-name = "apu-edma-rpmsg";
};
apu_mnoc {
compatible = "mediatek,apu-mnoc-rpmsg";
mtk,rpmsg-name = "apu-mnoc-rpmsg";
};
mdla_tx_rpmsg {
compatible = "mediatek,mdla-tx-rpmsg";
mtk,rpmsg-name = "mdla-tx-rpmsg";
};
mdla_rx_rpmsg {
compatible = "mediatek,mdla-rx-rpmsg";
mtk,rpmsg-name = "mdla-rx-rpmsg";
};
};
mtk_apu_mem_code: mtk_apu_mem_code {
compatible = "mediatek, apu_mem_code";
type = <1>;
mask = /bits/ 64 <0x00000003ffffffff>;
dma-ranges = <0x0 0x0 0x0 0x40000000 0x1 0x0>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_DATA>;
};
mtk_apu_mem_data: mtk_apu_mem_data {
compatible = "mediatek, apu_mem_data";
type = <2>;
mask = /bits/ 64 <0x00000003ffffffff>;
dma-ranges = <0x0 0x8000000 0x0 0x40000000 0x0 0x8000000>;
iommus = <&iommu_apu0 IOMMU_PORT_APU_VLM>;
};
iommu_apu0: iommu@19010000 {
compatible = "mediatek,mt8195-iommu-apu";
reg = <0 0x19010000 0 0x5000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>;
#iommu-cells = <1>;
mediatek,apu_power = <&apusys_rv>;
};
iommu_apu1: iommu@19015000 {
compatible = "mediatek,mt8195-iommu-apu";
reg = <0 0x19015000 0 0x5000>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
#iommu-cells = <1>;
mediatek,apu_power = <&apusys_rv>;
};
apusys_pll: syscon@190f3000 {
compatible = "mediatek,mt8195-apusys_pll", "syscon";
reg = <0 0x190f3000 0 0x1000>;
#clock-cells = <1>;
};
opp_table_apu_conn: opp-table-apu-conn {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <728000000>;
opp-microvolt = <775000>;
};
opp-1 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <750000>;
};
opp-2 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <700000>;
};
opp-3 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <650000>;
};
opp-4 {
opp-hz = /bits/ 64 <238000000>;
opp-microvolt = <600000>;
};
opp-5 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <575000>;
};
};
opp_table_apu_rv: opp-table-apu-rv {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <728000000>;
opp-microvolt = <775000>;
};
opp-1 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <750000>;
};
opp-2 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <700000>;
};
opp-3 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <650000>;
};
opp-4 {
opp-hz = /bits/ 64 <238000000>;
opp-microvolt = <600000>;
};
opp-5 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <575000>;
};
};
opp_table_vpu: opp-table-vpu {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <832000000>;
opp-microvolt = <775000>;
};
opp-1 {
opp-hz = /bits/ 64 <728000000>;
opp-microvolt = <750000>;
};
opp-2 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <700000>;
};
opp-3 {
opp-hz = /bits/ 64 <525000000>;
opp-microvolt = <650000>;
};
opp-4 {
opp-hz = /bits/ 64 <358000000>;
opp-microvolt = <600000>;
};
opp-5 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <575000>;
};
};
opp_table_dla: opp-table-dla {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <960000000>;
opp-microvolt = <800000>;
};
opp-1 {
opp-hz = /bits/ 64 <832000000>;
opp-microvolt = <750000>;
};
opp-2 {
opp-hz = /bits/ 64 <688000000>;
opp-microvolt = <700000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <650000>;
};
opp-4 {
opp-hz = /bits/ 64 <385000000>;
opp-microvolt = <600000>;
};
opp-5 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <575000>;
};
};
vcu: vcu@18000000 {
compatible = "mediatek-vcu";
mediatek,vcuid = <0>;
mediatek,vcuname = "vcu";
mediatek,vcu-off = <0>;
reg = <0 0x18000000 0 0x40000>,/* VDEC_BASE */
<0 0x1a020000 0 0x10000>,/* VENC_BASE */
<0 0x1b020000 0 0x10000>;/* VENC_C1_BASE */
iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
mediatek,mailbox-gce = <&gce1>;
mediatek,dec_gce_th_num = <1>;
mediatek,enc_gce_th_num = <2>;
mboxes = <&gce1 16 CMDQ_THR_PRIO_1>,
<&gce1 17 CMDQ_THR_PRIO_1>,
<&gce1 18 CMDQ_THR_PRIO_1>;
gce-event-names = "venc_eof",
"venc_eof_c1",
"venc_wp_2nd_done",
"venc_wp_3nd_done";
gce-events = <CMDQ_EVENT_VENC_TOP_FRAME_DONE>,
<CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE>,
<CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE>,
<CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE>;
gce-gpr = <GCE_GPR_R10>, <GCE_GPR_R11>;
};
vdec: vdec@18000000 {
compatible = "mediatek,mt8195-vcodec-dec";
mediatek,platform = "platform:mt8195";
mediatek,ipm = <2>;
reg = <0 0x18000000 0 0x800>,/* VDEC_BASE */
<0 0x18020000 0 0x1000>,/* VDEC_VLD */
<0 0x18025000 0 0x1000>,/* VDEC_MISC */
<0 0x18010000 0 0x800>,/* VDEC_LAT_MISC */
<0 0x18004000 0 0x1000>,/* VDEC_RACING_CTRL */
<0 0x18035000 0 0x1000>,/* VDEC_CORE1_MISC */
<0 0x18018000 0 0x800>,/* VDEC_LAT1_MISC */
<0 0x1800f000 0 0x800>,/* VDEC_SOC_GCON */
<0 0x18010800 0 0x800>,/* VDEC_LAT_WDMA */
<0 0x18018800 0 0x800>,/* VDEC_LAT1_WDMA */
<0 0x18001000 0 0x1000>,/* VDEC_LAT_TOP */
<0 0x18000800 0 0x800>;/* VDEC_UFO_ENC */
reg-names = "VDEC_BASE",
"VDEC_VLD",
"VDEC_MISC",
"VDEC_LAT_MISC",
"VDEC_RACING_CTRL",
"VDEC_CORE1_MISC",
"VDEC_LAT1_MISC",
"VDEC_SOC_GCON",
"VDEC_LAT_WDMA",
"VDEC_LAT1_WDMA",
"VDEC_LAT_TOP",
"VDEC_UFO_ENC";
iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* SOC */
interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys_core1 CLK_VDEC_CORE1_LARB1>,
<&vdecsys_core1 CLK_VDEC_CORE1_VDEC>;
clock-names = "SOC_MT_CG_LARB1",
"LAT_MT_CG_VDEC",
"SOC_MT_CG_VDEC",
"CORE_MT_CG_LARB1",
"CORE_MT_CG_VDEC",
"CORE_MT_CG_CORE1_LARB1",
"CORE_MT_CG_CORE1_VDEC";
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_VDECPLL>;
assigned-clock-rates = <680000000>;
mediatek,vcu = <&vcu>;
};
venc@1a020000 {
compatible = "mediatek,mt8195-vcodec-enc";
mediatek,platform = "platform:mt8195";
mediatek,ipm = <2>;
reg = <0 0x1a020000 0 0x10000>,/* VENC_C0 */
<0 0x1b020000 0 0x10000>;/* VENC_C1 */
reg-names = "VENC_SYS",
"VENC_C1_SYS";
iommus = <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_VENC>;
clock-names = "MT_CG_VENC0",
"MT_CG_VENC1";
assigned-clocks = <&topckgen CLK_TOP_VENC>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
mediatek,vcu = <&vcu>;
port-arg-num = <3>;
port-def = <0 M4U_PORT_L19_VENC_RCPU 0>,
<0 M4U_PORT_L19_VENC_REC 0>,
<0 M4U_PORT_L19_VENC_BSDMA 0>,
<0 M4U_PORT_L19_VENC_SV_COMV 0>,
<0 M4U_PORT_L19_VENC_RD_COMV 0>,
<0 M4U_PORT_L19_VENC_NBM_RDMA 1>,
<0 M4U_PORT_L19_VENC_NBM_RDMA_LITE 1>,
<0 M4U_PORT_L19_VENC_SUB_W_LUMA 0>,
<0 M4U_PORT_L19_VENC_FCS_NBM_RDMA 1>,
<0 M4U_PORT_L19_VENC_NBM_WDMA 1>,
<0 M4U_PORT_L19_VENC_NBM_WDMA_LITE 1>,
<0 M4U_PORT_L19_VENC_FCS_NBM_WDMA 1>,
<0 M4U_PORT_L19_VENC_CUR_LUMA 0>,
<0 M4U_PORT_L19_VENC_CUR_CHROMA 0>,
<0 M4U_PORT_L19_VENC_REF_LUMA 0>,
<0 M4U_PORT_L19_VENC_REF_CHROMA 0>,
<0 M4U_PORT_L19_VENC_SUB_R_CHROMA 0>,
<1 M4U_PORT_L20_VENC_RCPU 0>,
<1 M4U_PORT_L20_VENC_REC 0>,
<1 M4U_PORT_L20_VENC_BSDMA 0>,
<1 M4U_PORT_L20_VENC_SV_COMV 0>,
<1 M4U_PORT_L20_VENC_RD_COMV 0>,
<1 M4U_PORT_L20_VENC_NBM_RDMA 1>,
<1 M4U_PORT_L20_VENC_NBM_RDMA_LITE 1>,
<1 M4U_PORT_L20_VENC_SUB_W_LUMA 0>,
<1 M4U_PORT_L20_VENC_FCS_NBM_RDMA 1>,
<1 M4U_PORT_L20_VENC_NBM_WDMA 1>,
<1 M4U_PORT_L20_VENC_NBM_WDMA_LITE 1>,
<1 M4U_PORT_L20_VENC_FCS_NBM_WDMA 1>,
<1 M4U_PORT_L20_VENC_CUR_LUMA 0>,
<1 M4U_PORT_L20_VENC_CUR_CHROMA 0>,
<1 M4U_PORT_L20_VENC_REF_LUMA 0>,
<1 M4U_PORT_L20_VENC_REF_CHROMA 0>,
<1 M4U_PORT_L20_VENC_SUB_R_CHROMA 0>;
};
venc_l19 {
compatible = "mediatek,mt8195-venc-larb";
mediatek,larb-id = <19>;
mediatek,hw-id = <0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
<&iommu_vdo M4U_PORT_L19_VENC_REC>,
<&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
<&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
<&iommu_vdo M4U_PORT_L19_VENC_NBM_RDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_NBM_RDMA_LITE>,
<&iommu_vdo M4U_PORT_L19_VENC_SUB_W_LUMA>,
<&iommu_vdo M4U_PORT_L19_VENC_FCS_NBM_RDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_NBM_WDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_NBM_WDMA_LITE>,
<&iommu_vdo M4U_PORT_L19_VENC_FCS_NBM_WDMA>,
<&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
<&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
<&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
<&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>,
<&iommu_vdo M4U_PORT_L19_VENC_SUB_R_CHROMA>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
venc_l20 {
compatible = "mediatek,mt8195-venc-larb";
mediatek,larb-id = <20>;
mediatek,hw-id = <1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>,
<&iommu_vpp M4U_PORT_L20_VENC_REC>,
<&iommu_vpp M4U_PORT_L20_VENC_BSDMA>,
<&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>,
<&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>,
<&iommu_vpp M4U_PORT_L20_VENC_NBM_RDMA>,
<&iommu_vpp M4U_PORT_L20_VENC_NBM_RDMA_LITE>,
<&iommu_vpp M4U_PORT_L20_VENC_SUB_W_LUMA>,
<&iommu_vpp M4U_PORT_L20_VENC_FCS_NBM_RDMA>,
<&iommu_vpp M4U_PORT_L20_VENC_NBM_WDMA>,
<&iommu_vpp M4U_PORT_L20_VENC_NBM_WDMA_LITE>,
<&iommu_vpp M4U_PORT_L20_VENC_FCS_NBM_WDMA>,
<&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>,
<&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>,
<&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>,
<&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>,
<&iommu_vpp M4U_PORT_L20_VENC_SUB_R_CHROMA>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
vdec_l21 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <21>;
mediatek,hw-id = <0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;/* core0 */
iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
<&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
vdec_l22 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <22>;
mediatek,hw-id = <2>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;/* core1 */
iommus = <&iommu_vpp M4U_PORT_L22_VDEC_MC_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_UFO_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_PP_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_PRED_RD_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_PRED_WR_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_PPWRAP_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_TILE_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_VLD_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_VLD2_EXT>,
<&iommu_vpp M4U_PORT_L22_VDEC_AVC_MV_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
vdec_l23 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <23>;
mediatek,hw-id = <1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* soc */
iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
<&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
vdec_l24 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <24>;
mediatek,hw-id = <3>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* soc */
iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_VLD_EXT>,/*LAT1*/
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_VLD2_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_TILE_EXT>,
<&iommu_vdo M4U_PORT_L24_VDEC_LAT1_WDMA_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>;
};
};
thermal-zones {
soc_max {
cooling-maps {
map2 {
trip = <&target>;
cooling-device = <&mdla_devfreq
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&vpu_devfreq
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
};
chosen {
stdout-path = "serial0:921600n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0x1 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
* | | TA_RAM 8MiB |
* + TZDRAM +--------------+ 0x4340_0000
* | | TEE_RAM 2MiB |
* +-----------------------+ 0x4320_0000
*/
optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
scp_mem_reserved: scp_mem_region {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
snd_dma_mem_reserved: snd_dma_mem_region {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0x1100000>;
no-map;
};
apu_reserve_memory: apu-reserve-memory{
compatible = "shared-dma-pool";
size = <0 0x1400000>; //20 MB
alignment = <0 0x10000>;
reg = <0 0x62000000 0 0x1400000>;
};
vpu_reserve_memory: vpu-reserve-memory {
compatible = "shared-dma-pool";
size = <0 0x1400000>; //20 MB
alignment = <0 0x10000>;
reg = <0 0x53000000 0 0x1400000>;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
key-f15 {
wakeup-source;
debounce-interval = <100>;
gpios = <&pio 106 GPIO_ACTIVE_LOW>;
label = "KEY_F15";
linux,code = <KEY_F15>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
red-led {
label = "red-led";
gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
blue-led {
label = "blue-led";
gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "on";
};
};
mtk_fsource: fsource {
compatible = "mtk-fsource";
vfsource-supply = <&mt6359_vefuse_ldo_reg>;
};
wifi_pwr_fixed_3v3: wifi-pwr-fixed-3v3 {
compatible = "regulator-fixed";
regulator-name = "wifi_pwr_fixed_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 67 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
dmic_codec: dmic-codec {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <2>;
wakeup-delay-ms = <200>;
};
};
&scp {
memory-region = <&scp_mem_reserved>;
status = "okay";
};
&mmc0 {
status = "disabled";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-hw-reset;
no-sdio;
no-sd;
hs400-ds-delay = <0x14c11>;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
non-removable;
};
&ufshci {
status = "okay";
vcc-supply = <&mt6359_vemc_1_ldo_reg>;
vccq2-supply = <&mt6359_vufs_ldo_reg>;
};
&ufsphy {
status = "okay";
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <208000000>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
no-mmc;
no-sdio;
vmmc-supply = <&mt6360_ldo5>;
vqmmc-supply = <&mt6360_ldo3>;
status = "okay";
};
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
it5205fn: it5205fn@48 {
compatible = "mediatek,it5205fn";
reg = <0x48>;
type3v3-supply = <&mt6359_vibr_ldo_reg>;
svid = /bits/ 16 <0xff01>;
status = "okay";
};
};
&i2c6 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c6_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mt6360: mt6360@34 {
compatible = "mediatek,mt6360";
reg = <0x34>;
pinctrl-0 = <&mt6360_pins>;
pinctrl-names = "default";
interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
tcpc {
compatible = "mediatek,mt6360-tcpc";
interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "PD_IRQB";
tcpc-vbus-supply = <&otg_vbus_regulator>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
op-sink-microwatt = <10000000>;
orientation-switch = <&it5205fn>;
mode-switch = <&it5205fn>;
displayport = <&dp_intf1>;
altmodes {
dp {
svid = <0xff01>;
vdo = <0x1c1c47>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mt6360_ssusb_ep: endpoint {
remote-endpoint = <&ssusb_ep>;
};
};
};
};
};
};
&ssusb {
pinctrl-names = "default";
pinctrl-0 = <&u3_p0_vbus>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
dr_mode = "otg";
mediatek,usb3-drd;
usb-role-switch;
status = "okay";
port {
ssusb_ep: endpoint {
remote-endpoint = <&mt6360_ssusb_ep>;
};
};
};
&ssusb1 {
pinctrl-names = "default";
pinctrl-0 = <&u2_default>;
maximum-speed = "high-speed";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
mediatek,force-vbus;
usb-role-switch;
dr_mode = "otg"; /* host, peripheral, otg */
status = "disabled";
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
id-gpios = <&pio 130 GPIO_ACTIVE_HIGH>;
};
};
&xhci0 {
status = "okay";
};
&xhci1 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&xhci2 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "disabled";
};
&xhci3 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "disabled";
};
&u3port0 {
status = "okay";
};
&u2port1 {
status = "okay";
};
&u3port1 {
status = "okay";
};
&u2port2 {
status = "okay";
};
&u2port3 {
status = "disabled";
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&u3phy3 {
status = "disabled";
};
&mt6359_vproc1_buck_reg {
regulator-always-on;
};
&mt6359_vproc2_buck_reg {
regulator-always-on;
};
&mt6359_vsram_md_ldo_reg {
regulator-always-on;
};
&mt6359_vgpu11_buck_reg {
regulator-always-on;
};
&mt6359_vpu_buck_reg {
regulator-always-on;
};
&mt6359_vcore_buck_reg {
regulator-always-on;
};
&mt6359_vbbck_ldo_reg {
regulator-always-on;
};
&mt6359_vaud18_ldo_reg {
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
&mt6359_vcn33_2_bt_ldo_reg {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* DEBUG: to remove */
&mt6359_vibr_ldo_reg {
regulator-always-on;
};
/* For USB Hub */
&mt6359_vcamio_ldo_reg {
regulator-always-on;
};
#include "mt6360.dtsi"
/* For EMI_VDD2 */
&mt6360_buck1 {
regulator-always-on;
};
/* For EMI_VDDQ */
&mt6360_buck2 {
regulator-always-on;
};
&mt6360_ldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
&mt6360_ldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&mt6360_ldo5 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* For EMI_VMDDR_EN */
&mt6360_ldo7 {
regulator-always-on;
};
&spmi {
#address-cells = <2>;
#size-cells = <2>;
grpid = <11>;
mt6315_6: mt6315@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 0 0xb 1>;
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
mt6315_7: mt6315@7 {
compatible = "mediatek,mt6315-regulator";
reg = <0x7 0 0xb 1>;
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};
};
};
};
&eth {
phy-mode ="rgmii-rxid";
phy-handle = <&eth_phy0>;
snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
snps,reset-delays-us = <0 10000 10000>;
mediatek,tx-delay-ps = <2030>;
mediatek,mac-wol;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default>;
pinctrl-1 = <&eth_sleep>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: eth_phy0@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
};
};
};
&afe {
#sound-dai-cells = <0>;
memory-region = <&snd_dma_mem_reserved>;
mediatek,dmic-iir-on;
status = "okay";
};
&mt6359codec {
mediatek,mic-type-1 = <3>; /* DCC */
};
&sound {
compatible = "mediatek,mt8395-evk";
model = "mt8395-evk";
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
status = "okay";
dai-link-0 {
sound-dai = <&afe>;
dai-link-name = "DL_SRC_BE";
codec-0 {
sound-dai = <&pmic 0>;
};
};
dai-link-1 {
sound-dai = <&afe>;
dai-link-name = "UL_SRC1_BE";
codec-0 {
sound-dai = <&pmic 0>;
};
codec-1 {
sound-dai = <&dmic_codec>;
};
};
dai-link-2 {
sound-dai = <&afe>;
dai-link-name = "UL_SRC2_BE";
codec-0 {
sound-dai = <&pmic 1>;
};
};
dai-link-3 {
sound-dai = <&afe>;
dai-link-name = "ETDM3_OUT_BE";
codec-0 {
sound-dai = <&hdmi0>;
};
};
dai-link-4 {
sound-dai = <&afe>;
dai-link-name = "DPTX_BE";
codec-0 {
sound-dai = <&dp_tx>;
};
};
dai-link-5 {
sound-dai = <&afe>;
dai-link-name = "DMIC_BE";
codec-0 {
sound-dai = <&dmic_codec>;
};
};
};
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
&pcie0 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&pcie0_pins_default>;
pinctrl-1 = <&pcie0_pins_idle>;
status = "okay";
};
&pciephy {
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins_default>;
status = "okay";
};
&u3phy1 {
status = "okay";
};
&dp_intf1 {
status = "okay";
mediatek,indicated-display-path = <1>;
mediatek,oob-hpd;
ports {
port {
dp_intf1_out: endpoint {
remote-endpoint = <&dptx_in>;
};
};
};
};
&dp_tx {
pinctrl-names = "default";
pinctrl-0 = <&dptx_pin>;
status = "okay";
ports {
port {
dptx_in: endpoint {
remote-endpoint = <&dp_intf1_out>;
};
};
};
};
&disp_dpi1 {
status = "okay";
mediatek,indicated-display-path = <0>;
};
&hdmi0 {
status = "okay";
};
&ovl1 {
/* DSI0 does not support dualpipe output,
* so disable dualpipe by disabling ovl1 node
*/
status = "okay";
mediatek,enable-dualpipe;
};
&dsi0 {
status = "disabled";
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&hdmirx0 {
pinctrl-names = "default";
pinctrl-0 = <&hdmi0_pins_default>;
hdmi33v-supply = <&mt6359_vcn33_1_wifi_ldo_reg>;
hdmi08v-supply = <&mt6359_va09_ldo_reg>;
status = "okay";
};
&pio {
u3_p0_vbus: u3_p0vbusdefault {
pins_cmd_dat {
pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
input-enable;
};
};
u2_default: u2default {
pin-id {
pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>;
input-enable;
bias-pull-up;
};
pin-usb-vbus {
pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>;
output-low;
};
};
mmc0_pins_default: mmc0default {
pins_cmd_dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_pins_uhs: mmc0uhs{
pins_cmd_dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc1_pins_default: mmc1-pins-default {
pins_cmd_dat {
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_insert {
pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
bias-pull-up;
};
};
mmc1_pins_uhs: mmc1-pins-uhs {
pins_cmd_dat {
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
i2c0_pins: i2c0-pins {
pins {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins: i2c1-pins {
pins {
pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
<PINMUX_GPIO11__FUNC_SCL1>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
mediatek,drive-strength-adv = <7>;
};
};
i2c2_pins: i2c2-pins {
pins {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-pull-up;
mediatek,rsel = <MTK_PULL_SET_RSEL_111>;
mediatek,drive-strength-adv = <7>;
drive-strength = <MTK_DRIVE_6mA>;
};
};
i2c4_pins: i2c4-pins {
pins {
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
bias-pull-up;
mediatek,rsel = <MTK_PULL_SET_RSEL_111>;
mediatek,drive-strength-adv = <7>;
};
};
i2c6_pins: i2c6-pin {
pins {
pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
<PINMUX_GPIO26__FUNC_SCL6>;
bias-pull-up;
mediatek,rsel = <MTK_PULL_SET_RSEL_111>;
};
};
uart0_pins: uart0-pins {
pins {
pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
<PINMUX_GPIO99__FUNC_URXD0>;
};
};
uart1_pins: uart1-pins {
pins {
pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
<PINMUX_GPIO103__FUNC_URXD1>,
<PINMUX_GPIO100__FUNC_URTS1>,
<PINMUX_GPIO101__FUNC_UCTS1>;
};
};
spi1_pins: spi1-pins {
pins {
pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
<PINMUX_GPIO137__FUNC_SPIM1_CLK>,
<PINMUX_GPIO138__FUNC_SPIM1_MO>,
<PINMUX_GPIO139__FUNC_SPIM1_MI>;
bias-disable;
};
};
spi2_pins: spi-pins {
pins {
pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
<PINMUX_GPIO141__FUNC_SPIM2_CLK>,
<PINMUX_GPIO142__FUNC_SPIM2_MO>,
<PINMUX_GPIO143__FUNC_SPIM2_MI>;
bias-disable;
};
};
eth_default: eth_default {
txd_pins {
pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
drive-strength = <MTK_DRIVE_8mA>;
};
cc_pins {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO86__FUNC_GBE_RXC>;
drive-strength = <MTK_DRIVE_8mA>;
};
rxd_pins {
pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
<PINMUX_GPIO82__FUNC_GBE_RXD2>,
<PINMUX_GPIO83__FUNC_GBE_RXD1>,
<PINMUX_GPIO84__FUNC_GBE_RXD0>;
};
mdio_pins {
pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
<PINMUX_GPIO90__FUNC_GBE_MDIO>;
input-enable;
};
power_pins {
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
<PINMUX_GPIO92__FUNC_GPIO92>;
output-high;
};
phy_reset_pin {
pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
};
};
eth_sleep: eth_sleep {
txd_pins {
pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
<PINMUX_GPIO78__FUNC_GPIO78>,
<PINMUX_GPIO79__FUNC_GPIO79>,
<PINMUX_GPIO80__FUNC_GPIO80>;
};
cc_pins {
pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
<PINMUX_GPIO88__FUNC_GPIO88>,
<PINMUX_GPIO87__FUNC_GPIO87>,
<PINMUX_GPIO86__FUNC_GPIO86>;
};
rxd_pins {
pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
<PINMUX_GPIO82__FUNC_GPIO82>,
<PINMUX_GPIO83__FUNC_GPIO83>,
<PINMUX_GPIO84__FUNC_GPIO84>;
};
mdio_pins {
pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
<PINMUX_GPIO90__FUNC_GPIO90>;
input-disable;
bias-disable;
};
power_pins {
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
<PINMUX_GPIO92__FUNC_GPIO92>;
input-disable;
bias-disable;
};
phy_reset_pin {
pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
input-disable;
bias-disable;
};
};
pcie0_pins_default: pcie0default {
pins {
pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
<PINMUX_GPIO20__FUNC_PERSTN>,
<PINMUX_GPIO21__FUNC_CLKREQN>;
bias-pull-up;
};
};
pcie0_pins_idle: pcie0idle {
pins {
pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
bias-disable;
output-low;
};
};
pcie1_pins_default: pcie1default {
pins {
pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
<PINMUX_GPIO1__FUNC_CLKREQN_1>,
<PINMUX_GPIO2__FUNC_WAKEN_1>;
bias-disable;
};
};
gpio_keys: gpio-keys {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
bias-pull-up;
input-enable;
};
};
mt6360_pins: mt6360-pins {
pins {
pinmux = <PINMUX_GPIO100__FUNC_GPIO100>,
<PINMUX_GPIO101__FUNC_GPIO101>;
input-enable;
bias-pull-up;
};
};
hdmi0_pins_default: hdmi0default {
hdmirxhpd {
pinmux = <PINMUX_GPIO27__FUNC_HDMIRX20_HTPLG>;
};
hdmirx5v {
pinmux = <PINMUX_GPIO28__FUNC_HDMIRX20_PWR5V>;
bias-disable;
};
hdmirxscl {
pinmux = <PINMUX_GPIO29__FUNC_HDMIRX20_SCL>;
};
hdmirxsda {
pinmux = <PINMUX_GPIO30__FUNC_HDMIRX20_SDA>;
drive-strength = <MTK_DRIVE_10mA>;
};
};
dptx_pin: dptx_pin_default {
pins_cmd_dat1 {
pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
bias-pull-up;
};
};
aud_pins_default: audiodefault {
pins_cmd_dat {
pinmux = <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
<PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
<PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
<PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
<PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
<PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
<PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>;
};
};
};
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