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23604e8a0d
* Introducing Rockchip rk322x SoC support Main features: - Legacy kernel flavour based upon stable v2.x rk3288 Rockchip branch (https://github.com/rockchip-linux/kernel/tree/stable-4.4-rk3288-linux-v2.x) - Current kernel flavour based on mainline 5.6.y kernel - Mainline u-boot (v2020.04) - Single generic tv box target (rk322x-box) which boots on all the known tv boxes - Hardware devices (eMMC/NAND, led wiring configuration, SoC variant selection) modulation done by user at runtime via device tree overlays - a script (rk322x-config) is provided for autodetection and simple configuration by inexperienced users; - Bits added to armbian-hardware-optimization to set affinity for irq handlers - rk322x-box targets already added to targets.conf for automatic image creation * Removed disabled patches * Restored mysteriously removed comment character
99 lines
3.8 KiB
Diff
99 lines
3.8 KiB
Diff
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 0127d702720c..6ef71ec239ae 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -353,7 +353,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(10), 12, GFLAGS),
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COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
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- RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
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+ RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
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RK2928_CLKGATE_CON(2), 15, GFLAGS),
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COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
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--
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2.17.1
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From 3acbbe5eb438e8b1061a803881579030d3c2b424 Mon Sep 17 00:00:00 2001
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From: Chen Lei <lei.chen@rock-chips.com>
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Date: Tue, 25 Dec 2018 18:29:04 +0800
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Subject: [PATCH] clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228
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mmc sample shift should be 1 for rk3228, or it will fail
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if we enable mmc tuning for rk3228.
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Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373
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Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
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---
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drivers/clk/rockchip/clk-rk3228.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 6ef71ec239ae..27adfca1a095 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -610,13 +610,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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/* PD_MMC */
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MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
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- MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
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+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
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MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
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- MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
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+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
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MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
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- MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
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+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
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};
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static const char *const rk3228_critical_clocks[] __initconst = {
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--
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2.17.1
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From a692001c1249473bdfe975ef53d2bdb8a4df736d Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Mon, 5 Feb 2018 10:04:15 +0800
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Subject: [PATCH] clk: rockchip: rk3228: Fix armclk parent
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Change-Id: I09830d96b37cca600f1782b9013b25e043467f97
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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---
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drivers/clk/rockchip/clk-rk3228.c | 8 +++++++-
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1 file changed, 7 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 58292f80ad66..fba513de94eb 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -170,7 +170,7 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
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[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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RK2928_MODE_CON, 8, 8, 0, NULL),
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[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
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- RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
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+ RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates),
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};
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#define MFLAGS CLK_MUX_HIWORD_MASK
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--
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2.17.1
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From f57d5061e7357a8f7a181517530658a223ba415b Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Thu, 22 Jun 2017 19:53:46 +0800
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Subject: [PATCH] clk: rockchip: rk3228: fix gpu gate-register
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Fix a typo making the aclk_gpu and aclk_gpu_noc access a wrong register to
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handle its gate.
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Change-Id: Ie0bac8014363af7c0409b8a56eacf2e858818843
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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---
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drivers/clk/rockchip/clk-rk3228.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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