mirror of
https://github.com/armbian/build
synced 2025-09-24 19:47:06 +07:00
7b99735c44
Changes to be committed: deleted: patch/kernel/archive/meson64-6.1/board-bananapim5-002-switch-VDDIO_C-pin-to-OP.patch - Patch upstreamed in 6.1.16: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts?h=v6.1.20&id=58dccc65221c6465a35cb6bb2ff41f2b75b367f0 modified: patch/kernel/archive/meson64-6.1/board-bananapim5-003-convert-dts-to-dtsi.patcha - Fixed patch due to upstream change in 6.1.16: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts?h=v6.1.20&id=e35feeb3fdbe3eeffae5e75123fa44523b5076b8 deleted: patch/kernel/archive/meson64-6.1/board-radxa-zero-dts-otg-fix.patch - Patch upstreamed in 6.1.16: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts?h=v6.1.20&id=b556778f76f975ccf7f008729b5bc2531c58ea95 deleted: patch/kernel/archive/meson64-6.1/general-arm64-dts-amlogic-Make-mmc-host-controller-interrupt.patch - Patch upstreamed in 6.1.12: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.20&id=274d9a28527d64a95107a1e62c71632065f0924f https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.20&id=222b1070b0fa12be25f9503a503724a899c6326b https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.20&id=a01ad536becb5d4c001a7d50dc1ca9fa14ef75a8 modified: patch/kernel/archive/meson64-6.1/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch - Fixed patch due to upstream change in 6.1.13 by copying the 6.2 version which was already rebased
109 lines
3.4 KiB
Diff
109 lines
3.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
|
From: Vyacheslav Bocharov <adeep@lexina.in>
|
|
Date: Mon, 7 Nov 2022 14:19:08 +0100
|
|
Subject: arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase
|
|
clock settings from devicetree data
|
|
|
|
The mmc driver has the same phase values for all meson platforms. However,
|
|
some platforms (and even some boards) require different values. This patch
|
|
transfers the values from the set in the code to the variables in the
|
|
device-tree file.
|
|
|
|
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
|
|
---
|
|
drivers/mmc/host/meson-gx-mmc.c | 19 +++--
|
|
include/dt-bindings/mmc/meson-gx-mmc.h | 35 ++++++++++
|
|
2 files changed, 48 insertions(+), 6 deletions(-)
|
|
|
|
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
|
|
index 64a1520321b0..fa9ec777e4a2 100644
|
|
--- a/drivers/mmc/host/meson-gx-mmc.c
|
|
+++ b/drivers/mmc/host/meson-gx-mmc.c
|
|
@@ -27,6 +27,7 @@
|
|
#include <linux/interrupt.h>
|
|
#include <linux/bitfield.h>
|
|
#include <linux/pinctrl/consumer.h>
|
|
+#include <dt-bindings/mmc/meson-gx-mmc.h>
|
|
|
|
#define DRIVER_NAME "meson-gx-mmc"
|
|
|
|
@@ -36,8 +37,6 @@
|
|
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
|
|
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
|
|
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
|
|
-#define CLK_PHASE_0 0
|
|
-#define CLK_PHASE_180 2
|
|
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
|
|
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
|
|
#define CLK_V2_ALWAYS_ON BIT(24)
|
|
@@ -428,13 +427,21 @@ static int meson_mmc_clk_init(struct meson_host *host)
|
|
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
|
|
const char *clk_parent[1];
|
|
u32 clk_reg;
|
|
-
|
|
+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
|
|
+
|
|
+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
|
|
+ "amlogic,mmc-phase", phase, 3) < 0)) {
|
|
+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
|
|
+ phase[0] = CLK_PHASE_180;
|
|
+ phase[1] = CLK_PHASE_0;
|
|
+ phase[2] = CLK_PHASE_0;
|
|
+ }
|
|
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
|
|
clk_reg = CLK_ALWAYS_ON(host);
|
|
clk_reg |= CLK_DIV_MASK;
|
|
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
|
|
- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
|
|
- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
|
|
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
|
|
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
|
|
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
|
|
if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
|
|
clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
|
|
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
|
|
diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
|
|
new file mode 100644
|
|
index 000000000000..cfc4a9d75b2b
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
|
|
@@ -0,0 +1,35 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
|
+/*
|
|
+ * Copyright (c) 2022 Vyacheslav Bocharov
|
|
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
|
|
+#define _DT_BINDINGS_MESON_GX_MMC_H
|
|
+
|
|
+/*
|
|
+ * Cfg_rx_phase: RX clock phase
|
|
+ * bits: 9:8 R/W
|
|
+ * default: 0
|
|
+ * Recommended value: 0
|
|
+ *
|
|
+ * Cfg_tx_phase: TX clock phase
|
|
+ * bits: 9:8 R/W
|
|
+ * default: 0
|
|
+ * Recommended value: 2
|
|
+ *
|
|
+ * Cfg_co_phase: Core clock phase
|
|
+ * bits: 9:8 R/W
|
|
+ * default: 0
|
|
+ * Recommended value: 2
|
|
+ *
|
|
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
|
|
+ */
|
|
+
|
|
+#define CLK_PHASE_0 0
|
|
+#define CLK_PHASE_90 1
|
|
+#define CLK_PHASE_180 2
|
|
+#define CLK_PHASE_270 3
|
|
+
|
|
+
|
|
+#endif
|
|
--
|
|
Armbian
|
|
|