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efee17f217
* bump uboot version to v2024.01 * add hdmi, vop driver for rk3328, enable hdmi * add inno hdmi phy driver
226 lines
6.7 KiB
Diff
226 lines
6.7 KiB
Diff
From c6c14957e96c46f0f197f787f407f8c3c152c17a Mon Sep 17 00:00:00 2001
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From: Jagan Teki <jagan@edgeble.ai>
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Date: Sun, 19 Feb 2023 00:01:34 +0530
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Subject: [PATCH] video: dw_hdmi: Add Vendor PHY handling
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Signed-off-by: Jagan Teki <jagan@edgeble.ai>
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---
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drivers/video/dw_hdmi.c | 29 +++++++++++++++++++++++++++-
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drivers/video/meson/meson_dw_hdmi.c | 11 ++++++++++-
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drivers/video/rockchip/rk3399_hdmi.c | 8 +++++++-
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drivers/video/rockchip/rk_hdmi.c | 2 +-
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drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++++++++++-
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include/dw_hdmi.h | 14 +++++++++++++-
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6 files changed, 69 insertions(+), 6 deletions(-)
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diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
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index c4fbb182944..ea12a094074 100644
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--- a/drivers/video/dw_hdmi.c
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+++ b/drivers/video/dw_hdmi.c
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@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
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hdmi_av_composer(hdmi, edid);
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- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
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+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
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if (ret)
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return ret;
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@@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
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return 0;
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}
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+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
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+ .phy_set = dw_hdmi_phy_cfg,
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+};
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+
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+static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
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+{
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+ if (!hdmi->data)
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+ return;
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+
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+ /* hook Synopsys PHYs ops */
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+ if (!hdmi->data->phy_force_vendor) {
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+ hdmi->ops = &dw_hdmi_synopsys_phy_ops;
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+ return;
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+ }
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+
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+ /* Vendor HDMI PHYs must assign phy_ops in plat_data */
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+ if (!hdmi->data->phy_ops) {
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+ printf("Unsupported Vendor HDMI phy_ops\n");
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+ return;
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+ }
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+
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+ /* hook Vendor HDMI PHYs ops */
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+ hdmi->ops = hdmi->data->phy_ops;
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+}
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+
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void dw_hdmi_init(struct dw_hdmi *hdmi)
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{
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uint ih_mute;
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+ dw_hdmi_detect_phy(hdmi);
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+
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/*
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* boot up defaults are:
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* hdmi_ih_mute = 0x03 (disabled)
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diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
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index c4fbb18294..1c5ee25280 100644
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--- a/drivers/video/dw_hdmi.c
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+++ b/drivers/video/dw_hdmi.c
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@@ -1009,6 +1025,23 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
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return 0;
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}
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+int dw_hdmi_disable(struct dw_hdmi *hdmi)
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+{
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+ uint clkdis;
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+
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+ /* disable pixel clock and tmds data path */
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+ clkdis = 0x7f;
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+ hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
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+
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+ /* disable phy */
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+ hdmi_phy_sel_interface_control(hdmi, 0);
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+ hdmi_phy_enable_tmds(hdmi, 0);
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+ hdmi_phy_enable_power(hdmi, 0);
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+
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+ return 0;
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+
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+}
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+
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void dw_hdmi_init(struct dw_hdmi *hdmi)
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{
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uint ih_mute;
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diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
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index e5f28132053..d03e8e493b7 100644
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--- a/drivers/video/meson/meson_dw_hdmi.c
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+++ b/drivers/video/meson/meson_dw_hdmi.c
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@@ -374,6 +374,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
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return -ETIMEDOUT;
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}
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+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
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+ .phy_set = meson_dw_hdmi_phy_cfg,
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+};
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+
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+static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = {
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+ .phy_force_vendor = true,
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+ .phy_ops = &dw_hdmi_meson_phy_ops,
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+};
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+
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static int meson_dw_hdmi_probe(struct udevice *dev)
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{
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struct meson_dw_hdmi *priv = dev_get_priv(dev);
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@@ -396,7 +405,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
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priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
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- priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
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+ priv->hdmi.data = &dw_hdmi_meson_plat_data;
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
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priv->hdmi.reg_io_width = 1;
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else {
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diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c
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index 3041360c6ed..b32139a8a6e 100644
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--- a/drivers/video/rockchip/rk3399_hdmi.c
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+++ b/drivers/video/rockchip/rk3399_hdmi.c
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@@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = {
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.enable = rk3399_hdmi_enable,
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};
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+static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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+};
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+
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static const struct udevice_id rk3399_hdmi_ids[] = {
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- { .compatible = "rockchip,rk3399-dw-hdmi" },
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+ {
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+ .compatible = "rockchip,rk3399-dw-hdmi",
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+ .data = (ulong)&rk3399_hdmi_drv_data
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+ },
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{ }
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};
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diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
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index b75a1744896..e34f532cd68 100644
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--- a/drivers/video/rockchip/rk_hdmi.c
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+++ b/drivers/video/rockchip/rk_hdmi.c
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@@ -83,6 +83,7 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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+ hdmi->data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev);
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hdmi->ioaddr = (ulong)dev_read_addr(dev);
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hdmi->mpll_cfg = rockchip_mpll_cfg;
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hdmi->phy_cfg = rockchip_phy_config;
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@@ -90,7 +91,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
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/* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
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hdmi->reg_io_width = 4;
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- hdmi->phy_set = dw_hdmi_phy_cfg;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
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index 19ed80b48a..8e4922c759 100644
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--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
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+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
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@@ -322,6 +322,15 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
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return 0;
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}
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+static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = {
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+ .phy_set = sunxi_dw_hdmi_phy_cfg,
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+};
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+
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+static const struct dw_hdmi_plat_data dw_hdmi_sunxi_plat_data = {
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+ .phy_force_vendor = true,
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+ .phy_ops = &dw_hdmi_sunxi_phy_ops,
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+};
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+
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static int sunxi_dw_hdmi_probe(struct udevice *dev)
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{
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struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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@@ -379,7 +386,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
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hdmi->i2c_clk_high = 0xd8;
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hdmi->i2c_clk_low = 0xfe;
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hdmi->reg_io_width = 1;
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- hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
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+ hdmi->data = &dw_hdmi_sunxi_plat_data;
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret)
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diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
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index 8acae3839fb..4ad8b39f84d 100644
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--- a/include/dw_hdmi.h
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+++ b/include/dw_hdmi.h
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@@ -534,6 +534,17 @@ struct hdmi_data_info {
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struct hdmi_vmode video_mode;
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};
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+struct dw_hdmi;
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+
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+struct dw_hdmi_phy_ops {
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+ int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
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+};
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+
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+struct dw_hdmi_plat_data {
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+ bool phy_force_vendor;
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+ const struct dw_hdmi_phy_ops *phy_ops;
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+};
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+
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struct dw_hdmi {
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ulong ioaddr;
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const struct hdmi_mpll_config *mpll_cfg;
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@@ -543,8 +554,9 @@ struct dw_hdmi {
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u8 reg_io_width;
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struct hdmi_data_info hdmi_data;
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struct udevice *ddc_bus;
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+ const struct dw_hdmi_phy_ops *ops;
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+ const struct dw_hdmi_plat_data *data;
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- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
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void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
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u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
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};
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