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* meson64-edge/5.19: use `tag:v5.19-rc2`, meson64 kernel config and kernel patches, by @adeepv * meson64-edge/5.19: we don't need `CONFIG_ARCH_ROCKCHIP=y` for meson64, right? * meson64-edge/5.19: remove `meson_drv_shutdown` revert patch, instead `CONFIG_DRM_MESON=y` and its dependencies in .config - this allows other meson64's to shutdown properly, while allowing the N2(+) to reboot without kernel-side hangs * meson64-edge/5.19: odroidn2(+): remove SD UHS modes patch for ODROID N2(+) - it works when cold-booted - but changes voltage to enable - when rebooted, voltage persists and uboot can't read the SD anymore - adding the "odroid,reboot" driver+dt that is supposed to fix this, doesn't - so for now remove it * meson64-edge/5.19: odroidn2(+): add dumb gpio fan at 30 celsius - backport from rework in 5.10 * meson64-edge/5.19: odroidhc4: bring back `fan1_input` by adding fan details to DT - yeah, I know; the cooling map is right there too, so empty, poor thing. for later. * meson64-edge/5.19: bump to 5.19-rc3 * meson64-edge/5.19: radxa-zero: add patch to remove UHS mode so `wifi` works - sent by @pyavitz: https://raw.githubusercontent.com/pyavitz/debian-image-builder/feature/patches/amlogic/radxazero/wifi/001-arm64-dts-amlogic-radxa-zero-sdio-card-speed.patch - tested by @lanefu * meson64-edge/5.19: bump to 5.19-rc4 * meson64-edge/5.19: bump to 5.19-rc5 * meson64-edge/5.19: bump to 5.19-rc7 * meson64-edge/5.19: bump to 5.19.y branch, which is 5.19.0 right now * Add kernel config - tested on Odroid N2+ Co-authored-by: Vyacheslav Bocharov <adeep@lexina.in> Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>
203 lines
6.9 KiB
Diff
203 lines
6.9 KiB
Diff
From dd29d3d05631c4afdab56fb696424565a4afefba Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 23 Dec 2018 02:24:38 +0100
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Subject: [PATCH 53/90] WIP: ASoC: hdmi-codec: reorder channel allocation list
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Wrong channel allocation is selected by hdmi_codec_get_ch_alloc_table_idx().
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E.g when ELD reports FL|FR|LFE|FC|RL|RR or FL|FR|LFE|FC|RL|RR|RC|RLC|RRC
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ca_id 0x01 with speaker mask FL|FR|LFE gets selected instead of
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ca_id 0x03 with speaker mask FL|FR|LFE|FC for 4 channels
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and
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ca_id 0x04 with speaker mask FL|FR|RC gets selected instead of
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ca_id 0x0b with speaker mask FL|FR|LFE|FC|RL|RR for 6 channels
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Fix this by reorder the channel allocation list with
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most specific speaker mask at the top.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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sound/soc/codecs/hdmi-codec.c | 140 +++++++++++++++++++---------------
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1 file changed, 77 insertions(+), 63 deletions(-)
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diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
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index b07607a9ecea..a12015471ea2 100644
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--- a/sound/soc/codecs/hdmi-codec.c
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+++ b/sound/soc/codecs/hdmi-codec.c
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@@ -188,84 +188,97 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
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/*
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* hdmi_codec_channel_alloc: speaker configuration available for CEA
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*
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- * This is an ordered list that must match with hdmi_codec_8ch_chmaps struct
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+ * This is an ordered list where ca_id must exist in hdmi_codec_8ch_chmaps
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* The preceding ones have better chances to be selected by
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* hdmi_codec_get_ch_alloc_table_idx().
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*/
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static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
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{ .ca_id = 0x00, .n_ch = 2,
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- .mask = FL | FR},
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- /* 2.1 */
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- { .ca_id = 0x01, .n_ch = 4,
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- .mask = FL | FR | LFE},
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- /* Dolby Surround */
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+ .mask = FL | FR },
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+ { .ca_id = 0x03, .n_ch = 4,
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+ .mask = FL | FR | LFE | FC },
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{ .ca_id = 0x02, .n_ch = 4,
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.mask = FL | FR | FC },
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- /* surround51 */
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+ { .ca_id = 0x01, .n_ch = 4,
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+ .mask = FL | FR | LFE },
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{ .ca_id = 0x0b, .n_ch = 6,
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- .mask = FL | FR | LFE | FC | RL | RR},
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- /* surround40 */
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- { .ca_id = 0x08, .n_ch = 6,
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- .mask = FL | FR | RL | RR },
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- /* surround41 */
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- { .ca_id = 0x09, .n_ch = 6,
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- .mask = FL | FR | LFE | RL | RR },
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- /* surround50 */
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+ .mask = FL | FR | LFE | FC | RL | RR },
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{ .ca_id = 0x0a, .n_ch = 6,
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.mask = FL | FR | FC | RL | RR },
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- /* 6.1 */
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- { .ca_id = 0x0f, .n_ch = 8,
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- .mask = FL | FR | LFE | FC | RL | RR | RC },
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- /* surround71 */
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+ { .ca_id = 0x09, .n_ch = 6,
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+ .mask = FL | FR | LFE | RL | RR },
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+ { .ca_id = 0x08, .n_ch = 6,
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+ .mask = FL | FR | RL | RR },
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+ { .ca_id = 0x07, .n_ch = 6,
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+ .mask = FL | FR | LFE | FC | RC },
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+ { .ca_id = 0x06, .n_ch = 6,
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+ .mask = FL | FR | FC | RC },
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+ { .ca_id = 0x05, .n_ch = 6,
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+ .mask = FL | FR | LFE | RC },
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+ { .ca_id = 0x04, .n_ch = 6,
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+ .mask = FL | FR | RC },
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{ .ca_id = 0x13, .n_ch = 8,
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.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
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- /* others */
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- { .ca_id = 0x03, .n_ch = 8,
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- .mask = FL | FR | LFE | FC },
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- { .ca_id = 0x04, .n_ch = 8,
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- .mask = FL | FR | RC},
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- { .ca_id = 0x05, .n_ch = 8,
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- .mask = FL | FR | LFE | RC },
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- { .ca_id = 0x06, .n_ch = 8,
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- .mask = FL | FR | FC | RC },
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- { .ca_id = 0x07, .n_ch = 8,
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- .mask = FL | FR | LFE | FC | RC },
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- { .ca_id = 0x0c, .n_ch = 8,
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- .mask = FL | FR | RC | RL | RR },
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- { .ca_id = 0x0d, .n_ch = 8,
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- .mask = FL | FR | LFE | RL | RR | RC },
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- { .ca_id = 0x0e, .n_ch = 8,
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- .mask = FL | FR | FC | RL | RR | RC },
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- { .ca_id = 0x10, .n_ch = 8,
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- .mask = FL | FR | RL | RR | RLC | RRC },
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- { .ca_id = 0x11, .n_ch = 8,
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- .mask = FL | FR | LFE | RL | RR | RLC | RRC },
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+ { .ca_id = 0x1f, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
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{ .ca_id = 0x12, .n_ch = 8,
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.mask = FL | FR | FC | RL | RR | RLC | RRC },
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- { .ca_id = 0x14, .n_ch = 8,
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- .mask = FL | FR | FLC | FRC },
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- { .ca_id = 0x15, .n_ch = 8,
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- .mask = FL | FR | LFE | FLC | FRC },
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- { .ca_id = 0x16, .n_ch = 8,
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- .mask = FL | FR | FC | FLC | FRC },
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- { .ca_id = 0x17, .n_ch = 8,
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- .mask = FL | FR | LFE | FC | FLC | FRC },
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- { .ca_id = 0x18, .n_ch = 8,
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- .mask = FL | FR | RC | FLC | FRC },
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- { .ca_id = 0x19, .n_ch = 8,
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- .mask = FL | FR | LFE | RC | FLC | FRC },
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- { .ca_id = 0x1a, .n_ch = 8,
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- .mask = FL | FR | RC | FC | FLC | FRC },
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- { .ca_id = 0x1b, .n_ch = 8,
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- .mask = FL | FR | LFE | RC | FC | FLC | FRC },
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- { .ca_id = 0x1c, .n_ch = 8,
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- .mask = FL | FR | RL | RR | FLC | FRC },
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- { .ca_id = 0x1d, .n_ch = 8,
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- .mask = FL | FR | LFE | RL | RR | FLC | FRC },
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{ .ca_id = 0x1e, .n_ch = 8,
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.mask = FL | FR | FC | RL | RR | FLC | FRC },
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- { .ca_id = 0x1f, .n_ch = 8,
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- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
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+ { .ca_id = 0x11, .n_ch = 8,
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+ .mask = FL | FR | LFE | RL | RR | RLC | RRC },
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+ { .ca_id = 0x1d, .n_ch = 8,
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+ .mask = FL | FR | LFE | RL | RR | FLC | FRC },
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+ { .ca_id = 0x10, .n_ch = 8,
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+ .mask = FL | FR | RL | RR | RLC | RRC },
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+ { .ca_id = 0x1c, .n_ch = 8,
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+ .mask = FL | FR | RL | RR | FLC | FRC },
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+ { .ca_id = 0x0f, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC | RL | RR | RC },
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+ { .ca_id = 0x1b, .n_ch = 8,
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+ .mask = FL | FR | LFE | RC | FC | FLC | FRC },
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+ { .ca_id = 0x0e, .n_ch = 8,
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+ .mask = FL | FR | FC | RL | RR | RC },
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+ { .ca_id = 0x1a, .n_ch = 8,
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+ .mask = FL | FR | RC | FC | FLC | FRC },
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+ { .ca_id = 0x0d, .n_ch = 8,
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+ .mask = FL | FR | LFE | RL | RR | RC },
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+ { .ca_id = 0x19, .n_ch = 8,
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+ .mask = FL | FR | LFE | RC | FLC | FRC },
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+ { .ca_id = 0x0c, .n_ch = 8,
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+ .mask = FL | FR | RC | RL | RR },
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+ { .ca_id = 0x18, .n_ch = 8,
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+ .mask = FL | FR | RC | FLC | FRC },
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+ { .ca_id = 0x17, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC | FLC | FRC },
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+ { .ca_id = 0x16, .n_ch = 8,
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+ .mask = FL | FR | FC | FLC | FRC },
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+ { .ca_id = 0x15, .n_ch = 8,
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+ .mask = FL | FR | LFE | FLC | FRC },
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+ { .ca_id = 0x14, .n_ch = 8,
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+ .mask = FL | FR | FLC | FRC },
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+ { .ca_id = 0x0b, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC | RL | RR },
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+ { .ca_id = 0x0a, .n_ch = 8,
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+ .mask = FL | FR | FC | RL | RR },
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+ { .ca_id = 0x09, .n_ch = 8,
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+ .mask = FL | FR | LFE | RL | RR },
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+ { .ca_id = 0x08, .n_ch = 8,
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+ .mask = FL | FR | RL | RR },
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+ { .ca_id = 0x07, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC | RC },
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+ { .ca_id = 0x06, .n_ch = 8,
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+ .mask = FL | FR | FC | RC },
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+ { .ca_id = 0x05, .n_ch = 8,
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+ .mask = FL | FR | LFE | RC },
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+ { .ca_id = 0x04, .n_ch = 8,
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+ .mask = FL | FR | RC },
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+ { .ca_id = 0x03, .n_ch = 8,
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+ .mask = FL | FR | LFE | FC },
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+ { .ca_id = 0x02, .n_ch = 8,
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+ .mask = FL | FR | FC },
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+ { .ca_id = 0x01, .n_ch = 8,
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+ .mask = FL | FR | LFE },
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};
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struct hdmi_codec_priv {
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@@ -374,7 +387,8 @@ static int hdmi_codec_chmap_ctl_get(struct snd_kcontrol *kcontrol,
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struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
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struct hdmi_codec_priv *hcp = info->private_data;
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- map = info->chmap[hcp->chmap_idx].map;
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+ if (hcp->chmap_idx != HDMI_CODEC_CHMAP_IDX_UNKNOWN)
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+ map = info->chmap[hcp->chmap_idx].map;
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for (i = 0; i < info->max_channels; i++) {
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if (hcp->chmap_idx == HDMI_CODEC_CHMAP_IDX_UNKNOWN)
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--
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2.35.1
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