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101 lines
2.9 KiB
Diff
101 lines
2.9 KiB
Diff
From 8b02771befadcb1b666488c48fa92ec14a07407a Mon Sep 17 00:00:00 2001
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From: Teguh Sobirin <teguh@sobir.in>
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Date: Wed, 12 Feb 2025 20:50:35 +0800
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Subject: [PATCH] arm64: dts: qcom: sm8550: Add iris video-codec node
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Signed-off-by: Teguh Sobirin <teguh@sobir.in>
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---
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arch/arm64/boot/dts/qcom/sm8550.dtsi | 69 ++++++++++++++++++++++++++++
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1 file changed, 69 insertions(+)
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diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
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index a2daf9712fc0..42cd9649a962 100644
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--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
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+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -14,6 +14,7 @@
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#include <dt-bindings/firmware/qcom,scm.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@@ -2867,6 +2868,74 @@ opp-202000000 {
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};
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};
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+ video-codec@aa00000 {
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+ compatible = "qcom,sm8550-iris";
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+ reg = <0 0x0aa00000 0 0xf0000>;
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+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
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+ <&videocc VIDEO_CC_MVS0_GDSC>,
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+ <&rpmhpd RPMHPD_MXC>,
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+ <&rpmhpd RPMHPD_MMCX>;
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+ power-domain-names = "venus", "vcodec0", "mxc", "mmcx";
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+
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+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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+ <&videocc VIDEO_CC_MVS0C_CLK>,
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+ <&videocc VIDEO_CC_MVS0_CLK>;
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+ clock-names = "iface", "core", "vcodec0_core";
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+
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+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
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+ <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
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+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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+ interconnect-names = "cpu-cfg", "video-mem";
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+
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+ memory-region = <&video_mem>;
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+
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+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
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+ reset-names = "bus";
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+
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+ iommus = <&apps_smmu 0x1940 0x0000>,
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+ <&apps_smmu 0x1947 0x0000>;
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+ dma-coherent;
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+
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+ operating-points-v2 = <&iris_opp_table>;
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+
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+ iris_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+
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+ opp-240000000 {
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+ opp-hz = /bits/ 64 <240000000>;
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+ required-opps = <&rpmhpd_opp_svs>,
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+ <&rpmhpd_opp_low_svs>;
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+ };
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+
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+ opp-338000000 {
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+ opp-hz = /bits/ 64 <338000000>;
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+ required-opps = <&rpmhpd_opp_svs>,
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+ <&rpmhpd_opp_svs>;
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+ };
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+
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+ opp-366000000 {
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+ opp-hz = /bits/ 64 <366000000>;
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+ required-opps = <&rpmhpd_opp_svs_l1>,
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+ <&rpmhpd_opp_svs_l1>;
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+ };
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+
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+ opp-444000000 {
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+ opp-hz = /bits/ 64 <444000000>;
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+ required-opps = <&rpmhpd_opp_turbo>,
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+ <&rpmhpd_opp_turbo>;
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+ };
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+
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+ opp-533333334 {
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+ opp-hz = /bits/ 64 <533333334>;
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+ required-opps = <&rpmhpd_opp_turbo_l1>,
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+ <&rpmhpd_opp_turbo_l1>;
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+ };
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+ };
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+ };
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+
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,sm8550-videocc";
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reg = <0 0x0aaf0000 0 0x10000>;
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--
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2.34.1
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