mirror of
https://github.com/armbian/build
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249 lines
5.6 KiB
Diff
249 lines
5.6 KiB
Diff
From 690ebb1dae52d8c30ed4a5dadb9a5c3ef7004e9c Mon Sep 17 00:00:00 2001
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From: Jisheng Zhang <jszhang@kernel.org>
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Date: Tue, 17 Oct 2023 17:40:52 +0800
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Subject: [PATCH 6/8] add lpi3h defconfig and dts
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---
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arch/arm/dts/sun50i-h618-longanpi-3h.dts | 190 ++
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configs/longanpi_3h_defconfig | 2062 ++++++++++++++++++++++
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2 files changed, 2252 insertions(+)
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create mode 100644 arch/arm/dts/sun50i-h618-longanpi-3h.dts
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create mode 100644 configs/longanpi_3h_defconfig
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diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts
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new file mode 100644
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index 0000000000..b0ff07ce72
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--- /dev/null
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+++ b/arch/arm/dts/sun50i-h618-longanpi-3h.dts
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@@ -0,0 +1,190 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (C) Jisheng Zhang <jszhang@kernel.org>
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+ */
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+
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+/dts-v1/;
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+
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+#include "sun50i-h616.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "LonganPi 3H";
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+ compatible = "sipeed,longanpi-3h", "allwinner,sun50i-h618";
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+
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+ aliases {
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+ ethernet0 = &emac0;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ // linux,initrd-start = <0x4a000000>;
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+ // linux,initrd-end = <0x4a0759bc>;
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+ };
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+
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+ /*memory@41000000 {
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+ device_type = "memory";
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+ reg = <0x0 0x41000000 0x0 0xff000000>;
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+ };*/
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+
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+ reg_vcc5v: vcc5v {
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+ /* board wide 5V supply directly from the USB-C socket */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-5v";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+};
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+
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+&ehci1 {
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+ status = "okay";
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+};
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+
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+&ohci1 {
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+ status = "okay";
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+};
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+
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+&ehci2 {
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+ status = "okay";
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+};
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+
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+&ohci2 {
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+ status = "okay";
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+};
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+
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+&ehci3 {
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+ status = "okay";
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+};
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+
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+&ohci3 {
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+ status = "okay";
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+};
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+
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+&emac0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ext_rgmii_pins>;
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+ phy-mode = "rgmii";
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+ phy-handle = <&ext_rgmii_phy>;
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+ allwinner,rx-delay-ps = <3100>;
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+ allwinner,tx-delay-ps = <700>;
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+ phy-supply = <®_dldo1>;
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+ status = "okay";
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+};
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+
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+&mdio0 {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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+&mmc0 {
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+ bus-width = <4>;
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+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
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+ vmmc-supply = <®_dldo1>;
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+ status = "okay";
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+};
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+
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+&mmc2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc2_pins>;
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+ vmmc-supply = <®_dldo1>;
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+ vqmmc-supply = <®_aldo1>;
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+ bus-width = <8>;
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+ non-removable;
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+ cap-mmc-hw-reset;
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+ mmc-ddr-1_8v;
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+ mmc-hs200-1_8v;
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+ mmc-hs400-1_8v;
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&usbotg {
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+ /*
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+ * PHY0 pins are connected to a USB-C socket, but a role switch
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+ * is not implemented: both CC pins are pulled to GND.
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+ * The VBUS pins power the device, so a fixed peripheral mode
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+ * is the best choice.
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+ * The board can be powered via GPIOs, in this case port0 *can*
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+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
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+ * then provided by the GPIOs. Any user of this setup would
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+ * need to adjust the DT accordingly: dr_mode set to "host",
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+ * enabling OHCI0 and EHCI0.
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+ */
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ usb1_vbus-supply = <®_vcc5v>;
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+ status = "okay";
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+};
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+
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+&r_i2c {
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+ status = "okay";
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+
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+ axp313: pmic@36 {
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+ compatible = "x-powers,axp313a";
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+ reg = <0x36>;
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+
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+ vin1-supply = <®_vcc5v>;
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+ vin2-supply = <®_vcc5v>;
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+ vin3-supply = <®_vcc5v>;
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+
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+ regulators {
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+ /* Supplies VCC-PLL, so needs to be always on. */
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+ reg_aldo1: aldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc1v8";
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+ };
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+
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+ /* Supplies VCC-IO, so needs to be always on. */
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+ reg_dldo1: dldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc3v3";
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+ };
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+
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+ reg_dcdc1: dcdc1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <810000>;
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+ regulator-max-microvolt = <990000>;
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+ regulator-name = "vdd-gpu-sys";
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+ };
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+
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+ reg_dcdc2: dcdc2 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <810000>;
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+ regulator-max-microvolt = <1100000>;
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+ regulator-name = "vdd-cpu";
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+ };
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+
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+ reg_dcdc3: dcdc3 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ regulator-name = "vdd-dram";
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+ };
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+ };
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+ };
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+};
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+
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+&pio {
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+ vcc-pc-supply = <®_dldo1>;
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+ vcc-pf-supply = <®_dldo1>;
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+ vcc-pg-supply = <®_aldo1>;
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+ vcc-ph-supply = <®_dldo1>;
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+ vcc-pi-supply = <®_dldo1>;
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+};
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diff --git a/configs/longanpi_3h_defconfig b/configs/longanpi_3h_defconfig
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new file mode 100644
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index 0000000000..7111b173be
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--- /dev/null
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+++ b/configs/longanpi_3h_defconfig
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@@ -0,0 +1,30 @@
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+CONFIG_ARM=y
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+CONFIG_ARCH_SUNXI=y
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+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-longanpi-3h"
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+CONFIG_SPL=y
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+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
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+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
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+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
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+CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee
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+CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080
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+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
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+CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524
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+CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f
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+CONFIG_MACH_SUN50I_H616=y
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+CONFIG_SUNXI_DRAM_H616_LPDDR4=y
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+CONFIG_DRAM_CLK=792
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+CONFIG_R_I2C_ENABLE=y
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+CONFIG_SPL_SPI_SUNXI=y
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+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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+CONFIG_SPL_I2C=y
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+CONFIG_SPL_SYS_I2C_LEGACY=y
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+CONFIG_SYS_I2C_MVTWSI=y
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+CONFIG_SYS_I2C_SLAVE=0x7f
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+CONFIG_SYS_I2C_SPEED=400000
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+CONFIG_MTD=y
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+CONFIG_SPI_FLASH_ZBIT=y
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+CONFIG_AXP313_POWER=y
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+CONFIG_SPI=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_MUSB_GADGET=y
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--
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2.34.1
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